Fluorine reduction is silicon-containing film

Abstract

A method of filling a gap with a dielectric material includes using a suppression plasma during deposition. The suppression of the plasma increases the nucleation barrier of the deposited film. The passivation plasma may remove inhibitor species adsorbed on the surface or in the body on which the dielectric material has been deposited.

Description

Related Applications

[0001] The PCT application form is filed concurrently with this specification as a part of this application. Each application identified in the concurrently filed PCT application form to which this application claims the benefit or priority is incorporated herein by reference in its entirety. Background Art

[0002] Many semiconductor device processes involve film formation, including silicon-containing films such as silicon oxide or silicon nitride. Plasma enhanced atomic layer deposition (PEALD) can be used to deposit silicon-containing films. Depositing high-quality films can be particularly challenging when depositing films in gaps. Inhibitor species can be used when depositing a portion of a film in a gap.

[0003] The background description provided here is for the purpose of generally presenting the context of the present disclosure. The work of the presently designated inventors is neither explicitly nor implicitly admitted to be prior art against the present disclosure to the extent that it is described in this background section and to aspects of the specification that could not be determined as prior art at the time of filing the application. Summary of the invention

[0004] Disclosed herein are methods and systems for depositing dielectric materials. In one aspect of the embodiments herein, a method is provided, the method comprising: providing a substrate in a processing chamber, the substrate having one or more structures, each structure comprising a gap; performing a first set of cycles of the following steps: (a) exposing the substrate to a suppression plasma to suppress deposition on a portion of each gap, wherein the suppression plasma comprises a fluorine-containing species, and (b) after (a), depositing a dielectric material in each gap, and after performing the first set of cycles, exposing the substrate to a passivation plasma to reduce the fluorine concentration in the dielectric material, wherein after exposing the substrate to the passivation plasma, the fluorine concentration is less than about 10 20 Atom / cm 3 In some embodiments, the fluorine concentration in the dielectric material is measured from a bulk portion of the dielectric material. In some embodiments, the fluorine concentration in the dielectric material is an average concentration at a depth of at least 5 nm from the surface of the substrate. In some embodiments, after exposing the substrate to the passivating plasma, the fluorine concentration is less than about 10 19 Atom / cm 3 In some embodiments, the duration of the passivation plasma is at least about 80 seconds. In some embodiments, the passivation plasma has a high frequency (HF) power of at least about 5000 W. In some embodiments, the passivation plasma has a low frequency (LF) power between about 0 W and about 2000 W. In some embodiments, the dielectric material has a power of less than In some embodiments, the suppression plasma comprises a nitrogen-containing species. In some embodiments, the passivation plasma reduces the nitrogen concentration in the dielectric material. In some embodiments, the dielectric material comprises a silicon-containing material. In some embodiments, the silicon-containing material comprises silicon oxide. In some embodiments, the passivation plasma comprises an oxygen-containing species. In some embodiments, the passivation plasma comprises a hydrogen-containing species. In some embodiments, the passivation plasma comprises an oxygen-containing species and a hydrogen-containing species.

[0005] In another aspect of the embodiments herein, a system is provided, comprising: a processing chamber; and one or more processors and one or more memories, the one or more processors and the one or more memories comprising computer executable instructions for: providing a substrate in the processing chamber, the substrate having one or more structures, each structure comprising a gap; performing a first set of cycles of: exposing the substrate to an inhibition plasma to inhibit deposition on a portion of each gap, wherein the inhibition plasma comprises a fluorine-containing species, and after (a), depositing a dielectric material in each gap, and after performing the first set of cycles, exposing the substrate to a passivation plasma, wherein the duration of the passivation plasma is at least about 80 seconds and the high frequency (HF) power of the passivation plasma is at least about 5000 W.

[0006] These and other features of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A flowchart is presented for the operation of an exemplary embodiment.

[0008] Figure 2 A graph showing the variation of fluorine concentration with depth for various deposition processes is presented.

[0009] Figure 3 A flowchart is presented for the operation of an exemplary embodiment.

[0010] Figure 4 A flow diagram of operations for an atomic layer deposition process is presented.

[0011] Figures 5 to 8 is a schematic diagram of an example of a processing chamber for performing the method of the disclosed embodiments. DETAILED DESCRIPTION

[0012] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments presented. The disclosed embodiments may be implemented without some or all of these specific details. In other cases, well-known processing operations are not described in detail so as not to unnecessarily obscure the disclosed embodiments. Although the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that they are not intended to limit the disclosed embodiments.

[0013] Semiconductor manufacturing processes typically include dielectric gap filling using chemical vapor deposition (CVD) and / or atomic layer deposition (ALD) methods to fill features. Methods of filling features using dielectric materials (including but not limited to silicon-containing films, such as silicon oxides), and related systems and devices are disclosed herein. The methods described herein can be used to fill features formed in a substrate in a vertical orientation. Such features may be referred to as gaps, recessed features, negative features, unfilled features, or simply features. Filling such features may be referred to as gap filling. Features formed in a substrate may be characterized by one or more narrow and / or concave openings, constrictions within the feature, and a high aspect ratio. In certain embodiments, the feature may have an aspect ratio of at least about 2:1, at least about 4:1, at least about 6:1, at least about 20:1, at least about 100:1, or greater. The substrate may be a silicon or other semiconductor wafer, such as a 200-mm wafer, a 300-mm wafer, a 450-mm wafer, including a wafer having one or more layers of material (eg, dielectric, conductive, or semiconductive material) deposited thereon.

[0014] Aspects of the present disclosure relate to methods for using a suppressed plasma during atomic layer deposition (ALD) of a dielectric material in a gap that promotes void-free bottom-up gap filling. The suppressed plasma creates a passivated surface and increases the nucleation barrier for the deposited ALD film. When the suppressed plasma interacts with the material in the feature, the material at the bottom of the feature is subjected to less plasma processing due to geometric shielding effects than the material located closer to the top of the feature or on the field surrounding the feature. Thus, deposition at the top of the feature is selectively suppressed, while deposition in the lower portion of the feature proceeds with less suppression or without suppression. Thus, bottom-up filling in the ALD process is achieved, resulting in a more favorable sloped profile that mitigates seam effects and prevents void formation. Halogen-containing plasmas can be effective suppressed plasmas. For example, for some applications, a plasma produced from nitrogen trifluoride (NF 3 ) can be compared to plasma produced from molecular nitrogen (N 2 ) plasma provides suppression effect in a significantly reduced time.

[0015] Figure 1A process flow diagram is shown for a method of filling a gap with a dielectric material. The method begins by providing a structure having one or more gaps to be filled (101). The structure may be formed from one or more material layers deposited on a substrate. The substrate may be a silicon or other semiconductor wafer (e.g., a 200-mm wafer, a 300-mm wafer, or a 450-mm wafer), including a wafer having one or more material layers, such as a dielectric material, a conductive material, or a semiconductor material deposited thereon. The method may also be applied to gap fill other substrates (e.g., glass, plastic, etc.), including in the manufacture of microelectromechanical (MEMS) devices.

[0016] Examples of structures include 3D NAND structures, DRAM structures, and shallow trench isolation (STI) structures. The structures include gaps, and the sidewalls of the gaps are formed of materials susceptible to etching. In an example, the 3D NAND structure includes an oxide-nitride-oxide-nitride (ONON) stack covered with a polysilicon layer. In another example, the structure may include a lateral / tunnel structure extending horizontally from a common vertical trench. Other examples of sidewall materials include oxides, metals, and semiconductor materials. The methods described herein are not limited to a particular type of sidewall material and can be used to suppress any susceptible material.

[0017] The dielectric material is deposited in the gap using a suppression plasma and a passivation plasma (105). As discussed further below, this may involve performing a cycle of suppression plasma followed by a cycle of ALD of the dielectric material. The suppression plasma treatment may result in the adsorption of suppressor species, specifically halogen species such as fluorine and nitrogen, e.g., when NF 3 Used as an inhibitor species. Although fluorine is discussed throughout this application, in some embodiments, different halogen species can be used as inhibitors for the processes described herein. The adsorbed inhibitor species can then prevent the adsorption of the precursor species, thereby inhibiting the atomic layer deposition (ALD) process of the dielectric material. A passivation plasma can then be used to remove the inhibitor species.

[0018] The suppressed plasma process can be characterized as the inhibition effective depth (IED). The IED describes the depth beyond which deposition will be suppressed. During the design of a bottom-up fill process, multiple suppression zones can be planned, where the suppressed plasma process is varied between these suppression zones. For example, the suppressed plasma process can be adjusted so that the IED is closer to the bottom of the feature, for example, 75% of the total depth of the feature will be suppressed. Then, the ALD process cycle can be performed to fill the bottom 25% of the feature. Then, the suppressed plasma parameters can be adjusted to suppress, for example, the top 50% of the feature (relative to the total depth and regardless of any fill), and then fill the next bottom portion of the feature.

[0019] In some embodiments, a passivation plasma is used to remove inhibitor species before changing the properties of the inhibition plasma to change the way the surface is inhibited. For example, a passivation plasma can be used between inhibition blocks to remove any inhibitor species remaining under the IED required for the subsequent inhibition block. This helps to increase the deposition rate of the dielectric material and reduce the incorporation of fluorine into the deposited dielectric material.

[0020] In some embodiments, the passivation plasma can be a hydrogen plasma and / or an oxygen plasma. In some embodiments, the hydrogen plasma reacts with the adsorbed fluorine to form HF gas, which can then be exhausted from the processing chamber (hydrogen plasma can also be used with many halogen inhibitor species to form HX, where X is a halogen). Similarly, the oxygen plasma can react with the adsorbed nitrogen to form NO and / or NO 2 gas, and the NO and / or NO 2 The gas may then be exhausted from the process chamber.

[0021] Although hydrogen and / or oxygen plasmas are effective in removing surface adsorbed fluorine and / or nitrogen, in some embodiments, fluorine and / or nitrogen species may diffuse into the film. Such diffusion may occur between the suppression plasma treatment that causes the inhibitor species to adsorb and the passivation treatment used to remove the adsorbed inhibitor species. An increase in the concentration of fluorine and / or nitrogen in the film is undesirable.

[0022] Figure 2 A graph of fluorine concentration versus depth for suppressed and unsuppressed treatments based on secondary ion mass spectrometry (SIMS) is shown. The suppression treatment used the suppression plasma described herein (using NF 3 to generate the plasma) and the passivation plasma (using O 2 and H 2The non-suppressed process does not use a suppressed plasma or a passivation plasma. Specifically, the passivation plasma is performed at a pressure of 2 Torr, a HF power of 1250 W, and a duration of 40 seconds. Figure 2 As shown in Figure 2, the fluorine concentration of the inhibition treatment is much higher than that of the non-inhibition treatment. The fluorine concentration in the non-inhibition treatment film is about 3.9×10 19 Atom / cm 3 , while the fluorine concentration in the inhibition treatment film is about 4.2×10 21 Atom / cm 3 In some embodiments, the concentration may be an average concentration measured in a bulk portion of the film. The bulk portion may be a portion of the semiconductor material that has consistent properties throughout the segment, and when measured in those portions of the segment, the measured value of the property does not change due to proximity to the boundaries of the segment. For example, in Figure 2 In the non-inhibited treatment, the concentration can be measured at depths greater than about 5 nm. Below 5 nm, the fluorine concentration may vary with depth; however, at depths greater than 5 nm, the concentration may be relatively stable until another boundary layer (for the non-inhibited treatment film) is shown at about 20 nm.

[0023] This concentration difference may be caused by diffusion of adsorbed fluorine from the suppression plasma into the film, since the non-suppression process will not have another source of fluorine species incorporated into the film (in some embodiments, the chamber cleaning process may include fluorine-containing species that may be incorporated into the film as a contaminant, but both processes will be affected by such fluorine contaminants). It is worth noting that while a passivation plasma treatment can be performed to remove fluorine, in Figure 2 In the inhibition treatment shown, this was not sufficient to remove fluorine from the bulk film. Figure 2 The suppression process shown may be sufficient for a bottom-up fill process, but the passivation plasma does not remove fluorine that diffused into the film due to exposure to the suppression plasma.

[0024] It should be noted that Figure 2 The treatments shown were each performed for the same number of cycles. The film growth / cycle for the inhibited treatment was generally slower than that for the non-inhibited treatment, so Figure 2 The depths shown in are not calibrated between the two treatments shown. Both treatments were run for the same number of cycles, resulting in a thinner deposited film from the suppressed treatment and therefore a shift / compression of the fluorine concentration vs. depth curve for the suppressed treatment compared to the non-suppressed treatment. The fluorine concentration curves are presented for qualitative illustration and concentrations may vary based on differences in film deposition and measurement techniques.

[0025] In order to remove fluorine from the bulk film, the passivation process can be adjusted to reduce the fluorine concentration in the bulk film, and to remove fluorine from the surface of the substrate. In some embodiments, high power, long duration or high hydrogen / oxygen flow passivation can be performed to reduce the fluorine concentration in the film. In some embodiments, high power passivation can have a plasma power having a low frequency (LF) and a high frequency (HF) component, wherein the LF power can be between about 0W and about 5000W, and the HF power can be between about 1250W and about 6000W. In some embodiments, a higher HF power and a lower LF power may be advantageous because the LF power may increase the sputtering effect of the plasma on the deposited film, which is undesirable. In general, a higher RF power can increase the energy of the substance and drive the reaction kinetics toward forming HF, which can then be discharged from the processing chamber.

[0026] In some embodiments, a long passivation treatment may also be used. For example, the passivation treatment may be at least about 40 seconds, at least about 60 seconds, at least about 80 seconds, at least about 100 seconds, at least about 120 seconds, between about 40 seconds and about 120 seconds, or between 60 seconds and about 120 seconds. In some embodiments, a longer duration of the passivation plasma treatment may remove fluorine at the surface, thereby creating a concentration gradient that allows additional fluorine to diffuse to the surface, react, and drain over the duration of the passivation plasma.

[0027] In some embodiments, the gas flow of hydrogen or oxygen-containing species may be increased. 2 and O 2 Typically used as hydrogen-containing or oxygen-containing species, respectively, but other hydrogen-containing or oxygen-containing species may be used in some embodiments. Since hydrogen and oxygen can react with halogen / nitrogen species to form gaseous species that can be discharged, a higher partial pressure of such species can improve reaction kinetics and further reduce halogen / nitrogen impurities. In some embodiments, an inert gas may also be co-flowed, wherein the inert gas may be, for example, helium or argon. In some embodiments, the inert gas may not be co-flowed to further increase the partial pressure of the hydrogen-containing and oxygen-containing species.

[0028] In some embodiments, the flow rate of the hydrogen-containing species may be at least about 2000 sccm or between about 2000 sccm and about 5000 sccm, and the flow rate of the oxygen-containing species may be between about 0 sccm and about 5000 sccm.

[0029] In some embodiments, the pressure may also be increased to reduce sputtering of the film. In some embodiments, the pressure of the passivation process may be between about 2 Torr and about 12 Torr.

[0030] Table 1 below summarizes two passivation treatments that can be used to reduce the concentration of fluorine (or other halogens). Figure 2 In some embodiments, the passivation treatment described herein can reduce the fluorine concentration to less than about 10 20 Atom / cm 3 , less than about 10 19 Atom / cm 3 , less than about 10 18 Atom / cm 3 , or between about 10 20 Atom / cm 3 With about 10 18 Atom / cm 3 It should be understood that the parameters below are exemplary processes and a range of parameters are used as described herein. Table 1

[0031] In some embodiments, in addition to reducing fluorine impurities, the high power / long duration passivation treatment described herein can also improve other material properties of the deposited film. Table 2 below shows the material properties of films deposited using the suppression plasma and passivation plasma treatments described herein, as well as plasma enhanced ALD treatments that do not use suppression or passivation plasmas. A 5000W ALD film will typically have better material properties than a 1250W ALD film, such as a lower wet etch rate (WER) and wet etch rate ratio (WERR). It is noteworthy that the high HF passivation treatment (including the passivation plasma treatment described in Table 1 above) has similar properties to the 5000W ALD film. It is noteworthy that the ALD portion of the high HF passivation deposition process has similar deposition parameters to the 1250W ALD film in Table 2, but the high HF passivation plasma improves the film properties to make it closer to the 5000W ALD film.

[0032] Thus, in some embodiments, the passivation treatments described herein can reduce the fluorine concentration in the film, as well as improve WER, WERR, refractive index (RI) and other material properties. In some embodiments, the WER of a dielectric material deposited using the passivation treatments described herein can be less than about 1 A / sec. Table 2

[0033] Figure 3 An example of a processing sequence that may be used in accordance with the disclosed embodiments is shown. Figure 3 The processing sequence in includes treating the substrate using a suppressed plasma. In some embodiments, other operations (such as soaking) can be omitted, and in some embodiments, operations can be added. Figure 3 In an exemplary processing sequence of , one or more wafers undergo gap filling. The process may begin with a soak (302) after being provided to a deposition chamber. This may be useful, for example, for particle removal or other pre-processing. Then, n1 cycles of ALD deposition of a liner are performed (304). The liner, if deposited, is a material that protects the underlying structure from plasma damage. It may be the same or a different material than the gap fill material.

[0034] After depositing the optional liner, n suppression blocks are performed, of which the operations of the first suppression block (n=1) are shown. The first operation is to suppress the plasma, which is a surface treatment. As discussed above (308), the plasma may include halogen species, including, for example, F - , Cl - ,I - Br - , fluorine radicals and other anionic and radical species. Other suppression plasmas may be used. In some embodiments, the suppression plasma is generated from non-halogen-containing species, including nitrogen-containing and non-halogen-containing species. For example, the suppression plasma generated from molecular nitrogen (N 2 ), molecular hydrogen (H 2 ), ammonia (NH 3 ), amines, diols, diamines, amino alcohols, thiols, alkyl halides, halides, HF, fluorine-containing species, chlorine-containing species, iodine-containing species, or a combination thereof as a suppression plasma. In some embodiments, the suppression plasma treatment is performed at a high pressure as described herein.

[0035] When the plasma is inhibited from interacting with the material in the feature, material at the bottom of the feature is less processed by the plasma due to geometric shadowing effects than material located closer to the top or in the field of the feature. Thus, deposition at the top of the feature is selectively inhibited, while deposition in the lower portion of the feature proceeds with less inhibition or without inhibition. Figure 3 , the next operation in the suppression block is n2 cycles of ALD fill (310). The dielectric material is selectively deposited at the bottom of the feature. The suppression plasma and n2 cycles of ALD fill together constitute a growth cycle. This can be repeated n3 times to continue filling the feature with intermittent suppression operations as the suppression effect decreases.

[0036] exist Figure 3In the example of , the inhibition block ends at a passivation operation (312). In some embodiments, a passivation operation may not be performed in every inhibition block. A passivation operation is a surface treatment that removes residual inhibitors and may also densify the deposited film. In some embodiments, the passivation operation includes exposing the substrate to a passivation plasma. The passivation plasma may be a hydrogen and / or oxygen plasma. In some embodiments, the passivation plasma includes hydrogen-containing and / or oxygen-containing species co-flowing with an inert gas. In some embodiments, the passivation plasma may include hydrogen species including free radicals or ionic species, such as H + , H - , hydrogen radicals, etc., which can be composed of, for example, H 2 In some embodiments, the passivation plasma may include oxygen-containing species, including free radicals or ionic species, such as O 2 + , O 2 - , O 3 ,O,O + , O - , free ozone and metastable excited oxygen, which can be generated from oxygen-containing species such as O 2. The passivation operation can be performed according to the various embodiments discussed above.

[0037] One or more additional suppression blocks (314) including growth cycles and passivation may be performed for a total of n suppression blocks. The number of suppression blocks depends on how much material is used to fill the feature. The suppression plasma, ALD, and passivation conditions may be varied between suppression blocks to fill the feature. For example, the duration of the suppression plasma may be 20 seconds until the bottom quarter of the feature is filled (suppression block 1), then changed to 5 seconds for the middle 50% of the structure (suppression block 2), etc. Each suppression block may have a different IED, where the processing parameters for the suppression plasma treatment of the suppression block are varied to target the different IEDs. Each suppression block may fill a portion of the feature below the IED of that suppression block.

[0038] When the feature is nearly filled, inhibition may no longer be needed, and the filling may be completed with n4 cycles of ALD fill (316). In some embodiments, an optional cap or cover layer of dielectric may then be deposited (318). Plasma enhanced chemical vapor deposition (PECVD) may be used for rapid deposition at this stage.

[0039] As described above, ALD is used to deposit dielectric materials in features. ALD is a technique for sequentially depositing thin layers of material. ALD processes use surface-mediated deposition reactions to cyclically deposit films on a layer-by-layer basis. The concept of an ALD "cycle" is relevant to the discussion of many embodiments herein. In general, a cycle is used to perform a minimum set of operations for a surface deposition reaction. The result of the cycle is that at least a portion of a silicon-containing film layer is produced on the substrate surface. Typically, an ALD cycle includes operations for transporting and adsorbing at least one reactant to the substrate surface, and then reacting the adsorbed reactant with one or more reactants to form a partial film layer. The cycle may include, for example, several auxiliary operations to sweep away one of the reactants or byproducts and / or process the deposited partial film. In general, a cycle includes examples of unique sequences of operations.

[0040] For example, an ALD cycle may include the following operations: (i) delivery / adsorption of a precursor; (ii) purging of the precursor from the chamber; (iii) delivery of a second reactant and optional plasma ignition; and (iv) purging of byproducts from the chamber. The reaction between the second reactant and the adsorbed precursor that forms a film on the substrate surface can affect film composition and properties, such as non-uniformity, stress, wet etch rate, dry etch rate, electrical properties (such as breakdown voltage and leakage current), etc.

[0041] In one example of an ALD process, a substrate surface containing a number of surface active sites is exposed to a gas phase distribution of a first precursor (e.g., a silicon-containing precursor) provided in a certain dosage to a chamber containing the substrate. Molecules of the first precursor are adsorbed onto the substrate surface, including chemically adsorbed species and / or physically adsorbed molecules of the first precursor. When a compound is adsorbed onto the substrate surface as described herein, the adsorption layer may include the compound and derivatives of the compound. For example, the adsorption layer of a silicon-containing precursor may include the silicon-containing precursor and derivatives of the silicon-containing precursor. After the first precursor is dosed, the chamber is then evacuated to remove most or all of the remaining gas phase first precursor, so that most or only the adsorbed substances remain. In some embodiments, the chamber may not be completely evacuated. For example, the reactor may be vented so that the partial pressure of the gas phase first precursor is low enough to moderate the reaction. A second reactant, such as an oxygen-containing gas or a nitrogen-containing gas, is introduced into the chamber so that some of these molecules react with the first precursor adsorbed on the surface. In some processes, the second reactant reacts immediately with the adsorbed first precursor. In other embodiments, the second reactant reacts only when an activation source such as a plasma is temporarily applied. The chamber may then be evacuated again to remove unbound second reactant molecules. As described above, in certain embodiments, the chamber may not be completely evacuated. Additional ALD cycles may be used to build up film thickness.

[0042] Figure 4 A process flow diagram is presented for a single plasma enhanced ALD cycle that can be implemented as Figure 3 4. In operation 402, the substrate is exposed to a silicon-containing precursor to adsorb the precursor onto the surface of the feature. This operation may be self-limiting. In some embodiments, the precursor adsorbs to less than all active sites on the surface of the feature. In operation 404, the processing chamber is optionally purged to remove any unadsorbed silicon-containing precursor. In operation 406, the substrate is exposed to a plasma produced from a co-reactant. Examples include silicon oxide layers or silicon oxynitride layers formed by forming silicon oxide layers. 2 and / or N 2 O, N for forming a silicon nitride layer 2 or NH 3 , methane (CH 4 ) etc. In operation 408, the process chamber is optionally purged to remove byproducts from the reaction between the silicon-containing precursor and the oxidant. Operations 402 to 408 are repeated for several cycles to deposit a silicon-containing layer in the feature to a desired thickness.

[0043] It should be noted that the processes described herein are not limited to a particular reaction mechanism. Figure 4 The processes described include all deposition processes using sequential exposure to silicon-containing reactants and conversion plasmas (including those that are not strictly self-limiting). The processes include sequences in which one or more gases used to generate the plasma flow continuously throughout the process with intermittent plasma ignition.

[0044] In some embodiments, the suppression plasma treatment may be performed at a pressure greater than about 1 Torr, at least about 10 Torr, at least about 15 Torr, at least about 20 Torr, between about 10 Torr and about 30 Torr, or between about 15 Torr and about 30 Torr.

[0045] The duration of the suppression plasma treatment can be between about 0.3 seconds and about 60 seconds, between about 0.3 seconds and about 30 seconds, at least about 0.3 seconds, at least about 1 second, at least about 5 seconds, at least about 10 seconds, at least about 20 seconds, or at least about 30 seconds. Suppression plasma treatments using halogen-containing species can generally be used for shorter durations than non-halogen-containing species because halogen-containing species can passivate surfaces more effectively than non-halogen-containing species.

[0046] High pressure suppressed plasma processing can be used for a variety of aspect ratios and structure depths. In some embodiments, high pressure suppressed plasma processing can be used for low aspect ratio structures. Low aspect ratio structures can have aspect ratios between about 3:1 and about 7:1, less than about 10:1, between about 3:1 and about 10:1, between about 3:1 and about 15:1, or less than about 15:1. Low aspect ratio structures can have a depth of at least about 100 nm, at least about 1 μm, at least about 2 μm, or at least about 3 μm.

[0047] In some embodiments, IED may have a percentage characteristic, for example, 30% IED means that the deposition is inhibited at an effective depth of 30% of the total depth of the feature. Thus, if the feature has a depth of 1 μm, 30% IED means that deposition will be inhibited along the sidewall surface of the feature (i.e., within 300 nm from the top of the feature), while the remaining depth is not inhibited.

[0048] In some embodiments, the ratio of the inhibitory substance to the inert gas can be about 1:5, about 1:10, or between about 1:10 to about 1:20, or between about 1:5 to about 1:5000. In general, the addition of an inhibitory substance (e.g., NF 3 ) gas flow ratio may result in an increased suppression effect and / or exposure of the substrate to an etch component of the suppression plasma. 2 ) may flow between about 10 slm and about 100 slm. In some embodiments, the inert gas may co-flow with the substance used for suppression. The inert gas may include helium, argon, xenon, or other gases that do not react with other substances in the surface of the gas or substrate. When used, the flow rate of the inert gas may be between about 3.5 and about 15 slm. In some embodiments, oxygen-containing or hydrogen-containing substances may co-flow with the substance used for suppression. If the substance used for suppression includes nitrogen atoms, the nitrogen atoms may react with the silicon-containing precursor or silicon film to form silicon nitride. Adding oxygen-containing or hydrogen-containing substances can suppress the conversion of silicon oxide or silicon into silicon nitride, respectively. In some embodiments, the co-flow of oxygen-containing or hydrogen-containing substances may be at least about 100 sccm, or between about 0 and about 5 slm.

[0049] In various embodiments, the plasma is an in-situ plasma such that the plasma is formed directly above the substrate surface in the station. In some embodiments, an exemplary power per substrate area of ​​the in-situ plasma is about 0.2122 W / cm 2 About 2.122W / cm 2For example, for a chamber that processes four 300 mm wafers, the power range may be from about 1000 W to about 6000 W. In one embodiment, for four 300 mm wafers, the power may be between about 2500 W and 6000 W. The plasma for ALD processing may be generated by applying a radio frequency (RF) field to a gas using two capacitively coupled plates. The plasma is ignited by the ionization of the gas between the plates by the RF field, thereby forming free electrons in the plasma discharge region. These electrons are accelerated by the RF field and may collide with gas phase reactant molecules. The collision of these electrons with the reactant molecules may form free radical species that participate in the deposition process. It should be understood that the RF field may be coupled via any suitable electrode. Non-limiting examples of electrodes include a process gas distribution nozzle and a substrate support pedestal. It should be understood that, in addition to the capacitive coupling of the RF field to the gas, the plasma for ALD processing may be formed by one or more suitable methods. In one embodiment, the plasma is a remote plasma, so that the second reactant is ignited in a remote plasma generator upstream of the station and then transported to the station that accommodates the substrate.

[0050] To deposit the silicon-containing material, one or more silicon-containing precursors may be used. In some examples, the silicon-containing precursor may include silane (e.g., SiH 4 ), polysilane (H 3 Si-(SiH 2 ) n -SiH 3 ), wherein n≥1, organic alkane, halogenated silane, aminosilane, alkoxysilane, etc. For example, methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di(tert-butyl)silane, allylsilane, sec-butylsilane, tert-hexylsilane, isopentylsilane, tert-butyldisilane, di(tert-butyl)disilane and other organic silanes.

[0051] Halogen silanes include at least one halogen group and may or may not include hydrogen and / or carbon groups. Examples of halogen silanes are iodosilanes, bromosilanes, chlorosilanes and fluorosilanes. Specific chlorosilanes are tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallyl silane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di-tert-butylchlorosilane, chloroisopropylsilane, chloro-sec-butylsilane, tert-butyldiethylchlorosilane, n-hexyldimethylchlorosilane etc.

[0052] Aminosilanes contain at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon. Examples of aminosilanes are mono-, di-, tri-, and tetra-aminosilane (H 3 Si(NH 2 ), H 2 Si(NH 2 )2 、HSi(NH 2 ) 3 , and Si(NH 2 ) 4 ) and substituted mono-, di-, tri-, and tetra-aminosilanes, such as tert-butylaminosilane, methylaminosilane, tert-butylsilylamine, di(tert-butylamino)silane (SiH 2 (NHC(CH 3 ) 3 ) 2 (BTBAS), tert-butylsilylcarbamate, SiH(CH 3 )-(N(CH 3 ) 2 ) 2 、SiHCl-(N(CH 3 ) 2 ) 2 、(Si(CH 3 ) 2 NH) 3 , di-isopropylaminosilane (DIPAS), di-sec-butylaminosilane (DSBAS), SiH 2 [N(CH 2 CH 3 ) 2 ] 2 (BDEAS) etc. A further example of aminosilane is trisilylamine (N(SiH 3 )). In some embodiments, aminosilanes having two or more amine groups attached to the central silicon atom may be used. These may cause less damage than aminosilanes having only a single amine group attached.

[0053] Another example of a silicon-containing precursor includes trimethylsilane (3MS); ethylsilane; butylsilane; pentasilane; octylsilane; heptylsilane; hexasilane; cyclotetrasilane; cycloheptylsilane; cyclohexasilane; cyclooctylsilane; cyclopentasilane; 1,4-dioxa-2,3,5,6-tetrasilcyclohexane; diethoxymethylsilane (DEMS); diethoxysilane (DES); dimethoxymethylsilane; dimethoxysilane (DMOS); methyldiethoxysilane (MDES); methyldimethoxysilane (MDMS); octamethoxydodecyloxane (OMODDS); tert-butoxydisilane; tetramethylcyclotetrasiloxane (TMCTS); tetraoxymethylcyclotetrasiloxane (TOMCTS); triethoxysilane (TES); triethoxysiloxane (TRIES); and trimethoxysilane (TMS or TriMOS).

[0054] In certain embodiments, the silicon-containing precursor may include siloxane or siloxane containing amino groups. In certain embodiments, the siloxane used herein may have a chemical formula X(R 1 ) a Si-O-Si(R 2 ) b Y, wherein a and b are integers from 0 to 2, X and Y can independently be H or NR 3 R 4 , where R 1 , R 2 , R 3 , and R 4 Each of X and Y is hydrogen, a linear alkyl group, a branched alkyl group, a saturated heterocyclic group, an unsaturated heterocyclic group, or a combination thereof. In certain embodiments, when at least one of X or Y is NR 3 R 4 When R 3 With R 4Together with the atoms to which each of them is attached, a saturated heterocyclic compound is formed. In certain embodiments, the silicon-containing precursor is a pentamethylated siloxane containing an amino group, or a dimethylated siloxane containing an amino group. Examples of siloxanes containing amino groups include: 1-diethylamino 1,1,3,3,3,-pentamethyldisiloxane, 1-diisopropylamino-1,1,3,3,3,-pentamethyldisiloxane, 1-dipropylamino-1,1,3,3,3,-pentamethyldisiloxane, 1-di-n-butylamino-1,1,3,3,3,-pentamethyldisiloxane, 1-di-sec-butylamino-1,1,3,3,3,-pentamethyldisiloxane, 1-N-methylethylamino 1,1,3,3,3,-pentamethyldisiloxane disiloxane, 1-N-methylpropylamino-1,1,3,3,3,-pentamethyldisiloxane, 1N-methylbutylamino-1,1,3,3,3,-pentamethyldisiloxane, 1-tert-butylamino-1,1,3,3,3,-pentamethyldisiloxane, 1-piperidinyl-1,1,3,3,3,-pentamethyldisiloxane, 1-dimethylamino-1,1-dimethyldisiloxane, 1-diethylamino-1,1-dimethyldisiloxane, 1-diisopropylamino-1,1-dimethyldisiloxane 1-dipropylamino-1,1-dimethyldisiloxane, 1-di-n-butylamino-1,1-dimethyldisiloxane, 1-di-sec-butylamino-1,1-dimethyldisiloxane, 1-N-methylethylamino-1,1-dimethyldisiloxane, 1-N-methylpropylamino-1,1-dimethyldisiloxane, 1-N-methylbutylamino-1,1-dimethyldisiloxane, 1-piperidinyl-1,1-dimethyldisiloxane, 1-tert-butylamino-1,1-dimethyldisiloxane, 1-dimethyl The invention discloses 1-amino-disiloxane, 1-di-n-butylamino-disiloxane, 1-di-sec-butylamino-disiloxane, 1-N-methylethylamino-disiloxane, 1-N-methylpropylamino-disiloxane, 1-N-methylbutylamino-disiloxane, 1-piperidinyl-disiloxane, 1-tert-butylamino-disiloxane, and 1-dimethylamino-1,1,5,5,5-pentamethyldisiloxane.

[0055] In the case where the deposited film contains oxygen, an oxygen-containing reactant may be used. Examples of oxygen-containing reactants include, but are not limited to, oxygen (O 2 ), ozone (O 3 ), nitrous oxide (N 2 O), nitric oxide (NO), nitrogen dioxide (NO 2 ), nitrogen trioxide (N 2 O 3 ), nitrogen tetroxide (N 2 O 4), dinitrogen pentoxide (N 2 O 5 ), carbon monoxide (CO), carbon dioxide (CO 2 ), sulfur oxides (SO), sulfur dioxide (SO 2 ), oxygen-containing hydrocarbons (C x H y O z ), water (H 2 O), formaldehyde (CH 2 O), carbonyl sulfide (COS), and mixtures thereof.

[0056] In the case where the deposited film contains nitrogen, a nitrogen-containing reactant may be used. The nitrogen-containing reactant contains at least one nitrogen, such as nitrogen (N 2 ), ammonia (NH 3 ), hydrazine (N 2 H 4 ), such as methylamine (CH 5 N), dimethylamine ((CH 3 ) 2 NH), ethylamine (C 2 H 5 NH 2 ), isopropylamine (C 3 H 9 N), tert-butylamine (C 4 H 11 N), di(tert-butylamine)(C 8 H 19 N), cyclopropylamine (C 3 H 5 NH 2 ), sec-butylamine (C 4 H 11 N), cyclobutylamine (C 4 H 7 NH 2 ), isopentylamine (C 5 H 13 N), 2-methylbutyl-2-amine (C 5 H 13 N), trimethylamine (C 3 H 9 N), diisopropylamine (C 6 H 15 N), diethylisopropylamine (C 7 H 17 N), di(tert-butyl)hydrazine (C 8 H 20 N 2) and aromatic amines such as aniline, pyridine, and benzylamine. The amines can be primary, secondary, tertiary, or quaternary (e.g., tetraalkylammonium compounds). In addition to nitrogen, the nitrogen-containing reactants can include heteroatoms such as hydroxylamine, tert-butyloxycarbonylamine, and N-tert-butylhydroxylamine are nitrogen-containing reactants. Other examples include nitrous oxide (N 2 O), nitric oxide (NO), nitrogen dioxide (NO 2 ), nitrogen trioxide (N 2 O 3 ), nitrogen tetroxide (N 2 O 4 ) and / or nitrogen pentoxide (N 2 O 5 ) x O y Compound. Device

[0057] Figure 5 Schematically shows an embodiment of a process station 500 that can be used to deposit materials using atomic layer deposition (ALD) and / or chemical vapor deposition (CVD), either of which can be plasma enhanced. For simplicity, the process station 500 is depicted as a stand-alone process station having a process chamber body 502 for maintaining a low pressure environment. However, it should be understood that multiple process stations 500 can be included in a common process tool environment. In addition, it should be understood that in some embodiments, one or more hardware parameters of the process station 500 can be programmatically adjusted by one or more computer controllers 550, including those hardware parameters discussed in detail below.

[0058] The processing station 500 is in fluid communication with a reactant delivery system 501 to deliver the process gas to the distribution showerhead 506. The reactant delivery system 501 includes a mixing container 504 for mixing and / or regulating the process gas for delivery to the showerhead 506. One or more mixing container inlet valves 520 can control the introduction of the process gas into the mixing container 504. Similarly, the showerhead inlet valve 505 can control the introduction of the process gas into the showerhead 506. In some embodiments, the inhibitor or other gas can be delivered directly to the chamber body 502. One or more mixing container inlet valves 520 can control the introduction of the process gas into the mixing container 504. These valves can be controlled depending on whether the process gas, the suppression gas, or the carrier gas can be activated during a number of operations. In some embodiments, the suppression gas can be generated by using a suppression liquid and vaporization using a heated vaporizer.

[0059] For example, Figure 5Embodiments include a vaporization point 503, which is used to vaporize liquid reactants to be supplied to the mixing container 504. In some embodiments, the vaporization point 503 can be a heated vaporizer. The reactant vapor produced from such a vaporizer will condense in the downstream delivery pipeline. Incompatible gases exposed to condensed reactants will produce small particles. These small particles may block pipelines, hinder valve operation, contaminate substrates, etc. Some methods for dealing with these problems involve cleaning and / or evacuating the delivery pipeline to remove residual reactants. However, cleaning the delivery pipeline will increase the processing station cycle time and reduce the processing station throughput. Therefore, in some embodiments, the delivery pipeline downstream of the vaporization point 503 can be heat traced. In some examples, the mixing container 504 can also be heat traced. In a non-limiting example, the pipeline downstream of the vaporization point 503 has a temperature distribution of an increase from about 100°C to about 150°C at the mixing container 504.

[0060] In some embodiments, the reactant liquid can be vaporized at the liquid injector. For example, the liquid injector can inject a pulse of the liquid reactant into the carrier gas flow upstream of the mixing vessel. In one case, the liquid injector can vaporize the reactant by flashing the liquid from a higher pressure to a lower pressure. In another case, the liquid injector can atomize the liquid into dispersed droplets that are then vaporized in a heated delivery pipe. It should be understood that smaller droplets can vaporize faster than larger droplets, thereby reducing the delay between liquid injection and completion of vaporization. Faster vaporization can reduce the length of the pipeline downstream of the vaporization point 503. In one case, the liquid injector can be directly loaded into the mixing vessel 504. In another case, the liquid injector can be directly loaded into the spray head 506.

[0061] In some embodiments, a liquid flow controller (LFC) can be set upstream of the vaporization point 503 to control the mass flow rate of the liquid for vaporization and delivery to the processing station 500. For example, the liquid flow controller can include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC can then be adjusted in response to a feedback control signal provided by a proportional integral differential (PID) controller that is electrically communicated with the MFM. However, it can take one second or longer to use feedback control to stabilize the liquid flow. This can extend the time of dosing liquid reactants. Therefore, in some embodiments, the LFC can be dynamically switched between a feedback control mode and a direct control mode. In some embodiments, the LFC can be dynamically switched from a feedback control mode to a direct control mode by disabling the sensing pipeline and PID controller of the LFC.

[0062] Showerhead 506 distributes processing gas toward substrate 512. Figure 5In the illustrated embodiment, substrate 512 is positioned below showerhead 506 and is shown resting on pedestal 508. It will be appreciated that showerhead 506 may have any suitable shape and may have any suitable number and arrangement of ports to distribute process gases to substrate 512.

[0063] In some embodiments, microvolume 507 is located below showerhead 506. Performing ALD and / or CVD processing in a microvolume rather than in the entire volume of the processing station can reduce reactant exposure and sweep time, can reduce the time to change processing conditions (e.g., pressure, temperature, etc.), can limit the exposure of the processing station robot to the processing gas, etc. Exemplary microvolume sizes include, but are not limited to, volumes between 0.1 liters and 2 liters. This microvolume also affects productivity throughput. When the deposition rate per cycle decreases, the cycle time is also reduced. In some cases, for a given target film thickness, the effect of the cycle time reduction is significant enough to increase the overall yield of the module.

[0064] In some embodiments, the pedestal 508 can be raised or lowered to expose the substrate 512 to the microvolume 507 and / or to change the volume of the microvolume 507. For example, during a substrate transfer phase, the pedestal 508 can be lowered so that the substrate 512 can be loaded on the pedestal 508. During a deposition process phase, the pedestal 508 can be raised to position the substrate 512 within the microvolume 507. In some embodiments, the microvolume 507 can completely surround the substrate 512 and a portion of the pedestal 508 to form an area of ​​high flow impedance during the deposition process.

[0065] Optionally, the pedestal 508 can be lowered and / or raised during portions of the deposition process to adjust the process pressure, reactant concentration, etc. within the microvolume 507. In one case where the process chamber body 502 is maintained at a base pressure during the deposition process, lowering the pedestal 508 can allow the microvolume 507 to be evacuated. Exemplary ratios of microvolume to process chamber volume include, but are not limited to, volume ratios between 1:500 and 1:10. It should be understood that in some embodiments, the pedestal height can be programmatically adjusted by a suitable computer controller.

[0066] In another case, adjusting the height of pedestal 508 can allow for changing plasma density during plasma startup and / or processing cycles included in a deposition process. At the end of a deposition process phase, pedestal 508 can be lowered during another substrate transfer phase to enable removal of substrate 512 from pedestal 508.

[0067] Although the exemplary microvolume variations described herein relate to a height-adjustable pedestal, it should be understood that in some embodiments, the position of the showerhead 506 can be adjusted relative to the pedestal 508 to change the volume of the microvolume 507. In addition, it should be understood that the vertical position of the pedestal 508 and / or showerhead 506 can be changed by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 508 may include a rotation axis for rotating the orientation of the substrate 512. It should be understood that in some embodiments, one or more of these exemplary adjustments can be performed programmatically by one or more appropriate computer controllers.

[0068] Back to Figure 5 In the embodiment shown, the showerhead 506 and the base 508 are in electrical communication with the RF power source 514 and the matching network 516 for powering the plasma. In some embodiments, the energy of the plasma can be controlled by controlling one or more of the pressure of the processing station, the concentration of the gas, the RF source power, the RF source frequency, and the plasma power pulse timing. For example, the RF power source 514 and the matching network 516 can be operated at any suitable power to form a plasma with a component of a desired free radical substance. The embodiment of suitable power is included above. Similarly, the RF power source 514 can provide RF power of any appropriate frequency. In some embodiments, the RF power source 514 can be configured to control a high-frequency RF power source and a low-frequency RF power source that are independent of each other. Exemplary low-frequency RF frequencies may include, but are not limited to, frequencies between 50kHz and 500kHz. Exemplary high-frequency RF frequencies may include, but are not limited to, frequencies between 1.8MHz and 2.45GHz. It should be understood that any suitable parameter can be adjusted discretely or continuously to provide plasma energy for surface reactions. In one non-limiting example, the plasma power may be intermittently pulsed to reduce ion bombardment of the substrate surface relative to a continuously powered plasma.

[0069] In some embodiments, the plasma can be monitored in situ by one or more plasma monitors. In one case, the plasma power can be monitored by one or more voltage and current sensors (e.g., VI probes). In another case, the plasma density and / or the concentration of the process gas can be measured by one or more optical emission spectrometer sensors (OES). In some embodiments, one or more plasma parameters can be adjusted programmatically based on the measurement results from such an in-situ plasma monitor. For example, an OES sensor can be used in a feedback loop to provide programmatic control of the plasma power. It should be understood that in some embodiments, other monitors can be used to monitor plasma and other processing characteristics. Such monitors may include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure sensors.

[0070] In some embodiments, plasma can be controlled via input / output control (IOC) sequencing instructions. In one example, instructions for setting the plasma conditions of the plasma treatment stage may be included in the corresponding plasma activation recipe stage of the deposition process recipe. In some cases, the process recipe stages may be arranged in sequence so that all instructions for the deposition process stage are executed simultaneously with the process stage. In some embodiments, instructions for setting one or more plasma parameters may be included in the recipe stage before the plasma treatment stage. For example, the first recipe stage may include instructions for setting the flow rate of an inert gas and / or a reactant gas, instructions for setting a plasma generator to a power set point, and time delay instructions for the first recipe stage. The subsequent second recipe stage may include instructions for enabling a plasma generator and time delay instructions for a second recipe stage. The third recipe stage may include instructions for disabling a plasma generator and time delay instructions for a third recipe stage. It should be understood that these recipe stages may be further subdivided and / or iterated in any suitable manner within the scope of the present disclosure.

[0071] In some deposition processes, the plasma excitation duration is several seconds or longer. In some implementations, shorter plasma excitations may be used. These may be about 10 ms to 1 second, typically about 20 to 80 ms, with 50 ms being a specific example. Such very short RF plasma excitations require very fast stabilization of the plasma. To achieve this, the plasma generator may be configured so that the impedance match is set to a preset specific voltage while the frequency is allowed to float. Typically, a high frequency plasma is generated at an RF frequency of about 13.56 MHz. In various embodiments disclosed herein, the frequency is allowed to float to values ​​different from this standard value. By allowing the frequency to float while fixing the impedance match to a predetermined voltage, the plasma may stabilize more quickly, which may be important when using very short plasma excitations associated with certain types of deposition cycles.

[0072] In some embodiments, the susceptor 508 can be temperature controlled by a heater 510. Additionally, in some embodiments, pressure control of the deposition processing station 500 can be provided by a butterfly valve 518. Figure 5 In the embodiment shown in FIG. 5 , butterfly valve 518 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, the pressure control of the process station 500 can also be adjusted by changing the flow rate of one or more gases introduced into the process station 500.

[0073] Figure 6 600 is a block diagram of a processing system suitable for performing thin film deposition processing according to certain embodiments. System 600 includes a transfer module 603. The transfer module 603 provides a clean, pressurized environment to minimize the risk of contamination of the processed substrate when it moves between the various reactor modules. According to certain embodiments, mounted on the transfer module 603 are two multi-station reactors 609 and 610, each reactor capable of performing atomic layer deposition (ALD) and / or chemical vapor deposition (CVD). Reactors 609 and 610 may include multiple stations 611, 613, 615, and 617, which may perform operations sequentially or non-sequentially according to the disclosed embodiments. These stations may include a heated pedestal or substrate support, one or more gas inlets or nozzles, or a dispersion plate.

[0074] Mounted on the transfer module 603 may also be one or more single-station or multi-station modules 607 capable of performing plasma or chemical (non-plasma) pre-cleaning, or any other processing associated with the disclosed method. In some cases, the module 607 may be used for various processing, such as preparing a substrate for a deposition process. The module 607 may also be designed / configured to perform various other processing, such as etching or polishing. The system 600 also includes one or more wafer source modules 601, in which wafers are stored before and after processing. An atmospheric manipulator (not shown) in the atmospheric transfer chamber 619 may first move the wafer from the source module 601 to the load lock 621. The wafer transfer device (typically a robot arm unit) in the transfer module 603 moves the wafer from the load lock 621 to the module mounted on the transfer module 603 and moves the wafer from the load lock 621 between the modules mounted on the transfer module 603.

[0075] In various embodiments, the system controller 629 is used to control the processing conditions during the deposition process. The controller 629 will generally include one or more memory devices and one or more processors. The processor may include a CPU or calculator, analog and / or digital input / output connections, a stepper motor controller board, etc. The one or more memories may include computer executable code that can be executed by the one or more processors.

[0076] The controller 629 can control all of the activities of the deposition apparatus. The system controller 629 executes system control software, which includes a set of instructions for controlling timing, mixtures of gases, chamber pressure, room temperature, wafer temperature, radio frequency (RF) power levels, wafer chuck or pedestal position, and other parameters of a particular process. Other computer programs stored in a memory device associated with the controller 629 may be employed in some embodiments.

[0077] There will typically be a user interface associated with the controller 629. The user interface may include a display screen, a graphical software display of the device and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, and the like.

[0078] The system control logic can be configured in any suitable manner. In general, the logic can be designed or configured in hardware and / or software. The instructions for controlling the drive circuit can be hard-coded or provided as software. The instructions can be provided by "programming". Such programming is understood to include any form of logic, including hard-coded logic in digital signal processors, application-specific integrated circuits, and other devices with specific algorithms implemented as hardware. Programming is also understood to include software or firmware instructions that can be executed on a general-purpose processor. The system control software can be encoded in any suitable computer-readable programming language.

[0079] The computer program code for controlling the flow of inhibitors, hydrogen, oxygen and silicon-containing precursors, and other processes in the process sequence can be written in any commonly used computer-readable programming language: for example, assembly language, C, C++, Pascal, Fortran or others. The compiled object code or script is executed by the processor to perform the tasks identified in the program. Also as indicated, the program code can be hard-coded.

[0080] Controller parameters relate to process conditions such as, for example, process gas composition and flow rate, temperature, pressure, cooling gas pressure, substrate temperature, and chamber wall temperature. These parameters are provided to the user in the form of recipes and can be input using a user interface. Signals for monitoring the process can be provided via analog and / or digital input connections of the system controller 629. Signals for controlling the process are output via analog and digital output connections of the deposition apparatus 600.

[0081] The system software may be designed or configured in many different ways. For example, various chamber component subroutines or control objects may be written to control the operation of chamber components necessary to perform deposition processes (and in some cases other processes) in accordance with the disclosed embodiments. Examples of programs or program segments for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code.

[0082] In some implementations, a controller (e.g., controller 550 or 629) is part of a system, which can be part of the above-described embodiments. Such a system can include a semiconductor processing device that includes one or more processing tools, one or more processing chambers, one or more platforms for processing, and / or specific processing components (wafer bases, gas flow systems, etc.). These systems can be integrated with electronic devices for controlling their operations before, during, and after processing semiconductor wafers or substrates. The electronic device can be referred to as a "controller", which can control various components or subcomponents of one or more systems. Depending on the processing requirements and / or the type of system, the controller 629 can be programmed to control any of the processes disclosed herein, including controlling process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools and / or load locks connected to or connected to a specific system through an interface.

[0083] Broadly speaking, a controller can be defined as an electronic device with various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits can include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), and other components. S ASIC S ) chip and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions transmitted to the controller in the form of various individual settings (or program files) that define operating parameters for performing specific processes on or for a semiconductor wafer or system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer for completing one or more processing steps during the preparation of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0084] In some implementations, the controller may be part of or coupled to a computer that is integrated with, coupled to, or connected to the system or a combination thereof via a network. For example, the controller may be in the "cloud" or all or part of a wafer fab host system, thereby allowing remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, check the history of past manufacturing operations, check trends or performance criteria for multiple manufacturing operations, change parameters of a current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide a processing recipe to the system via a network, which may include a local network or the Internet. The remote computer may include a user interface that allows input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be for the type of process to be performed and the type of tool to which the controller is configured to connect or control the tool type. Thus, as described above, the controller may be distributed, for example, by including one or more discrete controllers that are networked together and work toward a common goal (e.g., the processing and control described herein). An embodiment of a distributed controller for these purposes may be one or more integrated circuits on the chamber that communicate with one or more remote integrated circuits (e.g., at a platform level or as part of a remote computer) that are combined to control the processing within the chamber.

[0085] Example systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin sweep chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the preparation and / or manufacture of semiconductor wafers.

[0086] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more of the following: other tool circuits or modules, other tool components, combination tools, other tool interfaces, adjacent tools, adjacent tools, tools located throughout the factory, a host computer, another controller, or tools used in material handling to move containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0087] It should be understood that multiple processing stations may be included in a multi-station processing tool environment, such as Figure 7 , which depicts a schematic diagram of an embodiment of a multi-station processing tool. Processing apparatus 700 uses an integrated circuit fabrication chamber 763 that includes a plurality of fabrication processing stations, each of which can be used to perform processing operations on a substrate supported in a substrate support such as a platform at a particular processing station. Figure 7 In the embodiment of the present invention, the integrated circuit fabrication chamber 763 is shown having four processing stations 751, 752, 753 and 754. Other similar multi-station processing apparatuses may have more or fewer processing stations depending on the implementation and, for example, the desired degree of parallel wafer processing, size / space constraints, cost constraints, etc. Figure 7 Also visible is a substrate handling robot 775, which can be operated under the control of the system controller 790 to transfer substrates from a wafer box ( Figure 7 Multiple substrates (not shown) are moved from the loading port 780 into the integrated circuit manufacturing chamber 763 and moved to one of the processing stations 751, 752, 753 and 754.

[0088] Figure 7 Also shown is one implementation of a system controller 790 for handling processing conditions and hardware states of the apparatus 700. As described herein, the system controller 790 may include one or more memory devices, one or more mass storage devices, and one or more processors.

[0089] RF subsystem 795 can generate RF power and transmit the RF power to integrated circuit manufacturing chamber 763 through RF input port 767. In a specific embodiment, integrated circuit manufacturing chamber 763 can include input ports in addition to RF input port 767 (additional input ports are not shown). Figure 7 ). Thus, eight RF input ports may be used by the integrated circuit fabrication chamber 763. In a particular embodiment, each of the processing stations 751-754 in the integrated circuit fabrication chamber 763 may use a first and a second input port, wherein the first input port may transmit a signal having a first frequency and the second input port may transmit a signal having a second frequency. Using dual frequencies may provide enhanced plasma characteristics.

[0090] As described above, one or more processing stations may be included in a multi-station processing tool. Figure 8 A schematic diagram of an embodiment of a multi-station processing tool 800 with an inbound loading lock 802 and an outbound loading lock 804 is shown, any one or both of which may include a remote plasma source. A robot 806 at atmospheric pressure is configured to move a substrate or wafer from a box loaded by a pod 808 to the inbound loading lock 802 via an atmospheric port. In the inbound loading lock 802, the robot 806 places the substrate on a pedestal 812, the atmospheric port is closed, and the loading lock is evacuated. In the case where the inbound loading lock 802 includes a remote plasma source, the substrate may be exposed to a remote plasma treatment in the loading lock before being introduced into the processing chamber 814. In addition, the substrate may also be heated in the inbound loading lock 802, such as for removing moisture and adsorbed gases. Next, a chamber delivery port 816 leading to the processing chamber 814 is opened, and another robot 890 places the substrate in the reactor on the pedestal of the first station shown in the reactor for processing. 9 includes a load lock, it should be understood that in some embodiments, the substrate may be made to enter the processing station directly. In various embodiments, when the substrate is placed on the pedestal 812 by the robot 806, the soak gas is introduced to the station.

[0091] The depicted processing chamber 814 includes four processing stations, Figure 8The stations are numbered 1 to 4 in the illustrated embodiment. Each station has a heated pedestal (shown as 818 for station 1) and a gas line inlet. It should be understood that in some embodiments, each processing station can be used for different or multiple purposes. For example, in some embodiments, the processing station can switch between suppression plasma, passivation plasma, ALD and / or PEALD processing modes. Additionally or alternatively, in some embodiments, the processing chamber 814 may include one or more matched pairs of ALD and plasma-enhanced ALD processing stations. Although the depicted processing chamber 814 includes four stations, it should be understood that a processing chamber according to the present invention may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, while in other embodiments, the processing chamber may have three or fewer stations.

[0092] Figure 8 An embodiment of a wafer handling system 890 for transferring substrates within a processing chamber 814 is depicted. In some embodiments, the wafer handling system 890 can transfer substrates between various processing stations and / or between a processing station and a load lock. It should be understood that any suitable wafer handling system can be employed. Non-limiting examples include wafer conveyors and wafer handling robots. Figure 8 Also depicted is an embodiment of a system controller 850 for controlling processing conditions and hardware states of the processing tool 800. The system controller 850 may include one or more memory devices 856, one or more mass storage devices 854, and one or more processors 852. The processor 852 may include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, etc. In some embodiments, the system controller 850 includes machine-readable instructions for performing operations such as those described herein.

[0093] In some embodiments, the system controller 850 controls the activities of the processing tool 800. The system controller 850 executes system control software 858 stored in the mass storage device 854, loaded into the storage device 856 and executed on the processor 852. Alternatively, the control logic can be hard-coded in the system controller 850. Application-specific integrated circuits, programmable logic devices (such as field programmable gate arrays or FPGAs), etc. can be used for these purposes. In the following discussion, wherever "software" or "coding" is used, functionally comparable hard-coded logic can be used therein. The system control software 858 can include other parameters for controlling timing, gas mixtures, gas flow rates, chamber and / or station pressures, chamber and / or station temperatures, substrate temperatures, target power levels, RF power levels, substrate pedestals, chucks and / or sensor positions, and specific processes performed by the processing tool 800. The system control software 858 can be configured in any suitable manner. For example, various processing tool component subroutines or control objects can be written to control the operation of the processing tool components used to perform various processing tool processes. System control software 858 may be coded in any suitable computer readable programming language. in conclusion

[0094] Although the foregoing embodiments have been described in some detail for the purpose of clear understanding, it is apparent that certain changes and modifications may be practiced within the scope of the appended claims. The embodiments disclosed herein may be practiced without some or all of these specific details. In other cases, well-known processing operations are not described in detail so as not to unnecessarily obscure the disclosed embodiments. In addition, although the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that the specific embodiments are not intended to limit the disclosed embodiments. It should be noted that there are many alternative ways to implement the processing, systems, and devices of the presented embodiments. Therefore, the presented embodiments are considered to be illustrative rather than restrictive, and the embodiments are not limited to the details given herein.

Claims

1. A method comprising: providing a substrate in a processing chamber, the substrate having one or more structures, each structure comprising a gap; Perform the first set of loops of the following steps: (a) exposing the substrate to an inhibition plasma to inhibit deposition on a portion of each gap, wherein the inhibition plasma comprises a fluorine-containing species, and (b) after (a), depositing a dielectric material in each gap, and After performing the first set of cycles, exposing the substrate to a passivating plasma to reduce the fluorine concentration in the dielectric material, in, After exposing the substrate to the passivating plasma, the fluorine concentration is less than about 10 20 Atom / cm 3 .

2. The method according to claim 1, in, The fluorine concentration in the dielectric material is measured from a bulk portion of the dielectric material.

3. The method according to claim 1, in, The fluorine concentration in the dielectric material is an average concentration at a depth of at least 5 nm from a surface of the substrate.

4. The method according to claim 1, in, After exposing the substrate to the passivating plasma, the fluorine concentration is less than about 10 19 Atom / cm 3 .

5. The method according to claim 1, in, The duration of the passivating plasma is at least about 80 seconds.

6. The method according to claim 1, in, The passivation plasma has a high frequency (HF) power of at least about 5000W.

7. The method according to claim 1, in, The passivation plasma has a low frequency (LF) power between about 0W and about 2000W.

8. The method according to any one of claims 1 to 7, in, The dielectric material has a The wet etching rate.

9. The method according to any one of claims 1 to 7, in, The suppression plasma includes a nitrogen-containing species.

10. The method according to claim 9, in, The passivation plasma reduces the nitrogen concentration in the dielectric material.

11. The method according to any one of claims 1 to 7, in, The dielectric material includes a silicon-containing material.

12. The method according to claim 11, in, The silicon-containing material includes silicon oxide.

13. The method according to any one of claims 1 to 7, in, The passivating plasma includes oxygen-containing species.

14. The method according to any one of claims 1 to 7, in, The passivation plasma includes hydrogen-containing species.

15. The method according to any one of claims 1 to 7, in, The passivation plasma includes oxygen-containing species and hydrogen-containing species.

16. A system comprising: Processing chamber; and One or more processors and one or more memories containing computer executable instructions for: providing a substrate in the process chamber, the substrate having one or more structures, each structure comprising a gap; Perform the first set of loops of the following steps: (a) exposing the substrate to an inhibition plasma to inhibit deposition on a portion of each gap, wherein the inhibition plasma comprises a fluorine-containing species, and (b) after (a), depositing a dielectric material in each gap, and After performing the first set of cycles, exposing the substrate to a passivating plasma, in, The duration of the passivation plasma is at least about 80 seconds, and the high frequency (HF) power of the passivation plasma is at least about 5000W.

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