Request merging method, unit and chip
Patent Information
- Application Number
- CN202380011287.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-19
- Publication Date
- 2025-06-06
AI Technical Summary
In the prior art, when merging requests in memory access instructions, a large number of comparators are required, resulting in a large chip area occupancy.
A request merging unit is designed to determine the target request from the multiple requests to be merged through a multiple selector, and to compare the target request with multiple requests using a group of comparator until all requests are compared, only a comparator with the same number as the request is required.
It effectively reduces the number of use of comparators, reduces the chip area occupied by the request merging unit, and improves the efficiency of request merging.
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Figure CN120112892A_ABST
Abstract
Description
Request for merging methods, units and chips Technical Field
[0001] The present application relates to the field of chip design, and in particular, to a request merging method, unit, and chip. Background Art
[0002] A memory access instruction can include 32 requests. Each request can access a different address in the memory. Different requests may also access the same memory address. Therefore, after receiving the memory access instruction, repeated requests to access the same memory address can be merged to obtain a merged memory access instruction.
[0003] Currently, when merging requests within a memory access instruction, a comparator is used to compare one request with another to determine whether the two access addresses are the same. A memory access instruction can include up to 32 requests. If a comparator is set between any two requests, merging a memory access instruction requires more comparators, resulting in a larger chip area occupied by the comparator circuits.
[0004] Summary of the Invention
[0005] In view of this, the present application aims to provide a request merging method, unit and chip to reduce the chip area occupied by the circuit for merging memory access instructions.
[0006] In a first aspect, an embodiment of the present application provides a request merging unit, comprising: a multiplexer, configured to determine a target request from a plurality of requests to be merged, the target request being a request selected from the plurality of requests according to preset conditions; a comparator group, connected to the multiplexer, the comparator group configured to compare the target request with the plurality of requests respectively, and determine a repeated request in the plurality of requests that is repeated with the target request; a first logic circuit, connected to the multiplexer, the first logic circuit being used to output the remaining requests in the plurality of requests except the repeated request and the target request to the multiplexer, so as to repeat the comparison process until all the plurality of requests are compared; the multiplexer is further configured to output the target request outside the request merging unit.
[0007] In an embodiment of the present application, a target request can be determined from a plurality of requests to be merged by a multiplexer, and after the comparator group can compare the target request with the plurality of requests to be merged respectively, the first logic circuit outputs the remaining requests other than the repeated request to the multiplexer, and redetermines the target request and repeats the comparison process until the comparison of the plurality of requests to be merged is completed. Compared with using a comparator for comparison between any two requests, an embodiment of the present application only needs to set a comparator to compare the target request with the plurality of requests to be merged, and only needs to use the number of comparators corresponding to the number of requests in the plurality of requests to be merged, which is much less than the number of comparators set between any two requests. Therefore, the above-mentioned request merging unit can effectively reduce the number of comparators used and reduce the chip area occupied by the request merging unit.
[0008] In one embodiment, each of the requests includes a request identification value, and the request identification value includes a valid value and an invalid value, the valid value indicates that the request corresponding to the request identification value is valid, and the invalid value indicates that the request corresponding to the request identification value is invalid; the request merging unit also includes: a second logic circuit, including a third logic input terminal and a second logic output terminal, the third logic input terminal is used to input the request identification values corresponding to the multiple requests; the second logic output terminal is connected to the selection control terminal of the multiplexer, and the selection control terminal is used to configure the preset condition; the second logic circuit is used to determine a target request identification value from the multiple request identification values corresponding to the multiple requests; the target request identification value is a valid value; the request corresponding to the target request identification value is the target request.
[0009] In an embodiment of the present application, the request identification value of the request can be input into the second logic circuit, and the target request identification value output by the second logic circuit is used as the condition for the multiplexer to determine the target request. Compared with setting a complete request as a preset condition, the request identification value is smaller, which can effectively reduce the amount of data required to process to determine the target request, thereby improving the efficiency of determining the target request and providing request merging efficiency.
[0010] In one embodiment, the request merging unit further includes a processor, which is connected to the selection input terminal and the selection output terminal of the multiplexer, and the processor is also connected to the third logic input terminal; the processor is configured to: extract the request identification value corresponding to each request in the multiple requests; combine all the request identification values into a request identification vector to determine the target request identification value from the request identification vector.
[0011] In an embodiment of the present application, the processor can combine request identification values into a request identification vector, so that the request identification vector includes request identification values of multiple requests. Therefore, when determining the target request identification vector from the request identification vector, multiple request identification values can be determined. Compared with determining different request identification values one by one, the efficiency of determining the valid identification value can be effectively improved, thereby improving the efficiency of determining the target request and improving the efficiency of request merging.
[0012] In one embodiment, the processor is further configured to: make the arrangement order of the request identification values corresponding to the requests in the request identification vector the same as the arrangement order of the requests in the multiple requests.
[0013] In this embodiment, the processor arranges the order of each request identification value in the request identification vector in the same way as the order of each request in multiple requests. Thus, the corresponding request can be determined from multiple requests based on the order of the request identification values in the request identification vector, thereby improving the efficiency of determining the target request and improving the efficiency of merging multiple requests.
[0014] In one embodiment, the first logic circuit is further configured to modify the request identification values of the repeated request and the target request to invalid values.
[0015] In this embodiment, the first logic circuit modifies the request identification values of the repeated request and the target request to invalid values. As a result, the repeated request and the target request will no longer be selected as new target requests for subsequent comparison, reducing the possibility of the same request or repeated request being repeatedly selected as the target request for comparison, so as to improve the accuracy and efficiency of determining the target request, thereby improving the efficiency of request merging.
[0016] In one embodiment, the request merging unit further includes: a two-to-one selector, the two-to-one selector including a second selection input terminal, a third selection input terminal and a second selection output terminal; the second selection input terminal is connected to the first logic output terminal of the first logic circuit; the third selection input terminal is used to input the request identification value corresponding to each request in the multiple requests to be merged; the second selection output terminal is connected to the third logic input terminal; the two-to-one selector is configured to output the input signal of the second selection input terminal when both the second selection input terminal and the third selection input terminal have inputs.
[0017] In this embodiment, the two-to-one selector is configured to output the input signal of the second selection input terminal when both the second selection input terminal and the third selection input terminal have inputs. The second selection input terminal is connected to the first logic output terminal, and the first logic terminal outputs the remaining requests excluding duplicate requests and target requests. Therefore, the two-to-one selector preferentially outputs requests that have not been compared, thereby reducing the possibility of repeated comparison of requests and improving the efficiency of request merging.
[0018] In a second aspect, an embodiment of the present application provides a chip, comprising a request merging unit as described in any one of the first aspects.
[0019] In a third aspect, an embodiment of the present application provides an electronic device comprising the chip as described in the second aspect.
[0020] In a fourth aspect, an embodiment of the present application provides a request merging method, comprising: determining a target request from a plurality of requests to be merged, the target request being a request selected from the plurality of requests according to preset conditions; comparing the target request with the plurality of requests based on a preset comparator group, and determining a repeated request that is repeated with the target request in the plurality of requests; the repeated request includes the target request; repeating the above-mentioned comparison process based on the remaining requests in the plurality of requests except the repeated request, until all the plurality of requests are compared; and outputting the target request.
[0021] In an embodiment of the present application, by selecting one request as a target request from multiple requests to be merged, and after comparing the target request with the remaining requests in the multiple requests, the target request is re-determined until all requests are compared. Therefore, it is only necessary to set a comparator when comparing the target request with multiple requests, so that the number of comparators can be the same as the number of requests in the multiple requests, and there is no need to set a comparator between any two requests, which effectively reduces the number of comparators and reduces the chip area occupied by the comparators.
[0022] In one embodiment, each of the requests includes a request identification value, and the request identification value includes a valid value and an invalid value, the valid value indicates that the request corresponding to the request identification value is valid, and the invalid value indicates that the request corresponding to the request identification value is invalid; the selecting of the target request from the multiple requests to be merged includes: determining a target request identification value from the multiple request identification values; the target request identification value is a valid value; and determining the request corresponding to the target request identification value as the target request.
[0023] In an embodiment of the present application, the request identification value has a smaller data volume than a complete request. Therefore, using the request identification value to determine the target request can reduce the amount of data processing when determining the target request, increase the speed of determining the target request, and thus improve the efficiency of request merging.
[0024] In one embodiment, before determining the target request identification value from the multiple request identification values, the method also includes: extracting the request identification value corresponding to each request in the multiple requests; combining all the request identification values into a request identification vector to determine the target request identification value from the request identification vector.
[0025] In an embodiment of the present application, request identification values are combined into a request identification vector, so that the request identification vector includes request identification values of multiple requests. Therefore, when determining the target request identification vector from the request identification vector, multiple request identification values can be determined. Compared with determining different request identification values one by one, the efficiency of determining the valid identification value can be effectively improved, thereby improving the efficiency of determining the target request and improving the efficiency of request merging.
[0026] In one embodiment, in the request identification vector, the arrangement order of the request identification values corresponding to the requests is the same as the arrangement order of the requests in the multiple requests.
[0027] In this embodiment, the arrangement order of each request identification value in the request identification vector is made the same as the arrangement order of each request in multiple requests. Thus, the corresponding request can be determined from multiple requests according to the order of the request identification values in the request identification vector, thereby improving the efficiency of determining the target request and improving the efficiency of merging multiple requests.
[0028] In one embodiment, after determining the duplicate request that is duplicate of the target request among the multiple requests, the method further includes: modifying the request identification values of the duplicate request and the target request to invalid values.
[0029] In this embodiment, the request identification values of the repeated request and the target request are modified to invalid values. As a result, the repeated request and the target request will no longer be selected as new target requests for subsequent comparison, reducing the possibility of the same request or repeated request being repeatedly selected as the target request for comparison, so as to improve the accuracy and efficiency of determining the target request, thereby improving the efficiency of request merging.
[0030] In one embodiment, the request includes a request address, and determining the duplicate request that is repeated with the target request among the multiple requests includes: inputting the request address of the target request and the request addresses of the multiple requests into the comparator group respectively, so that the comparator group compares the request address of the target request with the request addresses of the multiple requests to be merged; obtaining the output result of the comparator group, the output result indicating whether the request address of the target request is the same as the request address of the multiple requests to be merged; and determining the duplicate request based on the output result.
[0031] The main difference between different requests is the request address. Therefore, in this embodiment, the request address can be used to determine whether a request is a duplicate request. Request addresses are easier to process than complete requests. Therefore, comparing request addresses can improve the efficiency of determining duplicate requests, thereby improving the efficiency of request merging. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.
[0033] FIG1 is a schematic diagram of the structure of a request merging unit provided in one embodiment of the present application;
[0034] FIG2 is a schematic diagram of the structure of a request merging unit provided in another embodiment of the present application;
[0035] FIG3 is a flowchart of a request merging method provided in an embodiment of the present application.
[0036] Icons: multiplexer 110 ; comparator group 120 ; first logic circuit 130 ; second logic circuit 140 ; one-of-two selector 150 . DETAILED DESCRIPTION
[0037] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.
[0038] To facilitate understanding of the present application, memory instructions are first described before describing the embodiments of the present application.
[0039] When data is exchanged between different modules or electronic devices, requests are issued. Multiple requests may be issued at the same time, and different requests may be the same or different. For example, when some modules need to access the memory, memory access instructions are issued. The memory access instructions include multiple requests. Different requests may access the same address in the memory space. Therefore, requests for access to the same address can be merged to reduce the number of requests in the memory access instructions. Exemplarily, some memory access instructions may be shader groups. Shader groups include 32 thread requests. Each thread request includes an access address to the memory space. Different thread requests in the same shader group may include the same access address. Therefore, multiple thread requests with the same access address can be merged into a cache line. A shader group including 32 threads can be merged into a memory access instruction of less than 32 cache lines.
[0040] When merging memory access instructions, comparators can be used to compare the requests in the memory access instructions to identify requests with the same access address, and logic gate circuits can be used to merge the requests with the same access address. Some memory access instructions include more memory instructions. For example, a shader group includes 32 thread requests. If a comparator is set between any two thread requests, more comparators will need to be set. For example, if the 32 threads include thread0 to thread31, thread0 will need to be compared with thread1 to thread31, requiring 31 comparators. Then, thread1 will need to be compared with thread2 to thread31, requiring 30 comparators, and so on, requiring hundreds of comparators in total. Excessive comparators will occupy a large chip area.
[0041] The present application aims to provide a request merging unit and method, which selects a request from multiple requests by setting a multiplexer, and uses a comparator group to compare the request with the remaining requests in the multiple requests to determine the same request. Therefore, it is only necessary to set the same number of comparators as the number of requests for memory access instructions after the multiplexer. Compared with the circuit composed of hundreds of comparators, the number of comparators required by this application is relatively small, and the chip area occupied by the comparators and the multiplexer is much smaller than that of hundreds of comparators, thereby reducing the chip area occupied by the request merging unit.
[0042] Please refer to FIG1 , which is a schematic diagram of a request merging unit according to an embodiment of the present application. The request merging unit includes a multiplexer 110 , a comparator group 120 , and a first logic circuit 130 .
[0043] The multiplexer 110 includes a selection control terminal, a selection output terminal, and a selection input terminal.
[0044] In this embodiment, the selection input terminal can be used to input multiple requests to be merged. In some embodiments, the multiplexer 110 may include multiple selection input terminals, with different selection input terminals being used to input different requests. In other embodiments, the multiplexer 110 may include only one selection input terminal, with different requests being input to the selection input terminal in sequence. The above description is merely illustrative and does not limit the present application.
[0045] The difference between different requests usually lies in the different request addresses. For example, the main difference between different requests in memory access instructions lies in the different access addresses to the memory space. Therefore, in some embodiments, the selection input end can input the request addresses corresponding to different requests. Compared with the complete request, the data volume of the request address is smaller. Therefore, the workload when comparing multiple requests can be reduced and the efficiency of merging multiple requests can be improved.
[0046] The selection control terminal is used to configure output conditions. In this embodiment, the selection control terminal can be configured with preset conditions for determining a target request from multiple requests.
[0047] Since the embodiment of the present application determines whether the same request exists among multiple requests, each request must be compared. Therefore, the preset condition can be to determine any one of the remaining requests that is not determined as a duplicate request from the multiple requests as the target request. The selection input terminal can input a condition representing a duplicate request among the multiple requests, so that the multiplexer 110 selects the target request from the remaining requests excluding the duplicate request.
[0048] The selection output terminal is used to output the selection results of multiple requests.
[0049] In this embodiment, the multiplexer 110 is used to select a target request, and the selection output end outputs the selection result as the target request.
[0050] In this embodiment, a corresponding multiplexer 110 may be used based on the number of requests in the multiple requests. For example, when the multiple requests to be merged include 8 requests, an 8-to-1 selector may be selected, and when the multiple requests to be merged include 32 requests, a 32-to-1 selector may be selected. In some embodiments, the multiplexer 110 may also be a combination of multiple selectors. For example, the 32-to-1 selector may include two 16-to-1 selectors and one 2-to-1 selector.
[0051] The principle and structure of the multiplexer 110 can be referred to the prior art and will not be described in detail here. The above is only an example and is not intended to limit the present application.
[0052] The comparator group 120 includes a plurality of comparators.
[0053] As shown in Figure 1, a comparator includes two input terminals, namely a first comparison input terminal and a second comparison input terminal, and a comparison output terminal. The comparator can compare the input signals of the two input terminals to obtain a comparison result, and output the comparison result through the comparison output terminal.
[0054] In this embodiment, the first comparison input terminals of different comparators can be connected to the selection output terminal, and the second comparison input terminals of different comparators can be used to input different requests from the multiple requests. In this way, different comparators can compare the target request with different requests from the multiple requests, respectively, and output comparison results.
[0055] In an embodiment of the present application, the comparator group is configured to compare the target request with the multiple requests to be merged respectively, and determine the duplicate requests in the multiple requests that are duplicates of the target request.
[0056] The comparison output of the comparator can output a comparison result indicating whether the input signals at the two inputs are identical. Since the two inputs respectively input one of the multiple requests and the target request, the comparison result can also be a duplicate request, or the comparison result can indicate whether a request among the multiple requests is identical to the target request, i.e., the comparison result can indicate that a request among the multiple requests is a duplicate request. For example, when the target request input to the first comparison input is identical to the request input to the second comparison input, the comparison output can output a 0 or a 1. 0 indicates that the request input to the second comparison input is identical to the target request, i.e., the request input to the second comparison input is a duplicate of the target request. Conversely, 1 indicates that the request input to the second comparison input is different from the target request.
[0057] In this embodiment, the number of comparators in the comparator group 120 can be the same as the number of the multiple requests to be merged. For example, if the number of requests to be merged is 32, then 32 comparators can be set in the comparator group 120. Thus, the 32 requests, including the target request, can be input into different comparators and compared with the target request to determine whether they are the same as the target request. In this way, the target request and the duplicate requests that are the same as the target request can be determined among the 32 requests, so that the target request and the duplicate requests are no longer compared.
[0058] In some embodiments, the number of comparators in the comparator group 120 may be less than the number of the multiple requests to be merged. For example, if the number of requests to be merged is 32, the comparator group 120 may include 31 comparators and an additional selector. The input end of the selector sequentially inputs the multiple requests to be merged, and the output end is connected to different comparators of the comparator group 120. The control end of the selector is configured to sequentially output the other requests in the multiple requests to be merged, except the target request, to different comparators for comparison.
[0059] The above is only an example and does not limit the present application. The comparator group 120 can be reasonably combined according to needs. The principle and structure of the comparator can refer to the existing technology and will not be repeated here.
[0060] The first logic circuit 130 includes a first logic input terminal, a second logic input terminal, and a first logic output terminal.
[0061] In this embodiment, the first logic circuit 130 is configured to output other content of the input signal of the second logic input terminal in addition to the input signal of the first logic input terminal. For example, if the input signal of the first logic input terminal is 0-3 and the input signal of the second logic input terminal is 0-10, the first logic output terminal can output 4-10.
[0062] In this embodiment, the first logic circuit 130 can be implemented using logic gates. For example, an AND gate can be used to implement the functions of the first logic circuit 130. The first logic circuit 130 only needs to remove the signal input to the first logic input terminal from the signal input to the second logic input terminal. Those skilled in the art can combine existing logic devices such as AND gates, NOT gates, or OR gates to form the first logic circuit 130 according to actual needs, and this will not be elaborated here.
[0063] In this embodiment, the first logic input terminal can be connected to the comparison output terminal, and multiple requests can be input to the second logic input terminal. Thus, the first logic gate circuit can compare the multiple requests with the duplicate requests output by the comparison output terminal and eliminate duplicate requests from the multiple requests. For example, when the comparison output terminal outputs a value of 0 or 1 indicating whether the request is a duplicate request, the request with a value of 0 can be eliminated, and the request with a value of 1 can be output normally.
[0064] In this embodiment, the first logic output terminal is connected to the selection control terminal, so that the first logic circuit 130 can output the remaining requests after eliminating duplicate requests from the multiple requests to be merged to the multiplexer 110, so that the multiplexer 110 selects the target request again, thereby causing the comparator to compare the target request to be selected again with the remaining requests until all the multiple requests to be merged are eliminated.
[0065] Since non-repetitive requests are to access different addresses in the memory space, different requests do not need to be output at the same time. Therefore, in some optional embodiments of the present application, each time the multiplexer 110 determines a target request, it can directly output the target request to the request merging unit to access the memory space according to the target request.
[0066] In some embodiments, the request merging unit may also include a cache connected to the selection output end. The cache can temporarily store the target request output by the selection output end. After the multiple requests to be merged in the memory access instruction are compared, all target requests can be output outside the request merging unit to access the memory space according to the target request.
[0067] In an embodiment of the present application, the request includes an access address to the memory space. In some embodiments, a request identification value can also be configured for each request. For example, a 1-bit request identification value can be configured for a thread request. The request identification value can be 0 or 1 to indicate whether the thread request is valid. When the request identification value is 0, it indicates that the thread request is invalid. When the request identification value is 1, it indicates that the thread request is valid.
[0068] In embodiments of the present application, a request identification value can be used to determine whether the request corresponding to the request identification value is a duplicate request or has already been compared. Therefore, in some embodiments of the present application, the request merging unit may further include a second logic circuit 140, which is configured to input the request identification values of multiple requests and determine a target request identification value from the request identification values, so as to output the target request identification value to the multiplexer 110. The multiplexer 110 may output the request corresponding to the target request identification value, i.e., the request corresponding to the target request identification value is the target request.
[0069] Please refer to FIG. 2 , which is a schematic diagram of the structure of a request merging unit provided in another embodiment of the present application.
[0070] In one embodiment, the second logic circuit may be further configured to: extract a request identification value corresponding to each request from the multiple requests; and combine all request identification values into a request identification vector to determine a target request identification value from the request identification vector.
[0071] In this embodiment, the second logic circuit 140 may include a third logic input and a second logic output. The third logic input may be used to input request identification values corresponding to multiple requests. The request identification values may be sequentially input into the third logic input. The second logic circuit 140 may sequentially test the request identification values and output the first valid request identification value in order. For example, if the request identification values of eight requests are 0, 0, 1, 1, 0, 1, 1, 0, respectively, the second logic circuit 140 may output 3 to indicate that the third request identification value is the target request identification value.
[0072] In this embodiment, the second logic output terminal is connected to the selection control terminal, so that the target request identification value output by the second logic circuit 140 can be output to the multiplexer 110 to serve as a condition for the multiplexer 110 to select the target request. For example, when the second logic circuit 140 outputs 3, the multiplexer 110 can output the request with the third order or the request input to the third request input terminal.
[0073] In some embodiments, the request merging unit may include a processor connected to the select input and select output of the multiplexer 110 and further connected to the third logic input. The processor may extract request identification values from multiple requests and combine the request identification values into a request identification vector, thereby inputting the request identification vector into the second logic circuit 140.
[0074] In some embodiments, the processor may be further configured to ensure that the order in which the request identification values corresponding to the requests in the request identification vector are arranged is the same as the order in which the requests are arranged in the plurality of requests. The second logic circuit 140 may be implemented using existing logic circuits or constructed with reference to existing technologies, for example, using a leading one (a combinational logic module), and will not be further described here.
[0075] In one embodiment, the first logic circuit may further be configured to modify the request identification values of the repeated request and the target request to invalid values.
[0076] In this embodiment, a request identification vector or multiple request identification vectors may also be input into the second logic input of the first logic gate, so that the first logic circuit 130 performs a logical operation on the characterizing value representing the repeated request output by the comparator, thereby modifying the request identification value of the repeated request to an invalid value, so that it does not participate in the next round of comparison. For example, if the second logic input input is 00110011, and the value output by the comparator group 120 to the first logic input is 11011101, the first logic circuit 130 may output 00010001. If the third and seventh requests are repeated requests, the request identification values corresponding to the third and seventh requests may be modified to 0, so that they do not participate in the next round of comparison.
[0077] In one embodiment, the request merging unit may further include: a one-out-of-two selector 150 .
[0078] The initial request identification values or request identification vectors input to the second logic circuit 140 are all valid values, that is, all requests are compared and no repeated requests have been determined. After completing a round of comparison, some requests are determined to be repeated requests, and the target request has been determined. When a new round of comparison is performed, there is no need to compare the repeated requests and the target request again. Therefore, in this embodiment, a two-to-one selector 150 can be set to use the request identification value or request identification vector that has been determined to be a repeated request as the input of the second logic circuit 140.
[0079] In this embodiment, the two-to-one selector 150 includes a second selection input, a third selection input, and a second selection output. The second selection input is connected to the first logic output. The third selection input is used to input a request identification value corresponding to each of the multiple requests. The second selection output is connected to the third logic input. The two-to-one selector 150 can be configured to output the input signal at the second selection input when both the second and third selection inputs are input.
[0080] Thus, when the second selection input terminal has no input and the third selection input terminal has input, the input of the third selection input terminal can be output. When both the second and third selection input terminals have input, the input of the second selection input terminal can be output. Specifically, when only the initial request identification vector is present, the initial request identification vector is output; when both the initial request identification vector and the modified request identification vector are input, the modified request identification vector is output. This prevents repeated comparisons of each request, improving the efficiency of merging multiple requests.
[0081] Based on the same inventive concept, an embodiment of the present application also provides a request merging method.
[0082] Please refer to FIG3 , which is a flowchart of a request merging method provided in an embodiment of the present application. The request merging method includes:
[0083] S110: Determine a target request from multiple requests to be merged.
[0084] In this embodiment, multiple requests to be merged may be input to the multiplexer 110, so that the multiplexer 110 outputs a target request. The multiplexer 110 is configured with a preset condition for selecting the target request. Since it is necessary to determine whether the multiple requests include corresponding duplicate requests, the preset condition is to determine any one of the multiple requests that is not determined to be a duplicate request or a target request as the target request.
[0085] In some embodiments, a corresponding request identification value can be configured for each request. The request identification value includes a valid value and an invalid value. A valid value indicates that the request corresponding to the request identification value is valid, and an invalid value indicates that the request corresponding to the request identification value is invalid. Thus, the request identification value corresponding to a request that is not determined to be a repeated request or a target request can be made valid, and a request determined to be a repeated request or an invalid value can be modified to an invalid value. Thus, it is possible to determine whether the corresponding request is a repeated request or has been determined to be a target request based on the request identification value.
[0086] In some embodiments, selecting a target request from multiple requests to be merged may include: determining a target request identification value from multiple request identification values; the target request identification value is a valid value; and determining the request corresponding to the target request identification value as the target request.
[0087] In this embodiment, the request identification value corresponding to each request can be input into the second logic circuit 140, so that the second logic circuit 140 determines the target request identification value, and outputs the target request identification value to the multiplexer 110, so that the multiplexer 110 can determine the request corresponding to the target request identification value as the target request.
[0088] In this embodiment, the second logic circuit 140 may determine the target request identification value based on the request identification value corresponding to any valid value. In some embodiments, the target request identification value may be determined based on the request identification value corresponding to the first valid value in the order in which the request identification values are input into the second logic circuit 140. The above is merely an example and is not intended to be limiting.
[0089] In some embodiments, after extracting the request identification value, all request identification values may be combined into a request identification vector to determine a target request identification value from the request identification vector.
[0090] When there are a large number of requests to be merged, inputting each request identification value sequentially into the second logic circuit 140 may consume considerable time, impacting the efficiency of request merging. In this embodiment, the request identification values of different requests can be combined to generate a request identification vector, which is then input into the second logic circuit 140. Because the request identification vector includes the request identification values of multiple requests, the second logic circuit 140 can detect the request identification values of multiple requests in a relatively short period of time without having to wait for the request identification values to be input sequentially. This improves the efficiency of determining the target request, thereby improving the efficiency of request merging.
[0091] In some embodiments, in the request identification vector, the order in which the request identification values corresponding to the requests are arranged is the same as the order in which the requests are arranged in the multiple requests.
[0092] The requests in the memory access instruction are arranged in order and input into the multiplexer 110 in sequence according to the arrangement order. In this embodiment, the arrangement order of the request identification values corresponding to each request can be the same as the arrangement order of each request in the multiple requests. Therefore, after determining the target request identification value, the order of the target request identification value in the request identification vector can be directly output to the multiplexer 110, so that the multiplexer 110 outputs the requests of the corresponding order in the multiple requests, that is, the request corresponding to the request identification vector is determined as the target request. Therefore, the corresponding target request can be directly determined by the arrangement order of the target request identification, thereby improving the efficiency of determining the target request and improving the efficiency of request merging.
[0093] S120 , comparing the target request with the multiple requests based on a preset comparator group, and determining duplicate requests that are duplicates of the target request in the multiple requests.
[0094] In this embodiment, the comparator group 120 includes multiple comparators, and the target request can be input into the first comparison input terminals of all comparators, and different requests can be input into the second comparison input terminals of different comparators respectively, thereby realizing the comparison between the target request and multiple requests.
[0095] In this embodiment, the comparator may output a characterization value indicating whether the request is the same as the target request. For example, the characterization value may be 0 or 1, where 0 indicates that the request is the same as the target request, and 1 indicates that the request is different from the target request.
[0096] By determining the target request through the multiplexer 110 and then comparing the target request with other requests, the use of comparators can be effectively reduced. There is no need to set a comparator between any two requests. A comparator only needs to be set between the target request and other requests. The number of comparators used can be reduced to the same number of requests as the multiple requests to be merged, thereby reducing the chip area occupied by the comparators.
[0097] In some embodiments, the request address of the request can be input into the multiplexer 110 so that the multiplexer 110 outputs the request address, which is the address of the target request. Accordingly, determining a duplicate request that is duplicated with the target request among the multiple requests can include: inputting the request address of the target request and the request addresses of the multiple requests into the comparator group 120 respectively, so that the comparator group 120 compares the request address of the target request with the request addresses of the multiple requests to be merged; obtaining an output result of the comparator group 120, the output result indicating whether the request address of the target request is the same as the request addresses of the multiple requests to be merged; and determining the duplicate request based on the output result.
[0098] In this embodiment, since the request is to access the memory space, the access is based on the access address, that is, the request address. The difference between the requests is mainly the difference in the request address. Therefore, the request can be input into the multiplexer 110 and the comparator group 120, and the request address can be compared to determine the repeated request.
[0099] In this embodiment, the request address of the request may be input into the multiplexer 110 , and then the request address of the request may be used for comparison, thereby reducing the amount of data required for comparison by the comparator and improving the processing efficiency of the comparator.
[0100] S130 , repeating the above comparison process based on the remaining requests except the repeated request and the target request among the multiple requests until the comparison of the multiple requests is completed.
[0101] In this embodiment, after determining the repeat request, the first logic gate can send the repeat request and the target request to the multiplexer 110 to repeat S110 and S120, that is, to make the multiplexer select other request outputs except the repeat request and the target request from the multiple requests to re-determine the new target request for comparison again, thereby determining the repeat request that repeats the new target request, until all requests in the multiple requests are determined to be repeat requests or target requests, then it can be determined that the comparison of the multiple requests is completed.
[0102] S140: Output the target request.
[0103] In this embodiment, all target requests may be output after all requests have been compared, or the target request may be output after S110 , and there is no limitation here.
[0104] In an embodiment of the present application, the request merging method can be applied to a processor, chip, module, electronic device, etc. that is connected to a request merging unit or includes the above-mentioned request merging unit. In some embodiments, the request merging method can also be applied to a hardware structure having similar functions to the above-mentioned request merging unit. The request merging unit is only an example and is not intended to be limiting.
[0105] For the contents not described in the request merging method, please refer to the description of the aforementioned request merging unit or the prior art, and will not be elaborated here.
[0106] In an embodiment of the present application, by selecting one request as a target request from multiple requests to be merged, and after comparing the target request with the remaining requests in the multiple requests, the target request is re-determined until all requests are compared. Therefore, it is only necessary to set a comparator when comparing the target request with multiple requests, so that the number of comparators can be the same as the number of requests in the multiple requests, and there is no need to set a comparator between any two requests, which effectively reduces the number of comparators and reduces the chip area occupied by the comparators.
[0107] Based on the same inventive concept, an embodiment of the present application further provides a chip, which may include the request merging unit provided by any of the above embodiments.
[0108] In this embodiment, the chip may be a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an MCU (Microcontroller Unit), etc., which is not limited here.
[0109] Based on the same inventive concept, an embodiment of the present application further provides an electronic device, which may include the chip provided in the above embodiment.
[0110] In this embodiment, the electronic device may be a computer, a server, a single-chip device, an embedded device, etc., which is not limited here.
[0111] The technical features of the above embodiments can be freely combined without conflict, and the embodiments obtained by the combination are included in the protection scope of this application.
[0112] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.
[0113] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.
Claims
1. A request merging unit, characterized in that: include: a multiplexer configured to determine a target request from the multiple requests to be merged, wherein the target request is a request selected from the multiple requests according to a preset condition; a comparator group connected to the multiplexer, the comparator group being configured to compare the target request with the multiple requests respectively, and determine a repeated request in the multiple requests that is repeated with the target request; a first logic circuit connected to the multiplexer, the first logic circuit being used to output the remaining requests among the multiple requests except the repeated request and the target request to the multiplexer, so as to repeat the comparison process until the multiple requests are all compared; The multiplexer is further configured to output the target request to outside the request merging unit.
2. The request merging unit according to claim 1, characterized in that: Each of the requests includes a request identification value, and the request identification value includes a valid value and an invalid value, the valid value indicates that the request corresponding to the request identification value is valid, and the invalid value indicates that the request corresponding to the request identification value is invalid; The request merging unit also includes: a second logic circuit, comprising a third logic input terminal and a second logic output terminal, wherein the third logic input terminal is used to input request identification values corresponding to the multiple requests; the second logic output terminal is connected to the selection control terminal of the multiplexer, and the selection control terminal is used to configure the preset condition; The second logic circuit is used to determine a target request identification value from a plurality of request identification values corresponding to the plurality of requests; the target request identification value is a valid value; and the request corresponding to the target request identification value is the target request.
3. The request merging unit according to claim 2, characterized in that: The request merging unit further includes a processor, the processor being connected to the selection input terminal and the selection output terminal of the multiplexer, and the processor being further connected to the third logic input terminal; The processor is configured to: extract a request identification value corresponding to each request from the multiple requests; and combine all the request identification values into a request identification vector to determine the target request identification value from the request identification vector.
4. The request merging unit according to claim 3, characterized in that: The processor is further configured to: make the arrangement order of the request identification values corresponding to the requests in the request identification vector the same as the arrangement order of the requests in the multiple requests.
5. The request merging unit according to claim 2, characterized in that: The first logic circuit is further used to modify the request identification values of the repeated request and the target request to invalid values.
6. The request merging unit according to claim 2, characterized in that: The request merging unit further includes: a two-to-one selector, the two-to-one selector including a second selection input terminal, a third selection input terminal, and a second selection output terminal; the second selection input terminal is connected to the first logic output terminal of the first logic circuit; the third selection input terminal is used to input a request identification value corresponding to each request in the multiple requests; The second selection output terminal is connected to the third logic input terminal; the two-to-one selector is configured to output the input signal of the second selection input terminal when both the second selection input terminal and the third selection input terminal have inputs.
7. A chip, characterized in that: It comprises a request merging unit as described in any one of claims 1-6.
8. A request merging method, characterized in that: include: Determining a target request from the multiple requests to be merged, wherein the target request is a request selected from the multiple requests according to a preset condition; Comparing the target request with the multiple requests respectively based on a preset comparator group, and determining a repeated request in the multiple requests that is repeated with the target request; Repeating the comparison process based on the remaining requests among the multiple requests except the repeated request and the target request until all the multiple requests are compared; The target request is output.
9. The request merging method according to claim 8, characterized in that: Each of the requests includes a request identification value, and the request identification value includes a valid value and an invalid value, the valid value indicates that the request corresponding to the request identification value is valid, and the invalid value indicates that the request corresponding to the request identification value is invalid; The selecting a target request from the multiple requests to be merged includes: Determine a target request identification value from the multiple request identification values; the target request identification value is a valid value; The request corresponding to the target request identification value is determined as the target request.
10. The request merging method according to claim 9, characterized in that: Before determining the target request identification value from the multiple request identification values, the method further includes: Extracting a request identification value corresponding to each request from the multiple requests; All of the request identification values are combined into a request identification vector to determine the target request identification value from the request identification vector.
11. The request merging method according to claim 10, characterized in that: In the request identification vector, the arrangement order of the request identification values corresponding to the requests is the same as the arrangement order of the requests in the multiple requests.
12. The request merging method according to claim 9, characterized in that: After determining the repeated request that is repeated with the target request among the multiple requests, the method further includes: modifying the request identification values of the repeated request and the target request to invalid values.
13. The request merging method according to any one of claims 9 to 12, characterized in that: The request includes a request address, and determining a repeated request that is repeated with the target request among the multiple requests includes: inputting the request address of the target request and the request addresses of the multiple requests into the comparator group respectively, so that the comparator group compares the request address of the target request with the request addresses of the multiple requests to be merged; Obtaining an output result of the comparator group, wherein the output result indicates whether a request address of the target request is the same as the request addresses of the multiple requests to be merged; The repeat request is determined based on the output result.