Pixel driving circuit, display panel and driving method

Abstract

A pixel driving circuit, a display panel and a driving method, the pixel driving circuit comprises a driving transistor (DTFT), a light emitting device (L1), a compensation capacitor (C1), a threshold compensation sub-circuit (200), a data write-in sub-circuit (300), a conduction control sub-circuit (100) and a light emitting control sub-circuit (400), the threshold compensation sub-circuit (200) responds to a signal of a compensation signal end (S1), and the data write-in sub-circuit (300) is connected with the conduction control sub-circuit (100). The threshold voltage of the driving transistor (DTFT) is provided for the first end of the compensation capacitor (C1), the data writing sub-circuit (300) responds to the signal of the scanning signal end (S3) and provides the data voltage of the data signal end (Data) for the second end of the compensation capacitor (C1), and the conduction control sub-circuit (100) responds to the signal of the conduction control end (S4) and conducts the power signal end (ELVDD) and the second end of the compensation capacitor (C1). The light-emitting control sub-circuit (400) responds to a signal of a light-emitting control signal end (S4), driving current generated by the driving transistor (DTFT) is provided for the light-emitting device (L1), time-sharing implementation of threshold value compensation and data writing is achieved through the arrangement of the compensation capacitor (C1), and high-frequency refreshing is achieved while the requirement for displaying of the light-emitting device (L1) is met.

Description

Pixel driving circuit, display panel and driving method Technical Field

[0001] The present disclosure relates to the field of display technology and provides a pixel driving circuit, a display panel, and a driving method. Background Art

[0002] In the pixel driving circuit of related art, during the driving process, the threshold voltage of the driving transistor is compensated simultaneously with the writing of the data voltage to the gate of the driving transistor. However, since this threshold voltage compensation takes a long time, as the refresh rate of the display increases, the compensation period per unit time is greatly reduced. This results in insufficient compensation of the threshold voltage of the driving transistor, which in turn leads to poor display quality.

[0003] Summary of the Invention

[0004] The embodiments of the present disclosure provide a pixel driving circuit, a display panel, and a driving method for performing threshold voltage compensation and data voltage writing in different time periods to improve the threshold voltage compensation effect at a high refresh rate.

[0005] The specific technical solutions provided by this disclosure are as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a pixel driving circuit, comprising: a driving transistor, a light-emitting device, a compensation capacitor, a threshold compensation subcircuit, a data writing subcircuit, a conduction control subcircuit, and a light-emitting control subcircuit;

[0007] The threshold compensation sub-circuit is coupled to the gate of the driving transistor and the first terminal of the compensation capacitor, and is configured to provide the threshold voltage of the driving transistor to the first terminal of the compensation capacitor in response to a signal at the compensation signal terminal;

[0008] The data writing sub-circuit is coupled to the second end of the compensation capacitor and is configured to provide a data voltage from the data signal end to the second end of the compensation capacitor in response to a signal from the scan signal end;

[0009] a compensation capacitor configured to stabilize the voltage at the first terminal and the second terminal;

[0010] The conduction control subcircuit is coupled to the second terminal of the compensation capacitor and the power signal terminal, and is configured to connect the power signal terminal to the second terminal of the compensation capacitor in response to a signal from the conduction control terminal;

[0011] The light emitting control subcircuit is coupled to the driving transistor and the light emitting device, and is configured to provide the driving current generated by the driving transistor to the light emitting device in response to a signal at the light emitting control signal terminal.

[0012] Optionally, the conduction control subcircuit includes: a first transistor;

[0013] The control terminal of the first transistor is coupled to the conduction control terminal, the first terminal of the first transistor is coupled to the second terminal of the compensation capacitor, and the second terminal of the first transistor is coupled to the power signal terminal.

[0014] Optionally, the data writing sub-circuit provides a data voltage at the data signal terminal to the second terminal of the compensation capacitor in response to a first valid level of a signal at the scan signal terminal;

[0015] The threshold compensation subcircuit provides the threshold voltage of the driving transistor to the first terminal of the compensation capacitor in response to the second valid level of the signal at the compensation signal terminal;

[0016] The first effective level is within a time period of the second effective level.

[0017] Optionally, a high level duration of the first effective level is shorter than a low level duration of the second effective level.

[0018] Optionally, the threshold compensation sub-circuit includes: a second transistor;

[0019] The control terminal of the second transistor is coupled to the compensation signal terminal, the first terminal of the second transistor is coupled to the first terminal of the compensation capacitor, and the second terminal of the second transistor is coupled to the second terminal of the driving transistor.

[0020] Optionally, the data writing sub-circuit includes: a third transistor;

[0021] The control end of the third transistor is coupled to the scan signal end, the first end of the third transistor is coupled to the data signal end, and the second end of the third transistor is coupled to the second end of the compensation capacitor.

[0022] Optionally, the light emitting control subcircuit includes: a fourth transistor and a fifth transistor;

[0023] The control terminal of the fourth transistor is coupled to the light emitting control signal terminal, the first terminal of the fourth transistor is coupled to the power signal terminal, and the second terminal of the fourth transistor is coupled to the first terminal of the driving transistor;

[0024] The control terminal of the fifth transistor is coupled to the conduction control terminal, the first terminal of the fifth transistor is coupled to the second terminal of the driving transistor, and the second terminal of the fifth transistor is coupled to the anode of the light emitting device.

[0025] Optionally, a first initialization subcircuit is further included, which is coupled to the first end of the driving transistor and is configured to provide a signal from the first initialization signal end to the first end of the driving transistor in response to a signal from the first reset signal end.

[0026] Optionally, the first initialization sub-circuit includes: a sixth transistor;

[0027] The control terminal of the sixth transistor is coupled to the first reset signal terminal, the first terminal of the sixth transistor is coupled to the first terminal of the driving transistor, and the second terminal of the sixth transistor is coupled to the first initialization signal terminal.

[0028] Optionally, a second initialization subcircuit is further included, which is coupled to the anode of the light-emitting device and is configured to provide a signal from the second initialization signal terminal to the anode of the light-emitting device in response to a signal from the second reset signal terminal.

[0029] Optionally, the second initialization sub-circuit includes: a seventh transistor;

[0030] The control terminal of the seventh transistor is coupled to the second reset signal terminal, the first terminal of the seventh transistor is coupled to the anode of the light emitting device, and the second terminal of the seventh transistor is coupled to the second initialization signal terminal.

[0031] Optionally, a third initialization subcircuit is further included, which is coupled to the first end of the compensation capacitor and is configured to provide the signal of the third initialization signal end to the first end of the compensation capacitor in response to the signal of the third reset signal end.

[0032] Optionally, the third initialization sub-circuit includes: an eighth transistor;

[0033] The control terminal of the eighth transistor is coupled to the third reset signal terminal, the first terminal of the eighth transistor is coupled to the first terminal of the compensation capacitor, and the second terminal of the eighth transistor is coupled to the third initialization signal terminal.

[0034] In a second aspect, an embodiment of the present disclosure further provides a display panel, including:

[0035] A base substrate, comprising a plurality of sub-pixels, wherein the sub-pixels include any one of the above pixel driving circuits;

[0036] The pixel driving circuit includes: a driving transistor, a first transistor, a third transistor, and a compensation capacitor, wherein a first terminal of the first transistor is coupled to a second terminal of the compensation capacitor, a second terminal of the third transistor is coupled to a second terminal of the compensation capacitor, and a gate of the driving transistor is coupled to the first terminal of the compensation capacitor;

[0037] The orthographic projection of the active layer of the third transistor on the substrate is located between the orthographic projection of the active layer of the driving transistor on the substrate and the orthographic projection of the active layer of the first transistor on the substrate.

[0038] Optionally, the display panel includes: a first semiconductor layer, a first conductive layer, a second conductive layer, and a second semiconductor layer;

[0039] A first semiconductor layer is located on the base substrate, and the first semiconductor layer includes an active layer of the first transistor and an active layer of the driving transistor;

[0040] A first conductive layer is located on a side of the substrate away from the first semiconductor layer, and the first conductive layer includes a gate of the first transistor, a gate of the driving transistor, and a first signal line;

[0041] A second conductive layer is located on a side of the substrate away from the first conductive layer, and the second conductive layer includes a second end of the compensation capacitor, a gate of the third transistor and a fifth signal line;

[0042] The second semiconductor layer is located on a side of the substrate away from the second conductive layer, and the second semiconductor layer includes an active layer of a third transistor.

[0043] Optionally, an orthographic projection of the first signal line on the substrate and an orthographic projection of the active layer of the first transistor on the substrate have an overlapping area, and the first signal line in the overlapping area is the gate of the first transistor.

[0044] Optionally, the active layer of the first transistor includes a first active portion and a second active portion, the first active portion extends along the first direction, the second active portion extends along the second direction, and the orthographic projection of the first signal line on the substrate overlaps with the orthographic projection of the first active portion on the substrate.

[0045] Optionally, a third conductive layer is further included, the third conductive layer is located on a side of the substrate away from the second semiconductor layer, the third conductive layer includes a power signal line connected to the power signal terminal, and the power signal line covers the overlapping area.

[0046] Optionally, the third conductive layer includes a first connecting portion, the second conductive layer includes a second connecting portion, a first insulating layer is provided between the third conductive layer and the second conductive layer, and a second insulating layer is provided between the second conductive layer and the first conductive layer;

[0047] The power signal line is connected to the second connecting portion through a first via hole penetrating the first insulating layer;

[0048] The second connection portion is connected to the active layer of the first transistor through a second via hole penetrating the second insulating layer.

[0049] In a third aspect, an embodiment of the present disclosure further provides a driving method of any of the above pixel driving circuits, including:

[0050] The threshold compensation subcircuit provides the threshold voltage of the driving transistor to the first terminal of the compensation capacitor in response to the signal at the compensation signal terminal;

[0051] The data writing sub-circuit provides the data voltage of the data signal terminal to the second terminal of the compensation capacitor in response to the signal of the scan signal terminal;

[0052] The compensation capacitor stabilizes the voltage between the first terminal and the second terminal;

[0053] The conduction control subcircuit connects the power signal terminal to the second terminal of the compensation capacitor in response to a signal from the conduction control terminal;

[0054] The light emitting control sub-circuit provides the driving current generated by the driving transistor to the light emitting device in response to the signal of the light emitting control signal terminal.

[0055] The beneficial effects of the present disclosure are as follows:

[0056] In summary, a pixel driving circuit, a display panel and a driving method are provided in an embodiment of the present disclosure. The pixel driving circuit includes: a driving transistor, a light-emitting device, a compensation capacitor, a threshold compensation sub-circuit, a data writing sub-circuit, a conduction control sub-circuit and a light-emitting control sub-circuit. The threshold compensation sub-circuit responds to the signal of the compensation signal end and provides the threshold voltage of the driving transistor to the first end of the compensation capacitor. The data writing sub-circuit responds to the signal of the scan signal end and provides the data voltage of the data signal end to the second end of the compensation capacitor. The conduction control sub-circuit responds to the signal of the conduction control end and conducts the power signal end with the second end of the compensation capacitor. The light-emitting control sub-circuit responds to the signal of the light-emitting control signal end and provides the driving current generated by the driving transistor to the light-emitting device. The setting of the compensation capacitor realizes the time-sharing of threshold compensation and data writing, which satisfies the display of the light-emitting device while achieving high-frequency refresh.

[0057] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. The purposes and other advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0059] FIG1 is a connection diagram of a pixel driving circuit in the related art;

[0060] FIG2 is a connection diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0061] FIG3 is a circuit connection diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0062] FIG4 is a connection diagram of another pixel driving circuit according to an embodiment of the present disclosure;

[0063] FIG5 is a circuit connection diagram of another pixel driving circuit in an embodiment of the present disclosure;

[0064] FIG6 is a timing diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0065] FIG7 is a schematic diagram of a layout structure of a display panel in an embodiment of the present disclosure;

[0066] FIG8 is a schematic diagram of the layout structure of a first semiconductor layer in a display panel according to an embodiment of the present disclosure;

[0067] FIG9 is a schematic diagram of the layout structure of a first conductive layer in a display panel according to an embodiment of the present disclosure;

[0068] FIG10 is a schematic diagram of the layout structure of a second conductive layer in a display panel according to an embodiment of the present disclosure;

[0069] FIG11 is a schematic diagram of the layout structure of a second semiconductor layer in a display panel according to an embodiment of the present disclosure;

[0070] FIG12 is a schematic diagram of the layout structure of a third conductive layer in a display panel according to an embodiment of the present disclosure;

[0071] FIG13 is a schematic diagram of the layout structure of a film layer where a power signal terminal is located in a display panel according to an embodiment of the present disclosure;

[0072] FIG14 is a schematic diagram of the layout structure of a film layer where each connection line is located in a display panel according to an embodiment of the present disclosure;

[0073] FIG15 is a schematic diagram of the layout structure of the film layer where each connection line is located in another display panel according to an embodiment of the present disclosure;

[0074] FIG16 is a flow chart of a driving method of a pixel driving circuit in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0075] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the technical solutions of the present disclosure, but not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments described in this disclosure without making any creative efforts shall fall within the scope of protection of the technical solutions of the present disclosure.

[0076] The terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be practiced using orders other than those illustrated or described herein.

[0077] In related art, during the pixel driver circuit's driving process, the threshold voltage of the driver transistor is compensated simultaneously with the data voltage being written to the gate of the driver transistor. However, because this threshold voltage compensation takes a long time, as the refresh rate of the display increases, the compensation period per unit time is greatly reduced. This results in insufficient compensation of the driver transistor's threshold voltage, which in turn leads to poor display quality.

[0078] Referring to FIG. 1 , a detailed description will be given using the pixel driving circuit shown in FIG. 1 . The transistor M3 in FIG. 1 is a driving transistor. During operation of the driving transistor, the threshold voltage of the driving transistor M3 is written to the gate of the driving transistor via the turned-on transistor M2. Simultaneously, the data voltage is also written to the gate of the driving transistor via the turned-on transistor T4. When the refresh rate of the display screen where the driving transistor is located is high, the threshold voltage compensation is often insufficient at the end of the compensation period, thereby affecting the display effect of the display screen.

[0079] The preferred embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0080] Referring to Figure 2, a pixel driving circuit proposed in an embodiment of the present application includes: a driving transistor DTFT, a light-emitting device L1, a compensation capacitor C1, a threshold compensation sub-circuit 200, a data writing sub-circuit 300, a conduction control sub-circuit 100 and a light-emitting control sub-circuit 400.

[0081] During implementation, the conduction control subcircuit 100 is coupled to the second terminal of the compensation capacitor C1 and the power signal terminal ELVDD, and is configured to conduct the power signal terminal ELVDD and the second terminal of the compensation capacitor C1 in response to the signal of the conduction control terminal S4.

[0082] 3 , the conduction control sub-circuit 100 includes a first transistor T1 .

[0083] The connection relationship between the first transistor T1 and other components in Figure 3 is: the control end of the first transistor T1 is coupled to the conduction control end S4, the first end of the first transistor T1 is coupled to the second end of the compensation capacitor C1, and the second end of the first transistor T1 is coupled to the power signal end ELVDD.

[0084] During implementation, when the signal at the conduction control terminal S4 is at a low level, the control terminal of the first transistor T1 is turned on, and the level of the power signal terminal ELVDD is provided to the second terminal of the compensation capacitor C1 via the turned-on first transistor T1.

[0085] During implementation, the threshold compensation sub-circuit 200 is coupled to the gate of the driving transistor DTFT and the first end of the compensation capacitor C1, and is configured to provide the threshold voltage of the driving transistor DTFT to the first end of the compensation capacitor C1 in response to the signal of the compensation signal terminal S1.

[0086] 3 , the threshold compensation sub-circuit 200 includes a second transistor T2 .

[0087] The connection relationship between the second transistor T2 and other components in Figure 3 is: the control end of the second transistor T2 is coupled to the compensation signal end S1, the first end of the second transistor T2 is coupled to the first end of the compensation capacitor C1, and the second end of the second transistor T2 is coupled to the second end of the driving transistor DTFT.

[0088] It should be noted that, since the second transistor T2 is directly connected to the first end of the compensation capacitor C1, that is, the gate of the driving transistor DTFT, during the implementation process, the second transistor T2 can be replaced with an IGZO tube, which can ensure that the potential of the gate of the driving transistor DTFT will not change due to leakage of the second transistor T2.

[0089] During implementation, when the signal at the compensation signal terminal S1 is low, the control terminal of the second transistor T2 is low, the second transistor T2 is turned on, and the threshold voltage of the driving transistor DTFT is provided to the first terminal of the compensation capacitor C1 through the turned-on second transistor T2.

[0090] The data writing sub-circuit 300 is coupled to the second end of the compensation capacitor C1 and is configured to provide a data voltage of the data signal terminal Data to the second end of the compensation capacitor C1 in response to a signal of the scan signal terminal S3 .

[0091] 3 , the data writing sub-circuit 300 includes a third transistor T3 .

[0092] The connection relationship between the third transistor T3 and other components in Figure 3 is: the control end of the third transistor T3 is coupled to the scan signal end S3, the first end of the third transistor T3 is coupled to the data signal end Data, and the second end of the third transistor T3 is coupled to the second end of the compensation capacitor C1.

[0093] For example, in the embodiment of the present application, the third transistor T3 is an N-type transistor, and the material of the active layer of the third transistor is a metal oxide semiconductor material, such as IGZO. When the third transistor T3 is an N-type transistor, the other transistors are P-type transistors, and the material of the active layer of the other transistors can also be low-temperature polysilicon (LTPS), etc., without specific limitation here.

[0094] During implementation, when the scan signal terminal S3 is at a high level, the control terminal of the third transistor T3 is at a high level, the third transistor T3 is turned on, and the data voltage of the data signal terminal Data is provided to the second terminal of the compensation capacitor C1 through the turned-on third transistor T3.

[0095] It should be noted that, in the embodiment of the present application, in order to set the threshold compensation and data writing processes to be performed in different time periods, the effective time period for writing the data to the effective level of the sub-circuit 300 and the threshold compensation sub-circuit 200 is set as follows:

[0096] During specific implementation, the data writing sub-circuit 300 provides the data voltage of the data signal terminal Data to the second terminal of the compensation capacitor C1 in response to the first valid level of the signal at the scan signal terminal S3 .

[0097] That is, the duration for which the data voltage is written into the second end of the compensation capacitor C1 is the duration corresponding to the first effective level.

[0098] Accordingly, the threshold compensation sub-circuit 200 provides the threshold voltage of the driving transistor DTFT to the first terminal of the compensation capacitor C1 in response to the second valid level of the signal at the compensation signal terminal S1.

[0099] That is, the duration during which the threshold voltage is written into the first terminal of the compensation capacitor C1 is the duration corresponding to the second effective level.

[0100] Since the type of the third transistor is different from that of the other transistors, in some embodiments, the first effective level may be a high level, and correspondingly, the second effective level may be a low level. In other embodiments, the first effective level may be a low level, and correspondingly, the second effective level may be a high level.

[0101] It should be noted that the first effective level is within the time period of the second effective level.

[0102] That is, during implementation, the time period corresponding to the first effective level is set shorter than the time period corresponding to the second effective level, thereby ensuring that the time period of the threshold voltage writing circuit is longer than the time period of the data voltage writing circuit.

[0103] Furthermore, a high level duration of the first effective level is shorter than a low level duration of the second effective level.

[0104] Referring to Figure 3, when the second transistor T2 is an N-type transistor and the third transistor T3 is a P-type transistor, the above-mentioned first effective level is a high level effective, and the above-mentioned second effective level is a low level effective. In order to ensure that the duration of the threshold voltage writing is sufficient, the high level duration of the above-mentioned first effective level is shorter than the low level duration of the second effective level.

[0105] The compensation capacitor C1 is configured to stabilize the voltages at the first end and the second end.

[0106] Referring to FIG. 3 , during implementation, after the threshold voltage of the driving transistor DTFT is provided to the first terminal of the compensation capacitor C1 via the turned-on second transistor T2, and the data voltage is written to the second terminal of the compensation capacitor C1 via the turned-on third transistor T3, the first transistor T1 is turned on under the control of the turn-on control terminal S4, and the voltage at the first terminal of the compensation capacitor C1 jumps from the data voltage to the voltage of the power signal terminal ELVDD. In order to maintain a voltage balance between the first terminal and the second terminal of the compensation capacitor C1, the bootstrap effect of the compensation capacitor C1 couples the jump amount of the voltage at the first terminal to the second terminal of the compensation capacitor C1.

[0107] During implementation, the driving transistor DTFT generates a driving current according to the threshold voltage and the data voltage.

[0108] The light emitting control subcircuit is coupled to the driving transistor DTFT and the light emitting device L1 and is configured to provide the driving current generated by the driving transistor DTFT to the light emitting device L1 in response to the signal of the light emitting control signal terminal S4.

[0109] 3 , the light emitting control sub-circuit includes a fourth transistor T4 and a fifth transistor T5 .

[0110] The connection relationship between the fourth transistor T4 and other components in Figure 3 is: the control end of the fourth transistor T4 is coupled to the light-emitting control signal end S4, the first end of the fourth transistor T4 is coupled to the power signal end ELVDD, and the second end of the fourth transistor T4 is coupled to the first end of the driving transistor DTFT.

[0111] During implementation, when the light emitting control signal terminal S4 is at a low level, the fourth transistor T4 is turned on, and the signal in the power signal terminal ELVDD is provided to the driving transistor DTFT via the turned-on fourth transistor T4.

[0112] The connection relationship between the fifth transistor T5 and other components in Figure 3 is: the control end of the fifth transistor T5 is coupled to the conduction control end S4, the first end of the fifth transistor T5 is coupled to the second end of the driving transistor DTFT, and the second end of the fifth transistor T5 is coupled to the anode of the light-emitting device L1.

[0113] During implementation, when the signal at the conduction control terminal S4 is at a low level, the fifth transistor T5 is turned on, and the driving current generated by the driving transistor DTFT is provided to the anode of the light emitting device L1 through the turned-on fifth transistor T5, so that the light emitting device L1 emits light.

[0114] In addition, referring to Figure 4, the above-mentioned pixel driving circuit also includes a first initialization sub-circuit 500, which is coupled to the first end of the driving transistor DTFT and is configured to respond to the signal of the first reset signal terminal S5 and provide the signal of the first initialization signal terminal Vinit1 to the first end of the driving transistor DTFT.

[0115] 5 , the first initialization sub-circuit 500 includes a sixth transistor T6 .

[0116] The connection relationship between the sixth transistor T6 and other components in Figure 5 is: the control end of the sixth transistor T6 is coupled to the first reset signal end S5, the first end of the sixth transistor T6 is coupled to the first end of the driving transistor DTFT, and the second end of the sixth transistor T6 is coupled to the first initialization signal end Vinit1.

[0117] During implementation, when the signal of the first reset signal terminal S5 is at a low level, the sixth transistor T6 is turned on, and the first initialization signal of the first initialization signal terminal Vinit1 is provided to the first terminal of the driving transistor DTFT via the turned-on sixth transistor T6 to reset the first terminal of the driving transistor DTFT.

[0118] In addition, the above-mentioned pixel driving circuit also includes a second initialization sub-circuit 600, which is coupled to the anode of the light-emitting device L1 and is configured to provide the signal of the second initialization signal terminal Vinit2 to the anode of the light-emitting device L1 in response to the signal of the second reset signal terminal S5.

[0119] 5 , the second initialization sub-circuit 600 includes a seventh transistor T7 .

[0120] The connection relationship between the seventh transistor T7 and other components in Figure 5 is: the control end of the seventh transistor T7 is coupled to the second reset signal end S5, the first end of the seventh transistor T7 is coupled to the anode of the light-emitting device L1, and the second end of the seventh transistor T7 is coupled to the second initialization signal end Vinit2.

[0121] During implementation, when the signal of the second reset signal terminal S5 is at a low level, the seventh transistor T7 is turned on, and the second initialization signal of the second initialization signal terminal Vinit2 is provided to the anode of the light-emitting device L1 via the turned-on seventh transistor T7 to reset the anode of the light-emitting device L1.

[0122] In addition, the above-mentioned pixel driving circuit also includes a third initialization sub-circuit 700, which is coupled to the first end of the compensation capacitor C1 and is configured to respond to the signal of the third reset signal terminal S6 and provide the signal of the third initialization signal terminal Vinit3 to the first end of the compensation capacitor C1.

[0123] 5 , the third initialization sub-circuit 700 includes an eighth transistor T8 .

[0124] The connection relationship between the eighth transistor T8 and other components in Figure 5 is: the control terminal of the eighth transistor T8 is coupled to the third reset signal terminal S6, the first terminal of the eighth transistor T8 is coupled to the first terminal of the compensation capacitor C1, and the second terminal of the eighth transistor T8 is coupled to the third initialization signal terminal Vinit3.

[0125] During implementation, when the signal of the third reset signal terminal S6 is at a low level, the eighth transistor T8 is turned on, and the third initialization signal of the third initialization signal terminal Vinit3 is provided to the first end of the compensation capacitor C1 through the turned-on eighth transistor T8 to reset the first end of the compensation capacitor C1.

[0126] It should be noted that the cathode of the above-mentioned light-emitting device is coupled to the cathode power supply terminal ELVSS, and the voltage of the above-mentioned cathode power supply terminal ELVSS is lower than the voltage of the above-mentioned power signal terminal ELVDD. By setting the cathode power supply terminal ELVSS and the power signal terminal ELVDD, the normal operation of the light-emitting device L1 and the peripheral circuit can be guaranteed.

[0127] The working process of the pixel driving circuit in the embodiment of the present application is described in detail below in conjunction with the timing diagram 6 and FIG. 3 .

[0128] Timing T1 reset phase: S3 = 1, S1 = 0, S4 = 1, S5 = 0, S2 = 0

[0129] When S1 is a low level signal, the first transistor T1 is turned on, and the signal of the power signal terminal ELVDD is provided to the fifth node N5. The fifth node N5 is coupled to the second end of the compensation capacitor C1. At the same time, when S1 is a low level signal, the fifth transistor T5 is turned on. When S5 is a low-level signal, the sixth transistor T6 is turned on, and the signal of the first initialization signal terminal Vinit1 is provided to the second node N2, which is coupled to the first terminal of the sixth transistor. Simultaneously, when S5 is a low-level signal, the seventh transistor T7 is turned on, and the signal of the second initialization signal terminal Vinit2 is provided to the N4 node. Furthermore, the signal of the second initialization signal terminal Vinit2 is provided to the third node N3 via the fourth node N4 and the turned-on fifth transistor T5. The fourth node N4 is coupled to the anode of the light-emitting device, and the third node N3 is coupled to the second terminal of the driving transistor. Since, when S2 is a low-level signal, the second transistor T2 is turned on, the signal of the second initialization signal terminal Vinit2 is provided to the first node N1 via the third node N3 and the turned-on second transistor T2, which is coupled to the gate of the driving transistor. When S2 is a low-level signal, the second transistor T2 is turned on, and the signal of the first initialization signal terminal Vinit1 is provided to the second node N2.

[0130] Timing T2 compensation stage: S3 = 0, S1 = 1, S4 = 0, S5 = 1, S2 = 0

[0131] When S2 is a low-level signal, the second transistor T2 is turned on, and the driving transistor DTFT is turned on by the signal of the second initialization signal terminal Vinit2 at the first node N1. When S4 is a low-level signal, the fourth transistor T4 is turned on, and the signal of the power supply signal terminal ELVDD is provided to the driving transistor DTFT via the turned-on fourth transistor T4, causing the voltage at the gate of the driving transistor DTFT to change to Vth+VELVDD, where Vth is the threshold voltage of the driving transistor DTFT and VELVDD is the voltage of the power supply signal terminal ELVDD, which is the first terminal of the compensation capacitor C1. Because the first active level of the data writing sub-circuit 300 is within the time period of the second active level of the threshold compensation sub-circuit 200, that is, the start time of the low level of S3 is later than the start time of the low levels of S2 and S4, that is, when the compensation is about to end, S3 is a low-level signal, the third transistor T3 is turned on, and the data voltage of the data signal terminal Data is provided to the N5 node, which is the second terminal of the compensation capacitor C1, via the turned-on third transistor T3.

[0132] Timing T3 write phase: S3 = 1, S1 = 0, S4 = 0, S5 = 1, S2 = 1

[0133] When S1 is a low-level signal, the first transistor T1 is turned on, and the signal of the power signal terminal ELVDD is written into the second end of the compensation capacitor C1 through the turned-on first transistor T1 and the N5 node. The voltage at the second end of the compensation capacitor C1 jumps from the data voltage of the data signal terminal Data to VELVDD, and the voltage change is ELVDD-Data. Through the bootstrap effect of the above-mentioned compensation capacitor C1, the voltage change is coupled to the first end of the compensation capacitor C1. The voltage change at the first end of the compensation capacitor C1 is Vth+VELVDD+VELVDD-Data, that is, Vth-Data, so that the data voltage of the data signal terminal Data is written into the first node N1, that is, the gate of the driving transistor DTFT.

[0134] Timing T4 lighting stage: S3 = 1, S1 = 0, S4 = 0, S5 = 1, S2 = 1

[0135] When S1 is a low level signal, the fifth transistor T5 is turned on. When S4 is a low level signal, the fourth transistor T4 is turned on. The driving transistor DTFT generates a driving current. Exemplarily, the driving current Id=K*(VELVDD-Data) 2 , K is a constant, driving current is input into the light emitting device L1, thereby driving the light emitting device L1 to emit light.

[0136] Referring to FIG. 7 , based on the same inventive concept, an embodiment of the present disclosure provides a display panel comprising a substrate, the substrate comprising a plurality of sub-pixels, the sub-pixels comprising any of the above-described pixel driving circuits; the pixel driving circuit comprising: a driving transistor, a first transistor, a third transistor, and a compensation capacitor, wherein the first end of the first transistor is coupled to the second end of the compensation capacitor, the second end of the third transistor is coupled to the second end of the compensation capacitor, the gate of the driving transistor is coupled to the first end of the compensation capacitor, and the orthographic projection of the active layer of the third transistor on the substrate is located between the orthographic projection of the active layer of the driving transistor on the substrate and the orthographic projection of the active layer of the first transistor on the substrate. That is, the active layer of the newly added first transistor and the active layer of the third transistor coupled to the second end of the compensation capacitor are in the same layer.

[0137] Figure 7 is a schematic diagram of the layout structure of the pixel driving circuit provided in some embodiments of the present disclosure. Figures 8 to 15 are schematic diagrams of the various layers of the pixel driving circuit provided in some embodiments of the present disclosure. The examples shown in Figures 7 to 15 take the pixel driving circuit of a sub-pixel as an example. Figures 7 to 15 also show a first signal line S1, a fifth signal line S5 and a power signal line electrically connected to the pixel driving circuit. The power signal line is configured to input a voltage VELVDD to the power signal terminal ELVDD. For example, a plurality of signal lines can be arranged along a first direction F1.

[0138] For example, as shown in Figures 7 and 8, the first semiconductor layer of the pixel driving circuit is shown. The first semiconductor layer can be patterned using amorphous silicon or low-temperature polysilicon (LTPS) materials. The first semiconductor layer can be used to make the active layer of the first transistor T1, the active layer of the second transistor T2, the active layer of the third transistor T3, the active layer of the fifth transistor T5, the active layer of the sixth transistor T6, the active layer of the seventh transistor T7, and the active layer of the driving transistor DTFT. In addition, each active layer may include a first region, a second region, and a first channel region located between the first region and the second region. It should be noted that the first region and the second region can be regions in the first semiconductor layer doped with n-type impurities or p-type impurities to form conductive regions, so that the first region and the second region can serve as the source region and the drain region of the active layer for electrical connection.

[0139] For example, as shown in Figures 7 and 8, the active layer of the fifth transistor T5 can be extended roughly in a straight line along the second direction F2. For example, the extension direction of the active layer of the fifth transistor T5 is roughly parallel to the second direction F2. It should be noted that in actual processes, due to limitations of process conditions or other factors, the extension direction of the active layer of the fifth transistor T5 cannot be completely parallel to the second direction and may have some deviations. Therefore, as long as the extension direction of the active layer of the fifth transistor T5 and the second direction roughly meet the parallel condition, they are within the scope of protection of the present invention. For example, the above-mentioned parallel can be parallel to the extent allowed within the allowable error range.

[0140] Exemplarily, an insulating layer is formed on the first semiconductor layer to protect the first semiconductor layer. As shown in Figures 9 and 10, the first conductive layer of the pixel driving circuit is shown. The first conductive layer is arranged on the side of the substrate facing away from the first semiconductor layer, thereby being insulated from the first semiconductor layer. The first conductive layer may include: the gate of the first transistor T1, the gate of the second transistor T2, the gate of the third transistor T3, the gate of the fifth transistor T5, the gate of the sixth transistor T6, the gate of the seventh transistor T7, the gate of the driving transistor DTFT, the first signal line S1, the second signal line S2, the third signal line S3 and the fifth signal line S5. Exemplarily, the gate of the first transistor T1 may be the portion where the first signal line S1 overlaps with the first semiconductor layer. The gate of the driving transistor DTFT may be the portion where the first end of the compensation capacitor C1 overlaps with the first semiconductor layer.

[0141] As shown in Figure 10, the second conductive layer of the pixel driving circuit is shown. The second conductive layer is disposed on a side of the substrate facing away from the first conductive layer, and an insulating layer is disposed between the first and second conductive layers. The second conductive layer may include: the second end of the compensation capacitor C1, the gate of the third transistor, and the fifth signal line S5. For example, the gate of the third transistor T3 may be the portion where the fifth signal line S5 overlaps with the first semiconductor layer.

[0142] FIG11 shows the second semiconductor layer of the pixel driving circuit. The second semiconductor layer is disposed on the side of the substrate away from the second conductive layer. The second semiconductor layer can be made of a metal oxide semiconductor material. The second semiconductor layer can be used to form the active layer of the third transistor T3.

[0143] Moreover, the orthographic projection of the first signal line S1 on the substrate and the orthographic projection of the active layer of the first transistor T1 on the substrate have an overlapping area, that is, the gate of the first transistor T1 can be the portion where the first signal line S1 overlaps with the first semiconductor layer, and the gate T7-G of the second reset transistor T7 can be the portion where the fourth scan line GA4 overlaps with the first semiconductor layer.

[0144] As shown in Figure 11, the active layer of the first transistor T1 includes a first active portion 11 and a second active portion 12. The first active portion 11 extends along a first direction F1, and the second active portion 12 extends along a second direction F2. The orthographic projection of the first signal line S1 on the substrate overlaps with the orthographic projection of the first active portion 11 on the substrate. That is, the first active portion 11 and the second active portion 12 of the first transistor intersect, and the first active portion 11 and the second active portion 12 are arranged in two different directions. Furthermore, the first active portion 11 of the active layer of the first transistor T1 may be the portion where the first signal line S1 overlaps with the first semiconductor layer.

[0145] For example, as shown in FIG12 , the base substrate further includes a third conductive layer. Within the third conductive layer, the power signal line ELVDD, the fourth signal line S4, and the fifth signal line (Vinit2 and Vinit1 in FIG12 ) extend along a first direction F1. Furthermore, as shown in FIG13 , the power signal line ELVDD is also arranged along a second direction F2. Within each sub-pixel, the power signal lines ELVDD form a mesh-like connection structure. The above arrangement can be designed and determined based on actual application requirements and is not limited herein.

[0146] Exemplarily, the third conductive layer includes a first connecting portion 13, the second conductive layer includes a second connecting portion 14, a first insulating layer is provided between the third conductive layer and the second conductive layer, and a second insulating layer is provided between the second conductive layer and the first conductive layer. In other words, to ensure the normal operation of each conductive layer, insulating layers are provided between the first conductive layer, the second conductive layer, and the third conductive layer. Thus, the power signal line is connected to the second connecting portion 14 via a first via extending through the first insulating layer, and the second connecting portion is connected to the active layer of the first transistor T2 via a second via extending through the second insulating layer, thereby achieving conduction of the power signal line between the different conductive layers.

[0147] For example, as shown in FIG14 , the power signal line ELVDD and the first signal line S1 extend along the second direction F2. A first portion of the third signal line S3 extends along the second direction F2, and a second portion of the third signal line S3 extends in a direction that forms a 45-degree angle with the second direction F2 and is directed downward and to the left. A portion of the fourth signal line S4 extends in the second direction F2, and another portion of the fourth signal line S4 extends in a direction that forms a 45-degree angle with the second direction F2 and is directed upward and to the left. For example, as shown in FIG15 , the signal line connected to the anode of the light-emitting device extends in the second direction F2, and the signal line of the data signal terminal Data extends substantially in the second direction F2.

[0148] Based on the same inventive concept, an embodiment of the present disclosure provides a driving method for a pixel driving circuit, as shown in FIG16 , including:

[0149] Step 201: The threshold compensation sub-circuit provides the threshold voltage of the driving transistor to the first terminal of the compensation capacitor in response to the signal at the compensation signal terminal.

[0150] During implementation, when the signal at the compensation signal terminal is at a low level, the second transistor is turned on, and the threshold voltage of the driving transistor is written into the first terminal of the compensation capacitor.

[0151] Step 202: The data writing sub-circuit provides the data voltage of the data signal terminal to the second terminal of the compensation capacitor in response to the signal of the scan signal terminal.

[0152] During implementation, when the signal at the scan signal end is at a low level, the third transistor is turned on, and the data voltage at the data signal end is written into the second end of the compensation capacitor.

[0153] Step 203: The compensation capacitor stabilizes the voltages at the first terminal and the second terminal.

[0154] During implementation, the compensation capacitor is mainly used to stabilize the voltages at its first and second terminals. Due to the voltage stabilization function of the compensation capacitor, the threshold voltage of the driving transistor and the data voltage at the data signal terminal are written into the gate of the driving transistor.

[0155] Step 204: The conduction control sub-circuit connects the power signal terminal to the second terminal of the compensation capacitor in response to the signal of the conduction control terminal.

[0156] During implementation, when the signal at the conduction control terminal is at a low level, the loop connected to the light-emitting device is turned on, that is, the power signal terminal is turned on and the second end of the compensation capacitor is turned on, and the driving transistor generates a driving current according to the above threshold voltage and data voltage.

[0157] Step 205: The light emitting control sub-circuit provides the driving current generated by the driving transistor to the light emitting device in response to the signal at the light emitting control signal terminal.

[0158] During implementation, when the signal at the light emitting control signal terminal is at a low level, the light emitting control subcircuit is turned on, that is, the driving current generated by the driving transistor DTFT is provided to the anode of the light emitting device L1, so that the light emitting device L1 emits light.

[0159] It should be noted that the third transistor in the pixel driving circuit of the embodiment of the present application is an N-type transistor, and the other transistors are P-type transistors. In other embodiments, the above-mentioned third transistor is a P-type transistor, and the corresponding other transistors are N-type transistors.

[0160] In summary, in an embodiment of the present disclosure, a pixel driving circuit, a display panel and a driving method are provided. The pixel driving circuit includes: a driving transistor, a light-emitting device, a compensation capacitor, a threshold compensation sub-circuit, a data writing sub-circuit, a conduction control sub-circuit and a light-emitting control sub-circuit. The threshold compensation sub-circuit responds to the signal of the compensation signal end to provide the threshold voltage of the driving transistor to the first end of the compensation capacitor. The data writing sub-circuit responds to the signal of the scan signal end to provide the data voltage of the data signal end to the second end of the compensation capacitor. The conduction control sub-circuit responds to the signal of the conduction control end to conduct the power signal end and the second end of the compensation capacitor. The light-emitting control sub-circuit responds to the signal of the light-emitting control signal end to provide the driving current generated by the driving transistor to the light-emitting device. The setting of the compensation capacitor realizes the time-sharing of threshold compensation and data writing, which satisfies the display of the light-emitting device while achieving high-frequency refresh.

[0161] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program product systems. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0162] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program product systems according to the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0163] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0164] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0165] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A pixel driving circuit, wherein: include: A driving transistor, a light emitting device, a compensation capacitor, a threshold compensation subcircuit, a data writing subcircuit, a conduction control subcircuit and a light emitting control subcircuit; The threshold compensation subcircuit is coupled to the gate of the driving transistor and the first end of the compensation capacitor, and is configured to provide the threshold voltage of the driving transistor to the first end of the compensation capacitor in response to a signal at the compensation signal end; The data writing sub-circuit is coupled to the second end of the compensation capacitor and is configured to provide a data voltage of the data signal end to the second end of the compensation capacitor in response to a signal of the scan signal end; The compensation capacitor is configured to stabilize the voltages at the first end and the second end; The conduction control subcircuit is coupled to the second end of the compensation capacitor and the power signal end, and is configured to conduct the power signal end and the second end of the compensation capacitor in response to a signal at the conduction control end; The light emitting control subcircuit is coupled to the driving transistor and the light emitting device, and is configured to provide the driving current generated by the driving transistor to the light emitting device in response to a signal at the light emitting control signal terminal.

2. The pixel driving circuit according to claim 1, wherein: The conduction control subcircuit includes: a first transistor; The control terminal of the first transistor is coupled to the conduction control terminal, the first terminal of the first transistor is coupled to the second terminal of the compensation capacitor, and the second terminal of the first transistor is coupled to the power signal terminal.

3. The pixel driving circuit according to claim 1, wherein: The data writing subcircuit provides the data voltage of the data signal terminal to the second terminal of the compensation capacitor in response to the first effective level of the signal of the scanning signal terminal; The threshold compensation subcircuit provides the threshold voltage of the driving transistor to the first terminal of the compensation capacitor in response to the second effective level of the signal at the compensation signal terminal; The first effective level is within a time period of the second effective level.

4. The pixel driving circuit according to claim 3, wherein: A high level duration of the first effective level is shorter than a low level duration of the second effective level.

5. The pixel driving circuit according to any one of claims 1 to 4, wherein: The threshold compensation subcircuit includes: a second transistor; The control terminal of the second transistor is coupled to the compensation signal terminal, the first terminal of the second transistor is coupled to the first terminal of the compensation capacitor, and the second terminal of the second transistor is coupled to the second terminal of the driving transistor.

6. The pixel driving circuit according to any one of claims 1 to 5, wherein: The data writing sub-circuit comprises: a third transistor; The control end of the third transistor is coupled to the scan signal end, the first end of the third transistor is coupled to the data signal end, and the second end of the third transistor is coupled to the second end of the compensation capacitor.

7. The pixel driving circuit according to any one of claims 1 to 6, wherein: The light emitting control subcircuit comprises: a fourth transistor and a fifth transistor; The control terminal of the fourth transistor is coupled to the light emitting control signal terminal, the first terminal of the fourth transistor is coupled to the power signal terminal, and the second terminal of the fourth transistor is coupled to the first terminal of the driving transistor; The control terminal of the fifth transistor is coupled to the conduction control terminal, the first terminal of the fifth transistor is coupled to the second terminal of the driving transistor, and the second terminal of the fifth transistor is coupled to the anode of the light emitting device.

8. The pixel driving circuit according to any one of claims 1 to 7, wherein: It also includes a first initialization sub-circuit, which is coupled to the first end of the driving transistor and is configured to provide a signal from a first initialization signal end to the first end of the driving transistor in response to a signal from a first reset signal end.

9. The pixel driving circuit according to claim 8, wherein: The first initialization sub-circuit includes: a sixth transistor; The control terminal of the sixth transistor is coupled to the first reset signal terminal, and the One end is coupled to the first end of the driving transistor, and the second end of the sixth transistor is coupled to the first initialization signal end.

10. The pixel driving circuit according to any one of claims 1 to 9, wherein: The device further includes a second initialization subcircuit, which is coupled to the anode of the light-emitting device and configured to provide a signal from a second initialization signal terminal to the anode of the light-emitting device in response to a signal from a second reset signal terminal.

11. The pixel driving circuit according to claim 10, wherein: The second initialization sub-circuit comprises: a seventh transistor; The control terminal of the seventh transistor is coupled to the second reset signal terminal, the first terminal of the seventh transistor is coupled to the anode of the light emitting device, and the second terminal of the seventh transistor is coupled to the second initialization signal terminal.

12. The pixel driving circuit according to any one of claims 1 to 11, wherein: It also includes a third initialization sub-circuit, which is coupled to the first end of the compensation capacitor and is configured to provide a signal from the third initialization signal end to the first end of the compensation capacitor in response to a signal from the third reset signal end.

13. The pixel driving circuit according to claim 12, wherein: The third initialization sub-circuit comprises: an eighth transistor; The control terminal of the eighth transistor is coupled to the third reset signal terminal, the first terminal of the eighth transistor is coupled to the first terminal of the compensation capacitor, and the second terminal of the eighth transistor is coupled to the third initialization signal terminal.

14. A display panel, wherein: include: A substrate, comprising a plurality of sub-pixels, wherein the sub-pixels include a pixel driving circuit as claimed in any one of claims 1 to 13; The pixel driving circuit comprises: a driving transistor, a first transistor, a third transistor and a compensation capacitor, wherein a first end of the first transistor is coupled to a second end of the compensation capacitor, a second end of the third transistor is coupled to a second end of the compensation capacitor, and a gate of the driving transistor is coupled to a first end of the compensation capacitor; The orthographic projection of the active layer of the third transistor on the base substrate is located between the orthographic projection of the active layer of the driving transistor on the base substrate and the orthographic projection of the active layer of the first transistor on the base substrate.

15. The display panel according to claim 14, wherein: The display panel comprises: a first semiconductor layer, a first conductive layer, a second conductive layer, and a second semiconductor layer; The first semiconductor layer is located on the substrate, and the first semiconductor layer includes an active layer of the first transistor and an active layer of the driving transistor; The first conductive layer is located on a side of the substrate away from the first semiconductor layer, and the first conductive layer includes a gate of the first transistor, a gate of the driving transistor, and a first signal line; The second conductive layer is located on a side of the substrate away from the first conductive layer, and the second conductive layer includes a second end of the compensation capacitor, a gate of the third transistor and a fifth signal line; The second semiconductor layer is located on a side of the substrate away from the second conductive layer, and the second semiconductor layer includes an active layer of a third transistor.

16. The display panel according to claim 14, wherein: An orthographic projection of the first signal line on the base substrate and an orthographic projection of an active layer of the first transistor on the base substrate have an overlapping region, and the first signal line in the overlapping region is a gate of the first transistor.

17. The display panel according to claim 16, wherein: The active layer of the first transistor includes a first active portion and a second active portion, the first active portion extends along a first direction, the second active portion extends along a second direction, and an orthographic projection of the first signal line on the substrate and an orthographic projection of the first active portion on the substrate have an overlapping area.

18. The display panel according to claim 14, wherein: It also includes a third conductive layer, which is located on a side of the substrate away from the second semiconductor layer. The third conductive layer includes a power signal line connected to the power signal terminal, and the power signal line covers the overlapping area.

19. The display panel according to claim 14, wherein: The third conductive layer includes a first connecting portion, the second conductive layer includes a second connecting portion, a first insulating layer is provided between the third conductive layer and the second conductive layer, and a second insulating layer is provided between the second conductive layer and the first conductive layer; The power signal line is connected to the second connection portion through a first via hole penetrating the first insulating layer; The second connection portion is connected to the active layer of the first transistor through a second via hole penetrating the second insulating layer.

20. A driving method for a pixel driving circuit according to any one of claims 1 to 13, wherein: include: The threshold compensation subcircuit provides the threshold voltage of the driving transistor to the first terminal of the compensation capacitor in response to the signal at the compensation signal terminal; The data writing sub-circuit provides the data voltage of the data signal terminal to the second terminal of the compensation capacitor in response to the signal of the scanning signal terminal; The compensation capacitor stabilizes the voltages at the first end and the second end; The conduction control subcircuit conducts the power signal terminal with the second terminal of the compensation capacitor in response to the signal of the conduction control terminal; The light emitting control subcircuit provides the driving current generated by the driving transistor to the light emitting device in response to the signal at the light emitting control signal terminal.

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