Multilayer capacitor

Abstract

The invention relates to a multilayer capacitor, a circuit board including the multilayer capacitor, and an integrated circuit package including the multilayer capacitor. A multilayer capacitor includes a body having a top surface, a bottom surface, opposing side surfaces, and opposing end surfaces, and containing alternating dielectric layers and internal electrode layers. Each internal electrode layer includes at least one lead tab extending from at least one of a top edge and a bottom edge of a body of the internal electrode layer. The capacitor also includes external terminals electrically connected to the internal electrode layers and arranged in a linear manner on at least one of the top surface or the bottom surface. The external terminals are spaced apart from the side edges of the body such that only the dielectric material is disposed between the external terminals and the side edges of the body.

Description

[0001] Related Applications

[0002] This application is based on and claims priority from U.S. Provisional Patent Application No. 63 / 420,722, filed on October 31, 2022, which is incorporated herein by reference. Background Art

[0003] Multilayer capacitors are typically constructed with multiple dielectric layers and multiple internal electrode layers in a stacked arrangement. During manufacturing, the stacked dielectric layers and internal electrode layers are pressed and sintered to obtain a substantially unitary capacitor body. In order to improve the performance of these capacitors, various configurations and designs have been adopted for the dielectric layers and internal electrode layers.

[0004] However, as the electronics industry undergoes rapid changes, new performance standards are required, often manipulating these configurations. In particular, various application design considerations have necessitated the need to redefine capacitor parameters and their performance in high-speed environments, especially as integrated circuits become faster and denser. For example, higher currents, denser circuit boards, and rising costs have all focused on the need for better and more efficient capacitors. In addition, the design of various electronic components has been driven by the overall industry trend toward miniaturization and increased functionality.

[0005] In this regard, a need exists to provide a capacitor having improved operating characteristics. Summary of the invention

[0006] According to one embodiment of the present invention, a multilayer capacitor is disclosed. The multilayer capacitor includes a body having a top surface, a bottom surface opposite to the top surface, a pair of side surfaces opposite to each other in a transverse direction, and a pair of end surfaces opposite to each other in a longitudinal direction. The body also has side edges, which define the transverse boundaries of the top surface and the bottom surface, and the side edges include a first top side edge, a second top side edge, a first bottom side edge, and a second bottom side edge, and the first top side edge, the second top side edge, the first bottom side edge, and the second bottom side edge each extend between the pair of end surfaces along the longitudinal direction. The first top side edge and the second top side edge are opposite to each other in the transverse direction, and the first bottom side edge and the second bottom side edge are opposite to each other in the transverse direction. The body includes alternating dielectric layers and internal electrode layers. The internal electrode layers include a first internal electrode layer and a second internal electrode layer. Each internal electrode layer includes: a body having a top edge, a bottom edge opposite to the top edge, and two side edges extending between the top edge and the bottom edge; and at least one lead tab extending from the top edge of the body of the internal electrode layer and at least one lead tab extending from the bottom edge of the body of the internal electrode layer. The multilayer capacitor also has external terminals, which include a first external terminal disposed on at least one of the top surface or the bottom surface and electrically connected to the first internal electrode layers, and a second external terminal disposed on at least one of the top surface or the bottom surface and electrically connected to the second internal electrode layers. The external terminals are arranged in a linear manner on at least one of the top surface or the bottom surface of the body and are spaced apart from the side edges of the body, so that only dielectric material is disposed between the external terminals and the side edges of the body.

[0007] Other features and aspects of the invention are set forth in more detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A full and enabling disclosure of the invention, including the best mode thereof, to one skilled in the art, is more particularly set forth in the remainder of the specification, including with reference to the accompanying drawings, in which:

[0009] Figure 1A Shows a general top and side exterior perspective view of one embodiment of a capacitor including two exterior terminals according to the present invention;

[0010] Figure 1B Shows Figure 1A A side view of an internal electrode layer of a capacitor;

[0011] Figure 1C Shows Figure 1A and Figure 1BA three-dimensional top and side external stereogram of an internal electrode layer of a capacitor;

[0012] Figure 1D Shows Figures 1A to 1C A top external view of a capacitor;

[0013] Figure 2A shows a general top and side exterior perspective view of another embodiment of a capacitor according to the present invention including four exterior terminals;

[0014] Figure 2B Shows Figure 2A A side view of an internal electrode layer of a capacitor;

[0015] Figure 2C Shows Figure 2A and Figure 2B A three-dimensional top and side external stereogram of an internal electrode layer of a capacitor;

[0016] Figure 2D Shows FIG. 2A to FIG. 2C A top external view of a capacitor;

[0017] Figure 3A shows a general top and side exterior perspective view of one embodiment of a capacitor including two exterior terminals according to the present invention;

[0018] Figure 3B Shows Figure 3A A side view of an internal electrode layer of a capacitor;

[0019] Figure 3C yes Figure 3A and Figure 3B A top external view of a capacitor;

[0020] Figure 4 The invention is shown mounted on a mounting surface. Figure 3A a three-dimensional diagram of a capacitor; and

[0021] Figure 5 A side view of a printed circuit board and integrated circuit package containing a capacitor according to the present invention is shown. DETAILED DESCRIPTION

[0022] Those skilled in the art will appreciate that this discussion is merely a description of exemplary embodiments and is not intended to limit the broader aspects of the invention.

[0023] In general, the present invention relates to a multilayer capacitor. The multilayer capacitor (or simply capacitor) includes a body having alternating dielectric layers and internal electrode layers. The body has at least a pair of end surfaces and a pair of side surfaces. External terminals are formed on the body of the capacitor, and the external terminals are spaced apart from at least a pair of side surfaces of the body. The external terminals are arranged in a linear manner in a single dimension so that only dielectric material is disposed between at least two sides of each external terminal and adjacent edges of the capacitor surface on which the external terminals are disposed.

[0024] The specific arrangement of the components of the capacitor can provide several advantages. For example, the capacitor of the present invention can be mounted on a circuit board as a surface mount capacitor and can occupy a smaller area on the circuit board. This in turn can also allow the size of the circuit board to be reduced.

[0025] In addition, in certain applications, it is desirable to maintain as low an inductance (i.e., parasitic inductance) as possible. Using the capacitor of the present invention allows for a significant reduction in inductance. In particular, minimizing the distance or path to ground can help reduce the inductance. In general, using the capacitor of the present invention can allow the inductance to be reduced by at least one order of magnitude compared to using multiple separate multilayer ceramic capacitors. For example, using the capacitor of the present invention can produce an inductance of the picohenry level or even the femtohenry level compared to the prior art capacitors that exhibit a larger magnitude of inductance. In general, the inductance can be less than 1 nanohenry. In particular, the inductance can be 900 picohenries or less, such as 750 picohenries or less, such as 500 picohenries or less, such as 400 picohenries or less, such as 250 picohenries or less, such as 100 picohenries or less, such as 50 picohenries or less, such as 25 picohenries or less, such as 15 picohenries or less, such as 10 picohenries or less. The inductance may be 1 femtohenry or greater, such as 25 femtohenry or greater, such as 50 femtohenry or greater, such as 100 femtohenry or greater, such as 250 femtohenry or greater, such as 500 femtohenry or greater, such as 750 femtohenry or greater. Minimizing the inductance may result in good performance, particularly good decoupling performance, especially good decoupling performance under high-speed transient conditions.

[0026] In addition, the capacitor can provide a desired capacitance. In particular, the capacitance can be 1000 microfarads (μF) or less, such as 750 μF or less, such as 500 μF or less, such as 250 μF or less, such as 100 μF or less, such as 50 μF or less, such as 25 μF or less, such as 20 μF or less, such as 15 μF or less, such as 10 μF or less, such as 5 μF or less, such as 2.5 μF or less, such as 1 μF or less, such as 0.75 μF or less, such as 0.5 μF or less. The capacitance may be 1 picofarad (pF) or greater, such as 10 pF or greater, such as 25 pF or greater, such as 50 pF or greater, such as 100 pF or greater, such as 250 pF or greater, such as 500 pF or greater, such as 750 pF or greater, such as 900 pF or greater, such as 1 μF or greater, such as 2 μF or greater, such as 3 μF or greater, such as 5 μF or greater, such as 8 μF or greater, such as 10 μF or greater. Capacitance may be measured using common techniques known in the art.

[0027] In addition, the capacitor can provide a desired resistance. In particular, the resistance can be 100 milliohms (mOhm) or less, such as 75mOhm or less, such as 50mOhm or less, such as 40mOhm or less, such as 30mOhm or less, such as 25mOhm or less, such as 20mOhm or less, such as 15mOhm or less, such as 10mOhm or less, such as 5mOhm or less. The resistance can be 0.01mOhm or more, such as 0.1mOhm or more, such as 0.25mOhm or more, such as 0.5mOhm or more, such as 1mOhm or more, such as 1.5mOhm or more, such as 2mOhm or more, such as 5mOhm or more, such as 10mOhm or more. The resistance can be measured using general techniques known in the art.

[0028] As described above, the present invention includes a multilayer capacitor, which includes a body having a top surface and a bottom surface opposite to the top surface. The body of the capacitor also includes at least one side surface extending between the top surface and the bottom surface, in particular at least two side surfaces. The capacitor may include at least one end surface extending between the top surface and the bottom surface, in particular at least two end surfaces. In general, the side surface extends in the longitudinal direction or the length (L) direction and generally has a longer dimension than the end surface, and the end surface extends in the transverse direction or the width (W) direction and generally has a shorter dimension. In one embodiment, the capacitor includes at least a total of six surfaces (e.g., a top surface, a bottom surface, two side surfaces, and two end surfaces). For example, the capacitor may have a parallelepiped shape, such as a cuboid shape.

[0029] In addition, the capacitor may have a desired height. For example, the height may be 10 microns or more, such as 25 microns or more, such as 50 microns or more, such as 100 microns or more, such as 200 microns or more, such as 250 microns or more, such as 300 microns or more, such as 350 microns or more, such as 400 microns or more, such as 450 microns or more, such as 500 microns or more, such as 1000 microns or more, such as 2000 microns or more. The height may be 5000 microns or less, such as 4000 microns or less, such as 2500 microns or less, such as 2000 microns or less, such as 1000 microns or less, such as 750 microns or less, such as 600 microns or less, such as 500 microns or less, such as 450 microns or less. When the capacitor is surrounded by a ball grid array, the height of the capacitor can be within 10%, such as within 7%, such as within 5%, such as within 3%, such as within 2%, such as within 1% of the height (or diameter) of the balls of the ball grid array. For example, this height can be the original height before any reflow.

[0030] The capacitor may have a desired length. For example, the length may be 10 microns or more, such as 25 microns or more, such as 50 microns or more, such as 100 microns or more, such as 200 microns or more, such as 250 microns or more, such as 300 microns or more, such as 350 microns or more, such as 400 microns or more, such as 450 microns or more, such as 500 microns or more, such as 1000 microns or more, such as 1500 microns or more, such as 2000 microns or more, such as 2500 microns or more, such as 3000 microns or more, such as 3500 microns or more, such as 4000 microns or more. The length can be 10000 microns or less, for example 8000 microns or less, for example 6000 microns or less, for example 5000 microns or less, for example 4000 microns or less, for example 3000 microns or less, for example 2500 microns or less, for example 2000 microns or less, for example 1000 microns or less, for example 750 microns or less, for example 600 microns or less, for example 500 microns or less, for example 450 microns or less.

[0031] The capacitor may also have a desired width. For example, the width may be 10 microns or more, such as 25 microns or more, such as 50 microns or more, such as 100 microns or more, such as 200 microns or more, such as 250 microns or more, such as 300 microns or more, such as 350 microns or more, such as 400 microns or more, such as 450 microns or more, such as 500 microns or more, such as 750 microns or more, such as 1000 microns or more, such as 1500 microns or more, such as 2000 microns or more, such as 2500 microns or more, such as 3000 microns or more. The width can be 5000 microns or less, for example 4000 microns or less, for example 3000 microns or less, for example 2500 microns or less, for example 2000 microns or less, for example 1500 microns or less, for example 1000 microns or less, for example 750 microns or less, for example 600 microns or less, for example 500 microns or less, for example 450 microns or less.

[0032] In general, a multilayer capacitor comprises a set of alternating dielectric layers and internal electrode layers. In general, a capacitor comprises at least one set of alternating dielectric layers and internal electrode layers. The capacitor may also comprise a second set of alternating dielectric layers and internal electrode layers. In this regard, the capacitor may comprise at least two sets of alternating dielectric layers and internal electrode layers, such as at least three sets of alternating dielectric layers and internal electrode layers, such as at least four sets of alternating dielectric layers and internal electrode layers. However, it should be understood that the present invention may comprise any number of sets of alternating dielectric layers and internal electrode layers, and need not be limited. In addition, each set of alternating dielectric layers and internal electrode layers may be spaced a certain distance from an adjacent set. For example, the distance is greater than the thickness of a single dielectric layer in the set. In particular, the distance may be at least twice the thickness of a dielectric layer in the set, such as at least 3 times, such as at least 5 times, such as at least 10 times.

[0033] One or more sets of alternating dielectric layers and internal electrode layers may form at least a portion of the body of the capacitor. By arranging the dielectric layers and internal electrode layers in a stacked or laminated configuration, the capacitor may be referred to as a multilayer capacitor, particularly, for example, a multilayer ceramic capacitor when the dielectric layers comprise ceramic.

[0034] The capacitor also includes an external terminal electrically connected to the internal electrode layer. The external terminal is formed at least on the top surface of the capacitor and the bottom surface of the capacitor opposite to the top surface of the capacitor. In some embodiments, the external terminal may include a first end external terminal and a second end external terminal, and one or both of the first end external terminal and the second end external terminal may also be formed on a corresponding end surface adjacent to the corresponding end external terminal.

[0035] The alternating dielectric layers and internal electrode layers include dielectric layers arranged alternately with internal electrode layers. In particular, the internal electrode layers include first internal electrode layers and second internal electrode layers, the first internal electrode layers and the second internal electrode layers are interlaced in an opposing and spaced relationship, wherein the dielectric layers are located between each internal electrode layer.

[0036] In general, the thickness of the dielectric layer and the thickness of the internal electrode layer are not limited and can be any thickness required according to the performance characteristics. For example, the thickness of the internal electrode layer can be, but is not limited to, about 500 nanometers (nm) or more (e.g., about 1 micrometer (μm) or more, such as about 2 μm or more) to about 10 μm or less (e.g., about 5 μm or less, such as about 4 μm or less, such as about 3 μm or less, such as about 2 μm or less). For example, the internal electrode layer can have a thickness from about 1 μm to about 2 μm.

[0037] In addition, the present invention is not necessarily limited by the number of internal electrode layers in each set of alternating dielectric layers and internal electrode layers or the number of internal electrode layers in the entire capacitor. For example, each set may include the following number of internal electrode layers: 10 or more, such as 25 or more, such as 50 or more, such as 100 or more, such as 200 or more, such as 300 or more, such as 500 or more, such as 600 or more, such as 750 or more, such as 1000 or more. Each set may include the following number of internal electrode layers: 5000 or less, such as 4000 or less, such as 3000 or less, such as 2000 or less, such as 1500 or less, such as 1000 or less, such as 750 or less, such as 500 or less, such as 400 or less, such as 300 or less, such as 250 or less, such as 200 or less, such as 175 or less, such as 150 or less. In addition, the entire capacitor may include the aforementioned number of electrode layers.

[0038] The internal electrode layer has a top edge and a bottom edge opposite the top edge. The internal electrode layer also has two side edges extending between the top edge and the bottom edge. In one embodiment, the side edges, the top edge, and the bottom edge define a body of the internal electrode layer. Generally speaking, the body of the internal electrode layer can have a rectangular configuration or a rectangular shape.

[0039] In general, the top edge and the bottom edge may have the same size (e.g., length—L direction). Each side edge may have the same size (e.g., height—T direction). In general, the side edge may have a size (e.g., height—T direction) that is shorter than the size (e.g., length—L direction) of the top edge and / or the bottom edge. In this regard, the height of the side edge of the internal electrode layer when it extends between the top and bottom surfaces of the capacitor may be less than the length of the top and / or bottom edges of the internal electrode layer when the top and / or bottom edges of the internal electrode layer extend between the end surfaces of the capacitor. In other words, the internal electrode layer may have a top edge and / or a bottom edge that is larger than the side edge that is smaller in size. In this regard, the "short" side of the layer may be registered with the height direction of the capacitor.

[0040] The internal electrode layers have lead tabs extending from the body of each internal electrode layer. The lead tabs extend from the top edge and the bottom edge. In other words, the internal electrode layers can have lead tabs extending from the "long" side or "long" edge of the internal electrode layer. The lead tabs can extend to the edge of the dielectric layer and / or the surface of the capacitor. For example, when in a stacked configuration, the leading edge of the lead tab can extend to the edge of the dielectric layer. The leading edge can be used to form an external terminal. In addition, the top edge and the bottom edge of the layer can have at least one lead tab extending therefrom, such as at least two lead tabs, such as at least three lead tabs, such as at least four lead tabs.

[0041] Each top edge and bottom edge of the internal electrode layer can have the same number of lead tabs extending therefrom. For example, each top edge and bottom edge can have at least one lead tab extending therefrom. In another embodiment, each top edge and bottom edge can have at least two lead tabs extending therefrom. However, it should be understood that the present invention can include any number of lead tabs extending from the internal electrode layer and is not necessarily limited.

[0042] In one embodiment, at least one lead tab extends from the top edge and the bottom edge of the body of the internal electrode layer, and the edges of the lead tab are aligned with the side edges of the body of the internal electrode layer. For example, at least one lateral edge (i.e., an edge aligned in the height direction) of the lead tab can be substantially aligned with a corresponding side edge of the body of the internal electrode layer. In this regard, at least one lead tab may not deviate from the side edge of the internal electrode layer.

[0043] However, in some embodiments, at least one lead tab may be offset from a side edge of the internal electrode layer. For example, an edge of each lead tab is parallel to a side edge of the body of the internal electrode layer along the length direction or L direction, but is spaced apart from the side edge of the body of the internal electrode layer. For example, at least one lateral edge (i.e., an edge aligned in the height direction) of each lead tab may be substantially parallel to a corresponding side edge of the body of the internal electrode layer, but offset from the side edge of the internal electrode layer along the length of the body of the internal electrode layer.

[0044] Additionally or alternatively, when there may be more than one lead tab along an edge, the corresponding lead tabs may extend from the inner portions of the top and bottom edges of the body of the internal electrode layer. In this regard, the lead tabs may not extend directly from the side edges of the internal electrode layer. In other words, the lead tabs may be offset from the side edges of the internal electrode layer (e.g., in the length direction or L direction). The offset may cause the lead tab to deviate and be positioned between the side edges of the internal electrode layer, particularly at a position of at least 50% of the length of the internal electrode layer (e.g., beyond the center of the internal electrode layer).

[0045] Each lead tab extending from the top edge of each internal electrode layer and the bottom edge of the same internal electrode layer may be offset from the side edge by the same distance. In this regard, at least one lateral edge (i.e., an edge aligned in the height direction) of each lead tab may be substantially aligned. In one embodiment, two lateral edges of each lead tab may be substantially aligned.

[0046] Similarly, the length of the lead tab extending from the top edge (ie, the length extending from one end surface to the other end surface in the longitudinal direction) may be the same as the length of the corresponding lead tab extending from the bottom edge.

[0047] The length of each lead tab can be 0.3 millimeters (mm) or more, such as 0.4 mm or more, such as 0.5 mm or more, such as 0.6 mm or more, such as 0.7 mm or more. The length of each lead tab can be 1.1 or less, such as 0.9 or less, such as 0.8 or less, such as 0.7 or less, such as 0.6 or less, such as 0.5 or less. When there is more than one lead tab along an edge, each lead tab can have the same length.

[0048] In another embodiment, each lead tab may have a different length. For example, for an internal electrode layer having more than one lead tab extending from a top edge or a bottom edge, a lead tab that is substantially aligned with a side edge of the internal electrode layer may have a greater length than a lead tab that is offset from a side edge of the internal electrode layer. In this regard, the ratio of the length of the lead tab aligned with the side edge of the internal electrode layer to the length of the lead tab that is offset from the side edge of the internal electrode layer may be 0.3 or greater, such as 0.5 or greater, such as 0.7 or greater, such as 0.9 or greater, such as 1 or greater, such as 1.1 or greater, such as 1.2 or greater, such as 1.3 or greater, such as 1.4 or greater, such as 1.5 or greater. The ratio may be 5 or less, such as 4 or less, such as 3 or less, such as 2 or less, such as 1.8 or less, such as 1.7 or less, such as 1.6 or less, such as 1.5 or less, such as 1.4 or less.

[0049] Approximately aligned means that the offset of one lateral edge and side edge of the first lead tab and / or the second lead tab on the top edge is within + / -10%, for example within + / -5%, for example within + / -4%, for example within + / -3%, for example within + / -2%, for example within + / -1%, for example within + / -0.5% relative to the offset of the corresponding lateral edge and side edge of the first lead tab and / or the second lead tab on the bottom edge.

[0050] When the dielectric layer and the internal electrode layer are stacked together as described herein, the aligned lead tabs form the columns of so-called lead tabs or electrode tabs. The distance between each adjacent exposed lead tab of the internal electrode layer in a given column can be specially designed to ensure the guiding shaping of each termination. The distance between each exposed lead tab of the internal electrode layer in a given column can be about 10 microns or less, such as about 8 microns or less, such as about 5 microns or less, such as about 4 microns or less, such as about 2 microns or less, such as about 1.5 microns or less, such as about 1 micron or less. The distance can be about 0.25 micron or more, such as about 0.5 micron or more, such as about 1 micron or more, such as about 1.5 microns or more, such as about 2 microns or more, such as about 3 microns or more. However, it should be understood that the distance can be limited.

[0051] In addition, the distance between adjacent electrode tab columnar stacks may be, but is not limited to, at least twice the distance between adjacent lead tabs in a given column to ensure that different terminations are not connected together. In some embodiments, the distance between adjacent columnar stacks of exposed metallization is about four times the distance between adjacent exposed electrode tabs in a particular stack. However, this distance may vary depending on the desired capacitance performance and circuit board configuration.

[0052] The distance may be 0.1 mm or greater, such as 0.2 mm or greater, such as 0.3 mm or greater, such as 0.4 mm or greater, such as 0.5 mm or greater, such as 0.6 mm or greater. The distance may be 1.5 mm or less, such as 1.3 mm or less, such as 1 mm or less, such as 0.9 mm or less, such as 0.7 mm or less, such as 0.6 mm or less, such as 0.5 mm or less, such as 0.4 mm or less. In one embodiment, the distance may be determined based on the center point of each lead tab. In another embodiment, the distance may be based on the distance between adjacent lateral edges of the lead tab. In addition, the distance may correspond to the spacing distance of the balls on the ball grid array.

[0053] Within a set of alternating dielectric layers and internal electrode layers, the lead tabs of a first internal electrode layer and the lead tabs of a second internal electrode layer are offset from each other in a longitudinal direction or length direction. That is, the lead tabs of each internal electrode layer can be symmetrically offset from a center line of the internal electrode layer and / or the dielectric layer by a certain distance (e.g., symmetrically offset from a longitudinal center line of the internal electrode layer and / or the dielectric layer by a certain distance or symmetrically offset with respect to a vertical line of the internal electrode layer and / or the dielectric layer). That is, the lead tabs of each internal electrode layer can be symmetrically offset with respect to a vertical line of the internal electrode layer and / or the dielectric layer. In any case, a gap area will be formed between the lead tabs of each internal electrode layer.

[0054] In addition, regardless of the number of lead tabs extending from the internal electrode layers, the internal electrode layers may be symmetrical in a given direction. For example, the lead tabs may be symmetrical about a horizontal line passing through the center of the body of the internal electrode layer (i.e., a line extending from the center of one side edge of the internal electrode layer to the center of the other side edge).

[0055] In addition, as indicated herein, each internal electrode layer includes at least two side edges. When stacked to form the body of the capacitor, these side edges of the alternating internal electrode layers may not be substantially aligned with each other. For example, the side edges may be offset from each other. In addition, in at least some embodiments, the side edges may be offset from the side surface of the body of the capacitor.

[0056] The capacitor of the present invention also includes external terminals located on the top and bottom surfaces of the body of the capacitor. The external terminals are spaced apart from the side surfaces of the body of the capacitor so that only dielectric material is disposed between the external terminals and the side surfaces of the body. In some embodiments, the capacitor also includes external terminals on the opposite end surfaces of the capacitor body, but in other embodiments, in addition to being spaced apart from the side surfaces, the external terminals are also spaced apart from at least one of the opposite end surfaces so that only dielectric material is disposed between the external terminals and at least one end surface.

[0057] The external terminals include at least one first polarity terminal and at least one second opposite polarity terminal. The capacitor may include the following number of first polarity terminals and / or second opposite polarity terminals on the top surface of the body of the capacitor: at least one, such as at least two, such as at least four, such as at least six, such as at least eight. In addition, the capacitor may include the above number of terminals on the bottom surface of the body of the capacitor.

[0058] The capacitor may include an equal number of first polarity terminals and / or second polarity terminals on the top surface and the bottom surface. On the top surface, the number of first polarity terminals may be equal to the number of second opposite polarity terminals. On the bottom surface, the number of first polarity terminals may be equal to the number of second opposite polarity terminals. The total number of terminals present on the top surface of the capacitor may be equal to the total number of terminals present on the bottom surface of the capacitor. The total number of first polarity terminals present on the top and bottom surfaces of the capacitor may be equal to the total number of second opposite polarity terminals present on the top and bottom surfaces of the capacitor.

[0059] Generally speaking, the terminals of similar polarity corresponding to a particular set of alternating dielectric layers and internal electrode layers on the bottom surface of the capacitor are electrically connected to the terminals of similar polarity on the top surface of the capacitor. The terminals of similar polarity located on the top and bottom surfaces of the capacitor may not be staggered. In this regard, the terminals of similar polarity corresponding to the top and bottom surfaces may not be deviated by the terminal position, but may be located directly above or below another terminal of similar polarity on the opposite top or bottom surface. In other words, the corresponding terminals of similar polarity corresponding to a particular group of lead tabs may be roughly aligned. Roughly aligned means that the offset of one lateral edge of the polarity terminal on the top surface to the side edge is within + / -10%, such as within + / -5%, such as within + / -4%, such as within + / -3%, such as within + / -2%, such as within + / -1%, such as within + / -0.5%.

[0060] In general, the spacing of the external terminals (i.e., the nominal distance between the centers, also referred to as the center-to-center spacing) can be determined by the specific circuit board construction. The spacing of the external terminals in one direction (i.e., the x-direction or the y-direction) can be the same as the spacing of adjacent external terminals in another direction (i.e., the y-direction or the x-direction, respectively). In other words, the spacing between any two adjacent external terminals can be approximately the same as the spacing between any other two adjacent external terminals.

[0061] The spacing may be about 0.1 mm or more, such as about 0.2 mm or more, such as about 0.3 mm or more, such as 0.4 mm or more, such as about 0.5 mm or more, such as about 0.6 mm or more, such as about 0.7 mm or more, such as about 0.8 mm or more, such as about 0.9 mm or more, such as about 1.0 mm or more. The spacing may be about 2.0 mm or less, such as about 1.5 mm or less, such as about 1.4 mm or less, such as about 1.3 mm or less, such as about 1.2 mm or less, such as about 1.1 mm or less, such as about 1.0 mm or less. For example, the spacing may be about 0.2 mm, about 0.4 mm, about 0.6 mm, about 0.8 mm, about 1.0 mm, about 1.2 mm, etc. In particular, the spacing may be 0.6 mm, 0.8 mm or 1.0 mm. In one embodiment, the spacing may be about 0.6 mm, such as 0.6 mm + / - 10% (e.g., + / - 5%, such as + / - 2%, such as + / - 1%). In another embodiment, the spacing may be about 0.8 mm, such as 0.8 mm + / - 10% (e.g., + / - 5%, such as + / - 2%, such as + / - 1%). In yet another embodiment, the spacing may be about 1 mm, such as 1 mm + / - 10% (e.g., + / - 5%, such as + / - 2%, such as + / - 1%).

[0062] The ratio of the length of the capacitor body to the spacing can be 1.1 or greater, such as 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater. For example, the ratio of the length of the capacitor body to the spacing can be in the range of 1.1 to 1000, such as in the range of 2 to 500, in the range of 5 to 100, or in the range of 10 to 50.

[0063] As indicated above, extension of the leading edge of the lead tab can help form the external terminal. In this regard, the spacing between the lead tab on the first internal electrode layer and the lead tab on the second internal electrode layer can be the same as mentioned above. That is, the spacing between the lead tab on the first internal electrode layer and the lead tab on the second internal electrode layer can be approximately the same as the spacing between the corresponding external terminals that the lead tabs are used to form.

[0064] In addition, the external terminals can be positioned to be similar to the configuration of a ball grid array. For example, the external terminals can be arranged to form contacts that are commonly used in ball grid arrays (especially surround ball grid arrays). In this regard, the spacing of the external terminals can be the same as the spacing of the surround ball grid array. That is, the spacing can be within 10%, such as within 5%, such as within 2%, such as within 1%, such as within 0.5%, such as within 0.1% relative to the spacing of the surround ball grid array.

[0065] In addition, the external terminals can be arranged in a single row with multiple columns, which can be referred to as a 1 x n configuration of external terminals in a row x column designation, where n is the number of columns. For example, each external terminal can be arranged so that they are present in a row and at least two columns. For example, each external terminal can be presented in at least two columns, such as at least three columns, such as at least four columns. The number of columns can be determined by the number of different columnar tabs of the internal electrode.

[0066] In addition, the length of the external terminal extending along the top surface in the longitudinal direction or the length L direction can be the same as the length of the corresponding external terminal extending along the bottom surface. The length of the external terminal can be measured from one terminal end surface to another terminal end surface, which are opposite to each other in the longitudinal direction.

[0067] The length of the external terminal can be 0.3 mm or more, such as 0.4 mm or more, such as 0.5 mm or more, such as 0.6 mm or more, such as 0.7 mm or more. The length of the external terminal can be 1.1 mm or less, such as 0.9 mm or less, such as 0.8 mm or less, such as 0.7 mm or less, such as 0.6 mm or less, such as 0.5 mm or less. When there are more than one external terminal along a surface, each external terminal can have the same length. In addition, the length of the external terminal can be less than the length of the capacitor, for example, 50% or less of the length of the capacitor, such as 40% or less, such as 30% or less, such as 25% or less, such as 20% or less, such as 15% or less.

[0068] In another embodiment, each external terminal may have a different length. For example, the length of the external terminal adjacent to the end surface may be greater than the length of the external terminal deviating from the end surface. In this regard, the ratio of the length of the external terminal adjacent to the end surface to the length of the external terminal deviating from the end surface may be 0.3 or greater, such as 0.5 or greater, such as 0.7 or greater, such as 0.9 or greater, such as 1 or greater, such as 1.1 or greater, such as 1.2 or greater, such as 1.3 or greater, such as 1.4 or greater, such as 1.5 or greater. The ratio may be 5 or less, such as 4 or less, such as 3 or less, such as 2 or less, such as 1.8 or less, such as 1.7 or less, such as 1.6 or less, such as 1.5 or less, such as 1.4 or less.

[0069] In addition, the width of the external terminal extending in the lateral direction or width W may be the same on the top and bottom surfaces. The width of the external terminal may be measured from one terminal side surface to another terminal side surface, which are opposite to each other in the lateral direction.

[0070] The width of the external terminal can be 0.3 mm or more, such as 0.4 mm or more, such as 0.5 mm or more, such as 0.6 mm or more, such as 0.7 mm or more. The width of the external terminal can be 1.1 mm or less, such as 0.9 mm or less, such as 0.8 mm or less, such as 0.7 mm or less, such as 0.6 mm or less, such as 0.5 mm or less. When there are more than one external terminal along a surface, each external terminal can have the same width. In addition, the width of the external terminal can be less than the width of the capacitor.

[0071] In addition, each external terminal can be spaced apart from each other, and can also be spaced apart from the side and / or end of the capacitor so that the dielectric material is disposed between adjacent external terminals. The external terminals may include a first end external terminal disposed adjacent to or closest to the first end surface of the capacitor body and a second end external terminal disposed adjacent to or closest to the second end surface of the capacitor body. The first end external terminal and the second end external terminal may be spaced apart from each other in the longitudinal direction by an end external terminal spacing distance. The ratio of the length of the capacitor body to the end external terminal spacing distance may be 1.1 or greater, such as 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater. For example, the ratio of the length of the capacitor body to the end external terminal spacing distance may be in the range of 1.1 to 1000, such as in the range of 2 to 500, in the range of 5 to 100, or in the range of 10 to 50.

[0072] Adjacent external terminals may also be spaced apart from each other along the longitudinal direction on the top surface of the capacitor by adjacent external terminal spacing distances (e.g., between adjacent lateral sides of the external terminals). For example, for a pair of adjacent external terminals (the pair of adjacent external terminals having a lateral side toward the other of the pair of adjacent external terminals), the lateral side of one external terminal in the pair is spaced apart from the lateral side of the other external terminal in the pair by adjacent external terminal spacing distances. The ratio of the body length of the capacitor to the adjacent external terminal spacing distance may be 1.1 or greater, such as 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater. For example, the ratio of the body length of the capacitor to the adjacent external terminal spacing distance may be in the range of 1.1 to 1000, such as in the range of 2 to 500, in the range of 5 to 100, or in the range of 10 to 50.

[0073] According to Figures 1A to 1D , FIG. 2A to FIG. 2D and FIG. 3A to FIG. 3C The various embodiments shown are used to further describe the capacitor of the present invention.

[0074] Figure 1A A capacitor 100 is shown in a 1 by 2 configuration. That is, the capacitor 100 includes two external terminals arranged in a linear manner in a single dimension on the top and bottom surfaces of the capacitor. In the depicted embodiment, the capacitor 100 includes external terminals arranged in a linear manner or a single row (which may be referred to as a linear terminal arrangement) along a longitudinal direction L.

[0075] In this regard, the capacitor 100 includes a body 116 having external terminals 112, 114, which include a first internal electrode layer 1005 ( Figure 1B , Figure 1C ) and a first external terminal 112 disposed on at least one of the top surface 118 or the bottom surface 120 and electrically connected to the second internal electrode layer 1015 ( Figure 1B , Figure 1C ) of the second external terminal 114. More specifically, in the described embodiment, the capacitor 100 includes a first external terminal 112 and a second external terminal 114 disposed on the top surface 118 of the body 116, and two corresponding external terminals 112, 114 (not shown) disposed on the bottom surface 120 of the body 116, which can be referred to as a third external terminal 112 and a fourth external terminal 114.

[0076] The external terminals 112, 114 on the top surface 118 are electrically connected to the corresponding external terminals 112, 114 on the bottom surface 120. Figure 1A As shown, capacitor 100 includes at least one first polarity terminal and at least one second opposite polarity terminal located on top surface 118, and although not shown, bottom surface 120 also includes at least a first polarity terminal and a second opposite polarity terminal. In addition, first external terminal 112 and third external terminal 112 are electrically connected to first internal electrode layer 1005 ( Figure 1B , Figure 1C ), the second external terminal and the fourth external terminal 114 are electrically connected to the second internal electrode layer 1015 ( Figure 1B , Figure 1C ).

[0077] The body 116 includes a top surface 118 and a bottom surface 120 opposite to the top surface 118 in a height direction T. The body also includes a first side surface 122 extending between the top surface 118 and the bottom surface 120 in the height direction T and a second side surface 124 opposite to the first side surface 122 in a lateral direction or width direction W and extending between the top surface 118 and the bottom surface 120. The body also includes a first end surface 126 extending between the top surface 118 and the bottom surface 120 in the height direction T and a second end surface 128 opposite to the first end surface 126 in a longitudinal direction or length direction L and extending between the top surface 118 and the bottom surface 120. The body 116 has a body length 115 and a body width 125.

[0078] like Figure 1A As further shown, the body 116 includes end edges 130, 132 that define the longitudinal boundaries of the top surface 118 and the bottom surface 120, and side edges 134, 136 that define the lateral boundaries of the top surface 118 and the bottom surface 120. For example, the top surface 118 has a first top edge 130a and a second top edge 132a extending between a pair of side surfaces 122, 124 along the lateral direction W. The first top edge 130a and the second top edge 132a are opposite to each other along the longitudinal direction L. The top surface 118 also has a first top side edge 134a and a second top side edge 136a extending between the pair of end surfaces 126, 128 along the longitudinal direction L. The first top side edge 134a and the second top side edge 136a are opposite to each other along the lateral direction W. The top edges 130a, 132a define the longitudinal boundaries of the top surface 118, and the top side edges 134a, 136a define the lateral boundaries of the top surface 118.

[0079] Similarly, the bottom surface 120 has a first bottom edge 130b and a second bottom edge 132b extending between the pair of side surfaces 122, 124 along the transverse direction W. The first bottom edge 130b and the second bottom edge 132b are opposite to each other along the longitudinal direction L. The bottom surface 120 also has a first bottom side edge 134b and a second bottom side edge 136b extending between the pair of end surfaces 126, 128 along the longitudinal direction L. The first bottom side edge 134b and the second bottom side edge 136b are opposite to each other along the transverse direction W. The bottom edges 130b, 132b define the longitudinal boundaries of the bottom surface 120, and the bottom side edges 134b, 136b define the transverse boundaries of the bottom surface 120.

[0080] It should be understood that, although not shown in the figures, the bottom surface 120 can be configured similarly to the top surface 118. That is, the bottom surface 120 can also have a first end edge and a second end edge extending between a pair of side surfaces 122, 124 along the lateral direction W and opposite to each other along the longitudinal direction L. The bottom surface 120 can also have a first side edge and a second side edge extending between a pair of end surfaces 126, 128 along the longitudinal direction L and opposite to each other along the lateral direction W. These end edges and these side edges can define the longitudinal boundary and the lateral boundary of the bottom surface 120, respectively.

[0081] The external terminals 112, 114 of the capacitor 100 are offset from the sides and ends of the capacitor 100. Figure 1A and Figure 1D As shown, the external terminals 112, 114 are spaced apart from each of the first side edge 134 and the second side edge 136 of both the top surface 118 and the bottom surface 120, such that only dielectric material is disposed between the side edge 134, 136 and the external terminals 112, 114. For example, the external terminals 112, 114 are spaced apart from the first side edge 134a on the top surface 118 and the first side edge 134b on the bottom surface 120 to define a first edge gap 138 between the external terminals 112, 114 and each of the first side edges 134a, 134b. In addition, the external terminals 112, 114 are spaced apart from the second side edge 136a on the top surface 118 and the second side edge 136b on the bottom surface 120 to define a second edge gap 140 between the external terminals 112, 114 and each of the second side edges 136a, 136b.

[0082] The edge gaps 138, 140 may be greater than the thickness of a single layer, for example, greater than a single dielectric layer or a single internal electrode layer 1010 ( Figure 1B , Figure 1C ). For example, each edge gap 138, 140 can be at least two times, such as at least three times, such as at least five times, such as at least ten times, the thickness of a single dielectric layer or a single internal electrode layer. In some embodiments, the first edge gap 138 and the second edge gap 140 can be the same (e.g., for a given surface 118, 120, the distance of the external electrode 112, 114 from the corresponding first side edge 134 and the distance from the corresponding second side edge 136 can be the same or equal), but in other embodiments, the first edge gap 138 and the second edge gap 140 can be different (e.g., for a given surface 118, 120, the distance of the external electrode 112, 114 from one of the corresponding first side edge 134 or the corresponding second side edge 136 can be less than the distance from the other side edge of the corresponding surface 118, 120).

[0083] Similarly, the external terminals 112, 114 of the capacitor 100 are spaced apart from the end edges 130, 132 of the top surface 118 and the bottom surface 120. Figure 1A and Figure 1D As shown, the external terminals 112, 114 are spaced apart from each of the first end edge 130 and the second end edge 132 of the top surface 118 and the bottom surface 120 to define a first end gap 142 between the external terminal 112 and the first end edge 130a, 130b and a second end gap 144 between the external terminal 114 and the second end edge 132a, 132b.

[0084] The end gaps 142, 144 may be larger than the thickness of a single layer, for example, larger than the thickness of a single dielectric layer or a single internal electrode layer 1010 ( Figure 1B , Figure 1C ). For example, each end gap 142, 144 can be at least twice, such as at least three times, such as at least five times, such as at least ten times, the thickness of a separate dielectric layer or a separate internal electrode layer. In some embodiments, the first end gap 142 and the second end gap 144 can be the same (e.g., for a given surface 118, 120, the distance between the external terminal 112 and the corresponding first end edge 130 is the same as the distance between the external terminal 114 and the corresponding second end edge 132), but in other embodiments, the first end gap 142 and the second end gap 144 can be different (e.g., for a given surface 118, 120, the distance between one of the external terminals 112, 114 and its adjacent end edge 130, 132 can be smaller than the distance between the other external electrode 112, 114 and its adjacent end edge 130, 132).

[0085] refer to Figure 1A and Figure 1B , Figure 1A The capacitor 100 in FIG. 1 includes external terminals 112, 114, and a set of alternating dielectric layers and internal electrode layers 1010. Specifically referring to FIG. Figure 1B , the set of alternating dielectric layers and internal electrode layers 1010 includes alternatingly arranged internal electrode layers 1005, 1015 and dielectric layers (not shown).

[0086] In general, the internal electrode layers 1005, 1015 include at least one lead tab 1020, 1030, 1040, 1050 extending from the top and bottom edges of the body of the internal electrode layer. In general, the lead tabs 1020, 1030, 1040, 1050 of the internal electrode layers 1005, 1015 extend to the top and bottom surfaces of the capacitor and help form the external terminations 112, 114. In this regard, the lead tabs 1020, 1030, 1040, 1050 can be exposed on the top and bottom surfaces 118, 120 of the capacitor and allow for connection between the body of the internal electrode layer and the external terminations 112, 114. For example, the lead tabs 1020 , 1030 , 1040 , 1050 may include leading edges 1023 , 1033 , 1043 , 1053 that extend to the edge of the dielectric layer and allow for the formation of the external terminals 112 , 114 on the top and bottom surfaces 118 , 120 .

[0087] like Figure 1B and Figure 1C As shown, the first internal electrode layer 1005 includes a lead tab 1020 extending from the main body 1035 along the top edge 1005c and a lead tab 1020 extending from the main body 1035 along the bottom edge 1005d. The second internal electrode layer 1015 includes a lead tab 1040 extending from the main body 145 along the top edge and a lead tab 1050 extending from the main body 145 along the bottom edge.

[0088] The lead tabs 1020, 1030 on the top edge 1005c and the bottom edge 1005d of the first internal electrode layer 1005 may be aligned in the vertical direction or height direction T. That is, the lateral edges 1021, 1022 of the first lead tab 1020 along the top edge 1005c may be aligned with the lateral edges 1031, 1032 of the first lead tab 1030 along the bottom edge 1005d opposite to the top edge 1005c. In other words, the lateral edges 1021, 1022 of the first lead tab 1020 along the top edge 1005c may be offset (indicated by "O") by the same distance from the side edges 1005a, 1005b as the lateral edges 1031, 1032 of the first lead tab 1030 along the bottom edge 1005d opposite to the top edge 1005c are offset from the side edges 1005a, 1005b.

[0089] However, it should be understood that the two lateral edges 1021, 1022 of the first lead tab 1020 along the top edge 1005c can be aligned with the lateral edges 1031, 1032 of the first lead tab 1030 along the bottom edge 1005d opposite to the top edge 1005c. In other words, the distance that the two lateral edges 1021, 1022 of the first lead tab 1020 along the top edge 1005c deviate from the side edges 1005a, 1005b can be the same as the distance that the two lateral edges 1031, 1032 of the first lead tab 1030 along the bottom edge 1005d opposite to the top edge 1005c deviate from the side edges 1005a, 1005b.

[0090] Similarly, the lead tabs 1040, 1050 on the top and bottom edges of the second internal electrode layer 1015 may be aligned in the vertical direction. That is, the lateral edges 1041, 1042 of the first lead tab 1040 along the top edge may be aligned with the lateral edges 1051, 1052 of the first lead tab 1050 along the bottom edge opposite to the top edge. In one embodiment, the two lateral edges 1041, 1042 of the first lead tab 1040 along the top edge may be aligned with the lateral edges 1051, 1052 of the first lead tab 1050 along the bottom edge opposite to the top edge. The relationship between the respective lateral edges of the first lead tab on the top edge and the respective lateral edges of the first lead tab on the bottom edge as mentioned with respect to the internal electrode layer 1005 may also be applicable to the internal electrode layer 1015.

[0091] With this arrangement, a tab gap 1016 may be formed between the lead tab 1020 of the first internal electrode layer 1005 and the lead tab 1040 of the second internal electrode layer 1015. Similarly, a tab gap 1018 may be formed between the lead tab 1030 of the first internal electrode layer 1005 and the lead tab 1050 of the second internal electrode layer 1015. The sizes of the respective tab gaps 1016, 1018 may be substantially the same.

[0092] Lead tabs 1020 and 1040 may be arranged in parallel with lead tabs 1030 and 1050, respectively, extending from internal electrode layers 1005 and 1015, such that lead tabs extending from alternating electrode layers 1005 and 1015 may be aligned in corresponding columns. For example, lead tabs 1020 and 1030 of internal electrode layer 1005 may be arranged in a corresponding stacked configuration, and lead tabs 1040 and 1050 of internal electrode layer 1015 may be arranged in a corresponding stacked configuration.

[0093] It should be understood that lead tabs 1020 are connected to external terminals 112, while lead tabs 1040 are connected to external terminals 114. Therefore, the corresponding lead tabs 1020 will be staggered with the corresponding lead tabs 1040 in a manner similar to external terminals 112 and 114. The staggered lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0094] refer to Figure 1D , provides a top view of the top surface 118 of the capacitor 100. It should be understood that the bottom surface 120 can be configured substantially similar to the top surface 118, such that a description of the top surface 118 can similarly describe the bottom surface 120.

[0095] like Figure 1D As depicted, the external terminals 112, 114 may be spaced apart from each other, and may also be spaced apart from the sides and ends of the top surface 118 and the bottom surface 120 of the capacitor 100. As an example, the external terminals 112, 114 may include a first end external terminal 112 disposed on the top surface 118 adjacent to the first end surface 126 and the first end edge 130a, and a second end external terminal 114 disposed on the top surface 118 adjacent to the second end surface 128 and the second end edge 132a. The first end external terminal 112 and the second end external terminal 114 are spaced apart in the longitudinal direction L by an end external terminal spacing distance 150.

[0096] As previously described, the body 116 has a body length 115 along the longitudinal direction L. The ratio of the body length 115 to the end external terminal spacing distance 150 is 1.1 or greater. For example, the ratio of the body length 115 to the end external terminal spacing distance 150 can be 1.1 or greater, such as 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater.

[0097] like Figure 1D As further shown, a spacing 152 is defined between adjacent external terminals 112, 114. As previously described, the spacing 152 is the nominal distance between the centers of adjacent external terminals; the spacing 152 may also be referred to as the center-to-center spacing of the external terminals. The ratio of the body length 115 to the spacing 152 is 1.1 or greater, such as 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater.

[0098] like Figures 1A to 1DAs shown, capacitor 100 includes two external terminals 112, 114 on each surface, and each internal electrode layer 1010 includes at least one lead tab extending from the top edge and the bottom edge. However, as indicated above, the present invention is not limited by the number of external terminals and / or the number of lead tabs extending from the top edge and / or the bottom edge.

[0099] For example, Figure 2A A capacitor 200 is shown that includes four external terminals on each surface, and two lead tabs extending from the top and bottom surfaces of each internal electrode layer.

[0100] like Figure 2A As shown, capacitor 200 has a 1 by 4 configuration. That is, capacitor 200 includes four external terminals arranged in a linear manner in a single dimension on the top and bottom surfaces of the capacitor. In the depicted embodiment, capacitor 200 includes a plurality of external terminals arranged in a linear manner or a single row (which may be referred to as a linear terminal arrangement) along a longitudinal direction L.

[0101] In this regard, the capacitor 200 includes a body 216 having external terminals 212a, 212b, 214a, 214b that include a first internal electrode layer 2005 ( Figure 2B , Figure 2C ) and a first external terminal 212a disposed on at least one of the top surface 218 or the bottom surface 220 and electrically connected to the second internal electrode layer 2015 ( Figure 2B , Figure 2C ). More specifically, in the depicted embodiment, the capacitor 200 includes a first external terminal 212a, a second external terminal 214a, a third external terminal 212b, and a fourth external terminal 214b disposed on the top surface 218 of the body 216, and four corresponding external terminals 212a, 212b, 214a, 214b (not shown) disposed on the bottom surface 220 of the body 216, which may be referred to as a fifth external terminal 212a, a sixth external terminal 214a, a seventh external terminal 212b, and an eighth external terminal 214b.

[0102] The external terminals 212a, 212b, 214a, 214b on the top surface 218 are electrically connected to the corresponding external terminals 212a, 212b, 214a, 214b on the bottom surface 220. Figure 2AAs shown, the capacitor 200 includes at least two first polarity terminals and at least two second opposite polarity terminals on the top surface 218, and although not shown, the bottom surface 220 also includes at least two first polarity terminals and two second opposite polarity terminals. In addition, the first external terminal, the third external terminal, the fifth external terminal and the seventh external terminal 212a, 212b are electrically connected to the first internal electrode layer 2005 ( Figure 2B , Figure 2C ), and the second external terminal, the fourth external terminal, the sixth external terminal and the eighth external terminal 214a, 214b are electrically connected to the second internal electrode layer 2015 ( Figure 2B , Figure 2C ).

[0103] FIG. 2A to FIG. 2D The reference numerals used in Figures 1A to 1D The reference numerals used in the drawings are similar. Generally, similar reference numerals in the drawings refer to the same or similar features or components. Therefore, it should be understood that the body 216 of the capacitor 200 is configured to be similar to the body 116 of the capacitor 100. For example, the body 216 includes a top surface 218, a bottom surface 220 opposite to the top surface 218 along the height direction T, a first side surface 222 extending between the top surface 218 and the bottom surface 220 along the height direction T, a second side surface 224 opposite to the first side surface 222 and extending between the top surface 218 and the bottom surface 220 along the lateral direction or width direction W, a first end surface 226 extending between the top surface 218 and the bottom surface 220 along the height direction T, and a second end surface 228 opposite to the first end surface 226 and extending between the top surface 218 and the bottom surface 220 along the longitudinal direction or length direction L. The body 216 has a body length 2015 and a body width 225.

[0104] In addition, the top surface 218 has a first end edge 230 and a second end edge 232 extending between the pair of side surfaces 222, 224 along the transverse direction W. The top surface 218 also includes a first side edge 234 and a second side edge 236 extending between the pair of end surfaces 226, 228 along the longitudinal direction L. Although not shown in the figures, it is understood that the bottom surface 220 can be configured similarly to the top surface 218, having a first end edge and a second end edge and a first side edge and a second side edge.

[0105] The external terminals 212, 214 of the capacitor 200 are offset from the sides and ends of the capacitor 200. Figure 2A and Figure 2DAs shown, the external terminals 212a, 212b, 214a, 214b are spaced apart from each of the first side edge 234 and the second side edge 236 of both the top surface 218 and the bottom surface 220, such that only dielectric material is disposed between the external terminals 212a, 212b, 214a, 214b and the side edges 234, 236. For example, for each of the top surface 218 and the bottom surface 220, the external terminals 212a, 212b, 214a, 214b are spaced apart from each of the first side edges 234a, 234b and the second side edges 236a, 236b to define a first edge gap 238 between the external terminals 212a, 212b, 214a, 214b and the first side edges 234a, 234b, and a second edge gap 240 between the external terminals 212a, 212b, 214a, 214b and the second side edges 236a, 236b. Similarly, the external terminals 212a, 214b are spaced apart from each of the first end edges 230a, 230b and the second end edges 232a, 232b of the top surface 218 and the bottom surface 220, respectively, to define a first end gap 242 between the external terminal 212a and the first end edge 230a, 230b, and a second end gap 244 between the external terminal 214b and the second end edge 232a, 232b.

[0106] The edge gaps 238, 240 and the end gaps 242, 244 may be greater than the thickness of a single layer, such as a single dielectric layer or a single internal electrode layer 1010 ( Figure 1B , Figure 1C). For example, each edge gap 238, 240 and each end gap 242, 244 can be at least two times, such as at least three times, such as at least five times, such as at least ten times, the thickness of a single dielectric layer or a single internal electrode layer. In some embodiments, the first edge gap 238 and the second edge gap 240 can be the same (for example, for a given surface 218, 220, the distance of the external electrodes 212a, 212b, 214a, 214b from the corresponding first side edge 234a, 234b and the distance from the corresponding second side edge 236a, 236b can be the same or equal, but in other embodiments, the first edge gap 238 and the second edge gap 240 can be different (for example, for a given surface 218, 220, the distance of the external electrodes 212a, 212b, 214a, 214b from one of the first side edge 234 or the second side edge 236 can be less than the distance from the other of the corresponding surface 218, 220). Likewise, in some embodiments, the first end gap 242 and the second end gap 244 may be the same (e.g., for a given surface 218, 220, the distance between the external terminal 212a and the corresponding first end edge 230a, 230b may be the same as the distance between the external terminal 214b and the corresponding second end edge 232a, 232b), but in other embodiments, the first end gap 242 and the second end gap 244 may be different (e.g., for a given surface 218, 220, the distance between one of the external terminals 212a, 214b and its adjacent end edge 230, 232 may be smaller than the distance between the other external terminal 212a, 214b and its adjacent end edge 230, 232).

[0107] Figure 2A The capacitor 200 includes external terminals 212a, 212b, 214a, 214b and Figure 2B A set of alternating dielectric layers and internal electrode layers 2010 is shown. Figure 2B As shown, the set of alternating dielectric layers and internal electrode layers 2010 includes alternatingly arranged internal electrode layers 2005, 2015 and dielectric layers (not shown).

[0108] In general, the internal electrode layers 2005, 2015 include at least one lead tab 2020a, 2020b, 2030a, 2030b, 2040a, 2040b, 2050a, 2050b extending from the top and bottom edges of the body of the internal electrode layers. In general, the lead tabs 2020a, 2020b, 2030a, 2030b, 2040a, 2040b, 2050a, 2050b of the internal electrode layers 2005, 2015 extend to the top and bottom surfaces of the capacitor and help form external terminals. In this regard, the lead tabs 2020a, 2020b, 2030a, 2030b, 2040a, 2040b, 2050a, 2050b can be exposed on the top and bottom surfaces of the capacitor and allow connection between the body of the internal electrode layers and the external terminals. For example, the lead tabs 2020a, 2020b, 2030a, 2030b, 2040a, 2040b, 2050a, 2050b may include a leading edge 2023a, 2023b, 2033a, 2033b, 2043a, 2043b, 2053a, 2053b that extends to the edge of the dielectric layer and allows for the formation of external terminations.

[0109] like Figure 2B and Figure 2C As shown, the internal electrode layers 2005, 2015 include at least two lead tabs 2020a, 2020b, 2030a, 2030b, 2040a, 2040b, 2050a, 2050b along the top and bottom edges. Figure 2B and Figure 2C As shown, the first internal electrode layer 2005 includes two lead tabs 2020a, 2020b, 2030a, 2030b, respectively, extending from the body 235 along the top edge 2005c and the bottom edge 2005d. The second internal electrode layer 2015 includes two lead tabs 2040a, 2040b, 2050a, 2050b, respectively, extending from the body 245 along the top edge and the bottom edge.

[0110] The lead tabs 2020a, 2020b, 2030a, 2030b on the top edge 2005c and the bottom edge 2005d of the first internal electrode layer 2005 may be aligned in the vertical direction. That is, the lateral edges 2021a, 2022a of the first lead tab 2020a along the top edge 2005c may be aligned with the lateral edges 231a, 232a of the first lead tab 2030a along the bottom edge 2005d opposite to the top edge 2005c. In other words, the distance that the lateral edges 2021a, 2022a of the first lead tab 2020a along the top edge 2005c deviate from (indicated by "O") the side edges 2005a, 2005b can be the same as the distance that the lateral edges 231a, 232a of the first lead tab 2030a along the bottom edge 2005d opposite the top edge 2005c deviate from the side edges 2005a, 2005b. In addition, the two lateral edges 2021a, 2022a of the first lead tab 2020a along the top edge 2005c can be aligned with the lateral edges 231a, 232a of the first lead tab 2030a along the bottom edge 2005d opposite the top edge 2005c. That is, the two lateral edges can deviate from the side edges 2005a, 2005b by the same distance.

[0111] When the top edge 2005c and the bottom edge 2005d include at least two lead tabs 2020a, 2020b, 2030a, 2030b, at least one lateral edge of each lead tab on the top edge 2005c can be aligned with a corresponding lateral edge of a lead tab on the bottom edge 2005d. In addition, two lateral edges of each lead tab on the top edge 2005c can be aligned with corresponding lateral edges of a lead tab on the bottom edge 2005d.

[0112] Similarly, the lead tabs 2040a, 2040b, 2050a, 2050b on the top and bottom edges of the second internal electrode layer 2015 can be aligned in the vertical direction. That is, the lateral edges 2041a, 2042a of the first lead tab 2040a along the top edge can be aligned with the lateral edges 2051a, 2052a of the first lead tab 2050a along the bottom edge opposite to the top edge. The two lateral edges 2041a, 2042a of the first lead tab 2040a along the top edge can be aligned with the lateral edges 2051a, 2052a of the first lead tab 2050a along the bottom edge opposite to the top edge. The relationship between the lateral edges of the first lead tab on the top edge and the lateral edges of the first lead tab on the bottom edge as mentioned with respect to the internal electrode layer 2005 can also be applied to the internal electrode layer 2015.

[0113] With this arrangement, a tab gap may be formed between the lead tab along the top edge 2005c of the first internal electrode layer 2005, the lead tab along the top edge of the second internal electrode layer 2015, or any of the lead tabs in between. For example, a tab gap may be formed between any of the lead tabs 2020a, 2020b, 2040a, 2040b extending from the top edge of each internal electrode layer. In addition, a tab gap may be formed between the lead tab along the bottom edge 2005d of the first internal electrode layer 2005, the lead tab along the bottom edge of the second internal electrode layer 2015, or any of the lead tabs in between. For example, a tab gap may be formed between any of the lead tabs 2030a, 2030b, 2050a, 2050b extending from the bottom edge of each internal electrode layer. In addition, whether from the same internal electrode layer or from an adjacent internal electrode layer, the size of the tab gap between two corresponding tabs extending from the top edge can be approximately the same as the size of the tab gap between the corresponding two corresponding tabs extending from the bottom edge. For example, the first tab gap 2016a between lead tabs 2020a and 2020b can be approximately the same as the first tab gap 2018a between lead tabs 2030a and 2030b. Similarly, the second tab gap 2016b between lead tabs 2020a and 2040a can be approximately the same as the second tab gap 2018b between lead tabs 2030a and 2050a.

[0114] Any one or all of the lead tabs 2020a, 2020b, 2040a, 2040b may be arranged in parallel with the lead tabs 2030a, 2030b, 2050a, 2050b, respectively, extending from the layers 2005 and 2015, so that the leads extending from the alternating electrode layers 2005 and 2015 may be aligned in corresponding columns. For example, the lead tabs 2020a, 220b and 2030a, 230b of the inner electrode layer 2005 may be arranged in a corresponding stacked configuration, while the lead tabs 2040a, 240b and 2050a, 2050b of the inner electrode layer 2015 may be arranged in a corresponding stacked configuration.

[0115] It should be understood that the lead tabs 2020a, 2020b are connected to the external terminals 22a, 22b, respectively, while the lead tabs 2040a, 2040b are connected to the external terminals 24a, 24b, respectively. Therefore, the corresponding lead tabs 2020a, 2020b will be staggered with the corresponding lead tabs 2040a, 2040b in a manner similar to the external terminals 22a, 22b and 24a, 24b. The staggered lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0116] like Figure 2D As depicted, the external terminals 212a, 212b, 214a, 214b may be spaced apart from each other and may also be spaced apart from the sides and ends of the top surface 218 and the bottom surface 220 of the capacitor 200. The external terminals 212a, 212b, 214a, 214b may include a first end external terminal 212a disposed adjacent to the first end surface 226 and the first end edge 230 and a second end external terminal 214a disposed adjacent to the second end surface 228 and the second end edge 232. The first end external terminal 212a and the second end external terminal 214a are spaced apart in the longitudinal direction L by an end external terminal spacing distance 250.

[0117] As previously described, the body 216 has a body length 215 in the longitudinal direction L. The ratio of the body length 215 to the end external terminal spacing distance 250 is 1.1 or greater, such as 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater.

[0118] like Figure 2D As further shown, a spacing 252 is defined between adjacent external terminals 212a, 212b, 214a, 214b (e.g., between adjacent terminals 212a and 214b, between adjacent terminals 214b and 212b, or between adjacent terminals 212b and 214a). As previously described, the spacing 252 is the nominal distance between the centers of adjacent external terminals; the spacing 252 may also be referred to as the center-to-center spacing of the external terminals. The ratio of the body length 215 to the spacing 252 is 1.1 or greater, such as 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater.

[0119] Adjacent external terminals 212a, 212b, 214a, 214b are also spaced apart from each other along the longitudinal direction L on the top surface 228 by adjacent external terminal spacing distances 254 between adjacent lateral sides of the external terminals. Figure 2D As shown, the first lateral side 201a of the external terminal 212b (the first lateral side 201a facing the external terminal 214a) is spaced apart from the first lateral side 201b of the external terminal 214a (the first lateral side 201b facing the external terminal 212b) by an adjacent external terminal spacing distance 254. The ratio of the body length 215 to the adjacent external terminal spacing distance 254 is 1.1 or greater, such as 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater.

[0120] In addition, if Figure 2A As shown, FIG. 2A to FIG. 2DThe capacitor 200 includes at least one first polarity terminal and at least one second opposite polarity terminal on the top surface. Although not shown, the bottom surface includes at least the first polarity terminal and the second opposite terminal. In particular, Figure 2A Two positive terminals 212a and 212b and two negative terminals 214a and 214b are included on the top surface.

[0121] like FIG. 2A to FIG. 2D As shown, the capacitor includes four external terminals on each surface, and each internal electrode layer of the capacitor includes two lead tabs extending from each of the top edge and the bottom edge of the internal electrode layer. However, as indicated above, the present invention is not limited by the number of external terminals and / or the number of lead tabs of the internal electrode layer.

[0122] Now go to FIG. 3A to FIG. 3C , a capacitor 300 having a 1 by 2 configuration is shown. That is, the capacitor 300 includes two external terminals arranged in a linear manner in a single dimension on the top and bottom surfaces of the capacitor. In the depicted embodiment, the capacitor 300 includes a plurality of external terminals arranged in a linear manner or a single row (which may be referred to as a linear terminal arrangement) along the longitudinal direction L.

[0123] In this regard, the capacitor 300 includes a body 316 having external terminals 312, 314, which include a first internal electrode layer 3005 ( Figure 3B , Figure 3C ) and a first external terminal 312 disposed on at least one of the top surface 318 or the bottom surface 320 and electrically connected to the second internal electrode layer 3015 ( Figure 3B , Figure 3C )'s second external terminal 314.

[0124] It should be understood that FIG. 3A to FIG. 3C The capacitor 300 shown in FIG. Figures 1A to 1D The capacitor 100 is similar to that in FIG. FIG. 3A to FIG. 3C The reference numerals used in Figures 1A to 1DReference numerals used in the drawings are similar to those used to indicate the same or similar features. However, unlike the external terminals 112, 114 of capacitor 100, the external terminals 312, 314 of capacitor 300 are not spaced apart from the end surfaces 326, 328 of capacitor body 316. Instead, external terminal 312 is formed along a first end of body 316 from top surface 318 to bottom surface 320, such that a portion of external terminal 312 extends along first end surface 326. Similarly, external terminal 314 is formed along a second end of body 316 from top surface 318 to bottom surface 320, such that a portion of external terminal 314 extends along second end surface 328. Thus, unlike external terminals 112, 114 of capacitor 100, external terminals 312, 314 of capacitor 300 are not spaced apart from end surfaces 326, 328 of capacitor body 316. Instead, external terminal 312 is formed along a first end of body 316 from top surface 318 to bottom surface 320, such that a portion of external terminal 314 extends along second end surface 328. Figure 1A and 1D Unlike the external terminals shown formed on the top surface and the bottom surface respectively, the first external electrode 312 is wound from the top surface 318 to the bottom surface 320, so that the first external electrode 312 is arranged on the top surface 318, the first end surface 326 and the bottom surface 320, and the second external electrode 314 is wound from the top surface 318 to the bottom surface 320, so that the second external electrode 314 is arranged on the top surface 318, the second end surface 328 and the bottom surface 320.

[0125] In addition, the lead tabs 1020, 1030, 1040, 1050 of the electrode layers 1005, 1015 (the lead tabs 1020, 1030, 1040, 1050 of the electrode layers 1005, 1015 are offset from the side edge 100a (such as Figure 1B Unlike the "O" in the figure, the lead tabs 3020, 3030, 3040, 3050 of the electrode layers 3005, 3015 do not deviate from the side edge 3005a. In this way, the lateral edges 3021, 3031, 3042, 3052 of the lead tabs 3020, 3030, 3040, 3050 and the side edges 3005a of the electrode layers 3005, 3015 extend to the ends 326, 328 of the capacitor body 316 and can help, for example, form the external electrodes 312, 314 along the end surfaces 326, 328.

[0126] Additionally, the embodiments in the figures employ only two internal electrode layers in a stack of alternating dielectric layers and internal electrode layers. However, it should be understood that the present invention may include any number of internal electrode layers as indicated herein and is not necessarily limited.

[0127] In general, the present invention provides a capacitor with a unique construction that provides various benefits and advantages. In this regard, it should be understood that the materials used in the construction of the capacitor may not be limited and may be any material commonly used in the art and may be formed using any method commonly used in the art.

[0128] In general, the dielectric layer is often formed of a material having a relatively high dielectric constant (K), such as from about 10 to about 40,000, in some embodiments from about 50 to about 30,000, and in some embodiments from about 100 to about 20,000.

[0129] In this regard, the dielectric material may be a ceramic. The ceramic may be provided in a variety of forms such as a (eg, pre-fired) wafer or a co-fired dielectric material within the device itself.

[0130] Specific examples of high dielectric material types include, for example, NPO (COG) (up to about 100) materials, X7R (from about 3000 to about 7000) materials, X7S materials, Z5U materials and / or Y5V materials. It should be understood that the above materials are described by industry-recognized definitions, some of which are standard classifications established by the Electronic Industries Alliance (EIA), so these materials should be recognized by ordinary technicians in the field. For example, such materials may include ceramics. Such materials may include perovskites, such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lanthanum lead zirconate titanate) and sodium bismuth titanate, etc. In a specific embodiment, for example, a material with the chemical formula Ba x Sr 1-x TiO 3 Barium strontium titanate (BSTO), wherein x is from 0 to 1, in some embodiments x is from about 0.15 to about 0.65, and in some embodiments x is from about 0.25 to about 0.6. Other suitable perovskites may include, for example: Ba x Ca 1-x TiO 3 (wherein x is from about 0.2 to about 0.8, and in some embodiments x is from about 0.4 to about 0.6), Pb x Zr 1-x TiO 3 (“PZT”) (where x is in the range of from about 0.05 to about 0.4), lead lanthanum zirconate titanate (“PLZT”), lead titanate (PbTiO 3 ), barium calcium zirconium titanate (BaCaZrTiO 3 ), sodium nitrate (NaNO 3 ), potassium niobate (KNbO 3 ), lithium niobate (LiNbO 3 ), lithium tantalate (LiTaO 3), lead metaniobate (PbNb 2 O 6 ), lead tantalate (PbTa 2 O 6 )、KSr(NbO 3 ) and NaBa 2 (NbO 3 ) 5 HkDJ 2 PO 4 Other composite perovskites may include A[B1 1 / 3 B2 2 / 3 ]O 3 Materials, wherein A is Ba x Sr 1-x (x can be a value from 0 to 1); B1 is Mg y Zn 1-y (y can be a value from 0 to 1); B2 is Ta z Nb 1-z (z may have a value from 0 to 1.) In one particular embodiment, the dielectric layer may include titanate.

[0131] The internal electrode layer can be formed of any of a variety of different metals known in the art. The internal electrode layer can be made of a metal (e.g., a conductive metal). These materials can include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), etc., and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, as well as individual sputtered layers of chromium, nickel, and gold may also be suitable. In a particular embodiment, the internal electrode layer may include nickel or its alloys.

[0132] The external terminals may be formed of any of a variety of different metals known in the art. The external terminals may be made of metals (e.g., conductive metals). These materials may include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), etc., and various combinations thereof. In a particular embodiment, the external terminals may include copper or an alloy thereof.

[0133] The external terminals may be formed using any method known in the art. The external terminals may be formed using techniques such as sputtering, spraying, printing, chemical plating or fine copper termination (FCT), electroplating, plasma deposition, propellant spraying / air brushing, and the like.

[0134] The external terminal can be formed so that the external terminal is a thin film coating of metal. Such a thin film coating can be formed by depositing a conductive material (e.g., a conductive metal) on an exposed portion of the internal electrode layer. For example, the front edge of the internal electrode layer can be exposed so that the front edge can allow the formation of a plated termination.

[0135] The average thickness of the external terminal can be about 50 μm or less (e.g., about 40 μm or less, for example, about 30 μm or less, for example, about 25 μm or less, for example, about 20 μm or less) to about 5 μm or more (e.g., about 10 μm or more, for example, about 15 μm or more). For example, the average thickness of the external terminal can be from about 5 μm to about 50 μm, for example, from about 10 μm to about 40 μm, for example, from about 15 μm to about 30 μm, for example, from about 15 μm to about 25 μm.

[0136] Generally speaking, the external terminal may include a plated terminal. For example, the external terminal may include an electroplated terminal, a chemically plated terminal, or a combination thereof. For example, the electroplated terminal may be formed by electroplating. The chemically plated terminal may be formed by chemical plating.

[0137] When multiple layers constitute the external terminal, the external terminal can include an electroplated terminal and an electroless plating terminal. For example, an initial material layer can be deposited first using electroless plating. The plating technology can then be switched to an electrochemical plating system, which can allow for faster material deposition.

[0138] When forming the plated terminal using any plating method, the front edge of the lead tab of the internal electrode layer exposed from the body of the capacitor is subjected to the plating solution. In one embodiment, by the subjection, the capacitor is immersed in the plating solution.

[0139] The plated termination is formed using a plating solution containing a conductive material (e.g., a conductive metal). Such a conductive material may be any of the materials described above or any material generally known in the art. For example, the plating solution may be a nickel sulfamate bath solution or other nickel solution such that the plating layer and the external terminal include nickel. Alternatively, the plating solution may be a cupric acid bath or other suitable copper solution such that the plating layer and the external terminal include copper.

[0140] In addition, it should be understood that the plating solution may include other additives known in the art. For example, the additive may include other organic additives and media that may contribute to the plating process. In addition, additives may be used to use the plating solution under a desired pH value. In one embodiment, a drag reducing additive may be used in the solution to help complete coating coverage and bonding of the plating material to the exposed front edge of the lead tabs of the capacitor and the internal electrode layer.

[0141] The capacitor may be exposed, submerged or immersed in the plating solution for a predetermined amount of time. Such exposure time need not be limited, but may be for a sufficient amount of time to allow deposition of sufficient plating material to form plated terminals. In this regard, the time should be sufficient to allow a continuous connection to be formed between the desired exposed adjacent leading edges of the lead tabs of a given polarity of each internal electrode layer within a set of alternating dielectric layers and internal electrode layers.

[0142] Generally speaking, the difference between electroplating and chemical plating is that electroplating uses an electrical bias, such as by using an external power source. The plating solution can usually withstand a high current density range, for example, ten to fifteen amps per square foot (amp / ft 2 ) (rated voltage is 9.4 volts). A connection can be made in which the negative electrode is connected to the capacitor to which the plated terminal is to be formed and the positive electrode is connected to the solid material in the same plating solution (e.g., copper in a copper plating solution). That is, the capacitor is biased to a polarity opposite to the polarity of the plating solution. Using this method, the conductive material of the plating solution is attracted to the metal at the exposed front edge of the lead tab of the internal electrode layer.

[0143] Before the capacitor is immersed in or subjected to the plating solution, various pre-treatment steps may be employed. These steps may be performed for a variety of purposes including catalyzing, accelerating and / or improving the adhesion of the plating material to the leading edge of the lead tab.

[0144] In addition, an initial cleaning step may be employed prior to plating or any other pretreatment step. Such a step may be employed to remove any oxide buildup formed on the lead tabs where the internal electrode layers are exposed. When the internal electrodes or other conductive elements are formed of nickel, this cleaning step may be particularly helpful in helping to remove any buildup of nickel oxide. Part cleaning may be achieved by complete immersion in a pre-cleaning bath (e.g., a pre-cleaning bath comprising an acidic cleaner). In one embodiment, exposure may last for a predetermined time, such as on the order of about 10 minutes. Cleaning may also alternatively be achieved by a chemical polishing or grinding step.

[0145] In addition, the step of activating the metal front edge of the lead terminal tab of the internal electrode layer can be performed to promote the deposition of the conductive material. Activation can be achieved by immersing a palladium salt, a photopatterned palladium organic metal precursor (by a mask or laser), a palladium compound or electrophoretic palladium deposition deposited by screen printing or inkjet deposition. It should be understood that activation based on palladium is currently only disclosed as an example of an activation solution, and the activation solution usually works well with the activation of the exposed terminal tab portion formed by nickel or its alloy. However, it should be understood that other activation solutions may also be used, and therefore other activation solutions do not have to be limited.

[0146] Additionally, as an alternative to or in addition to the above activation step, an activating dopant may be introduced into the conductive material when forming the internal electrode layers of the capacitor. For example, when the internal electrode layers include nickel and the activating dopant includes palladium, the palladium dopant may be introduced into the nickel ink or composition that forms the internal electrode layers. Doing so may eliminate the palladium activation step. It should also be understood that some of the above activation methods (e.g., organometallic precursors) also lend themselves to co-deposition of the glass former to increase adhesion to the general ceramic body of the capacitor. When an activation step is taken as described above, traces of the activator material may typically remain at the exposed conductive portions before and after the terminations are plated.

[0147] In addition, the post-treatment step after the plating can also be adopted as required or necessary. These steps can be implemented for a variety of purposes, including strengthening and / or improving the adhesion of materials. For example, a heating (or annealing) step can be adopted after performing the plating step. This heating can be carried out by baking, laser irradiation, ultraviolet (UV) exposure, microwave exposure, arc welding, etc.

[0148] As indicated herein, the external terminal includes at least one plating layer. In one embodiment, the external terminal may include only one plating layer. However, it should be understood that the external terminal may include multiple plating layers. For example, the external terminal may include a first plating layer and a second plating layer. In addition, the external terminal may also include a third plating layer. In addition, the material of these plating layers may be any of the materials described above and known in the art.

[0149] For example, one coating (e.g., the first coating) may include copper or its alloy. Another coating (e.g., the second coating) may include nickel or its alloy. Alternatively, another coating (e.g., the second coating) may include copper or its alloy. Another coating (e.g., the third coating) may include tin, lead, gold, or a combination, such as an alloy. Alternatively, the initial coating may include nickel, followed by a coating of tin or gold. In another embodiment, an initial coating of copper may be formed, followed by a layer of nickel.

[0150] In one embodiment, the initial or first plating layer may be a conductive metal (e.g., copper). The area may then be covered with a second layer comprising a resistive polymeric material for sealing. The area may then be polished to selectively remove the resistive polymeric material and then plated again with a third layer comprising a conductive metal material (e.g., copper).

[0151] The aforementioned second layer above the initial plated layer may correspond to a solder barrier layer, such as a nickel solder barrier layer. In some embodiments, the aforementioned layer may be formed by electroplating an additional metal (e.g., nickel or copper) layer on an initial chemically plated or electroplated layer (e.g., plated copper). Other exemplary layer materials for the aforementioned solder barrier layer include nickel-phosphorus, gold, and silver. In some embodiments, the third layer on the aforementioned solder barrier layer may correspond to a conductive layer, such as plated nickel (Ni), nickel / chromium (Ni / Cr), silver (Ag), palladium (Pd), tin (Sn), lead / tin (Pb / Sn), or other suitable plated solder.

[0152] Additionally, a metal coating may be formed and then an electroplating step may be performed to provide a resistive alloy or higher resistive metal alloy coating over such metal coating, such as an electroless nickel-phosphorus (Ni-P) alloy. However, it should be understood that any metal coating may be included as would be appreciated by one of ordinary skill in the art from the complete disclosure herein.

[0153] It should be understood that any of the above steps can be performed as a batch process, such as a barrel plating process, a fluidized bed plating process, and / or a flow-through plating termination process, all of which are known in the art. Such a batch process can process multiple components at once, thereby providing an efficient and fast termination process. This is a particular advantage over conventional termination methods such as thick film termination printing that requires individual component processing.

[0154] As described herein, the formation of the external terminations is generally guided by the location of the exposed front edges of the lead tabs of the internal electrode layers. This phenomenon may be referred to as "self-determining" because the formation of the external plated terminations is determined by the configuration of the conductive metal exposed by the internal electrode layers at selected peripheral locations on the capacitor.

[0155] Other aspects of the above-described techniques for forming thin film plated terminations are described in the following patents: U.S. Pat. No. 7,177,137 to Ritter et al. and U.S. Pat. No. 7,463,474 to Ritter et al., which are incorporated herein by reference for all purposes. It should be understood that additional techniques for forming capacitor terminals may also be within the scope of the present technology. Exemplary alternatives include, but are not limited to, forming terminations by: plating; magnetic; masking; electrophoresis / electrostatic; sputtering; vacuum deposition; printing; or other techniques for forming thick film conductive layers or thin film conductive layers.

[0156] In addition, the capacitor can then be subjected to a solder mask. For example, this can allow the capacitor to be coated. Without limitation, such a mask can help prevent oxidation of a coating such as a copper coating, particularly where such a layer is the final coating of an external terminal. Such a solder mask material need not be limited by the present invention. For example, such a material can include any of those materials mentioned above for the solder barrier layer. Additionally or alternatively, such a material can include an epoxy resin, such as a liquid epoxy resin that is subsequently cured.

[0157] When providing such material on a capacitor, it may be necessary to touch the plating and external terminals to form an electrical connection. At this point, a laser may be used to form a hole through the mask layer. Such a hole may then be filled with a conductive material such as copper. This may then be used to form an electrical connection to the capacitor.

[0158] Go to Figure 4 and Figure 5 , the capacitors disclosed herein can be mounted using various means. For example, the capacitors can be mounted on a circuit board that includes a substrate (e.g., an insulating layer) having an upper surface and a lower surface. Figure 4 ,For example Figure 3A The capacitor 300 is shown mounted on a circuit board 450 having an upper surface 452 and a lower surface 454. The circuit board 450 has a plurality of current paths defined therein. The external terminals 312, 314 of the capacitor 300 are electrically connected to the predetermined current paths of the circuit board 450, respectively. In addition, any method known in the art (e.g., common welding techniques) can be used to physically connect the external terminals 312, 314 of the capacitor 300 to the circuit board 450. It should be understood that the capacitor 300 is used only by way of example; in other embodiments, the capacitor 100 and / or the capacitor 200 can be mounted to a mounting surface (e.g., the circuit board 450).

[0159] like Figure 5 As shown, an integrated circuit package 560 may also be disposed on the circuit board 550. The integrated circuit package 560 may be connected to the circuit board 550 using a ball grid array 562. The circuit board may also include a processor 564. The processor 564 may also be connected to the integrated circuit package 560 using a ball grid array 566.

[0160] Generally speaking, the ball grid array 562 can be configured so that the pitch is 1.5 mm or less (e.g., 1.25 mm or less, e.g., 1 mm or less, e.g., 0.8 mm or less, e.g., 0.6 mm or less) and 0.4 mm or greater (e.g., 0.5 mm or greater, e.g., 0.6 mm or greater).

[0161] In addition, the integrated circuit package 560 may also be connected to the circuit board 550 using the capacitor defined herein. In this regard, the internal electrode layers of the capacitor 100 / 200 / 300 may be arranged so that the internal electrode layers are orthogonal to the horizontal planes of the circuit board 550 and the integrated circuit package 560. In other words, the internal electrode layers of the capacitor 100 / 200 / 300 may be positioned so that the internal electrode layers are not substantially parallel to the circuit board 550. For example, the capacitor 100 / 200 / 300 may be positioned between the integrated circuit package 560 and the circuit board 550 so that the capacitor 100 / 200 / 300 is "sandwiched" between the two components. In this regard, the capacitor 100 / 200 / 300 is directly connected to the integrated circuit package 560 and the circuit board 550. For example, the capacitor 100 / 200 / 300 may be connected (e.g., physically connected and / or electrically connected) to the circuit board 550 and / or the circuit package 560 using any method known in the art (e.g., common soldering techniques).

[0162] By using capacitors in the above arrangement, capacitors 100 / 200 / 300 can allow for removal of portions of the original ball grid array 562. However, as Figure 5 As shown, capacitors 100 / 200 / 300 may still be surrounded by ball grid array 562 .

[0163] Therefore, if Figure 5 As shown, the capacitor 100 / 200 / 300 of the present invention can be directly connected to the integrated circuit package 560 and the circuit board 550 (eg, a printed circuit board). This direct connection allows current 568 to flow through the capacitor, thereby providing a direct power ground connection.

[0164] In addition to the above, although not shown herein, in one embodiment, the integrated circuit package itself may include a multilayer capacitor. In this regard, the capacitor may be embedded directly into the package. This combination of capacitors may allow for reduced size, which is beneficial for various electronic applications.

[0165] Although the foregoing provides an example of a means for mounting a capacitor as disclosed herein, it should be understood that other methods may also be utilized. For example, the capacitor may be mounted via a land grid array configuration. The capacitor may also be embedded in another substrate or component.

[0166] In the embodiments referenced above, the internal electrode layers are generally oriented in a vertical configuration. Of course, this is by no means necessary, and other geometric configurations (such as a horizontal configuration) are also equally suitable.

[0167] Those of ordinary skill in the art may practice these and other modifications and variations of the present invention without departing from the spirit and scope of the present invention. In addition, it should be understood that the various aspects of the various embodiments may be interchangeable in whole or in part. Furthermore, those of ordinary skill in the art will recognize that the foregoing description is by way of example only and is not intended to limit the present invention as further described in the appended claims.

Claims

1. A multilayer capacitor, the multilayer capacitor include: A body, the body having a top surface, a bottom surface opposite to the top surface, a pair of side surfaces opposite to each other in a transverse direction, and a pair of end surfaces opposite to each other in a longitudinal direction, the body also having side edges, the side edges defining the transverse boundaries of the top surface and the bottom surface, and the side edges including a first top side edge, a second top side edge, a first bottom side edge, and a second bottom side edge, the first top side edge, the second top side edge, the first bottom side edge, and the second bottom side edge each extending between the pair of end surfaces in the longitudinal direction, the first top side edge and the second top side edge opposite to each other in the transverse direction, the first bottom side edge and the second bottom edge opposite to each other in the transverse direction, the body comprising alternating dielectric layers and internal electrode layers, the internal electrode layers including a first internal electrode layer and a second internal electrode layer, each internal electrode layer including: a main body having a top edge, a bottom edge opposite to the top edge, and two side edges extending between the top edge and the bottom edge, at least one lead tab extending from the top edge of the body of the internal electrode layer and at least one lead tab extending from the bottom edge of the body of the internal electrode layer; and external terminals, the external terminals including a first external terminal disposed on at least one of the top surface or the bottom surface and electrically connected to the first internal electrode layer, and a second external terminal disposed on at least one of the top surface or the bottom surface and electrically connected to the second internal electrode layer, Wherein, the external terminals are arranged in a linear manner on at least one of the top surface or the bottom surface of the body and are spaced apart from the side edge of the body, so that only dielectric material is provided between the external terminals and the side edge of the body.

2. The multilayer capacitor according to claim 1, in, The first external terminal is disposed adjacent to a first end surface of the pair of end surfaces of the body, and the second external terminal is disposed adjacent to a second end surface of the pair of end surfaces of the body, wherein the first external terminal and the second external terminal are spaced apart from each other along the longitudinal direction on the top surface by an end external terminal spacing distance, wherein the body has a body length in the longitudinal direction, and Wherein, the ratio of the length of the body to the spacing distance between the end external terminals is 1.1 or greater.

3. The multilayer capacitor according to claim 2, in, The ratio of the body length to the distance between the end external terminals is in the range of 2 to 500.

4. The multilayer capacitor according to claim 2, in, The ratio of the body length to the distance between the end external terminals is in the range of 10 to 100.

5. The multilayer capacitor according to claim 1, in, The first external terminal is disposed adjacent to a first end surface of the pair of end surfaces of the body, and the second external terminal is disposed adjacent to a second end surface of the pair of end surfaces of the body, wherein the first external terminal is formed on the top surface, the bottom surface, and the first end surface from the top surface to the bottom surface, so that the first external terminal is arranged on the top surface, the bottom surface, and the first end surface, and Wherein, the second external terminal is formed on the top surface, the bottom surface and the second end surface from the top surface to the bottom surface, so that the second external terminal is arranged on the top surface, the bottom surface and the second end surface.

6. The multilayer capacitor according to claim 1, in, The external terminals are arranged in at least two columns, and the at least two columns are spaced apart from each other along the longitudinal direction.

7. The multilayer capacitor according to claim 6, in, The number of columns of the external terminals is equal to the number of lead tabs extending from the top edge of the body of a corresponding one of the internal electrode layers.

8. The multilayer capacitor according to claim 1, in, The body has end edges defining longitudinal boundaries of the top surface and the bottom surface, and the end edges include a first top edge, a second top edge, a first bottom edge, and a second bottom edge, the first top edge, the second top edge, the first bottom edge, and the second bottom edge each extending between the pair of side surfaces along the transverse direction, the first top edge and the second top edge facing each other along the longitudinal direction, the first bottom edge and the second bottom edge facing each other along the longitudinal direction, and The external terminal is spaced apart from the end edge of the body, so that only dielectric material is disposed between the external terminal and the end edge of the body.

9. The multilayer capacitor according to claim 1, in, The external terminals include adjacent terminals spaced apart from each other by an adjacent external terminal spacing distance in the longitudinal direction on the top surface, wherein the body has a body length in the longitudinal direction, and Wherein, the ratio of the length of the body to the spacing distance between adjacent external terminals is 1.1 or greater.

10. The multilayer capacitor according to claim 9, in, The ratio of the body length to the spacing distance between adjacent external terminals is in the range of 2 to 500.

11. The multilayer capacitor according to claim 9, in, The ratio of the body length to the spacing distance between adjacent external terminals is in the range of 10 to 100.

12. The multilayer capacitor according to claim 2, in, The external terminals include an adjacent terminal adjacent to the first external terminal on the same surface of the body, wherein the first external terminal and the adjacent terminal are spaced apart from each other in the longitudinal direction by an adjacent external terminal spacing distance on the same surface, and Wherein, the ratio of the spacing distance between the end external terminals to the spacing distance between the adjacent external terminals is 1.1 or greater.

13. The multilayer capacitor according to claim 12, in, The ratio of the distance between the end external terminals to the distance between the adjacent external terminals is in the range of 2 to 500.

14. The multilayer capacitor according to claim 12, in, The ratio of the distance between the end external terminals to the distance between the adjacent external terminals is in the range of 10 to 100.

15. The multilayer capacitor according to claim 1, in, Defines the spacing between adjacent external terminals, wherein the body has a body length in the longitudinal direction, and Wherein, the ratio of the body length to the spacing is 1.1 or greater.

16. The multilayer capacitor according to claim 15, in, The ratio of the body length to the spacing is in the range of 2 to 500.

17. The multilayer capacitor according to claim 15, in, The ratio of the body length to the spacing is in the range of 10 to 100.

18. The multilayer capacitor according to claim 1, in, The first external terminal is arranged on the top surface of the body, and the second external terminal is arranged on the top surface of the body, and wherein the external terminals also include a third external terminal arranged on the bottom surface and electrically connected to the first internal electrode layer and a fourth external terminal arranged on the bottom surface and electrically connected to the second internal electrode layer.

19. The multilayer capacitor according to claim 1, in, The first and second internal electrode layers are interleaved in opposing relationship with a dielectric layer positioned between each first and second internal electrode layer.

20. The multilayer capacitor according to claim 19, in, The dielectric layer includes ceramic.

21. The multilayer capacitor according to claim 1, in, Each internal electrode layer includes at least two lead tabs, which extend from the top edge of the main body, from the bottom edge of the main body, or from both the top edge and the bottom edge of the main body, and the two lead tabs include a first lead tab and a second lead tab.

22. The multilayer capacitor according to claim 21, in, The first lead tab extends from the top edge and the second lead tab extends from the bottom edge, and Wherein, at least one lateral edge of the first lead tab is substantially aligned with at least one lateral edge of the second lead tab.

23. The multilayer capacitor according to claim 21, in, The first lead tab extends from the top edge and the second lead tab extends from the bottom edge, wherein each of the first lead tab and the second lead tab comprises two lateral edges, and Wherein, two lateral edges of the first lead tab are substantially aligned with corresponding lateral edges of the second lead tab.

24. The multilayer capacitor according to claim 1, in, At least one lateral edge of the lead tab on the top edge is substantially aligned with at least one lateral edge of the lead tab on the bottom edge.

25. The multilayer capacitor according to claim 1, in, Two lateral edges of the lead tab on the top edge are substantially aligned with corresponding lateral edges of the lead tab on the bottom edge.

26. The multilayer capacitor according to claim 1, in, The at least one lead tab extending from the top edge of the body of the internal electrode layer and the at least one lead tab extending from the bottom edge of the body of the internal electrode layer include lateral edges aligned with side edges of the body of the internal electrode layer.

27. The multilayer capacitor according to claim 1, in, The internal electrode layer includes a conductive metal.

28. The multilayer capacitor according to claim 1, in, The external terminal includes a plating layer.

29. The multilayer capacitor according to claim 1, in, The external terminal includes an electroless plating layer.

30. The multilayer capacitor according to claim 1, in, The external terminal includes a chemical plating layer and an electroplating layer.

31. The multilayer capacitor according to claim 1, in, The external terminal includes a first chemical plating layer, a second electroplating layer, and a third electroplating layer.

32. The multilayer capacitor according to claim 31, in, The first chemical plating layer includes copper, the second electroplating layer includes nickel, and the third electroplating layer includes tin.

33. The multilayer capacitor according to claim 1, in, The capacitor includes at least three sets of alternating dielectric layers and internal electrode layers.

34. A circuit board comprising the multilayer capacitor of claim 1 positioned on the circuit board.

35. The circuit board according to claim 34, in, The board also includes an integrated circuit package, and wherein the multilayer capacitor is positioned vertically between the circuit board and the integrated circuit package such that the circuit board, the multilayer capacitor, and the integrated circuit package are presented in a stacked arrangement.

36. The circuit board according to claim 35, in, The multilayer capacitor is directly connected to the circuit board and the integrated circuit package.

37. An integrated circuit package comprising the multilayer capacitor of claim 1.

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