Hardware NVMe atomic writing implementation method

Abstract

The invention provides a hardware NVMe atomic writing implementation method. A data cache region is arranged on a data path; the data cache region caches data corresponding to the write instruction and detects the data corresponding to the write instruction, and if the data corresponding to the write instruction is smaller than the data size specified by atomic write and no error is detected, the write instruction and the data corresponding to the write instruction are sent; and if the write instruction has a data error during transmission, discarding the data, cached in the data cache region, of the write instruction. According to the method, the data cache region of the write instruction is added through hardware, and under the condition that the data size of the write instruction is smaller than the data size specified by atomic write Atomic, it is guaranteed that a CPU of the SSD controller does not receive the condition that only part of data of the write instruction appears, and then the Atomic function is achieved.

Description

Technical Field

[0001] The present invention relates to the field of solid - state drive storage, and more particularly to a method for implementing hardware NVMe atomic write. Background Art

[0002] The NVMe SSD Atomic function ensures that for an SSD, there will be no situation where only part of the data in a write instruction is written. Only two situations are allowed: either all the data within the same write instruction is written, or all the data within a write instruction is not written. Existing NVMe SSDs use the method of software L2P mapping table rollback to implement the atomic write function. For example, for a 128K write instruction, the first 64K of data has been successfully written to the NAND flash, and the L2P mapping table has been updated. However, the subsequent 64K cannot complete data transmission due to a PCIe link disconnection. To ensure the atomic write property, the software needs to roll back the L2P mapping table corresponding to the first 64K of data to ensure that all the data corresponding to this 128K instruction has not been written to the NAND flash. However, this solution has high complexity, and the situation becomes very complicated after garbage collection (GC), and functional errors are likely to occur. Summary of the Invention

[0003] The object of the present invention is to provide an easy - to - implement method for implementing hardware NVMe atomic write.

[0004] According to one aspect of the present invention, a method for implementing hardware NVMe atomic write is provided.

[0005] A data buffer is set on the data path.

[0006] The data buffer caches the data corresponding to the write instruction and detects the data corresponding to the write instruction.

[0007] If the data corresponding to the write instruction is less than the data size specified for atomic write and no error is detected, the write instruction and the data corresponding to the write instruction are sent.

[0008] If a data error occurs during the transmission of the write instruction, the data that has been cached in the data buffer for the write instruction is discarded.

[0009] If the data size of the data corresponding to the write instruction cached in the data buffer reaches the data size specified for atomic write and the data corresponding to the cached write instruction has passed the detection without error, the write instruction and the data corresponding to the write instruction that has been cached in the data buffer are sent.

[0010] In some embodiments, the write instructions are temporarily stored in the command queue and executed sequentially.

[0011] In some embodiments, it further includes the processing of read instructions and other instructions;

[0012] The logical address ranges of the write instruction, the read instruction, and the other instructions are stored in the command information set.

[0013] In some embodiments, it further includes the operation of the read instruction:

[0014] Compare the logical block address range of the read instruction with the logical block address range of the write instruction;

[0015] If the comparison is consistent, put the read instruction into the command queue for sequential execution;

[0016] If the comparison is inconsistent, put the read instruction into the read command queue for overtaking operation.

[0017] In some embodiments, it further includes the operation of other instructions, and put the other instructions into the command queue for sorting and execution.

[0018] In some embodiments, if there are other instructions stored in the command queue, put the read instruction into the command queue for sorting and execution.

[0019] In some embodiments, the command information set further stores other information corresponding to the write instruction, the read instruction, and the other instructions. After the write instruction, the read instruction, and the other instructions in the command queue and the read command queue are transmitted, clear the other information corresponding to the write instruction, the read instruction, and the other instructions stored in the command information set.

[0020] The beneficial effects are as follows: By adding a data buffer for write instructions in hardware, in the case where the data of a write instruction is less than the data size specified by Atomic Write (Atomic), it is ensured that the CPU of the SSD controller will not receive a situation where only partial data appears in the write instruction, thereby realizing the Atomic function. At the same time, it avoids the occurrence of the situation of falling back to the mapping table from logical address to physical address (L2P), greatly reducing the complexity of implementing the Atomic Write scheme. Description of the Drawings

[0021] Figure 1 It is a flowchart showing a method for implementing hardware NVMe atomic write according to an embodiment of the present invention. Detailed Embodiments

[0022] The present invention will be further described below with reference to the drawings.

[0023] Figure 1Schematically shows a hardware NVMe atomic write implementation method of the present invention. As Figure 1 shown, the present invention includes processing operations for write instructions, read instructions, and other instructions. The data corresponding to the write instruction is temporarily stored in the data buffer, and the read instruction and other instructions only have instruction information without data. Among them, hardware NVMe refers to a hardware device that supports the NVMe protocol, such as an SSD and its controller.

[0024] For the write instruction, a data buffer is added to the original data path. The write instruction will be temporarily stored in the command queue (CMD FIFO), and the data of the write instruction will be temporarily stored in the data buffer. The data buffer will send the write instruction out only after detecting that a complete write instruction has no errors, and give it to the CPU of the subsequent SSD master controller for processing. The data buffer caches a part of the data obtained by an instruction, and does not complete the error detection of all data. After all the data of an instruction is completed with error detection, the instruction is sent out. If a write instruction encounters a data error during transmission, such as data 0 being changed to data 1 during transmission, the occurrence of a data error will cause the PCIe link to disconnect. If the PCIe link disconnects during data transmission and subsequent data cannot be obtained, the SSD master controller will discard all the instruction information and data cached before this write command, thereby ensuring that part of the data of a write instruction will not be transmitted to the CPU of the SSD master controller, and thus the situation where part of the error data is transmitted to the CPU of the SSD master controller will not occur; at the same time, it can avoid the problem that too much data is cached in the write instruction, resulting in the subsequent read instruction being delayed, and thus the read instruction delay increases.

[0025] Specifically, write commands will all enter the command queue (CMD FIFO). The hardware determines whether the data buffer has collected all the data corresponding to a write command, or whether the amount of data collected in the data buffer meets the data size specified by the atomic write (Atomic). Among them, the data size that meets the atomic write requirement is determined by the capabilities of the NVMe device, that is, the size of the data buffer in this structure. After the NVMe device is recognized by the host, the NVMe device will report a value to the host. If the data transfer size of a write command meets the data size specified by the atomic write, even in abnormal situations such as power failure, the SSD controller can ensure that the write operation is either all successful or all failed, and there will be no partial write situation, thus ensuring the atomicity of the write command. That is, either all the data of a command is collected or the amount of data collected meets the data size specified by the atomic write (Atomic). As long as one of these two conditions is met, the atomic write (Atomic) requirement is satisfied. At the same time, if none of this data has the above-mentioned errors, the output control circuit of the SSD controller will control the write command and the data corresponding to the write command to be passed to the CPU of the SSD controller for subsequent processing. If a data error occurs during the execution of a write command, that is, the data within an instruction is not cached completely, all the information and corresponding data of the cached write command will be discarded. For example, for a 128KB write command, if a data error is found when the data is transferred to 64KB, the 64KB data previously cached in the data buffer will be read out and discarded from the data cache.

[0026] Continue as Figure 1As shown, when the present invention processes the read instruction overtaking mechanism, it first checks whether there is a conflict in the logical address of the instruction operation stored in the newly entered read instruction comparison command information set (CMD INFO). Among them, the command information set (CMD INFO) includes information such as instruction type, instruction data size, instruction error, etc., and also stores the logical address range of the instruction. The command information set quickly finds the logical block address range involved in the instruction through the logical address range. Specifically, the command information set quickly finds the logical block address range involved in the currently processed write instruction through the logical address range, and compares it with the logical block address range involved in the newly entered read instruction. If the logical block address (LBA) range of the read instruction is not within the space range of the cached write instruction, then this read instruction can be placed in the read command queue (RD CMD FIFO) for overtaking. If the LBA range of the read instruction is not within the space range of the cached write instruction, it means that the data to be read will not conflict with the write instruction currently being cached. At this time, the data corresponding to the read instruction is already stably stored in the storage medium and will not be changed due to the ongoing write instruction. Therefore, the read instruction can be inserted into the read command queue (RDCMD FIFO) for overtaking processing without affecting the consistency and integrity of the data. When the logical block address (LBA) range of the read instruction is within the space range of the cached write instruction, in order to ensure read-write consistency, the read instruction needs to be placed inside the command queue (CMD FIFO) for forced sorting with the cached write instruction. When a read instruction is received, it is compared whether there is an instruction with an overlapping logical block address (LBA) in the command information set (CMD INFO). If there is no overlapping instruction, the read instruction is placed in the read command queue (RD CMD FIFO) for the action of overtaking the command queue (CMD FIFO), that is, for the action of read overtaking and for out-of-order processing, without the need to ensure the sequentiality of data processing. If there is an overlapping instruction, the received read instruction is placed in the command queue (CMD FIFO) for forced sorting to ensure the consistency of read and write instructions.

[0027] Specifically, if there is a conflict in the logical address of the instruction operation stored in the newly entered read instruction comparison command information set (CMD INFO), it is placed in the command queue (CMD FIFO) like other commands and executed in the order of entry. If there is no conflict in the logical address of the instruction operation stored in the newly entered read instruction comparison command information set (CMD INFO), it is placed in the read command queue (RD CMD FIFO), thereby enabling the instructions in the read instruction overtaking command queue (CMD FIFO) to be executed preferentially.

[0028] Continue as Figure 1As shown, when receiving other instructions such as Trim instruction / write zero instruction etc. other than write instruction or read instruction, store the other instructions in the command queue (CMD FIFO), and at the same time store the relevant information into the command information set (CMD INFO). Specifically, if the newly entered instruction is an other instruction, there is no need to compare and it is forced to be put into the command queue (CMD FIFO) for execution. At the same time, if there is any one or more other instructions stored in the command information set (CMD INFO), all the newly entered read instructions are put into the command queue (CMD FIFO) for sorting and execution, and cannot overtake.

[0029] In addition, when the instructions in the command queue (CMD FIFO) and the read command queue (RD CMD FIFO) are transmitted out, the information stored in the corresponding command information set (CMD INFO) will also be cleared.

[0030] The above are only some embodiments of the present invention, which are only used to illustrate the technical solution of the present invention, rather than to limit it. For those of ordinary skill in the art, without departing from the inventive concept of the present invention, modifying the technical solution recorded in the foregoing embodiments, or equivalently replacing some or all of the technical features therein, all fall within the protection scope of the present invention.

Claims

1. A hardware NVMe atomic write implementation method, characterized in that: Setting a data buffer area on the data path; The data buffer area caches the data corresponding to the write instruction and detects the data corresponding to the write instruction. If the data corresponding to the write instruction is smaller than the data size specified by the atomic write and no error occurs after detection, the write instruction and the data corresponding to the write instruction are sent; If a data error occurs during the transmission of the write instruction, discarding the data of the write instruction that has been cached in the data cache area; If the data size corresponding to the write instruction cached in the data cache area reaches the data size specified by atomic write, and the data corresponding to the cached write instruction has no errors after detection, then the write instruction and the data corresponding to the write instruction cached in the data cache area are sent.

2. The hardware NVMe atomic write implementation method according to claim 1, characterized in that: The write instructions are temporarily stored in a command queue and executed sequentially.

3. The hardware NVMe atomic write implementation method according to claim 1, characterized in that: It also includes the processing of read instructions and other instructions; The logical address ranges of the write instruction, the read instruction and the other instructions are stored in a command information set.

4. The hardware NVMe atomic write implementation method according to claim 3, characterized in that: It also includes operations on read instructions: Comparing the logical block address range of the read instruction with the logical block address range of the write instruction; If the comparison is consistent, the read instruction is placed in the command queue and executed in sequence; If the comparison is inconsistent, the read instruction is placed in the read command queue for overtaking operation.

5. The hardware NVMe atomic write implementation method according to claim 4, characterized in that: It also includes operations on other instructions, placing the other instructions into a command queue and sequencing them for execution.

6. The hardware NVMe atomic write implementation method according to claim 5, characterized in that: If other instructions are stored in the command queue, the read instruction is put into the command queue for sequencing and execution.

7. The NVMe atomic write implementation method according to claim 3, characterized in that: The command information set also stores other information corresponding to the write instruction, the read instruction and the other instructions. After the write instruction, the read instruction and the other instructions in the command queue and the read command queue are transmitted, the other information corresponding to the write instruction, the read instruction and the other instructions stored in the command information set is cleared.

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