Register control method, processor, system on chip and computing equipment

Abstract

The invention discloses a register control method, a processor, a system on chip and computing equipment. The method comprises the steps that in the process that a first process accesses a target register, in response to a processor, the first process is switched into a second process, the first state of the target register is obtained, and the target register is allowed to be accessed by a plurality of processes; under the condition that the first state meets a first preset state, storing the value of the target register into a target storage space; in response to the processor, switching the second process back to the first process, and obtaining a second state of the target register; and under the condition that the second state meets a second preset state, recovering the target register based on the data stored in the target storage space. According to the method and the device, the technical problems that the processing overhead of the processor is relatively high when the corresponding register needs to be updated during process switching of the processor in the related technology, and the process which needs to be realized by a processor hardware manufacturer in advance is relatively complex, time-consuming and relatively high in cost are solved.

Description

Technical Field

[0001] This application relates to the field of processors, and in particular, to a register control method, a processor, a system on chip, and a computing device. Background Art

[0002] In application scenarios such as mode switching of a processor, process switching is usually required, and corresponding registers need to be updated, which may include operations such as saving and restoring.

[0003] Currently, in the related art, the implementation of the above process usually requires modifying the source code of the operating system in advance. For processor hardware manufacturers, the process of modifying the source code of the operating system and promoting it to the entire ecosystem is relatively complex, time-consuming, and costly. Moreover, the above process implemented based on modifying the source code of the operating system will cause the corresponding registers to be updated relatively frequently, and also generate processing overhead of the processor. In summary, in the related art, when the processor performs process switching and updates the corresponding registers, the processing overhead of the processor is relatively large, and the process that the processor hardware manufacturer needs to implement in advance is relatively complex, time-consuming, and costly.

[0004] In response to the above problems, no effective solution has been proposed yet. Summary of the Invention

[0005] Embodiments of this application provide a register control method, a processor, a system on chip, and a computing device, so as to at least solve the technical problems that in the related art, when the processor performs process switching and needs to update the corresponding registers, the processing overhead of the processor is relatively large, and the process that the processor hardware manufacturer needs to implement in advance is relatively complex, time-consuming, and costly.

[0006] According to an aspect of the embodiments of this application, a register control method is provided. The method includes: during the process of a first process accessing a target register, in response to the processor switching the first process to a second process, obtaining a first state of the target register, where the target register is allowed to be accessed by multiple processes; when the first state meets a first preset state, storing the value of the target register in a target storage space; in response to the processor switching the second process back to the first process, obtaining a second state of the target register; and when the second state meets a second preset state, restoring the target register based on the data stored in the target storage space.

[0007] In the above embodiments of the present application, in response to the processor switching the first process to the second process, obtaining the first state of the target register includes: in response to the processor switching the first process to the second process, reading the first value of the preset status bit from the preset register; determining the first state based on the first value of the preset status bit; in response to the processor switching the second process back to the first process, obtaining the second state of the target register includes: in response to the processor switching the second process back to the first process, reading the second value of the preset status bit from the preset register; determining the second state based on the second value of the preset status bit.

[0008] In the above embodiments of the present application, the first state includes one of the following: unmodified state, modified state, unaccessed state, and initial state, and the first preset state is the modified state.

[0009] In the above embodiments of the present application, the second state includes one of the following: unmodified state, modified state, unaccessed state, and initial state, and the second preset state includes one of the following: unmodified state, modified state, and initial state.

[0010] In the above embodiments of the present application, the method further includes: in response to a write request sent by the first process, modifying the value of the target register based on the write request; modifying the state of the target register to the modified state.

[0011] In the above embodiments of the present application, after storing the value of the target register into the target storage space, the method further includes: modifying the state of the target register to the unmodified state.

[0012] In the above embodiments of the present application, the method further includes: in response to a reset of the target register, modifying the state of the target register to the unaccessed state; in response to the first process accessing the target register, modifying the state of the target register to the initial state.

[0013] In the above embodiments of the present application, the target register is at least one register among at least one user-mode control register.

[0014] In the above embodiments of the present application, the target storage space is the process control block corresponding to the first process.

[0015] According to another aspect of the embodiments of the present application, there is also provided a processor, including: a target register, where the target register allows multiple processes to access; a target storage space for storing the value of the target register; and an operating system kernel unit for executing the methods in the various embodiments of the present application.

[0016] According to another aspect of the embodiments of the present application, there is also provided a system-on-chip including the processor in the various embodiments of the present application.

[0017] According to another aspect of the embodiments of the present application, there is also provided a computing device, including: a memory storing an executable program; a processor for running the program, wherein when the program runs, it executes the methods in the various embodiments of the present application.

[0018] According to another aspect of the embodiments of the present application, there is also provided a computer-readable storage medium, the computer-readable storage medium including a stored executable program, wherein when the executable program is executed by a processor, it implements the methods in the various embodiments of the present application.

[0019] According to another aspect of the embodiments of the present application, there is also provided a computer program product, including computer instructions, the computer instructions implementing the methods in the various embodiments of the present application when executed by a processor.

[0020] According to another aspect of the embodiments of the present application, there is also provided a computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing computer instructions, the computer instructions implementing the methods in the various embodiments of the present application when executed by a processor.

[0021] According to another aspect of the embodiments of the present application, there is also provided a computer program, the computer instructions implementing the methods in the various embodiments of the present application when executed by a processor.

[0022] In an embodiment of the present application, during the process of a first process accessing a target register, when the processor switches the first process to a second process, the first state of the target register can be obtained, and it can be determined whether the first state meets a first preset state. When the first state meets the first preset state, the value of the target register can be stored in a target storage space. When the processor switches the second process back to the first process, the second state of the target register can be obtained, and it can be determined whether the second state meets a second preset state. If the second state meets the second preset state, the target register can be restored based on the data in the target storage space. It is easy to note that in response to a process switch in the present application, the first state or the second state of the corresponding target register is obtained, and after determining that a certain condition is met based on the first state or the second state, the target register is stored or restored, so as to realize the conditional update of the target register, avoid frequent updates of the target register, facilitate the delayed saving and deferred restoration of the target register. In this way, it can ensure that the first process can continue to execute the previous operations when switching back, and on the premise that the second process can normally access the target register, reduce the overhead of the processor during process context switching. In particular, during the R & D and design process of the processor, the processor hardware manufacturer can perform corresponding pre-settings on the processor without modifying the source code of the operating system. The obtained processor can implement the above process in actual applications, reduce the processor overhead, and can reduce the complexity, cycle and cost of the processor hardware manufacturer during the R & D and design process of the processor, thereby solving the technical problems in the related art that when the processor switches processes and needs to update the corresponding registers, the processing overhead of the processor is relatively large, and the process that the processor hardware manufacturer needs to implement in advance is relatively complex, time-consuming and costly.

[0023] It is easy to note that the above general description and the following detailed description are only for exemplifying and explaining the present application, and do not constitute a limitation to the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The illustrative embodiments and descriptions thereof of the present application are used to explain the present application, and do not constitute an improper limitation to the present application. In the drawings:

[0025] Figure 1 is a hardware structure block diagram of a RISC-V system for implementing a register control method according to an embodiment of the present application;

[0026] Figure 2 is a schematic diagram of a system-on-chip of a RISC-V architecture according to an embodiment of the present application;

[0027] Figure 3It is a flowchart of a register control method according to an embodiment of the present application;

[0028] Figure 4 It is a schematic diagram of obtaining target registers by partitioning according to an embodiment of the present application;

[0029] Figure 5 It is a schematic diagram of a preset register and a preset status bit according to an embodiment of the present application;

[0030] Figure 6 It is a schematic diagram of implementing a delay save and a delay recovery process according to an embodiment of the present application;

[0031] Figure 7 It is a schematic diagram of a register control device according to an embodiment of the present application;

[0032] Figure 8 It is a structural block diagram of a computing device according to an embodiment of the present application. Detailed implementation manners

[0033] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data used can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily need to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0035] First, some nouns or terms that appear in the process of describing the embodiments of the present application are applicable to the following explanations:

[0036] A process control block may refer to the context in which a process exists, a data structure that stores information such as the machine state, file system state, and signal processing state of the process, and can complete all execution information representing a process when the process is switched.

[0037] Context delayed save may refer to recording the access situation of a specific extension or register group through status bits. When the corresponding register group is written, the status bit is marked as DIRTY; when context switching, the register group is saved to the process control block only when the status bit is DIRTY.

[0038] Context delayed restoration may refer to recording the access situation of a specific extension or register group through status bits. When the corresponding register group is accessed, the status bit is marked as NO_OFF; when context switching, the register group is restored from the process control block only when the status bit is NO_OFF.

[0039] User mode control register (User mode CSR) may refer to a control register that can be accessed by ordinary application programs in user mode.

[0040] According to an embodiment of the present application, a register control method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0041] The method embodiment provided by the first embodiment of the present application can be executed in a RISC-V system, a RISC-V chip or a similar device. Figure 1 A hardware structure block diagram of a RISC-V system for implementing a register control method is shown. As Figure 1 shown, the RISC-V system can be divided from the bottom layer to the upper layer into a reduced instruction set architecture 101 (including a basic instruction set 101-1 and an extended instruction set 101-2), a hardware layer 102 (including a processor 102-1, a peripheral hardware circuit 102-2, etc.), an interface layer 103, an operating system layer 104 (supporting multiple operating systems 104-1, 104-2,..., 104-n, such as Linux, FreeSBD, RT-Tread, etc.), a middleware and library layer 105 (including a system library 105-1, an API 105-2, and a middleware service 105-3), and an application layer 106 (including multiple user programs and services 106-1, 106-2,..., 106-n). The RISC-V system also includes a tool chain 107 between the bottom layer hardware and the application layer, and the tool chain can include a compiler and an assembler 107-1, a linker 107-2, a debugger 107-3, a simulator and an emulator 107-4, an integrated development environment 107-5, a hardware description language tool 107-6, a performance analysis tool 107-7, and a version control system 107-8, etc.

[0042] The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including the base instruction set and the extended instruction set. Among them, the base instruction set represents the basic integer instruction set, such as RV32I and RV64I, and the extended instruction set can be floating-point, atomic operations, compressed instructions, etc.

[0043] The interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution unit, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

[0044] The operating system layer 104 is located above the hardware and provides a hardware abstraction layer and management mechanism, enabling applications to interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, etc.

[0045] The middleware and library layer 105 provides a rich set of services and interfaces to help applications run more efficiently. For example, the standard library provides functions such as file operations and mathematical calculations, while middleware can provide complex services such as network communication and graphical user interfaces.

[0046] The application layer 106 utilizes the functions and services provided by the lower layers to implement specific application logics. These applications can be command-line tools, graphical interface applications, server-side services, etc.

[0047] The toolchain 107 is a key component connecting the underlying hardware to the upper-layer software. The various tools in the toolchain 107 play roles at different levels to support the entire process from hardware design to software development, ensuring the coherence and effectiveness of the entire system design.

[0048] It should be noted that the hierarchical design of the RISC-V architecture allows decoupling between different layers, enabling each layer to be developed and optimized independently.

[0049] In an alternative embodiment, Figure 2 shows the use of the above Figure 1 The schematic diagram of a System On Chip (SOC) using the RISC-V architecture shown. As Figure 2As shown, the SOC internally includes at least one RISC-V core 202 (only one is shown in the figure). The RISC-V core 202 is connected to peripheral devices through a bus 204, including but not limited to a ROM 206, a RAM 208, a timer 210, a UART (Universal Asynchronous Receiver / Transmitter) 212, a GPIO (General Purpose Input / Output) 214, an SPI (Serial Peripheral Interface Bus) 216, etc.

[0050] Under the above operating environment, the present application provides a register control method as Figure 3 shown, Figure 3 which is a flowchart of a register control method according to an embodiment of the present application. As Figure 3 shown, it may specifically include the following steps:

[0051] Step S302, during the process of a first process accessing a target register, in response to the processor switching the first process to a second process, obtain the first state of the target register.

[0052] Among them, the target register allows multiple processes to access.

[0053] The above-mentioned processor, that is, a Central Processing Unit (CPU), may refer to an electronic device capable of executing instructions and processing data. The processor completes various computing and data processing tasks by executing instructions stored in the memory, including arithmetic operations, logical operations, data transmission, etc. The processor can control the operation of the internal circuit through a clock signal and decode and execute different instructions according to the Instruction Set Architecture (ISA). The processor may be composed of an arithmetic unit, a control unit, and registers. Among them, the arithmetic unit can be used to perform arithmetic and logical operations, the control unit can be responsible for controlling the execution flow of instructions, and the registers are used to store temporary data and instructions.

[0054] The above-mentioned target register can be a user-mode control register that allows multiple user-mode processes to access it, or it can be other privileged-mode registers that allow multiple privileged-mode processes to access it. Among them, the user-mode control register can refer to a set of registers used to store the running state information and control information of the processor. These user-mode control registers can be accessed and operated by user-mode programs. The user-mode control register can be used to store the state during program operation, such as the program counter, stack pointer, etc.; the privileged-mode register can refer to a set of registers used to store the running state information and control information in the privileged mode of the processor. Through privileged-mode programs, such as the operating system kernel, these privileged-mode registers can be accessed and operated. The privileged-mode register can be used to store information such as the privileged level of the processor operation, the interrupt vector table, and the memory management unit configuration. The target register can also be determined according to actual needs and is not limited here.

[0055] In an alternative embodiment, in application scenarios such as mode switching by the processor, process switching is usually required, and the target register needs to be updated. Specifically, during the process of process switching, in response to the processor switching the first process to the second process, the processor can first obtain the first state of the target register, so that subsequent conditional determination-based updates of the target register can be realized, avoiding frequent updates of the target register, thereby realizing delayed saving of the target register. This can ensure that the first process can continue to execute the previous operations when switching back, and on the premise that the second process can normally access the target register, reduce the overhead during the process context switching of the processor. The technical solution proposed in this application can be applied to the processor control process. Processor hardware manufacturers can perform corresponding pre-settings on the processor during the processor design process without modifying the operating system source code. The obtained processor can execute the methods in the embodiments of this application in actual applications, realizing the reduction of processor overhead, and can reduce the R & D cycle and R & D cost of processor hardware manufacturers. Through reasonable design and implementation, the performance, flexibility, and reliability of the processor can be improved, providing guarantee for the stable operation and efficient task execution of the processor.

[0056] The above-mentioned processor's mode switching may refer to the need to switch the operation mode of the processor when executing different types of instructions or processing different data types. These operation modes may include, but are not limited to, rounding modes for floating-point operations, flushing denormalized numbers to 0, propagation of Not a Number (NaN), etc. For example, for floating-point operations, the processor may need to select different rounding modes according to specific application scenarios, such as rounding up, rounding down, rounding towards zero, etc. If the processor only supports the rounding modes defined by the Reduced Instruction Set Computer (RISC) standard specification, problems may occur when processing denormalized numbers or NaN propagation. To support these features, the processor needs to introduce new modes and achieve the switching of different operation modes through mode switching. In practical applications, the processor may perform mode switching at the instruction level or data level to ensure that the processor can correctly process various data types and operation modes. The processor's mode switching can support the processing of different types of instructions and data types, thereby improving the flexibility and performance of the processor. By introducing new modes and performing mode switching, the processor can better adapt to different application scenarios and provide more comprehensive function and performance support.

[0057] Step S304, when the first state meets the first preset state, store the value of the target register into the target storage space.

[0058] The above-mentioned first preset state may refer to a pre-set determination condition for judging the first state, which can determine whether the first state meets the preset determination condition. Only when the first state meets the first preset state will the value of the target register be stored into the target storage space, while when the first state does not meet the first preset state, the storage of the value of the target register into the target storage space can be postponed or not performed to achieve delayed saving.

[0059] The above-mentioned target storage space may refer to a process control block for storing the value of a target register, etc. A process control block (PCB) can be a data structure used by an operating system to manage and control processes. Each process can have a corresponding PCB in the operating system, which is used to store relevant information of the process, including the process identifier, status, priority, program counter, register value, memory allocation, open file list, resource usage, etc. Through the PCB, the operating system can track and manage the status of each process, and implement operations such as process creation, scheduling, switching, and termination. When a process is created, the operating system allocates a PCB for it and adds it to the process queue; when the process is scheduled to execute, the operating system restores the process context according to the information in the PCB and executes the corresponding program; when the process is blocked or terminated, the operating system updates the information in the PCB, releases resources, and removes it from the process queue. The PCB is a data structure used by the operating system to manage processes, stores relevant information of the process, and facilitates the operating system to manage and control processes. The target storage space can also be determined according to actual needs and is not limited here.

[0060] In an optional embodiment, after obtaining the first state, it can be determined whether the first state meets the first preset state. Specifically, when the first state meets the first preset state, the value of the target register is stored in the target storage space, that is, the value of the target register is saved. When the first state does not meet the first preset state, the value of the target register can be temporarily not saved, realizing delayed saving of the target register. Based on the first state of the target register, it is determined conditionally whether to save the target register, avoiding frequent saving of the target register, and realizing delayed saving of the target register. This can reduce the overhead of the processor during process context switching on the premise of ensuring that the first process can continue to execute the previous operations when switching back and ensuring that the second process can normally access the target register.

[0061] Step S306, in response to the processor switching the second process back to the first process, obtain the second state of the target register.

[0062] In an alternative embodiment, during the process of process switching, in response to the processor switching the second process back to the first process, the processor can obtain the second state of the target register, which facilitates subsequent conditional update of the target register based on the second state, avoiding frequent updates to the target register and facilitating the delayed restoration of the target register. This can reduce the overhead of the processor during process context switching on the premise of ensuring that the first process can continue to execute the previous operations when switched back and ensuring that the second process can normally access the target register. The above process can be applied to the processor control process, and the processor hardware manufacturer can perform corresponding pre-settings on the processor during the processor design process without modifying the source code of the operating system, thereby reducing the processor overhead.

[0063] Step S308, when the second state meets the second preset state, restore the target register based on the data stored in the target storage space.

[0064] The above-mentioned second preset state can refer to a pre-set determination condition for judging the second state, which can determine whether the second state meets the preset determination condition. Only when the second state meets the second preset state, restore the target register based on the data stored in the target storage space. When the second state does not meet the second preset state, the restoration of the target register based on the data stored in the target storage space can be postponed or not performed to achieve delayed restoration.

[0065] In an alternative embodiment, finally, after obtaining the second state, it can be determined whether the second state meets the second preset state. Specifically, when the second state meets the second preset state, the target register can be restored based on the data stored in the target storage space, that is, the target register is restored. When the second state does not meet the second preset state, the value of the target register can be temporarily not restored, realizing the delayed restoration of the target register. Based on the second state of the target register, the restoration of the target register is conditionally performed, avoiding frequent restoration of the target register and realizing the delayed restoration of the target register. This can reduce the overhead of the processor during process context switching on the premise of ensuring that the first process can continue to execute the previous operations when switched back and ensuring that the second process can normally access the target register.

[0066] In an embodiment of the present application, during the process that a first process accesses a target register, when the processor switches the first process to a second process, the first state of the target register can be obtained, and it can be determined whether the first state meets a first preset state. When the first state meets the first preset state, the value of the target register can be stored in a target storage space. When the processor switches the second process back to the first process, the second state of the target register can be obtained, and it can be determined whether the second state meets a second preset state. If the second state meets the second preset state, the target register can be restored based on the data in the target storage space. It can be easily noted that in response to a process switch in the present application, the first state or the second state of the corresponding target register is obtained, and after determining that the first state or the second state meets certain conditions, the target register is stored or restored, so as to realize the conditional update of the target register, avoid frequent updates of the target register, facilitate the delayed saving and postponed restoration of the target register. In this way, it can be ensured that the first process can continue to execute the previous operations when switching back, and on the premise that the second process can normally access the target register, the overhead of the processor during the process context switch can be reduced. In particular, during the research and development and design process of the processor, the processor hardware manufacturer can perform corresponding pre-settings on the processor without modifying the source code of the operating system. The obtained processor can implement the above process in actual applications, reduce the processor overhead, and can reduce the complexity, cycle and cost of the processor hardware manufacturer during the research and development and design process of the processor, thereby solving the technical problems in the related art that when the processor performs a process switch and needs to update the corresponding register, the processing overhead of the processor is relatively large, and the process that the processor hardware manufacturer needs to implement in advance is relatively complex, time-consuming and costly.

[0067] In the above embodiment of the present application, in response to the processor switching the first process to the second process, obtaining the first state of the target register includes: in response to the processor switching the first process to the second process, reading a first value of a preset status bit from a preset register; determining the first state based on the first value of the preset status bit; in response to the processor switching the second process back to the first process, obtaining the second state of the target register includes: in response to the processor switching the second process back to the first process, reading a second value of the preset status bit from the preset register; determining the second state based on the second value of the preset status bit.

[0068] The above-mentioned preset register may refer to a register pre-specified in the processor. Preferably, the preset register may refer to the extension status register (xstatus) in the processor. The xstatus is a register in the RISC-V instruction set architecture and can contain various extended function status information of the processor, such as the enable status of the floating-point arithmetic unit, the interrupt enable status, etc. The preset register can also be determined according to actual needs and is not limited here.

[0069] The above-mentioned preset status bit may be a status bit added by this application to the preset register. Preferably, it may be two cross-process (CS) bits added to the preset register. The CS bit can be a flag bit in the processor. The CS bit can be identified as different values and can be determined according to actual needs and is not limited here.

[0070] In an alternative embodiment, the process of obtaining the first state of the target register may specifically include: in response to the processor switching the first process to the second process, reading the first value of the preset status bit from the preset register, and then determining the first state based on the first value of the preset status bit. The mapping relationship between the first value of the preset status bit and the first state can be preset according to actual needs. For example, it can be a one-to-one, one-to-many, or many-to-one relationship and is not limited here. In another alternative embodiment, the process of obtaining the second state of the target register may specifically include: in response to the processor switching the second process back to the first process, reading the second value of the preset status bit from the preset register, and then determining the second state based on the second value of the preset status bit. The mapping relationship between the second value of the preset status bit and the second state can be preset according to actual needs. For example, it can be a one-to-one, one-to-many, or many-to-one relationship and is not limited here. In the above process, by pre-setting the preset status bit in the preset register and using the CS bit mechanism, that is, through the status bit, the delayed saving and delayed recovery of the process context are realized, reducing the context switching cost.

[0071] In the above embodiments of this application, the first state includes one of the following: unmodified state, modified state, unaccessed state, and initial state, and the first preset state is the modified state.

[0072] The above-mentioned unmodified state may refer to the CLEAN state. When the preset status bit is in the CLEAN state, it can indicate that the first process has not modified the target register during the running time slice.

[0073] The modified state described above may refer to the DIRTY state. When the preset status bit is in the DIRTY state, it may indicate that the first process has modified the target register during the running time slice.

[0074] The unaccessed state described above may refer to the OFF state. When the preset status bit is in the OFF state, it may indicate that the target register cannot be accessed or modified by an instruction.

[0075] The initial state described above may refer to the INITIAL state. When the preset status bit is in the INITIAL state, it may indicate that the target register is in a state where it can be accessed or modified by executing an instruction.

[0076] In an alternative embodiment, the first state may be any one of the unmodified state, the modified state, the unaccessed state, and the initial state. The first preset state may be set to the modified state. Specifically, after obtaining the first state, it may be determined whether the first state is the modified state. Specifically, in the case where the first state is the modified state, the value of the target register may be stored in the target storage space, that is, the value of the target register is saved. In the case where the first state is not the modified state, the value of the target register may not be saved temporarily, realizing delayed saving of the target register. Based on the first state of the target register, the target register is saved conditionally, avoiding frequent saving of the target register, realizing delayed saving of the target register, and reducing the overhead when the processor performs process context switching.

[0077] In the above embodiment of the present application, the second state includes one of the following: the unmodified state, the modified state, the unaccessed state, and the initial state. The second preset state includes one of the following: the unmodified state, the modified state, and the initial state.

[0078] The second preset state described above may be represented as NO_OFF, which may represent any one of the four states of the unmodified state, the modified state, the unaccessed state, and the initial state except the unaccessed state. That is, the second preset state may be any one of the unmodified state, the modified state, and the initial state.

[0079] In an alternative embodiment, the second state can be any one of an unmodified state, a modified state, an unaccessed state, and an initial state, and the second preset state can be set to any one of an unmodified state, a modified state, and an initial state. Specifically, after obtaining the second state, it can be determined whether the second state is any one of an unmodified state, a modified state, and an initial state. Specifically, when the second state is any one of an unmodified state, a modified state, and an initial state, the target register can be restored based on the data stored in the target storage space, that is, the target register is restored. When the second state is not any one of an unmodified state, a modified state, and an initial state, the value of the target register can be temporarily not restored, realizing delayed restoration of the target register. Based on the second state of the target register, conditional restoration of the target register is achieved, avoiding frequent restoration of the target register, and realizing delayed restoration of the target register. This can ensure that the first process can continue to execute the previous operations when switching back, and on the premise that the second process can normally access the target register, reduce the overhead when the processor performs process context switching.

[0080] In the above embodiment of the present application, the method further includes: in response to a write request sent by the first process, modifying the value of the target register based on the write request; modifying the state of the target register to a modified state.

[0081] In an alternative embodiment, when the first process sends a write request, that is, the process needs to modify the value of the target register. To ensure the correctness of the data, the processor can modify the value of the target register and modify the state of the target register to a modified state. Specifically, first, when the first process sends a write request, the request can be received and parsed by the control logic module of the processor. The control logic module can modify the value of the target register according to the new value carried in the write request. After modifying the value of the target register, the processor synchronously sets the status bit of the preset register to the modified state, and the modified state can indicate that the value of the target register has been modified. After modifying the status bit of the preset register to the modified state, the processor can delay writing the data back to the main memory to a certain extent, thereby reducing the number of data exchanges with the main memory in the read and write operations and improving the performance of the system.

[0082] In the above embodiment of the present application, after storing the value of the target register into the target storage space, the method further includes: modifying the state of the target register to an unmodified state.

[0083] In an alternative embodiment, after storing the value of the target register into the target storage space, the status of the target register can be modified to an unmodified status to prevent interference with subsequent calculations. Specifically, first, the data in the target register can be transmitted through the data bus to the target storage space. After the data is written into the target storage space, the preset register status bit is set to the unmodified status, which can ensure that the status of the target register is not misjudged during subsequent calculations.

[0084] In the above embodiments of the present application, the method further includes: in response to the reset of the target register, modifying the status of the target register to an unaccessed status; in response to the first process accessing the target register, modifying the status of the target register to an initial status.

[0085] In an alternative embodiment, in response to the reset of the target register, the status of the target register is modified to an unaccessed status. Specifically, when the target register is reset, the processor can detect this event and modify the status flag of the target register to an unaccessed status, which can disable all accesses to the target register; when the operating system modifies the status bit of the preset register to the initial status by executing an instruction, all accesses to the target register can be enabled. In the above process, by updating the status flag of the register in a timely manner, it can be ensured that the access control of the processor to the register is effectively executed, thereby improving the stability and reliability of the system. By effectively managing and controlling the status of the register, waste of system resources and redundant operations can be reduced, and thus the system performance and efficiency can be optimized.

[0086] In the above embodiments of the present application, the target register is at least one register among at least one user-mode control register.

[0087] In an alternative embodiment, the target register can be one or more registers among the user-mode control registers that allow multiple user-mode processes to access. The user-mode control registers can be used to store the running status information and control information of the processor. The user-mode program can access and operate these user-mode control registers. The target register can be specifically determined according to actual needs and is not limited here.

[0088] In the above embodiments of the present application, the target storage space is the process control block corresponding to the first process.

[0089] In an alternative embodiment, the target storage space may be a process control block (PCB) for storing the values of target registers. Through the PCB, the operating system can track and manage the states of various processes, and implement operations such as process creation, scheduling, switching, and termination. When a process is created, the operating system allocates a PCB for it and adds it to the process queue; when the process is scheduled to execute, the operating system restores the process context according to the information in the PCB and executes the corresponding program; when the process is blocked or terminated, the operating system updates the information in the PCB, releases resources, and removes it from the process queue. The PCB is a data structure used by the operating system to manage processes, storing relevant information about the process, which facilitates the operating system to manage and control the process. The target storage space can also be determined according to actual needs and is not limited here.

[0090] The technical solution proposed in this application will be described below in conjunction with an alternative embodiment. This application proposes a method for extending user-state control registers across processes. This application can increase the freedom of CPU hardware manufacturers to design multiple execution modes, and can avoid the modification of the operating system and the degradation of ecosystem support caused by the process context dependent on mode switching. The innovation of this application lies at least in achieving automatic process context saving by adding cross-process attributes to the user-state control and status register (CSR), and realizing delayed saving and restoration of cross-process CSR context by introducing status bits, thereby reducing the context switching overhead. The cross-process attribute here may refer to cross-process CSR. When the process context is switched, the operating system will help the process save or restore the CSR. From the perspective of the application program, these CSRs have the characteristic that their values remain unchanged before and after the process switch. The delayed saving and delayed restoration here can be understood as saving and restoring when the status bit meets certain conditions. This application can achieve saving and restoring only when the status bit meets certain conditions, thus avoiding saving and restoring every time the process switches. The above context switch can be understood as the switch of the process.

[0091] In the related art, in a processor product, mode switching is usually required. For example, for floating-point operations, the RISC-V standard specification defines floating-point rounding modes, etc., but lacks other configurations such as flushing denormalized numbers to 0 and NaN propagation. If a processor is to support these features, new modes need to be introduced. Processors usually use vendor-extensible user-mode control registers to configure new modes. Such user-mode control registers are process-related and can be configured by each process. Therefore, when switching process contexts, the operating system needs to save and restore the user-mode control registers of the process. However, for processor manufacturers, modifying the operating system source code and promoting it to the entire ecosystem is relatively long and complex, and the cost is relatively high. The technical solution proposed in this application addresses this pain point of this application and proposes a cross-process user-mode control register solution, which is automatically saved and restored by the operating system during context switching, avoiding the investment of processor manufacturers in this regard and shortening the product time to market.

[0092] The technical solution proposed in this application generally includes the following parts: Set aside a part from the standard user-mode CSR address space as the cross-process context CSR. Here, the cross-process context CSR is a part of the standard CSR. Each CSR has an integer number, and the numbers of the cross-process context CSRs are different from those of other standard CSRs. All user-mode processes can access these CSRs. Add two CS (Cross-Process) bits to xstatus. These two bits have four states: CLEAN, OFF, DIRTY, and INITIAL. NO_OFF in this application can refer to the other three states except OFF. The INITIAL state can represent the initial state migrated from the OFF state after enabling. After saving the process context, it migrates from the DIRTY state to the CLEAN state. CLEAN and INITIAL are also two necessary states for implementing delayed saving and restoration. The update of the above four states requires software intervention. It is OFF during reset. Once a process uses the cross-user-mode process CSR, an exception will be generated, and the operating system will switch the state to the INITIAL state. When an application writes to the cross-process CSR, the DIRTY state will be set. When switching the context process in the DIRTY state, the cross-process CSR will be saved to the process context and switched to the CLEAN state. After that, the state usually switches between CLEAN and DIRTY. When switching process contexts, the delayed saving and delayed restoration of the cross-process user-mode CSR are implemented according to the status of the CS bits.

[0093] This application is not limited to user-mode CSR. The method of using other privileged modes to achieve automatic context restoration is also within the scope of this application. In particular, this application proposes to add cross-process context attributes and CS bit mechanisms to CSR. This application uses cross-process user-mode CSR, avoiding the cost of developing a dedicated operating system. Implementing the deferred save and restore of cross-process CSR has no additional requirements or impact on the performance or power consumption of the hardware. Since it belongs to software behavior and does not require additional hardware caching or more complex logic to support this function. Through status bits, the deferred save and deferred restore of process context are achieved, reducing the context switching cost.

[0094] Figure 4 It is a schematic diagram of obtaining target registers according to an embodiment of this application, as Figure 4 shown. A part can be set aside from the address space of the standard CSR as the cross-process context CSR, that is, the target register is obtained. Based on the cross-process context CSR and the process control block, the process can be cut out and cut in.

[0095] Figure 5 It is a schematic diagram of a preset register and a preset status bit according to an embodiment of this application, as Figure 5 shown. A preset status bit can be added to the preset register, that is, CS is added to xstatus. CS can record the status based on these cross-process user-mode CSRs such as CSR_A, CSR_B, CSR_C, and CSR_D shown in the figure.

[0096] CSR_A, CSR_B, CSR_C, and CSR_D in the above cross-process user-mode CSR can be the values of the target register, and the values of the target register can also be determined according to actual needs, which are not limited here.

[0097] Figure 6 It is a schematic diagram of implementing the deferred save and deferred restore process according to an embodiment of this application, as Figure 6 shown. The deferred save and deferred restore process can be carried out between these cross-process user-mode CSRs such as CSR_A, CSR_B, CSR_C, and CSR_D and the process control block. Specifically, when the CS status in xstatus is DIRTY, the deferred save can be carried out, and when the CS status in xstatus is NO_OFF, the deferred save can be carried out.

[0098] This application can add two CS (Cross-Process) bits to xstatus. These two bits have four states: CLEAN, OFF, DIRTY, and INITIAL. Here, NO_OFF can refer to the other three states except OFF.

[0099] According to an embodiment of the present application, there is also provided a register control device for implementing the above register control method. Figure 7 It is a schematic diagram of a register control device according to an embodiment of the present application, as Figure 7 shown. The device includes: a first acquisition module 702, a storage module 704, a second acquisition module 706, and a recovery module 708.

[0100] Among them, the first acquisition module 702 is configured to obtain a first state of the target register in response to the processor switching the first process to the second process during the access of the first process to the target register, where the target register allows multiple processes to access; the storage module 704 is configured to store the value of the target register in the target storage space when the first state meets a first preset state; the second acquisition module 706 is configured to obtain a second state of the target register in response to the processor switching the second process back to the first process; the recovery module 708 is configured to recover the target register based on the data stored in the target storage space when the second state meets a second preset state.

[0101] Among them, the first acquisition module is further configured to read a first value of a preset status bit from a preset register in response to the processor switching the first process to the second process; determine the first state based on the first value of the preset status bit; the second acquisition module is further configured to read a second value of the preset status bit from the preset register in response to the processor switching the second process back to the first process; determine the second state based on the second value of the preset status bit.

[0102] Among them, the first state includes one of the following: an unmodified state, a modified state, an unaccessed state, and an initial state, and the first preset state is a modified state.

[0103] Among them, the second state includes one of the following: an unmodified state, a modified state, an unaccessed state, and an initial state, and the second preset state includes one of the following: an unmodified state, a modified state, and an initial state.

[0104] Among them, in response to a write request sent by the first process, the value of the target register is modified based on the write request; the state of the target register is modified to a modified state.

[0105] Among them, after storing the value of the target register in the target storage space, the storage module is further configured to modify the state of the target register to an unmodified state.

[0106] Among them, in response to the target register being reset, the state of the target register is modified to an unaccessed state; in response to the first process accessing the target register, the state of the target register is modified to an initial state.

[0107] Among them, the target register is at least one register among at least one user-mode control register.

[0108] Among them, the target storage space is the process control block corresponding to the first process.

[0109] According to another aspect of the embodiments of the present application, there is also provided a processor, including: a target register, where the target register is allowed to be accessed by multiple processes; a target storage space for storing the value of the target register; and an operating system kernel unit for executing the methods in the various embodiments of the present application.

[0110] According to another aspect of the embodiments of the present application, there is also provided a system on a chip including the processor in the various embodiments of the present application.

[0111] Optionally, Figure 8 is a structural block diagram of a computing device according to an embodiment of the present application. As Figure 8 shown, the computing device A may include: one or more (only one is shown in the figure) processors 102, a memory 104, and a peripheral interface 106, where the processors 102, the memory 104, and the peripheral interface 106 are interconnected through a bus 108.

[0112] Among them, the memory can be used to store software programs and modules, such as the program instructions / modules corresponding to the methods and devices in the embodiments of the present application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, implements the methods in the above embodiments. The memory may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some instances, the memory may further include a memory remotely provided with respect to the processor, and these remote memories may be connected to the terminal A through a network. Examples of the above network include but are not limited to the Internet, an enterprise internal network, a local area network, a mobile communication network, and combinations thereof.

[0113] The processor can call the information and application programs stored in the memory through a transmission device to execute the steps in the various embodiments.

[0114] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data that have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of relevant countries and regions, and corresponding operation entrances are provided for the user to select authorization or rejection.

[0115] It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited by the described action sequence, because according to this application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0116] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions for causing a processing unit to execute the methods in various embodiments of this application.

[0117] The embodiments of this application also provide a computer-readable storage medium. Optionally, in this embodiment, the above computer-readable storage medium can be used to store the program code executed by the method provided in the above embodiment.

[0118] Optionally, in this embodiment, the above storage medium can be located in any one of the computing devices in the computing device group.

[0119] Optionally, in this embodiment, the computer-readable storage medium is set to store the following program code for execution.

[0120] During the process of the first process accessing the target register, in response to the processor switching the first process to the second process, obtain the first state of the target register, where the target register allows multiple processes to access; when the first state meets the first preset state, store the value of the target register into the target storage space; in response to the processor switching the second process back to the first process, obtain the second state of the target register; when the second state meets the second preset state, restore the target register based on the data stored in the target storage space.

[0121] Optionally, in response to the processor switching the first process to the second process, obtaining the first state of the target register includes: in response to the processor switching the first process to the second process, reading a first value of a preset status bit from a preset register; determining the first state based on the first value of the preset status bit; in response to the processor switching the second process back to the first process, obtaining the second state of the target register includes: in response to the processor switching the second process back to the first process, reading a second value of the preset status bit from the preset register; determining the second state based on the second value of the preset status bit.

[0122] Optionally, the first state includes one of the following: unmodified state, modified state, unaccessed state, and initial state, and the first preset state is the modified state.

[0123] Optionally, the second state includes one of the following: unmodified state, modified state, unaccessed state, and initial state, and the second preset state includes one of the following: unmodified state, modified state, and initial state.

[0124] Optionally, the method further includes: in response to a write request sent by the first process, modifying the value of the target register based on the write request; modifying the state of the target register to the modified state.

[0125] Optionally, after storing the value of the target register into the target storage space, the method further includes: modifying the state of the target register to the unmodified state.

[0126] Optionally, the method further includes: in response to a reset of the target register, modifying the state of the target register to the unaccessed state; in response to the first process accessing the target register, modifying the state of the target register to the initial state.

[0127] Optionally, the target register is at least one register among at least one user-mode control register.

[0128] Optionally, the target storage space is the process control block corresponding to the first process.

[0129] An embodiment of the present application further provides a computer program product. Optionally, in this embodiment, the above computer program product may include computer instructions, and when the computer instructions are executed by a processor, the method provided by the above embodiment is implemented.

[0130] The above computer program product may refer to software instructions that have been written, tested, and released, and can run on a computer or other devices. The computer program product may include application programs, operating systems, tool software, etc., for implementing specific functions or solving specific problems.

[0131] Embodiments of the present application also provide a computer program product. Optionally, the above computer program product may include a non-volatile computer-readable storage medium, which may be used to store computer instructions. When the computer instructions are executed by a processor, the methods provided in the above embodiments are implemented.

[0132] The above non-volatile computer-readable storage medium may refer to a medium for storing data. The non-volatile computer-readable storage medium can keep data from being lost when powered off and can be used to store data for long-term preservation, such as operating systems, application programs, and user files. The non-volatile storage medium may include hard disk drives, solid-state drives, optical discs, and flash storage devices, etc.

[0133] Embodiments of the present application also provide a computer program. Optionally, in this embodiment, when the above computer instructions are executed by a processor, the methods provided in the above embodiments are implemented.

[0134] The above computer instructions may refer to a set of instructions used to tell a computer to perform specific tasks or operations. Computer instructions can be written by programmers using specific programming languages and may include content such as algorithms, data structures, logic, and control flows. Computer instructions can be used for various purposes, including application software, operating systems, etc.

[0135] In the above embodiments of the present application, the descriptions of the various embodiments have their own focuses. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0136] It should be noted that the preferred implementation schemes involved in the above embodiments of the present application are the same as the schemes, application scenarios, and implementation processes provided in the above embodiments, but are not limited to the schemes provided in the above embodiments.

[0137] In several embodiments provided by the present application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of units or modules can be in an electrical or other form.

[0138] The unit described as a separation component may or may not be physically separated. The component shown as a unit may or may not be a physical unit, that is, it may be located in one place or may be distributed over multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0139] In addition, each functional unit in various embodiments of the present application may be integrated in a processing unit, may exist separately as individual physical units, or two or more units may be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0140] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, read-only memories (ROMs), random access memories (RAMs), mobile hard disks, magnetic disks, or optical discs that can store program codes.

[0141] The above are only the preferred embodiments of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

[0142] The above are only the preferred embodiments of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

Claims

1. A register control method, characterized in that: include: In a process in which a first process accesses a target register, in response to a processor switching the first process to a second process, obtaining a first state of the target register, wherein the target register allows access by multiple processes; When the first state satisfies a first preset state, storing the value of the target register into a target storage space; In response to the processor switching the second process back to the first process, acquiring a second state of the target register; In a case where the second state satisfies a second preset state, the target register is restored based on the data stored in the target storage space.

2. The method according to claim 1, characterized in that: The acquiring the first state of the target register in response to the processor switching the first process to the second process includes: In response to the processor switching the first process to a second process, reading a first value of a preset state bit from a preset register; Determining the first state based on a first value of the preset state bit; In response to the processor switching the second process back to the first process, acquiring the second state of the target register includes: In response to the processor switching the second process back to the first process, reading a second value of the preset state bit from the preset register; The second state is determined based on a second value of the preset state bit.

3. The method according to claim 1, characterized in that The first state includes one of the following: an unmodified state, a modified state, an unaccessed state and an initial state, and the first preset state is a modified state.

4. The method according to claim 1, characterized in that The second state includes one of the following: an unmodified state, a modified state, an unaccessed state, and an initial state, and the second preset state includes one of the following: an unmodified state, a modified state, and an initial state.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: In response to the write request sent by the first process, modifying the value of the target register based on the write request; The state of the target register is modified to a modified state.

6. The method according to claim 5, characterized in that After storing the value of the target register in the target storage space, the method further includes: The state of the target register is modified to an unmodified state.

7. The method according to any one of claims 1 to 4, characterized in that The method further comprises: In response to the target register being reset, modifying the state of the target register to a non-accessed state; In response to the first process accessing the target register, the state of the target register is modified to an initial state.

8. The method according to any one of claims 1 to 4, characterized in that The target register is at least one register in at least one user-mode control register.

9. The method according to any one of claims 1 to 4, characterized in that: The target storage space is a process control block corresponding to the first process.

10. A processor, characterized in that: include: A target register, wherein the target register allows access by multiple processes; A target storage space, used to store the value of the target register; An operating system kernel unit, configured to execute the method described in any one of claims 1 to 9.

11. A system on chip, characterized in that: include: The processor of claim 10.

12. A computing device, characterized in that: include: A memory storing an executable program; A processor, configured to run the program, wherein the program executes the method according to any one of claims 1 to 9 when running.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored executable program, wherein when the executable program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

14. A computer program product, characterized in that The method comprises computer instructions which, when executed by a processor, implement the method according to any one of claims 1 to 9.

Images