Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display panel is configured by arranging a part of a third pull-up control module, a third pull-down maintenance module, a part of a third inverting module, and a third negative bias prevention module in a second direction, and arranging another part of the third pull-up control module, another part of the third inverting module, and a part of the third pull-down module in the second direction. The modules are arranged in a vertical direction, the horizontal space occupied by each module is reduced, the horizontal space occupied by the third type of gate circuit is reduced, the space occupied by the gate drive circuit is reduced, and the frame of the display panel is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] OLED (Organic Light-Emitting Diode) display devices are widely used in various fields due to their lightness, wide viewing angle, low power consumption, fast response speed, low temperature resistance, high luminous efficiency, and the ability to prepare flexible display screens. In order to reduce the driving chip, reduce the frame, and reduce the cost, a gate driving circuit is used to replace the gate driving chip to drive the pixel circuit. Specifically, the gate driving circuit includes a gate circuit for controlling the reset transistor of the pixel circuit. However, during the use of the display device, it is found that the gate circuit for controlling the reset transistor of the pixel circuit occupies a large space, resulting in a large frame of the display device.

[0003] Therefore, the current display device has the technical problem that the gate circuit for controlling the reset transistor of the pixel circuit occupies a large space, resulting in a large frame of the display device. SUMMARY

[0004] The embodiments of the present application provide a display panel and a display device to solve the technical problem that the current display device has the gate circuit for controlling the reset transistor of the pixel circuit occupying a large space, resulting in a large frame of the display device.

[0005] In order to achieve the above-mentioned purpose, according to the first aspect of the present application, a display panel is provided, which comprises:

[0006] a plurality of rows of pixels, the pixels comprising a light emitting device and a pixel driving circuit, the pixel driving circuit comprising a reset transistor;

[0007] The multi-stage gate drive circuit is electrically connected with the corresponding pixel drive circuit respectively. Each stage of the gate drive circuit includes a first type of gate circuit, a second type of gate circuit and a third type of gate circuit. A third signal output end of the third type of gate circuit is electrically connected with the reset transistor. The third type of gate circuit includes a third pull-up control module, a third pull-up module, a third pull-down module, a third pull-down maintenance module, a third inverting module and a third negative bias prevention module. The third pull-up control module and the third pull-up module are electrically connected at a third pull-up node of the third type of gate circuit. The third pull-down module is electrically connected with the third pull-up node and a third signal output end of the third type of gate circuit of the current stage. The third pull-down maintenance module is electrically connected between the third pull-up node and a second low potential signal line of the display panel. The third inverting module is electrically connected with the third pull-up node, a first high potential signal line of the display panel, the second low potential signal line, a first signal output end of a first type of gate circuit of a previous stage, a second signal output end of a second type of gate circuit of the current stage and a second signal output end of a second type of gate circuit of a next stage. The third negative bias prevention module is electrically connected between the first high potential signal line and the third pull-up node.

[0008] The pixel drive circuit and the third type of gate circuit are arranged along a first direction. Part of the third pull-up control module, the third pull-down maintenance module, part of the third inverting module and the third negative bias prevention module are arranged along a second direction. Another part of the third pull-up control module, another part of the third inverting module and part of the third pull-down module are arranged along the second direction. An included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

[0009] According to a second aspect of the present application, a display device is provided, which includes the display panel as described in any of the above embodiments.

[0010] The display panel and the display device provided by the embodiments of the present application arrange the modules in a vertical direction by arranging part of the third pull-up control module, the third pull-down maintenance module, part of the third inverting module and the third negative bias prevention module along a second direction, and arranging another part of the third pull-up control module, another part of the third inverting module and part of the third pull-down module along the second direction. In this way, the horizontal space occupied by each module is reduced, the horizontal space occupied by the third type of gate circuit is reduced, the space occupied by the gate drive circuit is reduced, and the frame of the display panel is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0011] FIG. 1 A schematic diagram of a display device is shown for comparison.

[0012] FIG. 2A plan view of a display panel provided by an embodiment of the present application.

[0013] FIG. 3 A cross-sectional view of a display panel provided by an embodiment of the present application.

[0014] FIG. 4 A circuit diagram of a pixel driving circuit provided by an embodiment of the present application.

[0015] FIG. 5 A circuit diagram of a first type of gate circuit provided by an embodiment of the present application.

[0016] FIG. 6 A circuit diagram of a second type of gate circuit provided by an embodiment of the present application.

[0017] FIG. 7 A circuit diagram of a third type of gate circuit provided by an embodiment of the present application.

[0018] FIG. 8 A stack diagram of a light shielding layer, an active layer, a gate layer and a first source-drain layer of a display panel provided by an embodiment of the present application.

[0019] FIG. 9 A stack diagram of a light shielding layer of a display panel in FIG. 8 .

[0020] FIG. 10 A stack diagram of an active layer of a display panel in FIG. 8 .

[0021] FIG. 11 A stack diagram of a gate layer of a display panel in FIG. 8 .

[0022] FIG. 12 A stack diagram of a first source-drain layer of a display panel in FIG. 8 .

[0023] FIG. 13 A stack diagram of a light shielding layer and an active layer of a display panel in FIG. 8 .

[0024] FIG. 14 A stack diagram of a light shielding layer, an active layer and a gate layer of a display panel in FIG. 8 .

[0025] FIG. 15 A stack diagram of a light shielding layer and a first via of a display panel in FIG. 8 .

[0026] FIG. 16 A stack diagram of a light shielding layer and a first source-drain layer in FIG. 8 .

[0027] FIG. 17 is a cross-sectional view of the display panel in FIG. FIG. 8 is a cross-sectional view of the display panel in FIG.

[0028] FIG. 18 is a cross-sectional view of the display panel in FIG. FIG. 8 is a cross-sectional view of the display panel in FIG.

[0029] FIG. 19 is a cross-sectional view of the display panel in FIG. FIG. 8 is a cross-sectional view of the display panel in FIG.

[0030] FIG. 20 is a cross-sectional view of the display panel in FIG. FIG. 19 is a cross-sectional view of the display panel in FIG.

[0031] FIG. 21 is a cross-sectional view of the display panel in FIG. FIG. 19 is a cross-sectional view of the display panel in FIG.

[0032] FIG. 22 is a cross-sectional view of the display panel in FIG. FIG. 19 is a cross-sectional view of the display panel in FIG.

[0033] FIG. 23 is a cross-sectional view of the display panel in FIG. FIG. 19 is a cross-sectional view of the display panel in FIG.

[0034] FIG. 24 is a cross-sectional view of the display panel in FIG. FIG. 8 is a cross-sectional view of the display panel in FIG.

[0035] FIG. 25 is a cross-sectional view of the display panel in FIG. FIG. 24 is a cross-sectional view of the display panel in FIG.

[0036] FIG. 26 is a cross-sectional view of the display panel in FIG. FIG. 24 is a cross-sectional view of the display panel in FIG.

[0037] FIG. 27 is a cross-sectional view of the display panel in FIG. FIG. 24 is a cross-sectional view of the display panel in FIG.

[0038] FIG. 28 is a cross-sectional view of the display panel in FIG. FIG. 24 is a cross-sectional view of the display panel in FIG.

[0039] FIG. 29 is a cross-sectional view of the display panel in FIG. FIG. 8 is a cross-sectional view of the display panel in FIG.

[0040] FIG. 30 is a cross-sectional view of the display panel in FIG. FIG. 29 is a cross-sectional view of the display panel in FIG.

[0041] FIG. 31FIG. 1 is a schematic diagram of a display device according to an embodiment of the present application. FIG. 29 FIG. 2 is a schematic diagram of a display panel according to an embodiment of the present application.

[0042] FIG. 32 FIG. 3 is a schematic diagram of a display panel according to an embodiment of the present application. FIG. 29 FIG. 4 is a schematic diagram of a display panel according to an embodiment of the present application.

[0043] FIG. 33 FIG. 5 is a schematic diagram of a display panel according to an embodiment of the present application. FIG. 29 FIG. 6 is a schematic diagram of a display panel according to an embodiment of the present application.

[0044] BRIEF DESCRIPTION OF DRAWINGS

[0045] 1. A display device; 11, a pixel circuit; 12, a gate circuit 12; 121, a wiring area; 122, a transistor area; 121a, a signal wiring; 122a, a thin film transistor.

[0046] 2. A display panel; 201, a display area; 202, a non-display area; 21, a pixel driving circuit; 22, a gate driving circuit; 22a, a first type of gate circuit; 22b, a second type of gate circuit; 22c, a third type of gate circuit.

[0047] 211, a substrate; 212, a light shielding layer; 213, a buffer layer; 214, a semiconductor layer; 215, a first gate insulating layer; 216, an active layer; 217, a second gate insulating layer; 218, a gate layer; 219, a first interlayer insulating layer; 221, a first source-drain layer; 222, a second interlayer insulating layer; 223, a second source-drain layer; 224, a passivation layer; 225, a third source-drain layer; 226, a first planarization layer; 227, a second planarization layer; 228, a pixel electrode layer; 229, a first pixel definition layer; 231, a second pixel definition layer; 411, a first via hole; 412, a second via hole; T1, a driving transistor; T2, a switching transistor; T3, a reset transistor; T4, an initialization transistor.

[0048] VST1, first reset control line; VST2, second reset control line; VGH1, first high potential signal line; VGH2, second high potential signal line; VGL1, first low potential signal line; VGL2, second low potential signal line; VGL3, third low potential signal line; LC, low frequency signal line; CKA, first clock signal line; CKA1, first clock first line; CKA2, first clock second line; CKA3, first clock third line; CKA4, first clock fourth line; CKB, second clock signal line; CKBi, first group of sub-lines; CKBj, second group of sub-lines; CKB1, second clock first line; CKB2, second clock second line; CKB3, second clock third line; CKB4, second clock fourth line; CKB5, second clock fifth line; CKB6, second clock sixth line; CKB7, second clock seventh line; CKB8, second clock eighth line; CKC, third clock signal line; CKC1, third clock first line; CKC2, third clock second line; CKC3, third clock third line; CKC4, third clock fourth line.

[0049] VST1a, first part of first reset control line; VST1b, second part of first reset control line; VST1c, third part of first reset control line; VST2a, first part of second reset control line; VST2b, second part of second reset control line; VST2c, third part of second reset control line; VGH1a, first part of first high potential signal line; VGH1b, second part of first high potential signal line; VGH1c, third part of first high potential signal line; VGH2a, first part of second high potential signal line; VGH2b, second part of second high potential signal line; VGH2c, third part of second high potential signal line; VGL1a, first part of first low potential signal line; VGL1b, second part of first low potential signal line; VGL1c, third part of first low potential signal line; VGL2a, first part of second low potential signal line; VGL2b, second part of second low potential signal line; VGL2c, third part of second low potential signal line; VGL3a, first part of third low potential signal line; VGL3b, second part of third low potential signal line; VGL3c, third part of third low potential signal line; LCa, first part of low frequency signal line; LCb, second part of low frequency signal line; LCc, third part of low frequency signal line; CKAa, first part of first clock signal line; CKAb, second part of first clock signal line; CKAc, third part of first clock signal line; CKA1a, first part of first clock first line; CKA1b, second part of first clock first line; CKA1c, third part of first clock first line; CKA2a, first part of first clock second line; CKA2b, second part of first clock second line; CKA2c, third part of first clock second line; CKA3a, first part of first clock third line; CKA3b, second part of first clock third line; CKA3c, third part of first clock third line; CKA4a, first part of first clock fourth line; CKA4b, second part of first clock third line; CKA4c, third part of first clock fourth line; CKBa, first part of second clock signal line; CKBb, second part of second clock signal line; CKBc, third part of second clock signal line; CKBia, first part of first group of sub lines; CKBib, second part of first group of sub lines; CKBic, third part of first group of sub lines; CKBja, first part of second group of sub lines; CKBjb, second part of second group of sub lines; CKBjc, third part of second group of sub lines; CKB1a, first part of second clock first line; CKB1b, second part of second clock first line; CKB1c, third part of second clock first line; CKB2a, first part of second clock second line; CKB2b, second part of second clock second line; CKB2c, third part of second clock second line;CKB2a, first part of second clock second line; CKB2b, second part of second clock second line; CKB2c, third part of second clock second line; CKB3a, first part of second clock third line; CKB3b, second part of second clock third line; CKB3c, third part of second clock third line; CKB4a, first part of second clock fourth line; CKB4b, second part of second clock fourth line; CKB4c, third part of second clock fourth line; CKB5a, first part of second clock fifth line; CKB5b, second part of second clock fifth line; CKB5c, third part of second clock fifth line; CKB6a, first part of second clock sixth line; CKB6b, second part of second clock sixth line; CKB6c, third part of second clock sixth line; CKB7a, first part of second clock seventh line; CKB7b, second part of second clock seventh line; CKB7c, third part of second clock seventh line; CKB8a, first part of second clock eighth line; CKB8b, second part of second clock eighth line; CKB8c, third part of second clock eighth line; CKCa, first part of third clock signal line; CKCb, second part of third clock signal line; CKCc, third part of third clock signal line; CKC1a, first part of third clock first line; CKC1b, second part of third clock first line; CKC1c, third part of third clock first line; CKC2a, first part of third clock second line; CKC2b, second part of third clock second line; CKC2c, third part of third clock second line; CKC3a, first part of third clock third line; CKC3b, second part of third clock third line; CKC3c, third part of third clock third line; CKC4a, first part of third clock fourth line; CKC4b, second part of third clock fourth line; CKC4c, third part of third clock fourth line.

[0050] 311, first pull-up control module; 312, first pull-up module; 313, first pull-down module; 314, first pull-down maintenance module; 315, first inverting module; 316, first negative bias prevention module; 317, first reset module; T11j, first pull-up control transistor; T12j, second pull-up control transistor; T81j, third pull-up control transistor; T81j1, first pull-up control sub-transistor; T81j2, second pull-up control sub-transistor; T21j, first pull-up transistor; T22j, second pull-up transistor; T23j, third pull-up transistor; T31j, first pull-down transistor; T32j, second pull-down transistor; T33j, third pull-down transistor; T41j, fourth pull-down transistor; T41j1, first pull-down sub-transistor; T41j2, second pull-down sub-transistor; T42j, first pull-down maintenance transistor; T42j1, first pull-down maintenance sub-transistor; T42j2, second pull-down maintenance sub-transistor; T51j, first inverting transistor; T51j1, first inverting sub-transistor; T51j2, second inverting sub-transistor; T52j, second inverting transistor; T53j, third inverting transistor; T54j, fourth inverting transistor; T55j, fifth inverting transistor; T71j, first negative bias prevention transistor; T71j1, first negative bias prevention sub-transistor; T71j2, second negative bias prevention sub-transistor; T43j, first reset transistor; T43j1, first reset sub-transistor; T43j2, second reset sub-transistor; C1, first capacitor; C11, first sub-capacitor; C12, second sub-capacitor; C13, third sub-capacitor; C14, fourth sub-capacitor.

[0051] T11jA, active part of the first pull-up control transistor; T12jA, active part of the second pull-up control transistor; T81jA, active part of the third pull-up control transistor; T81j1A, active part of the first pull-up control sub-transistor; T81j2A, active part of the second pull-up control sub-transistor; T21jA, active part of the first pull-up transistor; T22jA, active part of the second pull-up transistor; T23jA, active part of the third pull-up transistor; T31jA, active part of the first pull-down transistor; T32jA, active part of the second pull-down transistor; T33jA, active part of the third pull-down transistor; T41jA, active part of the fourth pull-down transistor; T41j1A, active part of the first pull-down sub-transistor; T41j2A, active part of the second pull-down sub-transistor; T42jA, active part of the first pull-down sustain transistor; T42j1A, active part of the first pull-down sustain sub-transistor; T42j2A, active part of the second pull-down sustain sub-transistor; T51jA, active part of the first inverting transistor; T51j1A, active part of the first inverting sub-transistor; T51j2A, active part of the second inverting sub-transistor; T52jA, active part of the second inverting transistor; T53jA, active part of the third inverting transistor; T54jA, active part of the fourth inverting transistor; T55jA, active part of the fifth inverting transistor; T43jA, active part of the first reset transistor; T43j1A, active part of the first reset sub-transistor; T43j1A, active part of the second reset sub-transistor; T71jA, active part of the first negative bias prevention transistor; T71j1A, active part of the first negative bias prevention sub-transistor; T71j2A, active part of the second negative bias prevention sub-transistor.

[0052] TlljG, gate of first pull-up control transistor; T12jG, gate of second pull-up control transistor; T81jG, gate of third pull-up control transistor; T81j1G, gate of first pull-up control sub-transistor; T81j2G, gate of second pull-up control sub-transistor; T21jG, gate of first pull-up transistor; T22jG, gate of second pull-up transistor; T23jG, gate of third pull-up transistor; T31jG, gate of first pull-down transistor; T32jG, gate of second pull-down transistor; T33jG, gate of third pull-down transistor; T41jG, gate of fourth pull-down transistor; T41j1G, gate of first pull-down sub-transistor; T41j2G, gate of second pull-down sub-transistor; T42jG, gate of first pull-down sustain transistor; T42j1G, gate of first pull-down sustain sub-transistor; T42j2G, gate of second pull-down sustain sub-transistor; T51jG, gate of first inverting transistor; T51j1G, gate of first inverting sub-transistor; T51j2G, gate of second inverting sub-transistor; T52jG, gate of second inverting transistor; T53jG, gate of third inverting transistor; T54jG, gate of fourth inverting transistor; T55jG, gate of fifth inverting transistor; T43jG, gate of first reset transistor; T43j1G, gate of first reset sub-transistor; T43j2G, gate of second reset sub-transistor; T71jG, gate of first negative bias protection transistor; T71j1G, gate of first negative bias protection sub-transistor; T71j2G, gate of second negative bias protection sub-transistor.

[0053] T11jS, first electrode of first pull-up control transistor; T12jS, first electrode of second pull-up control transistor; T81jS, first electrode of third pull-up control transistor; T81j2S, first electrode of second pull-up control sub transistor; T21jS, first electrode of first pull-up transistor; T22jS, first electrode of second pull-up transistor; T23jS, first electrode of third pull-up transistor; T31jS, first electrode of first pull-down transistor; T32jS, first electrode of second pull-down transistor; T33jS, first electrode of third pull-down transistor; T41jS, first electrode of fourth pull-down transistor; T41j1S, first electrode of first pull-down sub transistor; T41j2S, first electrode of second pull-down sub transistor; T42jS, first electrode of first pull-down sustain transistor; T42j1S, first electrode of first pull-down sustain sub transistor; T42j2S, first electrode of second pull-down sustain sub transistor; T51jS, first electrode of first inverter transistor; T51j1S, first electrode of first inverter sub transistor; T52jS, first electrode of second inverter transistor; T53jS, first electrode of third inverter transistor; T54jS, first electrode of fourth inverter transistor; T55jS, first electrode of fifth inverter transistor; T43jS, first electrode of first reset transistor; T43j1S, first electrode of first reset sub transistor; T71jS, first electrode of first negative bias prevention transistor; T71j2S, first electrode of second negative bias prevention sub transistor.

[0054] T11jD, second electrode of the first pull-up control transistor; T12jD, second electrode of the second pull-up control transistor; T81jD, second electrode of the third pull-up control transistor; T81j1D, second electrode of the first pull-up control sub-transistor; T81j2D, second electrode of the second pull-up control sub-transistor; T21jD, second electrode of the first pull-up transistor; T22jD, second electrode of the second pull-up transistor; T23jD, second electrode of the third pull-up transistor; T31jD, second electrode of the first pull-down transistor; T32jD, second electrode of the second pull-down transistor; T33jD, second electrode of the third pull-down transistor; T41jD, second electrode of the fourth pull-down transistor; T41j1D, second electrode of the first pull-down sub-transistor; T41j2D, second electrode of the second pull-down sub-transistor; T42jD, second electrode of the first pull-down sustain transistor; T42j2D, second electrode of the second pull-down sustain sub-transistor; T51jD, second electrode of the first inverter transistor; T51j1D, second electrode of the first inverter sub-transistor; T51j2D, second electrode of the second inverter sub-transistor; T52jD, second electrode of the second inverter transistor; T53jD, second electrode of the third inverter transistor; T54jD, second electrode of the fourth inverter transistor; T55jD, second electrode of the fifth inverter transistor; T43jD, second electrode of the first reset transistor; T43j1D, second electrode of the first reset sub-transistor; T43j2D, second electrode of the second reset sub-transistor; T71jD, second electrode of the first negative bias protection transistor; T71j1D, second electrode of the first negative bias protection sub-transistor; T71j2D, second electrode of the second negative bias protection sub-transistor; C11a, first plate of the first sub-capacitor; C11a1, first portion of the first plate of the first sub-capacitor; C11a2, second portion of the first plate of the first sub-capacitor; C11b, second plate of the first sub-capacitor; C12a, first plate of the second sub-capacitor; C12a1, first portion of the first plate of the second sub-capacitor; C12a2, second portion of the first plate of the second sub-capacitor; C12b, second plate of the second sub-capacitor; C13a, first plate of the third sub-capacitor; C13a1, first portion of the first plate of the third sub-capacitor; C13a2, second portion of the first plate of the third sub-capacitor; C13b, second plate of the fourth sub-capacitor; C14a, first plate of the fourth sub-capacitor; C14a1, first portion of the first plate of the fourth sub-capacitor; C14a2, second portion of the first plate of the fourth sub-capacitor; C14b, second plate of the fourth sub-capacitor.

[0055] Q1[n], first pull-up node; QB1[n], first pull-down node; N1[n], first internal node; Gn[n], first signal output terminal of the first type of gate circuit of the current stage; Gn[n-1], first signal output terminal of the first type of gate circuit of the previous stage; Gn[m], first signal output terminal of the first type of gate circuit of another stage; Cout[n], stage transmission output terminal of the first type of gate circuit of the current stage; Cout[n-2], stage transmission output terminal of the first type of gate circuit of the previous two stages; Cout[n+2], stage transmission output terminal of the first type of gate circuit of the next two stages.

[0056] 321, second pull-up control module; 322, second pull-up module; 323, second pull-down module; 324, second pull-down maintenance module; 325, second inverting module; 326, second negative bias prevention module; 327, second reset module; T11i, fourth pull-up control transistor; T12i, fifth pull-up control transistor; T81i, sixth pull-up control transistor; T81i1, third pull-up control sub-tube; T81i2, fourth pull-up control sub-tube; T21i, fourth pull-up transistor; T31i, fifth pull-down transistor; T41i, sixth pull-down transistor; T41i1, third pull-down sub-tube; T41i2, fourth pull-down sub-tube; T42i, second pull-down maintenance transistor; T42i1, third pull-down maintenance sub-tube; T42i2, fourth pull-down maintenance sub-tube; T51i, sixth inverting transistor; T51i1, third inverting sub-tube; T51i2, fourth inverting sub-tube; T52i, seventh inverting transistor; T53i, eighth inverting transistor; T54i, ninth inverting transistor; T55i, tenth inverting transistor; T61i, second negative bias prevention transistor; T61i1, third negative bias prevention sub-tube; T61i2, fourth negative bias prevention sub-tube; T43i, second reset transistor; T43i1, third reset sub-tube; T43i2, fourth reset sub-tube; C2, second capacitor.

[0057] T11iA, active portion of fourth pull-up control transistor; T12iA, active portion of fifth pull-up control transistor; T81iA, active portion of sixth pull-up control transistor; T81i1A, active portion of third pull-up control sub-transistor; T81i2A, active portion of fourth pull-up control sub-transistor; T21iA, active portion of fourth pull-up transistor; T31iA, active portion of fifth pull-down transistor; T41iA, active portion of sixth pull-down transistor; T41i1A, active portion of third pull-down sub-transistor; T41i2A, active portion of fourth pull-down sub-transistor; T42iA, active portion of second pull-down sustain transistor; T42i1A, active portion of third pull-down sustain sub-transistor; T42i2A, active portion of fourth pull-down sustain sub-transistor; T51iA, active portion of sixth inverter transistor; T51i1A, active portion of third inverter sub-transistor; T51i2A, active portion of fourth inverter sub-transistor; T52iA, active portion of seventh inverter transistor; T53iA, active portion of eighth inverter transistor; T54iA, active portion of ninth inverter transistor; T55iA, active portion of tenth inverter transistor; T43iA, active portion of second reset transistor; T43i1A, active portion of third reset sub-transistor; T43i1A, active portion of fourth reset sub-transistor; T61iA, active portion of second negative bias protection transistor; T61i1A, active portion of third negative bias protection sub-transistor; T61i2A, active portion of fourth negative bias protection sub-transistor.

[0058] T11iG, gate of fourth pull-up control transistor; T12iG, gate of fifth pull-up control transistor; T81iG, gate of sixth pull-up control transistor; T81i1G, gate of third pull-up control sub-transistor; T81i2G, gate of fourth pull-up control sub-transistor; T21iG, gate of fourth pull-up transistor; T31iG, gate of fifth pull-down transistor; T41iG, gate of sixth pull-down transistor; T41i1G, gate of third pull-down sub-transistor; T41i2G, gate of fourth pull-down sub-transistor; T42iG, gate of second pull-down sustain transistor; T42i1G, gate of third pull-down sustain sub-transistor; T42i2G, gate of fourth pull-down sustain sub-transistor; T51iG, gate of sixth inverter transistor; T51i1G, gate of third inverter sub-transistor; T51i2G, gate of fourth inverter sub-transistor; T52iG, gate of seventh inverter transistor; T53iG, gate of eighth inverter transistor; T54iG, gate of ninth inverter transistor; T55iG, gate of tenth inverter transistor; T43iG, gate of second reset transistor; T43i1G, gate of third reset sub-transistor; T43i1G, gate of fourth reset sub-transistor; T61iG, gate of second negative bias protection transistor; T61i1G, gate of third negative bias protection sub-transistor; T61i2G, gate of fourth negative bias protection sub-transistor.

[0059] Tllis, first electrode of a fourth pull-up control transistor; T12is, first electrode of a fifth pull-up control transistor; T81is, first electrode of a sixth pull-up control transistor; T81i2s, first electrode of a fourth pull-up control sub-transistor; T21is, first electrode of a fourth pull-up transistor; T31is, first electrode of a fifth pull-down transistor; T41is, first electrode of a sixth pull-down transistor; T41i1s, first electrode of a third pull-down sub-transistor; T41i2s, first electrode of a fourth pull-down sub-transistor; T42is, first electrode of a second pull-down sustain transistor; T42i1s, first electrode of a third pull-down sustain sub-transistor; T42i2s, first electrode of a fourth pull-down sustain sub-transistor; T51is, first electrode of a sixth inverter transistor; T51i1s, first electrode of a third inverter sub-transistor; T52is, first electrode of a seventh inverter transistor; T53is, first electrode of an eighth inverter transistor; T54is, first electrode of a ninth inverter transistor; T55is, first electrode of a tenth inverter transistor; T43is, first electrode of a second reset transistor; T43i1s, first electrode of a third reset sub-transistor; T61is, first electrode of a second negative bias prevention transistor; T61i2s, first electrode of a fourth negative bias prevention sub-transistor.

[0060] T11iD, second electrode of the fourth pull-up control transistor; T12iD, second electrode of the fifth pull-up control transistor; T81iD, second electrode of the sixth pull-up control transistor; T81i1D, second electrode of the third pull-up control sub-transistor; T81i2D, second electrode of the fourth pull-up control sub-transistor; T21iD, second electrode of the fourth pull-up transistor; T31iD, second electrode of the fifth pull-down transistor; T41iD, second electrode of the sixth pull-down transistor; T41i1D, second electrode of the third pull-down sub-transistor; T41i2D, second electrode of the fourth pull-down sub-transistor; T42iD, second electrode of the second pull-down sustain transistor; T42i2D, second electrode of the fourth pull-down sustain sub-transistor; T51iD, second electrode of the sixth inverter transistor; T51i1D, second electrode of the third inverter sub-transistor; T51i2D, second electrode of the fourth inverter sub-transistor; T52iD, second electrode of the seventh inverter transistor; T53iD, second electrode of the eighth inverter transistor; T54iD, second electrode of the ninth inverter transistor; T55iD, second electrode of the tenth inverter transistor; T43iD, second electrode of the second reset transistor; T43i1D, second electrode of the third reset sub-transistor; T43i1D, second electrode of the fourth reset sub-transistor; T61iD, second electrode of the second negative bias prevention transistor; T61i1D, second electrode of the third negative bias prevention sub-transistor; T61i2D, second electrode of the fourth negative bias prevention sub-transistor; C2a, first plate of the second capacitor; C2a1, first part of the first plate of the second capacitor; C2a2, second part of the first plate of the second capacitor; C2b, second plate of the second capacitor.

[0061] Q2[n], second pull-up node; QB2[n], second pull-down node; N2[n], second internal node; INI[n], second signal output terminal of the second type of gate circuit of the current stage; INI[n-2], second signal output terminal of the second type of gate circuit of the stage above two stages; INI[n+1], second signal output terminal of the second type of gate circuit of the stage below one stage; INI[n+2], second signal output terminal of the second type of gate circuit of the stage below two stages.

[0062] 331, third pull-up control module; 332, third pull-up module; 333, third pull-down module; 334, third pull-down maintaining module; 335, third inverting module; 336, third negative bias prevention module; T11r, seventh pull-up control transistor; T21r, fifth pull-up transistor; T31r, seventh pull-down transistor; T41r, eighth pull-down transistor; T41r1, fifth pull-down sub-transistor; T41r2, sixth pull-down sub-transistor; T42r, third pull-down maintaining transistor; T42r1, fifth pull-down maintaining sub-transistor; T42r2, sixth pull-down maintaining sub-transistor; T51r, eleventh inverting transistor; T51r1, fifth inverting sub-transistor; T51r2, sixth inverting sub-transistor; T52r, twelfth inverting transistor; T52r1, seventh inverting sub-transistor; T52r2, eighth inverting sub-transistor; T53r, thirteenth inverting transistor; T54r, fourteenth inverting transistor; T55r, fifteenth inverting transistor; T56r, sixteenth inverting transistor; T61r, third negative bias prevention transistor; T61r1, fifth negative bias prevention sub-transistor; T61r2, sixth negative bias prevention sub-transistor; C3, third capacitor; C4, fourth capacitor.

[0063] T11rA, active part of seventh pull-up control transistor; T21rA, active part of fifth pull-up transistor; T31rA, active part of seventh pull-down transistor; T41rA, active part of eighth pull-down transistor; T41r1A, active part of fifth pull-down sub-transistor; T41r2A, active part of sixth pull-down sub-transistor; T42rA, active part of third pull-down maintaining transistor; T42r1A, active part of fifth pull-down maintaining sub-transistor; T42r2A, active part of sixth pull-down maintaining sub-transistor; T51rA, active part of eleventh inverting transistor; T51r1A, active part of fifth inverting sub-transistor; T51r2A, active part of sixth inverting sub-transistor; T52rA, active part of twelfth inverting transistor; T52r1A, active part of seventh inverting sub-transistor; T52r2A, active part of eighth inverting sub-transistor; T53rA, active part of thirteenth inverting transistor; T54rA, active part of fourteenth inverting transistor; T55rA, active part of fifteenth inverting transistor; T56rA, active part of sixteenth inverting transistor; T61rA, active part of third negative bias prevention transistor; T61r1A, active part of fifth negative bias prevention sub-transistor; T61r2A, active part of sixth negative bias prevention sub-transistor.

[0064] T11rG, gate of seventh pull-up control transistor; T21rG, gate of fifth pull-up transistor; T31rG, gate of seventh pull-down transistor; T41rG, gate of eighth pull-down transistor; T41r1G, gate of fifth pull-down sub-transistor; T41r2G, gate of sixth pull-down sub-transistor; T42rG, gate of third pull-down sustain transistor; T42r1G, gate of fifth pull-down sustain sub-transistor; T42r2G, gate of sixth pull-down sustain sub-transistor; T51rG, gate of eleventh inverting transistor; T51r1G, gate of fifth inverting sub-transistor; T51r2G, gate of sixth inverting sub-transistor; T52rG, gate of twelfth inverting transistor; T52r1G, gate of seventh inverting sub-transistor; T52r2G, gate of eighth inverting sub-transistor; T53rG, gate of thirteenth inverting transistor; T54rG, gate of fourteenth inverting transistor; T55rG, gate of fifteenth inverting transistor; T56rG, gate of sixteenth inverting transistor; T61rG, gate of third negative bias prevention transistor; T61r1G, gate of fifth negative bias prevention sub-transistor; T61r2G, gate of sixth negative bias prevention sub-transistor.

[0065] T11rS, first electrode of seventh pull-up control transistor; T21rS, first electrode of fifth pull-up transistor; T31rS, first electrode of seventh pull-down transistor; T41rS, first electrode of eighth pull-down transistor; T41r1S, first electrode of fifth pull-down sub-transistor; T42rS, first electrode of third pull-down sustain transistor; T42r1S, first electrode of fifth pull-down sustain sub-transistor; T42r2S, first electrode of sixth pull-down sustain sub-transistor; T51rS, first electrode of eleventh inverting transistor; T51r1S, first electrode of fifth inverting sub-transistor; T52rS, first electrode of twelfth inverting transistor; T52r1S, first electrode of seventh inverting sub-transistor; T52r2S, first electrode of eighth inverting sub-transistor; T53rS, first electrode of thirteenth inverting transistor; T54rS, first electrode of fourteenth inverting transistor; T55rS, first electrode of fifteenth inverting transistor; T56rS, first electrode of sixteenth inverting transistor; T61rS, first electrode of third negative bias prevention transistor; T61r2S, first electrode of sixth negative bias prevention sub-transistor.

[0066] T11rD, second electrode of seventh pull-up control transistor; T21rD, second electrode of fifth pull-up transistor; T31rD, second electrode of seventh pull-down transistor; T41rD, second electrode of eighth pull-down transistor; T41r1D, second electrode of fifth pull-down sub-transistor; T41r2D, second electrode of sixth pull-down sub-transistor; T42rD, second electrode of third pull-down sustain transistor; T42r1D, second electrode of fifth pull-down sustain sub-transistor; T42r2D, second electrode of sixth pull-down sustain sub-transistor; T51rD, second electrode of eleventh inverting transistor; T51r1D, second electrode of fifth inverting sub-transistor; T51r2D, second electrode of sixth inverting sub-transistor; T52rD, second electrode of twelfth inverting transistor; T52r1D, second electrode of seventh inverting sub-transistor; T52r2D, second electrode of eighth inverting sub-transistor; T53rD, second electrode of thirteenth inverting transistor; T54rD, second electrode of fourteenth inverting transistor; T56rD, second electrode of sixteenth inverting transistor; T61rD, second electrode of third negative bias prevention transistor; T61r1D, second electrode of fifth negative bias prevention sub-transistor; T61r2D, second electrode of sixth negative bias prevention sub-transistor; C3a, first plate of third capacitor; C3a1, first part of first plate of third capacitor; C3a2, second part of first plate of third capacitor; C3b, second plate of third capacitor; C4a, first plate of fourth capacitor; C4b, second plate of fourth capacitor.

[0067] Q3[n], third pull-up node; QB3[n], third pull-down node; N3[n], third internal node; REF[n], third signal output terminal of third type of gate circuit of this stage.

[0068] X, first direction; Y, second direction. DETAILED DESCRIPTION

[0069] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative effort fall within the protection scope of the present application.

[0070] In the description of the present application, it should be noted that unless specifically defined and limited, the terms "mounting", "connection", "connecting", "electrically connecting" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electric connection or can communicate with each other; it can be directly connected, or indirectly connected through intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0071] In order to illustrate the principle of the technical problem of the embodiments of the present application, some comparative display devices are provided, and it can be understood that these comparative display devices cannot be used as prior art in the embodiments of the present application. As shown in FIG. 2 The comparative display device 1 includes a pixel circuit 11 and a gate circuit 12. The gate circuit 12 is provided with a wiring area 121 and a transistor area 122. The signal wiring 121a is arranged in the wiring area 121, and the thin film transistor 122a is arranged in the transistor area 122. The signal wiring 121a is connected to the corresponding transistor 122a by extending from the wiring area 121 to the transistor area 122, so as to realize the normal work of the gate circuit 12. However, from FIG. 1 It can be seen from the comparative display device 1 that because the wiring area 121 and the transistor area 122 are separately arranged, the wiring area 121 needs to occupy a large space. When the signal wiring 121a extends into the transistor area 122, in order to avoid the unconnected signal wiring 121a, each transistor needs to occupy more space, resulting in that the gate circuit 12 occupies a large space. Therefore, the current display device has the technical problem that the horizontal space occupied by the gate driving circuit is large, resulting in that the frame of the display device is large.

[0072] The embodiments of the present application provide a display panel 2 and a display device, which are used to solve the above technical problem.

[0073] The embodiments of the present application are based on the problem that the wiring area and the transistor area need to be separately arranged in the comparative display device, which results in that the wiring area and the transistor area occupy a large space. By adjusting the arrangement position of the signal line, the arrangement layer of the signal line, the arrangement mode of the signal line, and / or adjusting the arrangement position of the transistor, the arrangement mode of the transistor, and the structure design of the transistor, the occupied space of the gate driving circuit 22 is reduced, and the frame of the display panel 2 is reduced.

[0074] FIG. 1 The comparative display device is a schematic diagram. FIG. 2 The comparative display device is a schematic diagram. FIG. 3 The comparative display device is a schematic diagram. FIG. 4A circuit diagram of the pixel driving circuit provided for the embodiment of the present application. FIG. 5 A circuit diagram of the first type of gate circuit provided for the embodiment of the present application. FIG. 6 A circuit diagram of the second type of gate circuit provided for the embodiment of the present application. FIG. 7 A circuit diagram of the third type of gate circuit provided for the embodiment of the present application. FIG. 8 A laminated diagram of the light shielding layer, the active layer, the gate layer and the first source-drain layer of the display panel provided for the embodiment of the present application. FIG. 9 A laminated diagram of the light shielding layer and the active layer of the display panel in FIG. 8 A laminated diagram of the light shielding layer of the display panel in FIG. 10 A laminated diagram of the active layer of the display panel in FIG. 8 A laminated diagram of the active layer of the display panel in FIG. 11 A laminated diagram of the gate layer of the display panel in FIG. 8 A laminated diagram of the gate layer of the display panel in FIG. 12 A laminated diagram of the first source-drain layer of the display panel in FIG. 8 A laminated diagram of the first source-drain layer of the display panel in FIG. 13 A laminated diagram of the light shielding layer and the active layer of the display panel in FIG. 8 A laminated diagram of the light shielding layer and the active layer of the display panel in FIG. 14 A laminated diagram of the light shielding layer, the active layer and the gate layer of the display panel in FIG. 8 A laminated diagram of the light shielding layer, the active layer and the gate layer of the display panel in FIG. 15 A laminated diagram of the light shielding layer and the first via of the display panel in FIG. 8 A laminated diagram of the light shielding layer and the first source-drain layer of the display panel in FIG. 16 A laminated diagram of the light shielding layer and the first source-drain layer of the display panel in FIG. 8 A laminated diagram of the gate layer and the second via of the display panel in FIG. 17 A laminated diagram of the gate layer and the second via of the display panel in FIG. 8 A laminated diagram of the gate layer and the first source-drain layer of the display panel in FIG. 18 A laminated diagram of the gate layer and the first source-drain layer of the display panel in FIG. 8 A laminated diagram of the gate layer and the first source-drain layer of the display panel in FIG. 19 A local enlarged view of the corresponding area of the first type of gate circuit of the display panel in FIG. 8 A laminated diagram of the light shielding layer of the display panel in FIG. 20 A laminated diagram of the light shielding layer of the display panel in FIG. 19 A laminated diagram of the active layer of the display panel in FIG. 21 A laminated diagram of the active layer of the display panel in FIG. 19 A laminated diagram of the gate layer of the display panel in FIG. 22 A laminated diagram of the gate layer of the display panel in FIG. 19 A laminated diagram of the first source-drain layer of the display panel in FIG. 23 A laminated diagram of the first source-drain layer of the display panel in FIG. 19 A laminated diagram of the first source-drain layer of the display panel in FIG. 24 A local enlarged view of the corresponding area of the second type of gate circuit of the display panel in FIG. 8 A local enlarged view of the corresponding area of the second type of gate circuit of the display panel in A local enlarged view of the corresponding area of the second type of gate circuit of the display panel in

[0075] A local enlarged view of the corresponding area of the second type of gate circuit of the display panel in FIG. 25 A laminated diagram of the light shielding layer of the display panel in FIG. 24 A laminated diagram of the light shielding layer of the display panel in FIG. 26 A laminated diagram of the light shielding layer of the display panel in FIG. 24An exploded view of the active layer of the display panel. FIG. 27 for FIG. 24 An exploded view of the gate layer of the display panel. FIG. 28 for FIG. 24 An exploded view of the first source-drain layer of the display panel. FIG. 29 for FIG. 8 A magnified view of a portion of the area corresponding to the third type of gate circuit in the display panel. FIG. 30 for FIG. 29 An exploded view of the light-shielding layer of the display panel. FIG. 31 for FIG. 29 An exploded view of the active layer of the display panel. FIG. 32 for FIG. 29 An exploded view of the gate layer of the display panel. FIG. 33 for FIG. 29 An exploded view of the first source-drain layer of the display panel.

[0076] like FIG. 2 As shown, this application embodiment provides a display panel 2, which includes a display area 201 and a non-display area 202. The display area 201 is provided with a plurality of pixels 23. Each pixel 23 includes a light-emitting device (LED) and a pixel driving circuit 21 for driving the LED. The non-display area 202 is provided with a multi-level gate driving circuit 22. The multi-level gate driving circuit 22 can be arranged along the second direction Y. The gate driving circuit 22 outputs a scanning signal to the pixel driving circuit 21.

[0077] Specifically, such as FIG. 2 As shown, the non-display area 202 can be arranged around the display area 201, but this embodiment is not limited to this. The non-display area 202 can be arranged on one side, two sides, or three sides of the display area 201, and the non-display area 202 can be bent to the back of the display area 201. The non-display area 202 may include an upper border area, a lower border area, a left border area, and a right border area. The gate driving circuit 22 can be arranged in the left border area and / or the right border area. The gate driving circuit 22 can be arranged along the first direction X on one side or both sides of the display area 201.

[0078] like FIG. 3 As shown, as a specific structure of a display panel 2 in an embodiment of this application, the display panel 2 includes a substrate 211, a light-shielding layer 212, a buffer layer 213, a semiconductor layer 214, a first gate insulating layer 215, an active layer 216, a second gate insulating layer 217, a gate layer 218, a first interlayer insulating layer 219, a first source-drain layer 221, a second interlayer insulating layer 222, a second source-drain layer 223, a passivation layer 224, a third source-drain layer 225, a first planarization layer 226, a second planarization layer 227, a pixel electrode layer 228, a first pixel definition layer 229, and a second pixel definition layer 231, which are arranged sequentially.

[0079] Specifically, the material of the semiconductor layer 214 includes an oxide semiconductor, specifically can be a metal oxide, and more specifically can be indium gallium zinc oxide.

[0080] Specifically, the material of the active layer 216 includes a silicon semiconductor material, specifically can be low-temperature polysilicon.

[0081] Specifically, as shown in FIG. 2B, the display panel 2 includes the semiconductor layer 214 and the active layer 216, but the embodiments of the present application are not limited thereto, and the display panel 2 can include only one of the semiconductor layer 214 and the active layer 216. FIG. 3 FIG. 3 Specifically, as shown in FIG. 2B, the display panel 2 includes the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225, but the embodiments of the present application are not limited thereto, and the display panel 2 can include only one or two of the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225.

[0082] Specifically, as shown in FIG. 2B, the display panel 2 includes the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225, but the embodiments of the present application are not limited thereto, and the display panel 2 can include only one or two of the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225. FIG. 3 FIG. 3 Specifically, as shown in FIG. 2B, the display panel 2 includes the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225, but the embodiments of the present application are not limited thereto, and the display panel 2 can include only one or two of the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225.

[0083] Specifically, as shown in FIG. 2B, the display panel 2 includes the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225, but the embodiments of the present application are not limited thereto, and the display panel 2 can include only one or two of the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225. FIG. 3 FIG. 3 Specifically, as shown in FIG. 2B, the display panel 2 includes the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225, but the embodiments of the present application are not limited thereto, and the display panel 2 can include only one or two of the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225.

[0084] Specifically, as shown in FIG. 2B, the display panel 2 includes the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225, but the embodiments of the present application are not limited thereto, and the display panel 2 can include only one or two of the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225. FIG. 3 FIG. 3 Specifically, as shown in FIG. 2B, the display panel 2 includes the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225, but the embodiments of the present application are not limited thereto, and the display panel 2 can include only one or two of the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225.

[0085] Specifically, as shown in FIG. 2B, the display panel 2 includes the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225, but the embodiments of the present application are not limited thereto, and the display panel 2 can include only one or two of the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225. FIG. 3 FIG. 3 Specifically, as shown in FIG. 2B, the display panel 2 includes the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225, but the embodiments of the present application are not limited thereto, and the display panel 2 can include only one or two of the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225.

[0086] Specifically, as shown in FIG. 2B, the display panel 2 includes the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225, but the embodiments of the present application are not limited thereto, and the display panel 2 can include only one or two of the first source-drain layer 221, the second source-drain layer 223, and the third source-drain layer 225. FIG. 5 to FIG. 7 ​​​​​As shown, each stage of the gate drive circuit 22 includes a first type of gate circuit 22a, a second type of gate circuit 22b, and a third type of gate circuit 22c arranged along a first direction.

[0087] As shown, the display panel 2 provided by the embodiment of the present application includes a plurality of rows of pixels 23 and a plurality of stages of gate drive circuits 22, the pixels 23 include light emitting devices LED and pixel drive circuits 21, the gate drive circuits 22 are electrically connected to the corresponding pixel drive circuits 21 respectively, each stage of the gate drive circuits 22 includes a first type of gate circuit 22a, a second type of gate circuit 22b, and a third type of gate circuit 22c, the first type of gate circuit 22a is electrically connected to at least a first clock signal line CKA, a second clock signal line CKB, a first high potential signal line VGH1, a first low potential signal line VGL1, a second low potential signal line VGL2, a first reset control line VST1, and a low frequency signal line LC, the second type of gate circuit 22b is electrically connected to at least the first high potential signal line VGH1, the second low potential signal line VGL2, a third clock signal line CKC of the display panel, and a second reset control line VST2 of the display panel, and the third type of gate circuit 22c is electrically connected to at least the first high potential signal line VGH1, a second high potential signal line VGH2, the second low potential signal line VGL2, and a third low potential signal line VGL3. FIG. 2 to FIG. 33

[0088] Among them, the first reset control line VST1, the first type of gate circuit 22a, the second type of gate circuit 22b, the third type of gate circuit 22c, and the third low potential signal line VGL3 are arranged along a first direction, and at least one of the first clock signal line CKA, the second clock signal line CKB, the third clock signal line CKC, the first high potential signal line VGH1, the second high potential signal line VGH2, the first low potential signal line VGL1, the second low potential signal line VGL2, the second reset control line VST2, and the low frequency signal line LC is arranged between the first reset control line VST1 and the third low potential signal line VGL3 in the first direction.

[0089] ​The display panel 2 provided by the embodiment of the present application can shorten the connection line between at least one of the first clock signal line CKA, the second clock signal line CKB and the third clock signal line CKC and the corresponding transistor, and does not need to occupy the space outside the transistor area of the gate driving circuit 22, reduces the horizontal space occupied by the at least one clock signal line, reduces the horizontal space occupied by the gate driving circuit 22, and reduces the frame of the display panel 2.

[0090] In some embodiments, as shown in FIG. 1, in the first direction, at least one of the first clock signal line CKA, the second clock signal line CKB and the third clock signal line CKC is arranged between the first reset control line VST1 and the third low potential signal line VGL3. By arranging at least one of the first clock signal line CKA, the second clock signal line CKB and the third clock signal line CKC between the first reset control line VST1 and the third low potential signal line VGL3, the connection line between at least one of the first clock signal line CKA, the second clock signal line CKB and the third clock signal line CKC and the corresponding transistor can be shortened, and the horizontal space occupied by the at least one clock signal line can be reduced, the horizontal space occupied by the gate driving circuit 22 can be reduced, and the frame of the display panel 2 can be reduced. FIG. 8 to FIG. 18

[0091] Specifically, it can be understood that each clock signal line in the display panel 2 will include a plurality of clock lines, and arranging the plurality of clock lines outside the transistor area and connecting the clock lines to the transistors in the transistor area will occupy a large space, resulting in a large horizontal space occupied by the gate driving circuit 22 and a large frame of the display panel 2. By arranging at least one of the first clock signal line CKA, the second clock signal line CKB and the third clock signal line CKC between the first reset control line VST1 and the third low potential signal line VGL3, the space occupied by the clock signal line can be reduced, and the frame of the display panel 2 can be reduced.

[0092] Specifically, the first clock signal line CKA can be arranged between the first reset control line VST1 and the third low potential signal line VGL3.

[0093] ​Specifically, the second clock signal line CKB can be arranged between the first reset control line VST1 and the third low potential signal line VGL3.

[0094] Specifically, the third clock signal line CKC can be arranged between the first reset control line VST1 and the third low potential signal line VGL3.

[0095] In some embodiments, as shown in FIG. 2, in the first direction, the first clock signal line CKA and the second clock signal line CKB are arranged between the first reset control line VST1 and the third low potential signal line VGL3. FIG. 8 to FIG. 18 By arranging the first clock signal line CKA and the second clock signal line CKB between the first reset control line VST1 and the third low potential signal line VGL3, the horizontal space occupied by the first clock signal line CKA and the second clock signal line CKB can be reduced, thereby reducing the frame of the display panel 2.

[0096] Specifically, the first clock signal line CKA and the second clock signal line CKB each include a plurality of clock lines. By arranging the first clock signal line CKA and the second clock signal line CKB between the first reset control line VST1 and the third low potential signal line VGL3, the horizontal space occupied by the gate drive circuit 22 can be reduced, thereby reducing the frame of the display panel 2.

[0097] In some embodiments, as shown in FIG. 2, in the first direction, the first clock signal line CKA and the second clock signal line CKB are arranged between the first reset control line VST1 and the second type of gate circuit 22b. FIG. 8 to FIG. 18 By arranging the first clock signal line CKA and the second clock signal line CKB between the first reset control line VST1 and the second type of gate circuit 22b, the first clock signal line CKA and the second clock signal line CKB are closer to the transistors connected thereto, and the connection lines of each clock line are relatively short or even unnecessary, thereby further reducing the space occupied by the first clock signal line CKA and the second clock signal line CKB, and reducing the frame of the display panel 2.

[0098] Specifically, the first clock signal line CKA is connected with the transistor in the first type of gate circuit 22a, and the second clock signal line CKB is connected with the transistor in the second type of gate circuit 22b. The first clock signal line CKA and the second clock signal line CKB can be arranged between the first reset control line VST1 and the second type of gate circuit 22b, so that the first clock signal line CKA and the second clock signal line CKB are close to the transistors connected therewith, and the connection lines of each clock line are relatively short. Thus, the space occupied by the first clock signal line CKA and the second clock signal line CKB can be further reduced, and the frame of the display panel 2 can be reduced.

[0099] In some embodiments, as shown in FIG. 5 、 FIG. 8 to FIG. 18 、 FIG. 19 to FIG. 23 The first type of gate circuit 22a includes a first pull-up control module 311 and a first pull-up module 312. The first pull-up control module 311 is electrically connected to the first pull-up node Q1[n] with the first pull-up module 312. The second clock signal line CKB includes a first group of sub-lines CKBi and a second group of sub-lines CKBj. The first pull-up module 312 includes a first pull-up transistor T21j, a second pull-up transistor T22j, and a third pull-up transistor T23j. One electrode of the first pull-up transistor T21j is electrically connected to the first clock signal line CKA. One electrode of the second pull-up transistor T22j is electrically connected to the first group of sub-lines CKBi. One electrode of the third pull-up transistor T23j is electrically connected to the second group of sub-lines CKBj.

[0100] The first pull-up transistor T21j, the second pull-up transistor T22j, and the third pull-up transistor T23j are arranged in a first direction. In the first direction, the first clock signal line CKA is arranged between the first pull-up control module 311 and the first pull-up transistor T21j. The first group of sub-lines CKBi is arranged between the first pull-up transistor T21j and the second pull-up transistor T22j. The second group of sub-lines CKBj is arranged between the second pull-up transistor T22j and the third pull-up transistor T23j. By arranging the first clock signal line CKA between the first pull-up control module 311 and the first pull-up transistor T21j, the first group of sub-lines CKBi between the first pull-up transistor T21j and the second pull-up transistor T22j, and the second group of sub-lines CKBj between the second pull-up transistor T22j and the third pull-up transistor T23j, the transistors connected with each clock signal line are arranged adjacently. Thus, the length of the connection line of the transistor connected with each clock signal line can be shortened or even eliminated, the space occupied by each clock signal line can be reduced, and the frame of the display panel 2 can be reduced.

[0101] In some embodiments, as shown in FIG. 6, in the first direction, the third clock signal line CKC is arranged between the first reset control line VST1 and the third low potential signal line VGL3. By arranging the third clock signal line CKC between the first reset control line VST1 and the third low potential signal line VGL3, the third clock signal line CKC is closer to the transistor connected thereto, and the connection line of the third clock signal line CKC is relatively short or even unnecessary, thereby further reducing the space occupied by the third clock signal line CKC and reducing the frame of the display panel 2. FIG. 8 to FIG. 18 In some embodiments, as shown in FIG. 6, in the first direction, the third clock signal line CKC is arranged between the first type of gate circuit 22a and the third type of gate circuit 22c. By arranging the third clock signal line CKC between the first type of gate circuit 22a and the third type of gate circuit 22c, the third clock signal line CKC is closer to the transistor connected thereto, and the connection line of each clock line is relatively short or even unnecessary, thereby further reducing the space occupied by the third clock signal line CKC and reducing the frame of the display panel 2.

[0102] FIG. 8 to FIG. 18 In some embodiments, as shown in FIG. 6, in the first direction, the third clock signal line CKC is arranged between the first type of gate circuit 22a and the third type of gate circuit 22c. By arranging the third clock signal line CKC between the first type of gate circuit 22a and the third type of gate circuit 22c, the third clock signal line CKC is closer to the transistor connected thereto, and the connection line of each clock line is relatively short or even unnecessary, thereby further reducing the space occupied by the third clock signal line CKC and reducing the frame of the display panel 2.

[0103] Specifically, the third clock signal line CKC is connected to the transistor in the second type of gate circuit 22b, and the third clock signal line CKC can be arranged between the first type of gate circuit 22a and the third type of gate circuit 22c, so that the third clock signal line CKC is closer to the transistor connected thereto, and the connection line of each clock line is relatively short, thereby further reducing the space occupied by the third clock signal line CKC and reducing the frame of the display panel 2.

[0104] In some embodiments, as shown in FIG. 6, in the first direction, the third clock signal line CKC is arranged between the first type of gate circuit 22a and the third type of gate circuit 22c. By arranging the third clock signal line CKC between the first type of gate circuit 22a and the third type of gate circuit 22c, the third clock signal line CKC is closer to the transistor connected thereto, and the connection line of each clock line is relatively short or even unnecessary, thereby further reducing the space occupied by the third clock signal line CKC and reducing the frame of the display panel 2. FIG. 6 FIG. 8 to FIG. 18 FIG. 24 to FIG. 28 As shown in FIG. 6, the second type of gate circuit 22b includes a second pull-up control module 321 and a second pull-up module 322, the second pull-up control module 321 and the second pull-up module 322 are electrically connected to a second pull-up node Q2[n], and the second pull-up module 322 is electrically connected to the third clock signal line CKC.

[0105] ​​​In the first direction, the third clock signal line CKC is disposed between the second pull-up control module 321 and the second pull-up module 322. By disposing the third clock signal line CKC between the second pull-up control module 321 and the second pull-up module 322, the third clock signal line CKC is positioned adjacent to the transistor it is connected to, thereby shortening or even eliminating the connection line between the third clock signal line CKC and the transistor, reducing the space occupied by the third clock signal line CKC, and reducing the bezel of the display panel 2.

[0106] In some embodiments, in the first direction, the first high-potential signal line VGH1 is disposed between the first reset control line VST1 and the third low-potential signal line VGL3. By disposing the first high-potential signal line VGH1 between the first reset control line VST1 and the third low-potential signal line VGL3, the first high-potential signal line VGH1 is closer to the transistor it is connected to, and the connection line of the first high-potential signal line VGH1 is relatively short or even unnecessary, thereby further reducing the space occupied by the first high-potential signal line VGH1 and reducing the bezel of the display panel 2.

[0107] In some embodiments, such as FIG. 5 , FIG. 8 to FIG. 18 , FIG. 19 to FIG. 23 As shown, the first type of gate circuit 22a includes a first pull-up control module 311, which is electrically connected to the first high-potential signal line VGH1.

[0108] In the first direction, the first high-potential signal line VGH1 is disposed between the first reset control line VST1 and the first pull-up control module 311. By placing the first high-potential signal line VGH1 between the first reset control line VST1 and the first pull-up control module 311, the first high-potential signal line VGH1 is arranged adjacent to the transistor it is connected to, thereby shortening the length of the connection line between the first high-potential signal line VGH1 and the transistor it is connected to, or even eliminating the connection line, reducing the space occupied by the first high-potential signal line VGH1, and reducing the bezel of the display panel 2.

[0109] Specifically, in the case where the first high-potential signal line VGH1 is connected to the second type of gate circuit 22b and the third type of gate circuit 22c, the connection between each transistor and the first high-potential signal line VGH1 can be achieved by setting connection lines on the upper side of each level of gate driving circuit 22 or within each level of gate driving circuit 22.

[0110] In some embodiments, such as FIG. 8 to FIG. 18As shown in the first direction, the second high potential signal line VGH2 is disposed between the first reset control line VST1 and the third low potential signal line VGL3. By disposing the second high potential signal line VGH2 between the first reset control line VST1 and the third low potential signal line VGL3, the transistor connected to the second high potential signal line VGH2 is disposed adjacent to the second high potential signal line VGH2, and the connection line of the second high potential signal line VGH2 is relatively short or even unnecessary, so that the space occupied by the second high potential signal line VGH2 can be further reduced, and the frame of the display panel 2 can be reduced.

[0111] In some embodiments, as shown in the first direction, FIG. 7 , FIG. 8 to FIG. 18 , FIG. 29 to FIG. 33 As shown in the first direction, the third gate circuit 22c includes a third pull-up control module 331 and a third pull-up module 332, the third pull-up control module 331 and the third pull-up module 332 are electrically connected to the third pull-up node Q3[n], and the third pull-up module 332 is electrically connected to the second high potential signal line VGH2.

[0112] In the first direction, the second high potential signal line VGH2 is disposed between the third pull-up control module 331 and the third pull-up module 332. By disposing the second high potential signal line VGH2 between the third pull-up control module 331 and the third pull-up module 332, the transistor connected to the second high potential signal line VGH2 is disposed adjacent to the second high potential signal line VGH2, so that the length of the connection line of the transistor connected to the second high potential signal line VGH2 can be shortened or even eliminated, the space occupied by the second high potential signal line VGH2 can be reduced, and the frame of the display panel 2 can be reduced.

[0113] In some embodiments, as shown in the first direction, FIG. 8 to FIG. 18 In the first direction, the first low potential signal line VGL1 is disposed between the first reset control line VST1 and the third low potential signal line VGL3. By disposing the first low potential signal line VGL1 between the first reset control line VST1 and the third low potential signal line VGL3, the transistor connected to the first low potential signal line VGL1 is disposed adjacent to the first low potential signal line VGL1, and the connection line of the first low potential signal line VGL1 is relatively short or even unnecessary, so that the space occupied by the first low potential signal line VGL1 can be further reduced, and the frame of the display panel 2 can be reduced.

[0114] In some embodiments, as shown in the first direction, FIG. 5 , FIG. 8 to FIG. 18 , FIG. 19 to FIG. 23 As shown in the first direction, the first gate circuit 22a includes a first pull-down maintenance module 314, and the first pull-down maintenance module 314 is electrically connected to the first low potential signal line VGL1.

[0115] In the first direction, the first low potential signal line VGL1 is disposed between the first pull-down maintaining module 314 and the second type of gate circuit 22b. By disposing the first low potential signal line VGL1 between the first pull-down maintaining module 314 and the second type of gate circuit 22b, the first low potential signal line VGL1 is disposed adjacent to the transistor connected thereto, so that the length of the connection line of the transistor connected to the first low potential signal line VGL1 can be shortened or even eliminated, the space occupied by the first low potential signal line VGL1 is reduced, and the frame of the display panel 2 is reduced.

[0116] Specifically, for the case that the first low potential signal line VGL1 is connected with other modules, the connection of each transistor with the first low potential signal line VGL1 can be achieved by disposing a connection line on the upper side of each stage of gate driving circuit 22 or in each stage of gate driving circuit 22.

[0117] In some embodiments, as shown in FIG. 1, FIG. 2 to FIG. 33 In the first direction X, the second low potential signal line VGL2 is disposed between the first reset control line VST1 and the third low potential signal line VGL3. By disposing the second low potential signal line VGL2 between the first reset control line VST1 and the third low potential signal line VGL3, the transistor connected to the second low potential signal line VGL2 is closer, and the connection line of the second low potential signal line VGL2 is relatively short or even unnecessary, so that the space occupied by the second low potential signal line VGL2 can be further reduced, and the frame of the display panel 2 is reduced.

[0118] In some embodiments, as shown in FIG. 1, FIG. 2 to FIG. 33 In the first direction X, the second low potential signal line VGL2 is disposed between the second type of gate circuit 22b and the third low potential signal line VGL3. By disposing the second low potential signal line VGL2 between the second type of gate circuit 22b and the third low potential signal line VGL3, the distance between the transistor connected to the second low potential signal line VGL2 can be further shortened, and the connection line of the second low potential signal line VGL2 is relatively short or even unnecessary, so that the space occupied by the second low potential signal line VGL2 can be further reduced, and the frame of the display panel 2 is reduced.

[0119] In some embodiments, as shown in FIG. 1, FIG. 9 , FIG. 10 , FIG. 10 The third type of gate circuit 22c includes a third pull-down maintaining module 334, and the third pull-down maintaining module 334 is electrically connected with the second low potential signal line VGL2.

[0120] In the first direction, the second low-potential signal line VGL2 is disposed between the third pull-down sustaining module 334 and the third low-potential signal line VGL3. By disposing the second low-potential signal line VGL2 between the third pull-down sustaining module 334 and the third low-potential signal line VGL3, the second low-potential signal line VGL2 is arranged adjacent to the transistor it is connected to, thereby shortening the length of the connection line between the second low-potential signal line VGL2 and the transistor it is connected to, or even eliminating the connection line altogether, reducing the space occupied by the second low-potential signal line VGL2, and reducing the bezel of the display panel 2.

[0121] Specifically, in the case where the second low-potential signal line VGL2 is connected to the first type of gate circuit 22a and the second type of gate circuit 22b, the connection between each transistor and the second low-potential signal line VGL2 can be achieved by setting a connection line on the upper side of each level of gate driving circuit 22 or within each level of gate driving circuit 22.

[0122] In some embodiments, such as FIG. 11 As shown, in the first direction, the second reset control line VST2 is disposed between the first reset control line VST1 and the third low-potential signal line VGL3. By disposing the second reset control line VST2 between the first reset control line VST1 and the third low-potential signal line VGL3, the second reset control line VST2 is closer to the transistor it is connected to, and the connection line of the second reset control line VST2 is relatively short or even unnecessary, thereby further reducing the space occupied by the second reset control line VST2 and reducing the bezel of the display panel 2.

[0123] In some embodiments, such as FIG. 12 As shown, in the first direction, the second reset control line VST2 is disposed between the first type of gate circuit 22a and the third type of gate circuit 22c. By disposing the second reset control line VST2 between the first type of gate circuit 22a and the third type of gate circuit 22c, the distance between the second reset control line VST2 and the transistors it is connected to can be further shortened. The connection line of the second reset control line VST2 is relatively short or even unnecessary, thereby further reducing the space occupied by the second reset control line VST2 and reducing the bezel of the display panel 2.

[0124] In some embodiments, such as FIG. 13 to FIG. 18 , FIG. 13 , FIG. 14 As shown, the second type of gate circuit 22b includes a second reset module 327, which is electrically connected to the second reset control line VST2.

[0125] In the first direction, the second reset control line VST2 is arranged between the second reset module 327 and the first type of gate circuit 22a. By arranging the second reset control line VST2 between the second reset module 327 and the first type of gate circuit 22a, the second reset control line VST2 is arranged adjacent to the transistor connected thereto, so that the length of the connection line of the transistor connected to the second reset control line VST2 can be shortened or even eliminated, the space occupied by the second reset control line VST2 is reduced, and the frame of the display panel 2 is reduced.

[0126] In some embodiments, as shown in FIG. 11, in the first direction X, the low-frequency signal line LC is arranged between the first reset control line VST1 and the third low-potential signal line VGL3. By arranging the low-frequency signal line LC between the first reset control line VST1 and the third low-potential signal line VGL3, the low-frequency signal line LC is closer to the transistor connected thereto, and the connection line of the low-frequency signal line LC is relatively short or even unnecessary, so that the space occupied by the low-frequency signal line LC can be further reduced, and the frame of the display panel 2 is reduced. FIG. 8 In some embodiments, as shown in FIG. 11, in the first direction X, the low-frequency signal line LC is arranged between the first reset control line VST1 and the third low-potential signal line VGL3. By arranging the low-frequency signal line LC between the first reset control line VST1 and the third low-potential signal line VGL3, the low-frequency signal line LC is closer to the transistor connected thereto, and the connection line of the low-frequency signal line LC is relatively short or even unnecessary, so that the space occupied by the low-frequency signal line LC can be further reduced, and the frame of the display panel 2 is reduced.

[0127] FIG. 15 In some embodiments, as shown in FIG. 11, in the first direction X, the low-frequency signal line LC is arranged between the first reset control line VST1 and the third low-potential signal line VGL3. By arranging the low-frequency signal line LC between the first reset control line VST1 and the third low-potential signal line VGL3, the low-frequency signal line LC is closer to the transistor connected thereto, and the connection line of the low-frequency signal line LC is relatively short or even unnecessary, so that the space occupied by the low-frequency signal line LC can be further reduced, and the frame of the display panel 2 is reduced.

[0128] In some embodiments, as shown in FIG. 11, in the first direction X, the low-frequency signal line LC is arranged between the first reset control line VST1 and the third low-potential signal line VGL3. By arranging the low-frequency signal line LC between the first reset control line VST1 and the third low-potential signal line VGL3, the low-frequency signal line LC is closer to the transistor connected thereto, and the connection line of the low-frequency signal line LC is relatively short or even unnecessary, so that the space occupied by the low-frequency signal line LC can be further reduced, and the frame of the display panel 2 is reduced. FIG. 16 FIG. 17 FIG. 18 In some embodiments, as shown in FIG. 11, the first type of gate circuit 22a includes a first inverting module 315, and the first inverting module 315 is electrically connected to the low-frequency signal line LC.

[0129] In the first direction, the low-frequency signal line LC is arranged between the first inverting module 315 and the second type of gate circuit 22b. By arranging the low-frequency signal line LC between the first inverting module 315 and the second type of gate circuit 22b, the low-frequency signal line LC is arranged adjacent to the transistor connected thereto, so that the length of the connection line of the transistor connected to the low-frequency signal line LC can be shortened or even eliminated, the space occupied by the low-frequency signal line LC is reduced, and the frame of the display panel 2 is reduced.

[0130] ​​​Specifically, for the case that the low-frequency signal line LC is connected with the second type of gate circuit 22b, the connection of each transistor with the low-frequency signal line LC can be achieved by arranging a connection line on the upper side of each stage of gate drive circuit 22 or in each stage of gate drive circuit 22.

[0131] In some embodiments, as shown in FIG. 5 The first type of gate circuit 22a includes a first pull-up control module 311 and a first pull-up module 312 electrically connected, the first pull-up module 312 includes a first pull-up transistor T21j, a second pull-up transistor T22j and a third pull-up transistor T23j; the second type of gate circuit 22b includes a second pull-up control module 321 and a second pull-up module 322 electrically connected; the third type of gate circuit 22c includes a third pull-up control module 331 and a third pull-up module 332 electrically connected; and the second clock signal line CKB includes a first group of sub-lines CKBi and a second group of sub-lines CKBj.

[0132] In the first direction, the first reset control line VST1, the first high potential signal line VGH1, the first pull-up control module 311, the first low potential signal line VGL1, the low-frequency signal line LC, the first clock signal line CKA, the first pull-up transistor T21j, the first group of sub-lines CKBi, the second pull-up transistor T22j, the second group of sub-lines CKBj, the third pull-up transistor T23j, the second reset control line VST2, the second pull-up control module 321, the third clock signal line CKC, the second pull-up module 322, the third pull-up control module 331, the second low potential signal line VGL2, the second high potential signal line VGH2, the third pull-up module 332 and the third low potential signal line VGL3 are sequentially arranged; so that each signal line can be close to the corresponding transistor, the length of the connection line of each signal line can be reduced or even removed, the horizontal space occupied by the gate drive circuit 22 can be reduced, and the frame of the display panel 2 can be reduced.

[0133] In some embodiments, as shown in FIG. 8 to FIG. 12 The display panel 2 further includes a substrate 211, a light shielding layer 212, a gate layer 218 and a first source-drain layer 221; the light shielding layer 212 is arranged on one side of the substrate 211; the gate layer 218 is arranged on a side of the light shielding layer 212 away from the substrate 211; and the first source-drain layer 221 is arranged on a side of the gate layer 218 away from the light shielding layer 212.

[0134] The display panel 2 includes a multi-level gate driving circuit 22. At least one of the following components—the first clock signal line CKA, the second clock signal line CKB, the third clock signal line CKC, the first high-potential signal line VGH1, the second high-potential signal line VGH2, the first low-potential signal line VGL1, the second low-potential signal line VGL2, the third low-potential signal line VGL3, the first reset control line VST1, the second reset control line VST2, and the low-frequency signal line LC—includes a first part, a second part, and a third part. The first part is disposed on the light-shielding layer 212, the second part is disposed on the gate layer 218, and the third part is disposed on the first source-drain layer. The first part, the second part, and the third part all extend along a second direction.

[0135] The first portion within each level of the gate drive circuit 22 is continuous, the second portion within each level of the gate drive circuit 22 is disconnected, the third portion within each level of the gate drive circuit 22 is disconnected, the first portion is connected to the third portion, and the second portion is connected to the third portion;

[0136] The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By using a light-shielding layer 212, a gate layer 218, and a first source-drain layer 221 to form the first part, the second part, and the third part respectively, the impedance of each signal line can be reduced, and each signal line can be crossed and connected through the parts of different layers, so that each signal line can be connected to the corresponding transistor, and the space occupied is small.

[0137] Specifically, such as FIG. 19 to FIG. 23 As shown, in the first direction, the first part VST1a of the first reset control line VST1, the first part VGH1a of the first high-potential signal line VGH1, the first part VGL1a of the first low-potential signal line VGL1, the first part LCa of the low-frequency signal line LC, the first part CKAa of the first clock signal line CKA, the first part CKBia of the first group of sub-lines CKBi, the first part CKBja ​​of the second group of sub-lines CKBj, the first part VST2a of the second reset control line VST2, the first part CKCa of the third clock signal line CKC, the second low-potential signal line VGL2, the second high-potential signal line VGH2, and the third low-potential signal line VGL3 are arranged sequentially.

[0138] Specifically, such as FIG. 5 As shown, in the first direction, the active portions of each transistor in the first type of gate circuit 22a, the active portions of each transistor in the second type of gate circuit 22b, and the active portions of each transistor in the third type of gate circuit 22c are arranged sequentially.FIG. 19 to FIG. 23 The active portions of each transistor in the first type of gate circuit 22a, the active portions of each transistor in the second type of gate circuit 22b, and the active portions of each transistor in the third type of gate circuit 22c are respectively identified by reference numerals 216a, 216b, and 216c.

[0139] Specifically, such as FIG. 5 As shown, in the first direction, the second part VST1b of the first reset control line VST1, the second part VGH1b of the first high-potential signal line VGH1, the second part VGL1b of the first low-potential signal line VGL1, the second part LCb of the low-frequency signal line LC, the second part CKAb of the first clock signal line CKA, the second part CKBib of the first group of sub-lines CKBi, the second part CKBjb of the second group of sub-lines CKBj, the second part VST2b of the second reset control line VST2, the second part CKCb of the third clock signal line CKC, the second low-potential signal line VGL2, the second high-potential signal line VGH2, and the third low-potential signal line VGL3 are arranged sequentially.

[0140] Specifically, such as FIG. 19 to FIG. 23 As shown, in the first direction, the third part VST1c of the first reset control line VST1, the third part VGH1c of the first high-potential signal line VGH1, the third part VGL1c of the first low-potential signal line VGL1, the third part LCc of the low-frequency signal line LC, the third part CKAc of the first clock signal line CKA, the third part CKBic of the first group of sub-lines CKBi, the third part CKBjc of the second group of sub-lines CKBj, the third part VST2c of the second reset control line VST2, the third part CKCc of the third clock signal line CKC, the second low-potential signal line VGL2, the second high-potential signal line VGH2, and the third low-potential signal line VGL3 are arranged sequentially.

[0141] Specifically, it can be understood that the third part of the first group of sub-lines CKBi and the third part of the second group of sub-lines CKBj constitute the third part CKBc of the second clock signal line CKB, the second part of the first group of sub-lines CKBi and the second part of the second group of sub-lines CKBj constitute the second part CKBb of the second clock signal line CKB, and the first part of the first group of sub-lines CKBi and the first part of the second group of sub-lines CKBj constitute the first part CKBa of the second clock signal line CKB.

[0142] Meanwhile, to illustrate the correspondence between different film layers, the following is provided: FIG. 5 ,like FIG. 19 to FIG. 23As shown, the relative positional relationship between the light-shielding layer 212 and the active layer 216 can be seen; as FIG. 5 As shown, the relative positions of the light-shielding layer 212, the active layer 216, and the gate layer 218 can be observed; FIG. 19 to FIG. 23 As shown, the relative positions of the light-shielding layer 212, the active layer 216, the gate layer 218, and the first source / drain layer 221 can be observed; FIG. 5 As shown, the relative positional relationship between the light-shielding layer 212 and the first via 411 can be seen. The first via 411 refers to the via connecting the first source / drain layer 221 and the light-shielding layer 212, including the via of the buffer layer 213; as shown... FIG. 5 As shown, the relative positional relationship between the light-shielding layer 212 and the first source / drain layer 221, and their connection points, can be observed; FIG. 19 As shown, the relative positional relationship between the gate layer 218 and the second via 412 can be seen. The second via 412 refers to the via of the first interlayer insulating layer 219; as FIG. 5 As shown, the relative positions of the gate layer 218 and the first source / drain layer 221, as well as their connection points, can be observed.

[0143] In some embodiments, such as FIG. 19 , FIG. 19 , FIG. 5 As shown, in the first direction, at least one of the first clock signal line CKA, the second clock signal line CKB, the first high-potential signal line VGH1, the first low-potential signal line VGL1, and the low-frequency signal line LC is disposed between the first reset control line VST1 and the second type of gate circuit 22b. By disposing at least one of the first clock signal line CKA, the second clock signal line CKB, the first high-potential signal line VGH1, the first low-potential signal line VGL1, and the low-frequency signal line LC between the first reset control line VST1 and the second type of gate circuit 22b, the length of the connection line required when connecting the signal line to the corresponding transistor can be reduced. It eliminates the need to place the signal line outside the transistor region and then extend it into the transistor region, reducing the space occupied by the signal line outside and inside the transistor region. This reduces the lateral space occupied by the signal line connected to the first type of gate circuit 22a, thus reducing the lateral space occupied by the first type of gate circuit 22a and reducing the bezel of the display panel 2.

[0144] In some embodiments, such as FIG. 19 , FIG. 19As shown, the first type of gate circuit 22a includes a first pull-up control module 311, the first pull-up control module 311 is electrically connected with the first high potential signal line VGH1, and the first high potential signal line VGH1 is arranged between the first reset control line VST1 and the first pull-up control module 311 in the first direction. By arranging the first high potential signal line VGH1 between the first reset control line VST1 and the first pull-up control module 311, the horizontal space occupied by the first high potential signal line VGH1 (including the connection line for transmitting the signal of the first high potential signal line VGH1, and the same applies to other signal lines including their connection lines) can be reduced when the first high potential signal line VGH1 is connected to the first pull-up control module 311, the horizontal space occupied by the first type of gate circuit 22a can be reduced, and the frame can be reduced.

[0145] In some embodiments, as shown in FIG. 5 、 FIG. 19 As shown, the first type of gate circuit 22a includes a first pull-down maintenance module 314, the first pull-down maintenance module 314 is electrically connected with the first low potential signal line VGL1, and the first low potential signal line VGL1 is arranged between the first pull-down maintenance module 314 and the second type of gate circuit 22b in the first direction. By arranging the first low potential signal line VGL1 between the first pull-down maintenance module 314 and the second type of gate circuit 22b, the horizontal space occupied by the first low potential signal line VGL1 can be reduced when the first low potential signal line VGL1 is connected to the first pull-down maintenance module 314, the horizontal space occupied by the first type of gate circuit 22a can be reduced, and the frame can be reduced.

[0146] In some embodiments, as shown in FIG. 19 、 FIG. 5 As shown, the first type of gate circuit 22a includes a first inverting module 315, the first inverting module 315 is electrically connected with the low-frequency signal line LC, and the low-frequency signal line LC is arranged between the first low potential signal line VGL1 and the second type of gate circuit 22b in the first direction. By arranging the low-frequency signal line LC between the first low potential signal line VGL1 and the second type of gate circuit 22b, the horizontal space occupied by the low-frequency signal line LC can be reduced, the horizontal space occupied by the first type of gate circuit 22a can be reduced, and the frame can be reduced.

[0147] In some embodiments, as shown in FIG. 19 to FIG. 23 、 FIG. 5 As shown, the first type of gate circuit 22a includes a first pull-up module 312, the second clock signal line CKB includes a first group of sub-lines CKBi and a second group of sub-lines CKBj, and the first pull-up module 312 includes:

[0148] a first pull-up transistor T21j has one electrode electrically connected with the first clock signal line CKA;

[0149] a second pull-up transistor T22j has one electrode electrically connected with the first group of sub-lines CKBi;

[0150] a third pull-up transistor T23j has one electrode electrically connected with the second group of sub-lines CKBj;

[0151] The first pull-up transistor T21j, the second pull-up transistor T22j and the third pull-up transistor T23j are arranged in a first direction in sequence. In the first direction, the first clock signal line CKA is arranged between the low-frequency signal line LC and the first pull-up transistor T21j, the first group of sub-lines CKBi is arranged between the first pull-up transistor T21j and the second pull-up transistor T22j, and the second group of sub-lines CKBj is arranged between the second pull-up transistor T22j and the third pull-up transistor T23j. By arranging the first clock signal line CKA between the low-frequency signal line LC and the first pull-up transistor T21j, the first group of sub-lines CKBi between the first pull-up transistor T21j and the second pull-up transistor T22j, and the second group of sub-lines CKBj between the second pull-up transistor T22j and the third pull-up transistor T23j, the transverse space occupied by each clock signal line, the transverse space occupied by the first type of gate circuit 22a, and the frame can be reduced.

[0152] In some embodiments, as FIG. 19 to FIG. 23As shown, the first type of gate circuit 22a includes a first pull-up control module 311, a first pull-up module 312, a first pull-down module 313, a first pull-down maintenance module 314, a first inverting module 315, a first negative bias prevention module 316, and a first reset module 317. The first pull-up control module 311 and the first pull-up module 312 are electrically connected to a first pull-up node Q1[n], the first pull-down module 313 is electrically connected to the first pull-up node Q1[n] and a first signal output terminal Gn[n] of the first type of gate circuit 22a; the first pull-down maintenance module 314 is electrically connected between the first pull-up node Q1[n] and a first low potential signal line VGL1; the first inverting module 315 is electrically connected to the first pull-up node Q1[n], the first low potential signal line VGL1, and a low frequency signal line LC; the first negative bias prevention module 316 is electrically connected between a first high potential signal line VGH1 and the first pull-up node Q1[n], and the first reset module 317 is electrically connected between the first pull-up node Q1[n] and the first low potential signal line VGL1.

[0153] In some embodiments, as shown in FIG. 5 、 FIG. 19 to FIG. 23 At least two of the first pull-up control module 311, the first pull-up module 312, the first pull-down module 313, the first pull-down maintenance module 314, the first inverting module 315, the first negative bias prevention module 316, and the first reset module 317 are arranged along a second direction, and an included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By arranging at least two of the first pull-up control module 311, the first pull-up module 312, the first pull-down module 313, the first pull-down maintenance module 314, the first inverting module 315, the first negative bias prevention module 316, and the first reset module 317 along the second direction, the horizontal space occupied by the first type of gate circuit 22a can be shortened, thereby reducing the horizontal space occupied by the gate drive circuit 22 and reducing the frame of the display panel 2.

[0154] Specifically, compared with the transverse arrangement of each module in the comparative display device, by arranging at least two modules in the first type of gate circuit 22a along the second direction, the horizontal space occupied by the first type of gate circuit 22a can be reduced, the horizontal space occupied by the gate drive circuit 22 can be reduced, and the frame of the display panel 2 can be reduced.

[0155] In some embodiments, as shown in FIG. 5 、 FIG. 19 to FIG. 23As shown, the first pull-up control module 311 and the first reset module 317 are arranged along the second direction. By arranging the first pull-up control module 311 and the first reset module 317 along the second direction, the transverse space occupied by the first pull-up control module 311 and the first reset module 317 can be reduced, the transverse space occupied by the first gate circuit 22a can be reduced, the transverse space occupied by the gate drive circuit 22 can be reduced, and thus the frame of the display panel 2 can be reduced.

[0156] Specifically, as shown in FIG. 5 , it can be seen that, in the second direction, the first pull-up control module 311 is arranged above the first reset module 317.

[0157] In some embodiments, as shown in FIG. 19 to FIG. 23 , FIG. 5 , at least part of the first pull-down module 313, the first pull-down maintenance module 314, and the first inverting module 315 are arranged along the second direction. By arranging at least part of the first pull-down module 313, the first pull-down maintenance module 314, and the first inverting module 315 along the second direction, the transverse space occupied by the first gate circuit 22a can be reduced, the transverse space occupied by the gate drive circuit 22 can be reduced, and thus the frame of the display panel 2 can be reduced.

[0158] Specifically, as shown in FIG. 19 to FIG. 23 , it can be seen that, in the second direction, the first inverting module 315 and the first pull-down maintenance module 314 are arranged in sequence, part of the first pull-down module 313 is arranged between the first inverting module 315 and the first pull-down maintenance module 314, and another part of the first pull-down module 313 is arranged on the side of the first pull-down maintenance module 314 away from the first inverting module 315.

[0159] In some embodiments, as shown in FIG. 5 , FIG. 19 to FIG. 23 , part of the first inverting module 315 and part of the first pull-up control module 311 are arranged along the first direction, and another part of the first inverting module 315 and another part of the first pull-up control module 311 are arranged along the second direction. By arranging part of the first inverting module 315 and part of the first pull-up control module 311 along the second direction, the transverse space occupied by the gate drive circuit 22 can be further reduced, and thus the frame of the display panel 2 can be reduced.

[0160] Specifically, as shown in FIG. 5As shown, it can be seen that the widths of the various parts in the first pull-up control module 311 are different, a part of the first inverting module 315 is arranged along a first direction with a part of the first pull-up control module 311, and a part of the first inverting module 315 is arranged along a second direction with another part of the first pull-up control module 311.

[0161] In some embodiments, as shown in FIG. 19 to FIG. 23 、 FIG. 5 The first pull-up control module 311 includes a first pull-up control transistor T11j, a second pull-up control transistor T12j, and a third pull-up control transistor T81j. A gate T11jG of the first pull-up control transistor T11j is electrically connected with a stage transmission output end Cout[n-2] of the upper two-stage first type gate circuit 22a. A first electrode T11jS of the first pull-up control transistor T11j is electrically connected with the first high potential signal line VGH1. A second electrode T11jD of the first pull-up control transistor T11j is electrically connected with a first electrode T12jS of the second pull-up control transistor T12j. A gate T12jG of the second pull-up control transistor T12j is electrically connected with the stage transmission output end Cout[n-2] of the upper two-stage first type gate circuit 22a. A second electrode T12jD of the second pull-up control transistor T12j is electrically connected with a first pull-up node Q1[n]. A gate T81jG of the third pull-up control transistor T81j is electrically connected with the first high potential signal line VGH1. A first electrode T81jS of the third pull-up control transistor T81j is electrically connected with the first high potential signal line VGH1. A second electrode T81jD of the third pull-up control transistor T81j is electrically connected with the second electrode T11jD of the first pull-up control transistor T11j.

[0162] In each stage of the gate drive circuit 22, the third pull-up control transistor T81j, the first pull-up control transistor T11j, and the second pull-up control transistor T12j are arranged along the second direction in sequence. By arranging the third pull-up control transistor T81j, the first pull-up control transistor T11j, and the second pull-up control transistor T12j along the second direction in sequence, the space occupied by the first pull-up module 312 can be reduced, thereby reducing the frame of the display panel 2.

[0163] In some embodiments, as shown in FIG. 19 to FIG. 23 、 FIG. 5As shown, the third pull-up control transistor T81j includes a first pull-up control sub-transistor T81j1 and a second pull-up control sub-transistor T81j2, the gate T81j2G of the second pull-up control sub-transistor T81j2 and the first electrode T81j2S of the second pull-up control sub-transistor T81j2 are electrically connected with the first high potential signal line VGH1, the second electrode T81j2D of the second pull-up control sub-transistor T81j2 is electrically connected with the first electrode of the first pull-up control sub-transistor T81j1, the gate T81j1G of the first pull-up control sub-transistor T81j1 is electrically connected with the first high potential signal line VGH1, and the second electrode T81j1D of the first pull-up control sub-transistor T81j1 is electrically connected with the second electrode T11jD of the first pull-up control transistor T11j;

[0164] The first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2 are arranged along the second direction. By arranging the third pull-up control transistor T81j to include the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2, the performance of the third pull-up control transistor T81j can be improved, and arranging the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2 along the first direction can reduce the horizontal area occupied by the third pull-up control transistor T81j and reduce the frame of the display panel 2.

[0165] Specifically, the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2 can be regarded as two independent transistors, or as two sub-transistors in the third pull-up control transistor T81j. Similarly, other sub-transistors can be referred to the above description and will not be described in the following embodiments.

[0166] Specifically, when a transistor has multiple sub-transistors, the first electrode of the transistor is the electrode connected with the signal line. For example, the third pull-up control transistor T81j includes the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2, and since the first electrode T81j2S of the second pull-up control sub-transistor T81j2 is electrically connected with the first high potential signal line VGH1, the first electrode T81jS of the third pull-up control transistor T81j is the first electrode T81j2S of the second pull-up control sub-transistor T81j2. Similarly, the first electrode of other transistors can be determined.

[0167] Specifically, the multi-level gate drive circuit 22 includes a multi-level first-type gate circuit 22a. In the first-level first-type gate circuit 22a, the gate T11jG of the first pull-up control transistor T11j can be connected to the start signal line. In the other levels of the first-type gate circuit 22a, the gate T11jG of the first pull-up control transistor T11j and the gate T12jG of the second pull-up control transistor T12j are connected to the first signal output terminals of the two previous levels of the first-type gate circuit 22a. The first electrode T11jS of the first pull-up control transistor T11j and the first electrode T12jS of the second pull-up control transistor T12j are electrically connected to the first high-potential signal line VGH1.

[0168] In some embodiments, such as FIG. 19 to FIG. 23 , FIG. 5 As shown, the first pull-down module 313 includes a first pull-down transistor T31j, a second pull-down transistor T32j, a third pull-down transistor T33j, and a fourth pull-down transistor T41j. The gate T31jG of the first pull-down transistor T31j is electrically connected to the first pull-down node QB1[n]. The first electrode T31jS of the first pull-down transistor T31j is electrically connected to the first low-potential signal line VGL1. The second electrode T31jD of the first pull-down transistor T31j is electrically connected to the stage output terminal Cout[n] of the first type of gate circuit 22a of this stage. The gate T32jG of the second pull-down transistor T32j is electrically connected to the first pull-down node QB1[n]. The first electrode T32jS of the second pull-down transistor T32j is electrically connected to the second low-potential signal line VGL2. The second electrode T32jD of the second pull-down transistor T32j is electrically connected to the fourth pull-down transistor T41j. The first signal output terminal Gn[m] of the first-stage first-class gate circuit 22a is electrically connected; the gate T33jG of the third pull-down transistor T33j is electrically connected to the first pull-down node QB1[n]; the first electrode T33jS of the third pull-down transistor T33j is electrically connected to the second low-potential signal line VGL2; and the second electrode T33jD of the third pull-down transistor T33j is electrically connected to the first signal output terminal Gn[n] of the first-stage first-class gate circuit 22a. The gate T41jG of the fourth pull-down transistor T41j is electrically connected to the stage transmission output terminal Cout[n+2] of the next two stages of the first-class gate circuit 22a; the first electrode T41jS of the fourth pull-down transistor T41j is electrically connected to the first low-potential signal line VGL1; and the second electrode T41jD of the fourth pull-down transistor T41j is electrically connected to the first pull-up node Q1[n].

[0169] The first pull-down transistor T31j and the fourth pull-down transistor T41j are arranged along the second direction, and the second pull-down transistor T32j and the third pull-down transistor T33j are arranged along the second direction. By arranging the first pull-down transistor T31j and the fourth pull-down transistor T41j along the second direction, and arranging the second pull-down transistor T32j and the third pull-down transistor T33j along the second direction, the space occupied by the first pull-down module 313 can be reduced, and the frame of the display panel 2 can be reduced.

[0170] In some embodiments, as shown in FIG. 5 、 FIG. 19 to FIG. 23 The fourth pull-down transistor T41j includes a first pull-down sub-transistor T41j1 and a second pull-down sub-transistor T41j2. The gate T41j2G of the second pull-down sub-transistor T41j2 is electrically connected to the stage transmission output end Cout[n+2] of the lower two-stage first type gate circuit 22a. The first electrode T41j2S of the second pull-down sub-transistor T41j2 is electrically connected to the first low potential signal line VGL1. The second electrode T41j2D of the second pull-down sub-transistor T41j2 is electrically connected to the first electrode T41j1S of the first pull-down sub-transistor T41j1 at the first internal node N1[n]. The gate T41j1G of the first pull-down sub-transistor T41j1 is electrically connected to the stage transmission output end Cout[n+2] of the lower two-stage first type gate circuit 22a. The second electrode T41j1D of the first pull-down sub-transistor T41j1 is electrically connected to the first pull-up node Q1[n].

[0171] The first pull-down sub-transistor T41j1 and the second pull-down sub-transistor T41j2 are arranged along the second direction. By arranging the fourth pull-down transistor T41j to include the first pull-down sub-transistor T41j1 and the second pull-down sub-transistor T41j2, the performance of the fourth pull-down transistor T41j can be improved. Arranging the first pull-down sub-transistor T41j1 and the second pull-down sub-transistor T41j2 along the second direction can reduce the horizontal area occupied by the fourth pull-down transistor T41j, and reduce the frame of the display panel 2.

[0172] In some embodiments, as shown in FIG. 19 、 FIG. 20As shown, the first inverting module 315 includes a first inverting transistor T51j, a second inverting transistor T52j, a third inverting transistor T53j, a fourth inverting transistor T54j, and a fifth inverting transistor T55j, a gate electrode T51jG of the first inverting transistor T51j and a first electrode T51jS of the first inverting transistor T51j are electrically connected with a low-frequency signal line LC, a second electrode T51jD of the first inverting transistor T51j is electrically connected with a second electrode T52jD of the second inverting transistor T52j, a gate electrode T52jG of the second inverting transistor T52j is electrically connected with the first pull-up node Q1[n], a first electrode T52jS of the second inverting transistor T52j is electrically connected with the first low-potential signal line VGL1, a gate electrode T53jG of the third inverting transistor T53j is electrically connected with the second electrode T51jD of the first inverting transistor T51j, a first electrode T53jS of the third inverting transistor T53j is electrically connected with the low-frequency signal line LC, a second electrode T53jD of the third inverting transistor T53j is electrically connected with the first pull-down node QB1[n], a gate electrode T54jG of the fourth inverting transistor T54j is electrically connected with the first pull-up node Q1[n], a first electrode T54jS of the fourth inverting transistor T54j is electrically connected with the first low-potential signal line VGL1, a second electrode T54jD of the fourth inverting transistor T54j is electrically connected with the first pull-down node QB1[n], a gate electrode T55jG of the fifth inverting transistor T55j is electrically connected with a level-shift output end Cout[n-2] of the upper two-stage first-type gate circuit 22a, a first electrode T55jS of the fifth inverting transistor T55j is electrically connected with the first low-potential signal line VGL1, and a second electrode T55jD of the fifth inverting transistor T55j is electrically connected with the first pull-down node QB1[n].

[0173] In the first inverting module 315, the first inverting transistor T51j and the second inverting transistor T52j are arranged along the second direction, the third inverting transistor T53j, the fourth inverting transistor T54j, and the fifth inverting transistor T55j are arranged along the second direction, and the first inverting transistor T51j and the third inverting transistor T53j are arranged along the first direction. By arranging the first inverting transistor T51j and the second inverting transistor T52j along the second direction, the third inverting transistor T53j, the fourth inverting transistor T54j, and the fifth inverting transistor T55j along the second direction, the transverse space occupied by the first inverting module 315 can be reduced, thereby reducing the frame of the display panel 2.

[0174] In some embodiments, as FIG. 20 , FIG. 20As shown, the first inverting transistor T51j includes a first inverting sub-transistor T51j1 and a second inverting sub-transistor T51j2. The gate T51j1G and the first electrode T51j1S of the first inverting sub-transistor T51j1 are electrically connected to the low-frequency signal line LC. The second electrode T51j1D of the first inverting sub-transistor T51j1 is electrically connected to the first electrode of the second inverting sub-transistor T51j2. The gate T51j2G of the second inverting sub-transistor T51j2 is electrically connected to the low-frequency signal line LC. The second electrode T51j2D of the second inverting sub-transistor T51j2 is electrically connected to the second electrode T52jD of the second inverting transistor T52j.

[0175] The first inverting sub-transistor T51j1 and the second inverting sub-transistor T51j2 are arranged along a first direction. By including the first inverting sub-transistor T51j1 and the second inverting sub-transistor T51j2 in the first inverting transistor T51j, the performance of the first inverting transistor T51j can be improved.

[0176] In some embodiments, such as FIG. 20 , FIG. 19 As shown, the third inverting transistor T53j and the third pull-up control transistor T81j are arranged along the first direction, and the third inverting transistor T53j and the first pull-up control transistor T11j are arranged along the second direction; thereby reducing the horizontal space occupied by the first inverting module 315 and the first pull-up control module 311, and reducing the bezel of the display panel 2.

[0177] In some embodiments, such as FIG. 21 , FIG. 21 As shown, the first pull-down sustaining module 314 includes a first pull-down sustaining transistor T42j, the gate T42jG of the first pull-down sustaining transistor T42j is electrically connected to the first pull-down node QB1[n], the first electrode T42jS of the first pull-down sustaining transistor T42j is electrically connected to the first low-potential signal line VGL1, and the second electrode T42jD of the first pull-down sustaining transistor T42j is electrically connected to the first pull-up node Q1[n].

[0178] In the second direction, the first pull-down holding transistor T42j is disposed between the first pull-down transistor T31j and the fourth pull-down transistor T41j. This reduces the lateral space occupied by the first pull-down holding transistor T42j, the first pull-down transistor T31j, and the fourth pull-down transistor T41j, thereby reducing the bezel of the display panel 2.

[0179] In some embodiments, such as FIG. 21 , FIG. 21As shown in FIG. 7, the first pull-down maintenance transistor T42j includes a first pull-down maintenance sub-transistor T42j1 and a second pull-down maintenance sub-transistor T42j2, a gate T42j2G of the second pull-down maintenance sub-transistor T42j2 is electrically connected with the first pull-down node QB1[n], a first electrode T42j2S of the second pull-down maintenance sub-transistor T42j2 is electrically connected with the first low potential signal line VGL1, a second electrode T42j2D of the second pull-down maintenance sub-transistor T42j2 is electrically connected with a first electrode T42j1S of the first pull-down maintenance sub-transistor T42j1 at the first internal node N1[n], a gate T42j1G of the first pull-down maintenance sub-transistor T42j1 is electrically connected with the first pull-down node QB1[n], and a second electrode of the first pull-down maintenance sub-transistor T42j1 is electrically connected with the first pull-up node Q1[n].

[0180] In the embodiment, the first pull-down maintenance sub-transistor T42j1 and the second pull-down maintenance sub-transistor T42j2 are arranged along the second direction. By arranging the first pull-down maintenance transistor T42j to include the first pull-down maintenance sub-transistor T42j1 and the second pull-down maintenance sub-transistor T42j2, the performance of the first pull-down maintenance transistor T42j can be improved, and the first pull-down maintenance sub-transistor T42j1 and the second pull-down maintenance sub-transistor T42j2 are arranged along the second direction, so that the horizontal space occupied by the first pull-down maintenance transistor T42j can be reduced, and the frame of the display panel 2 can be reduced.

[0181] In some embodiments, as shown in FIG. 7, FIG. 21 FIG. 21 The first reset module 317 includes a first reset transistor T43j, a gate T43jG of the first reset transistor T43j is electrically connected with the first reset control line VST1, a first electrode T43jS of the first reset transistor T43j is electrically connected with the first low potential signal line VGL1, and a second electrode T43jD of the first reset transistor T43j is electrically connected with the first pull-up node Q1[n].

[0182] In the embodiment, the first reset transistor T43j is arranged on a side of the second pull-up control transistor T12j away from the first pull-up control transistor T11j. By arranging the first reset transistor T43j on the side of the second pull-up control transistor T12j away from the first pull-up control transistor T11j, the horizontal space occupied by the first reset transistor T43j and the first pull-up control module 311 can be reduced, so that the frame of the display panel 2 can be reduced, and the first reset transistor T43j is convenient to be connected to the first low potential signal line VGL1.

[0183] In some embodiments, as shown in FIG. 7, FIG. 21 FIG. 19 ​​As shown in FIG. 7, the first reset transistor T43j includes a first reset sub-transistor T43j1 and a second reset sub-transistor T43j2, a gate electrode T43j1G of the second reset sub-transistor T43j2 is electrically connected with the first reset control line VST1, a first electrode of the second reset sub-transistor T43j2 is electrically connected with the first low potential signal line VGL1, a second electrode T43j1D of the first reset sub-transistor T43j1 is electrically connected with a first electrode T43j1S of the first reset sub-transistor T43j1 at a first internal node N1[n], a gate electrode T43j1G of the first reset sub-transistor T43j1 is electrically connected with the first reset control line VST1, and the second electrode T43j1D of the first reset sub-transistor T43j1 is electrically connected with the first pull-up node Q1[n].

[0184] The first reset sub-transistor T43j1 and the second reset sub-transistor T43j2 are arranged along the second direction. By arranging the first reset sub-transistor T43j1 and the second reset sub-transistor T43j2 along the second direction, the performance of the first reset transistor T43j can be improved, and the transverse space occupied by the first reset transistor T43j can be reduced, thereby reducing the frame of the display panel 2.

[0185] In some embodiments, as shown in FIG. 7, the first negative bias prevention module 316 includes a first negative bias prevention transistor T71j, a gate electrode T71jG of the first negative bias prevention transistor T71j is electrically connected with the first pull-up node Q1[n], a first electrode T71jS of the first negative bias prevention transistor T71j is electrically connected with the first high potential signal line VGH1, and a second electrode T71jD of the first negative bias prevention transistor T71j is electrically connected with the first internal node N1[n]. FIG. 22 FIG. 22 The first negative bias prevention transistor T71j is arranged along the second direction between the second inverter transistor T52j and the first pull-down transistor T31j. By arranging the first negative bias prevention transistor T71j along the second direction between the second inverter transistor T52j and the first pull-down transistor T31j, the transverse area occupied by the first negative bias prevention module 316 can be reduced, thereby reducing the frame of the display panel 2.

[0186] The first negative bias prevention transistor T71j is arranged along the second direction between the second inverter transistor T52j and the first pull-down transistor T31j. By arranging the first negative bias prevention transistor T71j along the second direction between the second inverter transistor T52j and the first pull-down transistor T31j, the transverse area occupied by the first negative bias prevention module 316 can be reduced, thereby reducing the frame of the display panel 2.

[0187] ​In some embodiments, the first negative bias prevention transistor T71j comprises a first negative bias prevention sub-transistor T71j1 and a second negative bias prevention sub-transistor T71j2, a gate T71j2G of the second negative bias prevention sub-transistor T71j2 is electrically connected with the first pull-up node Q1[n], a first electrode T71j2S of the second negative bias prevention sub-transistor T71j2 is electrically connected with the first high potential signal line, a second electrode T71j2D of the second negative bias prevention sub-transistor T71j2 is electrically connected with a first electrode of the first negative bias prevention sub-transistor T71j1, a gate T71j1G of the first negative bias prevention sub-transistor T71j1 is electrically connected with the first pull-up node Q1[n], and a second electrode T71j1D of the first negative bias prevention sub-transistor T71j1 is electrically connected with the first internal node N1[n];

[0188] The first negative bias prevention sub-transistor T71j1 and the second negative bias prevention sub-transistor T71j2 are arranged along the second direction. By arranging the first negative bias prevention transistor T71j to comprise the first negative bias prevention sub-transistor T71j1 and the second negative bias prevention sub-transistor T71j2, the performance of the first negative bias prevention transistor T71j can be improved, and arranging the first negative bias prevention sub-transistor T71j1 and the second negative bias prevention sub-transistor T71j2 along the second direction can reduce the horizontal space occupied by the first negative bias prevention transistor T71j and reduce the frame of the display panel 2.

[0189] In some embodiments, the second clock signal line CKB comprises a first group of sub-lines CKBi and a second group of sub-lines CKBj, the first pull-up module 312 comprises a first pull-up transistor T21j, a second pull-up transistor T22j and a third pull-up transistor T23j, a gate T21jG of the first pull-up transistor T21j is electrically connected with the first pull-up node Q1[n], a first electrode T21jS of the first pull-up transistor T21j is electrically connected with the first clock signal line CKA, a second electrode T21jD of the first pull-up transistor T21j is electrically connected with the stage transmission output end Cout[n] of the first type of gate circuit 22a of the current stage, a gate T22jG of the second pull-up transistor T22j is electrically connected with the first pull-up node Q1[n], a first electrode T22jS of the second pull-up transistor T22j is electrically connected with the first group of sub-lines CKBi, a second electrode T22jD of the second pull-up transistor T22j is electrically connected with the first signal output end Gn[m] of the first type of gate circuit 22a of another stage, a gate T23jG of the third pull-up transistor T23j is electrically connected with the first pull-up node Q1[n], a first electrode T23jS of the third pull-up transistor T23j is electrically connected with the second group of sub-lines CKBj, and a second electrode T23jD of the third pull-up transistor T23j is electrically connected with the first signal output end Gn[n] of the first type of gate circuit 22a of the current stage.

[0190] Wherein, in the first direction, the first clock signal line CKA is arranged adjacent to the first pull-up transistor T21j, the first group of sub-lines CKBi is arranged adjacent to the second pull-up transistor T22j, and the second group of sub-lines CKBj is arranged adjacent to the third pull-up transistor T23j; so that the first clock signal line CKA and the second clock signal line CKB do not need to be extended to the transistor area after being wired from the outside of the transistor area, the clock signal lines are arranged adjacent to the transistors connected thereto, the number of crossing lines is reduced, the space occupied by each clock signal line is reduced, and the frame of the display panel 2 is reduced.

[0191] Specifically, the first clock signal line CKA can include a first clock first line CKA1, a first clock second line CKA2, a first clock third line CKA3, and a first clock fourth line CKA4. Every four levels of the first type of gate circuit 22a are connected in cycles with the four first clock signal lines CKA. For example, the first level of the first type of gate circuit 22a to the fourth level of the first type of gate circuit 22a are connected with the first clock first line CKA1, the first clock second line CKA2, the first clock third line CKA3, and the first clock fourth line CKA4, respectively. The fifth level of the first type of gate circuit 22a to the eighth level of the first type of gate circuit 22a are connected with the first clock first line CKA1, the first clock second line CKA2, the first clock third line CKA3, and the first clock fourth line CKA4, respectively. Similarly, the clock signal lines connected with other levels of the first type of gate circuit 22a can be determined.

[0192] Specifically, the above embodiment takes the first clock signal line CKA including four clock lines as an example for illustration, but the embodiments of the present application are not limited thereto. The first clock signal line CKA can include other number of clock lines, for example, can include 8 clock lines.

[0193] Specifically, the second clock signal line CKB may include a second clock first line CKB1, a second clock second line CKB2, a second clock third line CKB3, a second clock fourth line CKB4, a second clock fifth line CKB5, a second clock sixth line CKB6, a second clock seventh line CKB7, and a second clock eighth line CKB8. The second clock first line CKB1, the second clock third line CKB3, the second clock fifth line CKB5, and the second clock seventh line CKB7 form the first group of sub-lines CKBi. The second clock second line CKB2, the second clock fourth line CKB4, the second clock sixth line CKB6, and the second clock eighth line CKB8 form the second group of sub-lines CKBj. The second pull-up transistor T22j of every four stages of the first-class gate circuit 22a is cyclically connected to the first group of sub-lines CKBi, and the third pull-up transistor T23j of every four stages of the first-class gate circuit 22a is cyclically connected to the second group of sub-lines CKBj. For example, the second pull-up transistors of the first-class gate circuit 22a to the fourth-class gate circuit 22a... Transistor T22j is connected to the first line of the second clock (CKB1), the third line of the second clock (CKB3), the fifth line of the second clock (CKB5), and the seventh line of the second clock (CKB7), respectively. The third pull-up transistors T23j of the first-stage first-type gate circuit 22a to the fourth-stage first-type gate circuit 22a are connected to the second line of the second clock (CKB2), the fourth line of the second clock (CKB4), the sixth line of the second clock (CKB6), and the eighth line of the second clock (CKB8), respectively. The second pull-up transistors T22j of the fifth-stage first-type gate circuit 22a to the eighth-stage first-type gate circuit 22a are connected to the first line of the second clock (CKB1), the third line of the second clock (CKB3), the fifth line of the second clock (CKB5), and the seventh line of the second clock (CKB7), respectively. The third pull-up transistors T23j of the fifth-stage first-type gate circuit 22a to the eighth-stage first-type gate circuit 22a are connected to the second line of the second clock (CKB2), the fourth line of the second clock (CKB4), the sixth line of the second clock (CKB6), and the eighth line of the second clock (CKB8), respectively. Similarly, the clock signal lines connected to the other stages of the first-type gate circuit 22a can be determined.

[0194] Specifically, the above embodiment is illustrated by taking the second clock signal line CKB as an example, which includes eight clock lines. However, the embodiments of this application are not limited to this. The second clock signal line CKB may include other numbers of clock lines, such as four clock lines or sixteen clock lines.

[0195] In some embodiments, such as FIG. 22 As shown, the first type of gate circuit 22a also includes a first capacitor C1. One plate of the first capacitor C1 is electrically connected to the first pull-up node Q1[n], and the other plate of the first capacitor C1 is electrically connected to the stage output terminal Cout[n] of the first type of gate circuit 22a.

[0196] In some embodiments, as shown in FIG. 22 、 FIG. 22 the first capacitor C1 includes a first sub-capacitor C11, a second sub-capacitor C12, a third sub-capacitor C13, and a fourth sub-capacitor C14, in the second direction, the first sub-capacitor C11 and the second sub-capacitor C12 are arranged on both sides of the first pull-up transistor T21j; the third sub-capacitor C13 is arranged on one side of the second pull-up transistor T22j; the fourth sub-capacitor C14 is arranged on one side of the third pull-up transistor T23j; so that the capacitance of the first capacitor C1 is large, and the first capacitor C1 does not occupy the horizontal space.

[0197] Specifically, the first plate C11a of the first sub-capacitor C11, the first plate C12a of the second sub-capacitor C12, the first plate C13a of the third sub-capacitor C13, and the first plate C14a of the fourth sub-capacitor C14 can be connected together, and the second plate C11b of the first sub-capacitor C11, the second plate C12b of the second sub-capacitor C12, the second plate of the third sub-capacitor C13, and the second plate C13bC14b of the fourth sub-capacitor C14 can be connected together.

[0198] In some embodiments, as shown in FIG. 22 、 FIG. 22 the display panel 2 includes a light shielding layer 212, the light shielding layer 212 includes, in the first direction, a first part VST1a of the first reset control line VST1, a first part VGH1a of the first high potential signal line VGH1, a level transfer output end Cout[n] of the first type of gate circuit 22a of the current stage, a first part VGL1a of the first low potential signal line VGL1, a first part LCa of the low frequency signal line LC, a first part CKAa of the first clock signal line CKA, a first part C11a1 of the first plate C11a of the first sub-capacitor C11, a first part CKBia of the first group of sub-lines CKBi, a first part C13a1 of the first plate C13a of the third sub-capacitor C13, a first part CKBja of the second group of sub-lines CKBj, and a first part C14a1 of the first plate C14a of the fourth sub-capacitor C14; the light shielding layer 212 further includes a first part C12a1 of the first plate C12a of the second sub-capacitor C12, and the first part C12a1 of the first plate C12a of the second sub-capacitor C12 is arranged in the second direction with the first part C11a1 of the first plate C11a of the first sub-capacitor C11.

[0199] Specifically, the level transfer output end of each stage of the first type of gate circuit 22a passes through multiple stages of the first type of gate circuit 22a to be connected to the corresponding transistor.

[0200] Specifically, as shown in FIG. 22As shown, the first part CKAa of the first clock signal line CKA includes, in sequence along the first direction, a first part CKA4a of the first clock fourth line CKA4, a first part CKA3a of the first clock third line CKA3, a first part CKA2a of the first clock second line CKA2, and a first part CKA1a of the first clock first line CKA1.

[0201] Specifically, as shown in FIG. 6, the first part CKBia of the first group of sub-lines CKBi includes, in sequence along the first direction, a first part CKB7a of the second clock seventh line CKB7, a first part CKB5a of the second clock fifth line CKB5, a first part CKB3a of the second clock third line CKB3, and a first part CKB1a of the second clock first line CKB1. FIG. 22

[0202] Specifically, as shown in FIG. 6, the first part CKBia of the first group of sub-lines CKBi includes, in sequence along the first direction, a first part CKB7a of the second clock seventh line CKB7, a first part CKB5a of the second clock fifth line CKB5, a first part CKB3a of the second clock third line CKB3, and a first part CKB1a of the second clock first line CKB1. FIG. 22 In some embodiments, as shown in FIG. 6, the display panel 2 includes an active layer 216 including an active part T11jA of the first pull-up control transistor T11j, an active part T12jA of the second pull-up control transistor T12j, an active part T81jA of the third pull-up control transistor T81j, an active part T21jA of the first pull-up transistor T21j, an active part T22jA of the second pull-up transistor T22j, an active part T23jA of the third pull-up transistor T23j, an active part T31jA of the first pull-down transistor T31j, an active part T32jA of the second pull-down transistor T32j, an active part T33jA of the third pull-down transistor T33j, an active part T41jA of the fourth pull-down transistor T41j, an active part T42jA of the first pull-down sustain transistor T42j, an active part T51jA of the first inverting transistor T51j, an active part T52jA of the second inverting transistor T52j, an active part T53jA of the third inverting transistor T53j, an active part T54jA of the fourth inverting transistor T54j, an active part T55jA of the fifth inverting transistor T55j, an active part T43jA of the first reset transistor T43j, an active part T71jA of the first negative bias prevention transistor T71j, an active part T72jA of the second negative bias prevention transistor T72j, an active part T73jA of the third negative bias prevention transistor T73j, an active part T74jA of the fourth negative bias prevention transistor T74j, an active part T75jA of the fifth negative bias prevention transistor T75j, an active part T76jA of the sixth negative bias prevention transistor T76j, an active part T77jA of the seventh negative bias prevention transistor T77j, an active part T78jA of the eighth negative bias prevention transistor T78j, an active part T79jA of the ninth negative bias prevention transistor T79j, and an active part T80jA of the tenth negative bias prevention transistor T80j.

[0203] FIG. 19 FIG. 23 In some embodiments, as shown in FIG. 6, the display panel 2 includes an active layer 216 including an active part T11jA of the first pull-up control transistor T11j, an active part T12jA of the second pull-up control transistor T12j, an active part T81jA of the third pull-up control transistor T81j, an active part T21jA of the first pull-up transistor T21j, an active part T22jA of the second pull-up transistor T22j, an active part T23jA of the third pull-up transistor T23j, an active part T31jA of the first pull-down transistor T31j, an active part T32jA of the second pull-down transistor T32j, an active part T33jA of the third pull-down transistor T33j, an active part T41jA of the fourth pull-down transistor T41j, an active part T42jA of the first pull-down sustain transistor T42j, an active part T51jA of the first inverting transistor T51j, an active part T52jA of the second inverting transistor T52j, an active part T53jA of the third inverting transistor T53j, an active part T54jA of the fourth inverting transistor T54j, an active part T55jA of the fifth inverting transistor T55j, an active part T43jA of the first reset transistor T43j, an active part T71jA of the first negative bias prevention transistor T71j, an active part T72jA of the second negative bias prevention transistor T72j, an active part T73jA of the third negative bias prevention transistor T73j, an active part T74jA of the fourth negative bias prevention transistor T74j, an active part T75jA of the fifth negative bias prevention transistor T75j, an active part T76jA of the sixth negative bias prevention transistor T76j, an active part T77jA of the seventh negative bias prevention transistor T77j, an active part T78jA of the eighth negative bias prevention transistor T78j, an active part T79jA of the ninth negative bias prevention transistor T79j, and an active part T80jA of the tenth negative bias prevention transistor T80j.

[0204] ​​​The active portions T81jA of the third pull-up control transistor T81j, the first pull-up control transistor T11jA, the second pull-up control transistor T12jA, and the first reset transistor T43jA are sequentially arranged along the second direction. The active portions T51jA of the first inverting transistor T51j, the second inverting transistor T52jA, the first anti-negative bias transistor T71jA, the first pull-down transistor T31jA, the first pull-down holding transistor T42jA, and the fourth pull-down transistor T41jA are sequentially arranged along the second direction. The active portion T53jA of the third inverting transistor T53jA is also sequentially arranged along the second direction. A. The active portions T54jA of the fourth inverting transistor T54j and the active portions T55jA of the fifth inverting transistor T55j are arranged sequentially along the second direction. The active portions T32jA of the second pull-down transistor T32j and the active portions T33jA of the third pull-down transistor T33j are arranged sequentially along the second direction. The active portions T81jA of the third pull-up control transistor T81j, the active portions T53jA of the third inverting transistor T53j, the active portions T52jA of the second inverting transistor T52j, the active portions T21jA of the first pull-up transistor T21j, the active portions T32jA of the second pull-down transistor T32j, the active portions T22jA of the second pull-up transistor T22j, and the active portions T23jA of the third pull-up transistor T23j are arranged sequentially along the first direction.

[0205] Specifically, such as FIG. 19 to FIG. 23 As shown, the active portion T81jA of the third pull-up control transistor T81j includes the active portion T81j1A of the first pull-up control sub-transistor T81j1 and the active portion T81j2A of the second pull-up control sub-transistor T81j2. The active portion T81j1A of the first pull-up control sub-transistor T81j1 and the active portion T81j2A of the second pull-up control sub-transistor T81j2 are arranged sequentially along the second direction.

[0206] Specifically, such as FIG. 19 to FIG. 23 As shown, the active portion T41jA of the fourth pull-down transistor T41j includes the active portion T41j1A of the first pull-down sub-transistor T41j1 and the active portion T41j2A of the second pull-down sub-transistor T41j2, which are arranged along a second direction.

[0207] Specifically, such as FIG. 23As shown, the active part T42jA of the first pull-down maintaining transistor T42j includes an active part T42j1A of a first pull-down maintaining sub-transistor T42j1 and an active part T42j2A of a second pull-down maintaining sub-transistor T42j2, and the active part T42j1A of the first pull-down maintaining sub-transistor T42j1 and the active part T42j2A of the second pull-down maintaining sub-transistor T42j2 are arranged along the second direction.

[0208] Specifically, as shown in FIG. 6, the active part T43jA of the first reset transistor T43j includes an active part T43j1A of a first reset sub-transistor T43j1 and an active part T43j1A of a second reset sub-transistor T43j2, and the active part T43j1A of the first reset sub-transistor T43j1 and the active part T43j1A of the second reset sub-transistor T43j2 are arranged along the second direction. FIG. 19 to FIG. 23

[0209] Specifically, as shown in FIG. 6, the active part T43jA of the first reset transistor T43j includes an active part T43j1A of a first reset sub-transistor T43j1 and an active part T43j1A of a second reset sub-transistor T43j2, and the active part T43j1A of the first reset sub-transistor T43j1 and the active part T43j1A of the second reset sub-transistor T43j2 are arranged along the second direction. FIG. 23

[0210] Specifically, as shown in FIG. 6, the active part T43jA of the first reset transistor T43j includes an active part T43j1A of a first reset sub-transistor T43j1 and an active part T43j1A of a second reset sub-transistor T43j2, and the active part T43j1A of the first reset sub-transistor T43j1 and the active part T43j1A of the second reset sub-transistor T43j2 are arranged along the second direction. FIG. 19 to FIG. 23

[0211] Specifically, in order to facilitate identification of each sub-transistor, each sub-transistor is identified in the active layer of the display panel. It can be understood that other electrodes of each sub-transistor can be determined according to the position of the active part of each sub-transistor.

[0212] In some embodiments, as shown in FIG. 6, the active part T51jA of the first inverting transistor T51j includes an active part T51j1A of a first inverting sub-transistor T51j1 and an active part T51j2A of a second inverting sub-transistor T51j2, and the active part T51j1A of the first inverting sub-transistor T51j1 and the active part T51j2A of the second inverting sub-transistor T51j2 are arranged along the first direction. FIG. 23 , FIG. 19 to FIG. 23 ​​​As shown, the display panel 2 includes a gate layer 218, which includes a second portion VST1b of the first reset control line VST1, a second portion VGH1b of the first high potential signal line VGH1, a second portion VGL1b of the first low potential signal line VGL1, a second portion LCb of the low frequency signal line LC, a second portion CKAb of the first clock signal line CKA, a second plate C11b of the first sub capacitor C11, a second plate C12b of the second sub capacitor C12, a second portion CKBib of the first group of sub lines CKBi, a second plate of the third sub capacitor C13, a second portion CKBjb of the second group of sub lines CKBj, and a second plate C14b of the fourth sub capacitor C14, a gate T11jG of the first pull-up control transistor T11j, a gate T12jG of the second pull-up control transistor T12j, a gate T81jG of the third pull-up control transistor T81j, a gate T21jG of the first pull-up transistor T21j, a gate T22jG of the second pull-up transistor T22j, a gate T23jG of the third pull-up transistor T23j, a gate T31jG of the first pull-down transistor T31j, a gate T32jG of the second pull-down transistor T32j, a gate T33jG of the third pull-down transistor T33j, a gate T41jG of the fourth pull-down transistor T41j, a gate T42jG of the first pull-down sustain transistor T42j, a gate T51jG of the first inverting transistor T51j, a gate T52jG of the second inverting transistor T52j, a gate T53jG of the third inverting transistor T53j, a gate T54jG of the fourth inverting transistor T54j, a gate T55jG of the fifth inverting transistor T55j, a gate T43jG of the first reset transistor T43j, a gate T71jG of the first negative bias prevention transistor T71j;

[0213] In this configuration, the second plates C11b of the first sub-capacitor C11 and C12b of the second sub-capacitor C12 are disposed along a second direction on both sides of the gate T21jG of the first pull-up transistor T21j; the second plate of the third sub-capacitor C13 is disposed along a second direction with the gate T22jG of the second pull-up transistor T22j; and the second plates C13b and C14b of the fourth sub-capacitor C14 are disposed along a second direction with the gate T23jG of the third pull-up transistor T23j. The gate T81jG of the third pull-up control transistor T81j and the gate of the first pull-up control transistor T11j are also disposed along a second direction. The gates of the first and second pull-up control transistors T11jG, T12jG, and T43jG are arranged sequentially along the second direction. The gates of the first and second inverting transistors T51jG, T52jG, T71jG, T31jG, T31jG, T42jG, and T43jG are arranged sequentially along the second direction. The gates of the first and second inverting transistors T51jG, T52jG, T71jG, T31jG, T42jG, T42jG, and T41jG are arranged sequentially along the second direction. The gate of the third inverting transistor T11jG, T12jG, T43 ... The gates T53jG of the fourth inverting transistor T54j and the fifth inverting transistor T55j are sequentially arranged along the second direction. The gates T32jG of the second pull-down transistor T32j and the gates T33jG of the third pull-down transistor T33j are sequentially arranged along the second direction. The second part VST1b of the first reset control line VST1, the second part VGH1b of the first high-potential signal line VGH1, the gate T81jG of the third pull-up control transistor T81j, the gate T53jG of the third inverting transistor T53j, and the gate of the second inverting transistor T33j are sequentially arranged along the second direction. The gate T52jG of phase transistor T52j, the second part VGL1b of the first low-potential signal line VGL1, the second part LCb of the low-frequency signal line LC, the second part CKAb of the first clock signal line CKA, the gate T21jG of the first pull-up transistor T21j, the gate T32jG of the second pull-down transistor T32j, the second part CKBib of the first group of sub-lines CKBi, the gate T22jG of the second pull-up transistor T22j, the second part CKBjb of the second group of sub-lines CKBj, and the gate T23jG of the third pull-up transistor T23j are arranged sequentially along the first direction.

[0214] Specifically, such as FIG. 23 As shown, the second part CKAAb of the first clock signal line CKA includes the second part of the fourth line CKA4 of the first clock, the second part CKA3b of the third line CKA3 of the first clock, the second part CKA2b of the second line CKA2 of the first clock, and the second part CKA1b of the first line CKA1 of the first clock, arranged sequentially along the first direction.

[0215] Specifically, as shown in FIG. 8, the second part CKBib of the first group of sub-lines CKBi includes, in sequence along the first direction, a second part CKB7b of the second clock seventh line CKB7, a second part CKB5b of the second clock fifth line CKB5, a second part CKB3b of the second clock third line CKB3, and a second part CKB1b of the second clock first line CKB1. FIG. 23

[0216] Specifically, as shown in FIG. 8, the second part CKBib of the first group of sub-lines CKBi includes, in sequence along the first direction, a second part CKB7b of the second clock seventh line CKB7, a second part CKB5b of the second clock fifth line CKB5, a second part CKB3b of the second clock third line CKB3, and a second part CKB1b of the second clock first line CKB1. FIG. 23

[0217] Specifically, as shown in FIG. 8, the second part CKBib of the first group of sub-lines CKBi includes, in sequence along the first direction, a second part CKB7b of the second clock seventh line CKB7, a second part CKB5b of the second clock fifth line CKB5, a second part CKB3b of the second clock third line CKB3, and a second part CKB1b of the second clock first line CKB1. FIG. 23

[0218] Specifically, as shown in FIG. 8, the second part CKBib of the first group of sub-lines CKBi includes, in sequence along the first direction, a second part CKB7b of the second clock seventh line CKB7, a second part CKB5b of the second clock fifth line CKB5, a second part CKB3b of the second clock third line CKB3, and a second part CKB1b of the second clock first line CKB1. FIG. 23

[0219] Specifically, as shown in FIG. 8, the second part CKBib of the first group of sub-lines CKBi includes, in sequence along the first direction, a second part CKB7b of the second clock seventh line CKB7, a second part CKB5b of the second clock fifth line CKB5, a second part CKB3b of the second clock third line CKB3, and a second part CKB1b of the second clock first line CKB1. FIG. 23

[0220] Specifically, as shown in FIG. 8, the second part CKBib of the first group of sub-lines CKBi includes, in sequence along the first direction, a second part CKB7b of the second clock seventh line CKB7, a second part CKB5b of the second clock fifth line CKB5, a second part CKB3b of the second clock third line CKB3, and a second part CKB1b of the second clock first line CKB1. FIG. 6 ​​​​​As shown, the gate T43jG of the first reset transistor T43j includes the gate T43j1G of the first reset sub-transistor T43j1 and the gate T43j1G of the second reset sub-transistor T43j2, which are arranged along the second direction.

[0221] In particular, as shown in FIG. 5A, the gate T51jG of the first inverting transistor T51j includes the gate T51j1G of the first inverting sub-transistor T51j1 and the gate T51j2G of the second inverting sub-transistor T51j2, which are arranged along the first direction. FIG. 8 to FIG. 12

[0222] In particular, as shown in FIG. 5A, the gate T51jG of the first inverting transistor T51j includes the gate T51j1G of the first inverting sub-transistor T51j1 and the gate T51j2G of the second inverting sub-transistor T51j2, which are arranged along the first direction. FIG. 24 to FIG. 28

[0223] In some embodiments, as shown in FIG. 5A, the gate T71jG of the first negative bias prevention transistor T71j includes the gate T71j1G of the first negative bias prevention sub-transistor T71j1 and the gate T71j2G of the second negative bias prevention sub-transistor T71j2, which are arranged along the first direction. FIG. 6 FIG. 8 to FIG. 12 ​​​As shown, the display panel 2 includes a first source-drain layer 221, the first source-drain layer 221 including a third portion VST1c of the first reset control line VST1, a third portion VGH1c of the first high potential signal line VGH1, a third portion VGL1c of the first low potential signal line VGL1, a third portion LCc of the low frequency signal line LC, a third portion CKAc of the first clock signal line CKA, a second portion C11a2 of the first plate C11a of the first sub capacitor C11, a second portion C12a2 of the first plate C12a of the second sub capacitor C12, a third portion CKBic of the first group of sub lines CKBi, a second portion C13a2 of the first plate C13a of the third sub capacitor C13, a third portion CKBjc of the second group of sub lines CKBj, and a second portion C14a2 of the first plate C14a of the fourth sub capacitor C14, a first electrode T11jS of the first pull-up control transistor T11j, a first electrode T12jS of the second pull-up control transistor T12j, a first electrode T81jS of the third pull-up control transistor T81j, a first electrode T21jS of the first pull-up transistor T21j, a first electrode T22jS of the second pull-up transistor T22j, a first electrode T23jS of the third pull-up transistor T23j, a first electrode T31jS of the first pull-down transistor T31j, a first electrode T32jS of the second pull-down transistor T32j, a first electrode T33jS of the third pull-down transistor T33j, a first electrode T41jS of the fourth pull-down transistor T41j, a first electrode T42jS of the first pull-down sustain transistor T42j, a first electrode T51jS of the first inverting transistor T51j, a first electrode T52jS of the second inverting transistor T52j, a first electrode T53jS of the third inverting transistor T53j, a first electrode T54jS of the fourth inverting transistor T54j, a first electrode T55jS of the fifth inverting transistor T55j, a first electrode T43jS of the first reset transistor T43j, a first electrode T71jS of the first negative bias prevention transistor T71j, a second electrode T11jD of the first pull-up control transistor T11j, a second electrode T12jD of the second pull-up control transistor T12j, a second electrode T81jD of the third pull-up control transistor T81j, a second electrode T21jD of the first pull-up transistor T21j, a second electrode T22jD of the second pull-up transistor T22j, a second electrode T23jD of the third pull-up transistor T23j, a second electrode T31jD of the first pull-down transistor T31j, a second electrode T32jD of the second pull-down transistor T32j, a second electrode T33jD of the third pull-down transistor T33j, a second electrode T41jD of the fourth pull-down transistor T41j, a second electrode T42jD of the first pull-down sustain transistor T42j, a second electrode T51jD of the first inverting transistor T51j, a second electrode T52jD of the second inverting transistor T52j,the second electrode T53jD of the third inverter transistor T53j, the second electrode T54jD of the fourth inverter transistor T54j, the second electrode T55jD of the fifth inverter transistor T55j, the second electrode T43jD of the first reset transistor T43j, the second electrode T71jD of the first negative bias prevention transistor T71j,

[0224] The second part C11a2 of the first plate C11a of the first sub-capacitor C11 and the second part C12a2 of the first plate C12a of the second sub-capacitor C12 are arranged on both sides of the first electrode T21jS of the first pull-up transistor T21j along the second direction, the second part C13a2 of the first plate C13a of the third sub-capacitor C13 and the first electrode T22jS of the second pull-up transistor T22j are arranged along the second direction, and the second part C14a2 of the first plate C14a of the fourth sub-capacitor C14 and the first electrode T23jS of the third pull-up transistor T23j are arranged along the second direction; the first electrode T81jS of the third pull-up control transistor T81j, the first electrode T11jS of the first pull-up control transistor T11j, the first electrode T12jS of the second pull-up control transistor T12j, and the first electrode T43jS of the first reset transistor T43j are sequentially arranged along the second direction, the first electrode T51jS of the first inverter transistor T51j, the first electrode T52jS of the second inverter transistor T52j, the first electrode T71jS of the first negative bias prevention transistor T71j, the first electrode T31jS of the first pull-down transistor T31j, the first electrode T42jS of the first pull-down maintenance transistor T42j, and the first electrode T41jS of the fourth pull-down transistor T41j are sequentially arranged along the second direction, the first electrode T53jS of the third inverter transistor T53j and the first electrode T54jS of the fourth inverter transistor T54j are sequentially arranged along the second direction, the first electrode T32jS of the second pull-down transistor T32j and the first electrode T33jS of the third pull-down transistor T33j are sequentially arranged along the second direction, the third part VST1c of the first reset control line VST1, the third part VGH1c of the first high-potential signal line VGH1, the first electrode T81jS of the third pull-up control transistor T81j, the first electrode T53jS of the third inverter transistor T53j, the first electrode T52jS of the second inverter transistor T52j, the third part VGL1c of the first low-potential signal line VGL1, the third part LCc of the low-frequency signal line LC, the third part CKAc of the first clock signal line CKA, the first electrode T21jS of the first pull-up transistor T21j, the first electrode T32jS of the second pull-down transistor T32j, the third part CKBic of the first group of sub-lines CKBi, the first electrode T22jS of the second pull-up transistor T22j, the third part CKBjc of the second group of sub-lines CKBj, and the first electrode T23jS of the third pull-up transistor T23j are sequentially arranged along the first direction.

[0225] Specifically, in the circuit diagrams of this application embodiment, to illustrate the connection relationship of each transistor, each transistor has a gate, a first electrode, and a second electrode. However, in actual design, to reduce the space occupied by the transistors, the electrodes of some transistors may be formed using the same structure. For example, the first electrode of the first pull-up control sub-transistor T81j1 and the second electrode T81j2D of the second pull-up control sub-transistor T81j2 may be formed using the same structure. Therefore, only the second electrode T81j2D of the second pull-up control sub-transistor T81j2 is shown in the diagram. It can be understood that this structure is also the first electrode of the first pull-up control sub-transistor T81j1. In another example, the first electrode T54jS of the fourth inverting transistor T54j and the first electrode T55jS of the fifth inverting transistor T55j share the same structure. Therefore, only the first electrode T54jS of the fourth inverting transistor T54j is shown in the diagram. It can be understood that this structure is also the first electrode T55jS of the fifth inverting transistor T55j. Similarly, the structure of the electrodes of other transistors can be determined.

[0226] Specifically, such as FIG. 24 to FIG. 28 As shown, the first part of the first plate of the first capacitor C1 is connected to the second part of the first plate of the first capacitor C1; the second part C11a2 of the first plate C11a of the first sub-capacitor C11 is connected to the first part C11a1 of the first plate C11a of the first sub-capacitor C11; the second part C12a2 of the first plate C12a of the second sub-capacitor C12 is connected to the first part C12a1 of the first plate C12a of the second sub-capacitor C12; the second part C13a2 of the first plate C13a of the third sub-capacitor C13 is connected to the first part C13a1 of the first plate C13a of the third sub-capacitor C13; and the second part C14a2 of the first plate C14a of the fourth sub-capacitor C14 is connected to the first part C14a1 of the first plate C14a of the fourth sub-capacitor C14.

[0227] Specifically, such as FIG. 6As shown in the figure, the third part VST1c of the first reset control line VST1 is connected with the second part VST1b of the first reset control line VST1 and the first part VST1a of the first reset control line VST1, the third part VGH1c of the first high potential signal line VGH1 is connected with the second part VGH1b of the first high potential signal line VGH1 and the first part VGH1a of the first high potential signal line VGH1, the third part VGL1c of the first low potential signal line VGL1 is connected with the second part VGL1b of the first low potential signal line VGL1 and the first part VGL1a of the first low potential signal line VGL1, the third part LCC of the low frequency signal line LC is connected with the second part LCb of the low frequency signal line LC and the first part LCa of the low frequency signal line LC, the third part CKAc of the first clock signal line CKA is connected with the second part CKAb of the first clock signal line CKA and the first part CKAa of the first clock signal line CKA, the third part CKBic of the first group of sub-lines CKBi is connected with the second part CKBib of the first group of sub-lines CKBi and the first part CKBia of the first group of sub-lines CKBi, the third part CKBjc of the second group of sub-lines CKBj is connected with the second part CKBjb of the second group of sub-lines CKBj and the first part CKBja of the second group of sub-lines CKBj.

[0228] Specifically, as shown in the figure, FIG. 24 to FIG. 28 the third part CKAc of the first clock signal line CKA includes the third part CKA4c of the first clock fourth line CKA4, the third part CKA3c of the first clock third line CKA3, the third part CKA2c of the first clock second line CKA2, and the third part CKA1c of the first clock first line CKA1 arranged in the first direction in sequence.

[0229] Specifically, as shown in the figure, FIG. 6 the third part CKA1c of the first clock first line CKA1 is connected with the second part CKA1b of the first clock first line CKA1 and the first part CKA1a of the first clock first line CKA1, the third part CKA2c of the first clock second line CKA2 is connected with the second part CKA2b of the first clock second line CKA2 and the first part CKA2a of the first clock second line CKA2, the third part CKA3c of the first clock third line CKA3 is connected with the second part CKA3b of the first clock third line CKA3 and the first part CKA3a of the first clock third line CKA3, and the third part CKA4c of the first clock fourth line CKA4 is connected with the second part of the first clock fourth line CKA4 and the first part CKA4a of the first clock fourth line CKA4.

[0230] Specifically, as shown in the figure, FIG. 8 to FIG. 12As shown, the third part of the first group of sub-lines CKBi, CKBic, includes the third part of the seventh line of the second clock, CKB7c, the third part of the fifth line of the second clock, CKB5c, the third part of the third line of the second clock, CKB3c, and the third part of the first line of the second clock, CKB1c, arranged sequentially along the first direction.

[0231] Specifically, such as FIG. 24 to FIG. 28 As shown, the third part CKB1c of the first line of the second clock CKB1 is connected to the second part CKB1b of the first line of the second clock CKB1 and the first part CKB1a of the first line of the second clock CKB1. The third part CKB3c of the third line of the second clock CKB3 is connected to the second part CKB3b of the third line of the second clock CKB3 and the first part CKB3a of the third line of the second clock CKB3. The third part CKB5c of the fifth line of the second clock CKB5 is connected to the second part CKB5b of the fifth line of the second clock CKB5 and the first part CKB5a of the fifth line of the second clock CKB5. The third part CKB7c of the seventh line of the second clock CKB7 is connected to the second part CKB7b of the seventh line of the second clock CKB7 and the first part CKB7a of the seventh line of the second clock CKB7.

[0232] Specifically, such as FIG. 6 As shown, the third part of the second group of sub-lines CKBj, CKBjc, includes the third part of the eighth line of the second clock, CKB8c, the third part of the sixth line of the second clock, CKB6c, the third part of the fourth line of the second clock, CKB4c, and the third part of the second line of the second clock, CKB2, which are arranged sequentially along the first direction.

[0233] Specifically, such as FIG. 8 to FIG. 12 As shown, the third part of the second clock line CKB2 is connected to the second part CKB2b of the second clock line CKB2 and the first part CKB2a of the second clock line CKB2; the third part CKB4c of the second clock line CKB4 is connected to the second part CKB4b of the second clock line CKB4 and the first part CKB4a of the second clock line CKB4; the third part CKB6c of the second clock line CKB6 is connected to the second part CKB6b of the second clock line CKB6 and the first part CKB6a of the second clock line CKB6; and the third part CKB8c of the second clock line CKB8 is connected to the second part CKB8b of the second clock line CKB8 and the first part CKB8a of the second clock line CKB8.

[0234] Specifically, such as ​As shown in FIG. 8, the first source-drain layer 221 includes a first electrode of a first pull-up control sub-tube T81j1, a second electrode T81j1D of the first pull-up control sub-tube T81j1, a first electrode T81j2S of a second pull-up control sub-tube T81j2, a second electrode T81j2D of the second pull-up control sub-tube T81j2, and the second electrode T81j2D of the second pull-up control sub-tube T81j2, the first electrode T81j2S of the second pull-up control sub-tube T81j2, and the second electrode T81j1D of the first pull-up control sub-tube T81j1 are sequentially arranged along the second direction.

[0235] Specifically, as shown in FIG. 6, ​ As shown in FIG. 6, the first source-drain layer 221 includes a first electrode T41j1S of a first pull-down sub-tube T41j1, a second electrode T41j1D of the first pull-down sub-tube T41j1, a first electrode T41j2S of a second pull-down sub-tube T41j2, a second electrode T41j2D of the second pull-down sub-tube T41j2, and the second electrode T41j2D of the second pull-down sub-tube T41j2, the first electrode T41j2S of the second pull-down sub-tube T41j2, and the second electrode T41j1D of the first pull-down sub-tube T41j1 are sequentially arranged along the second direction.

[0236] Specifically, as shown in FIG. 6, ​ As shown in FIG. 6, the first source-drain layer 221 includes a first electrode T42j1S of a first pull-down maintenance sub-tube T42j1, a second electrode of the first pull-down maintenance sub-tube T42j1, a first electrode T42j2S of a second pull-down maintenance sub-tube T42j2, a second electrode T42j2D of the second pull-down maintenance sub-tube T42j2, and the second electrode T42j2D of the second pull-down maintenance sub-tube T42j2, the first electrode T42j2S of the second pull-down maintenance sub-tube T42j2, and the first electrode T42j1S of the first pull-down maintenance sub-tube T42j1 are sequentially arranged along the second direction.

[0237] Specifically, as shown in FIG. 6, ​ As shown in FIG. 6, the first source-drain layer 221 includes a first electrode T43j1S of a first reset sub-tube T43j1, a second electrode T43j1D of the first reset sub-tube T43j1, a first electrode of a second reset sub-tube T43j2, a second electrode T43j1D of the second reset sub-tube T43j2, and the second electrode T43j1D of the second reset sub-tube T43j2, the first electrode of the second reset sub-tube T43j2, and the second electrode T43j1D of the first reset sub-tube T43j1 are sequentially arranged along the second direction.

[0238] Specifically, as shown in FIG. 6, ​As shown, the first source-drain layer 221 includes a first electrode T51j1S of the first inverter sub-tube T51j1, a second electrode T51j1D of the first inverter sub-tube T51j1, a first electrode of the second inverter sub-tube T51j2, and a second electrode T51j2D of the second inverter sub-tube T51j2, which are sequentially arranged along the first direction.

[0239] Specifically, as shown in FIG. 6A, the first source-drain layer 221 includes a first electrode of the first negative-bias prevention sub-tube T71j1, a second electrode T71j1D of the first negative-bias prevention sub-tube T71j1, a first electrode T71j2S of the second negative-bias prevention sub-tube T71j2, and a second electrode T71j2D of the second negative-bias prevention sub-tube T71j2, which are sequentially arranged along the first direction. ​

[0240] Specifically, the first plate of the first capacitor C1 includes a first portion of the first plate of the first capacitor C1 and a second portion of the first plate of the first capacitor C1. The first plate C11a of the first sub-capacitor C11 includes a first portion C11a1 of the first plate C11a of the first sub-capacitor C11 and a second portion C11a2 of the first plate C11a of the first sub-capacitor C11; the first plate C12a of the second sub-capacitor C12 includes a first portion C12a1 of the first plate C12a of the second sub-capacitor C12 and a second portion C12a2 of the first plate C12a of the second sub-capacitor C12; the first plate C13a of the third sub-capacitor C13 includes a first portion C13a1 of the first plate C13a of the third sub-capacitor C13 and a second portion C13a2 of the first plate C13a of the third sub-capacitor C13; and the first plate C14a of the fourth sub-capacitor C14 includes a first portion C14a1 of the first plate C14a of the fourth sub-capacitor C14 and a second portion C14a2 of the first plate C14a of the fourth sub-capacitor C14.

[0241] In some embodiments, as shown in FIG. 6A, the first source-drain layer 221 includes a first electrode of the first inverter sub-tube T51j1, a second electrode T51j1D of the first inverter sub-tube T51j1, a first electrode of the second inverter sub-tube T51j2, and a second electrode T51j2D of the second inverter sub-tube T51j2, which are sequentially arranged along the first direction. ​ , ​ , ​ ​As shown in the first direction, at least one of the second reset control line VST2 and the third clock signal line CKC is arranged between the first type of gate circuit 22a and the third type of gate circuit 22c. By arranging at least one of the second reset control line VST2 and the third clock signal line CKC between the first type of gate circuit 22a and the third type of gate circuit 22c, the length of the connection line required to be arranged when the signal line and the corresponding transistor are connected can be reduced, the signal line does not need to be arranged outside the transistor area and then extended into the transistor area, the space occupied by the signal line outside the transistor area and the space occupied by the signal line inside the transistor area can be reduced, the horizontal space occupied by the signal line connected to the second type of gate circuit 22b can be reduced, the horizontal space occupied by the second type of gate circuit 22b can be reduced, and the frame of the display panel 2 can be reduced.

[0242] In some embodiments, as shown in the first direction, ​ , ​ , ​ As shown, the second type of gate circuit 22b includes a second reset module 327, the second reset module 327 is electrically connected with a second reset control line VST2, and the second reset control line VST2 is arranged between the first type of gate circuit 22a and the second reset module 327. By arranging the second reset control line VST2 between the first type of gate circuit 22a and the second reset module 327, the horizontal space occupied by the second reset control line VST2 can be reduced, the horizontal space occupied by the second type of gate circuit 22b can be reduced, and the frame of the display panel 2 can be reduced.

[0243] In some embodiments, as shown in the first direction, ​ , ​ As shown, the second type of gate circuit 22b includes a second pull-up module 322, and the second pull-up module 322 includes a fourth pull-up transistor T21i, and the fourth pull-up transistor T21i is electrically connected with the third clock signal line CKC.

[0244] Among them, in the first direction, the third clock signal line CKC is arranged between the second reset module 327 and the fourth pull-up transistor T21i. By arranging the third clock signal line CKC between the second reset module 327 and the fourth pull-up transistor T21i, the horizontal space occupied by the third clock signal line CKC can be reduced, the horizontal space occupied by the first type of gate circuit 22a can be reduced, and the frame can be reduced.

[0245] In some embodiments, as shown in the first direction, ​ , ​ , ​As shown in the first direction, at least one of the second reset control line VST2 and the third clock signal line CKC is arranged between the first type of gate circuit 22a and the third type of gate circuit 22c. By arranging at least one of the second reset control line VST2 and the third clock signal line CKC between the first type of gate circuit 22a and the third type of gate circuit 22c, the length of the connection line required to be arranged when the signal line and the corresponding transistor are connected can be reduced, the signal line does not need to be arranged outside the transistor area and then extended into the transistor area, the space occupied by the signal line outside the transistor area and the space occupied by the signal line inside the transistor area can be reduced, the lateral space occupied by the signal line connected to the second type of gate circuit 22b can be reduced, the lateral space occupied by the second type of gate circuit 22b can be reduced, and the frame of the display panel 2 can be reduced.

[0246] In some embodiments, as shown in the first direction, ​ , ​ , Figures 24 to 28 As shown, the second type of gate circuit 22b includes a second reset module 327, the second reset module 327 is electrically connected with a second reset control line VST2, and the second reset control line VST2 is arranged between the first type of gate circuit 22a and the second reset module 327. By arranging the second reset control line VST2 between the first type of gate circuit 22a and the second reset module 327, the lateral space occupied by the second reset control line VST2 can be reduced, the lateral space occupied by the second type of gate circuit 22b can be reduced, and the frame of the display panel 2 can be reduced.

[0247] In some embodiments, as shown in the first direction, Figure 6 , Figures 24 to 28 As shown, the second type of gate circuit 22b includes a second pull-up module 322, and the second pull-up module 322 includes a fourth pull-up transistor T21i, and the fourth pull-up transistor T21i is electrically connected with the third clock signal line CKC.

[0248] In the first direction, the third clock signal line CKC is arranged between the second reset module 327 and the fourth pull-up transistor T21i. By arranging the third clock signal line CKC between the second reset module 327 and the fourth pull-up transistor T21i, the lateral space occupied by the third clock signal line CKC can be reduced, the lateral space occupied by the second type of gate circuit 22b can be reduced, and the frame can be reduced.

[0249] In some embodiments, as shown in the first direction, Figure 6As shown, the second type of gate circuit 22b includes a second pull-up control module 321, a second pull-up module 322, a second pull-down module 323, a second pull-down maintenance module 324, a second inverting module 325, a second negative bias prevention module 326, and a second reset module 327. The second pull-up control module 321 and the second pull-up module 322 are electrically connected to a second pull-up node Q2[n]. The second pull-down module 323 is electrically connected to the second pull-up node Q2[n] and a second signal output end INI[n] of the second type of gate circuit 22b. The second pull-down maintenance module 324 is electrically connected between the second pull-up node Q2[n] and a second low potential signal line VGL2. The second inverting module 325 is electrically connected to the second pull-up node Q2[n], the second low potential signal line VGL2, and a low frequency signal line LC. The second negative bias prevention module 326 is electrically connected between a first high potential signal line VGH1 and the second pull-up node Q2[n]. The second reset module 327 is electrically connected between the second pull-up node Q2[n] and the second low potential signal line VGL2.

[0250] In some embodiments, as shown in Figure 6 、 Figure 24 At least two of the second pull-up control module 321, the second pull-up module 322, the second pull-down module 323, the second pull-down maintenance module 324, the second inverting module 325, the second negative bias prevention module 326, and the second reset module 327 are arranged along a second direction. An included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By arranging at least two of the second pull-up control module 321, the second pull-up module 322, the second pull-down module 323, the second pull-down maintenance module 324, the second inverting module 325, the second negative bias prevention module 326, and the second reset module 327 along the second direction, the transverse space occupied by the second type of gate circuit 22b can be shortened, thereby reducing the transverse space occupied by the gate drive circuit 22 and reducing the frame of the display panel 2.

[0251] Specifically, compared with the transverse arrangement of various modules in the comparative display device, by arranging at least two modules in the second type of gate circuit 22b along the second direction, the transverse space occupied by the second type of gate circuit 22b can be reduced, the transverse space occupied by the gate drive circuit 22 can be reduced, and the frame of the display panel 2 can be reduced.

[0252] In some embodiments, as shown in Figure 6 、 Figure 24As shown, the second pull-up control module 321 and the second reset module 327 are arranged along the second direction. By arranging the second pull-up control module 321 and the second reset module 327 along the second direction, the transverse space occupied by the second pull-up control module 321 and the second reset module 327 can be reduced, the transverse space occupied by the second gate circuit 22b can be reduced, the transverse space occupied by the gate drive circuit 22 can be reduced, and thus the frame of the display panel 2 can be reduced.

[0253] Specifically, as shown in Figure 24 , it can be seen that, in the second direction, the second pull-up control module 321 is arranged above the second reset module 327.

[0254] In some embodiments, as shown in Figure 6 , Figure 24 , the second pull-down module 323, the second pull-down maintenance module 324, and the second inverting module 325 are arranged along the second direction. By arranging the second pull-down module 323, the second pull-down maintenance module 324, and the second inverting module 325 along the second direction, the transverse space occupied by the second gate circuit 22b can be reduced, the transverse space occupied by the gate drive circuit 22 can be reduced, and thus the frame of the display panel 2 can be reduced.

[0255] Specifically, as shown in Figure 24 , it can be seen that, in the second direction, the second inverting module 325 and the second pull-down maintenance module 324 are arranged in sequence, a part of the second pull-down module 323 is arranged between the second inverting module 325 and the second pull-down maintenance module 324, and another part of the second pull-down module 323 is arranged on the side of the second pull-down maintenance module 324 away from the first inverting module 315.

[0256] In some embodiments, as shown in Figure 6 , Figure 24 , a part of the second inverting module 325, the second negative bias prevention module 326, and a part of the second pull-up control module 321 are arranged along the first direction, the part of the second inverting module 325 and another part of the second pull-up control module 321 are arranged along the second direction, and the second negative bias prevention module 326 and another part of the second pull-up control module 321 are arranged along the second direction. By arranging the part of the second inverting module 325, the second negative bias prevention module 326, and the part of the second pull-up control module 321 along the second direction, the transverse space occupied by the gate drive circuit 22 can be further reduced, and thus the frame of the display panel 2 can be reduced.

[0257] Specifically, as shown in Figure 24As shown, it can be seen that the widths of the various parts in the second pull-up control module 321 are different, the part of the second inverting module 325 and the second negative bias prevention module 326 are arranged along the first direction with a part of the second pull-up control module 321, and the part of the second inverting module 325 and the second negative bias prevention module 326 are arranged along the second direction with another part of the second pull-up control module 321.

[0258] In some embodiments, as shown in Figure 6 、 Figures 24 to 28 As shown, the second pull-up control module 321 includes a fourth pull-up control transistor T11i, a fifth pull-up control transistor T12i, and a sixth pull-up control transistor T81i, a gate electrode T11iG of the fourth pull-up control transistor T11i is electrically connected with the second signal output end INI[n-2] of the upper two-stage second type gate electrode circuit 22b, a first electrode T11iS of the fourth pull-up control transistor T11i is electrically connected with the first high potential signal line VGH1, a second electrode T11iD of the fourth pull-up control transistor T11i is electrically connected with a first electrode T12iS of the fifth pull-up control transistor T12i, a gate electrode T12iG of the fifth pull-up control transistor T12i is electrically connected with the second signal output end INI[n-2] of the upper two-stage second type gate electrode circuit 22b, a second electrode T12iD of the fifth pull-up control transistor T12i is electrically connected with the second pull-up node Q2[n], a gate electrode T81iG of the sixth pull-up control transistor T81i is electrically connected with the first high potential signal line VGH1, a first electrode T81iS of the sixth pull-up control transistor T81i is electrically connected with the first high potential signal line VGH1, and a second electrode T81iD of the sixth pull-up control transistor T81i is electrically connected with the second electrode T11iD of the fourth pull-up control transistor T11i.

[0259] In each of the gate driving circuits 22, the sixth pull-up control transistor T81i, the fourth pull-up control transistor T11i, and the fifth pull-up control transistor T12i are arranged along the second direction in sequence. By arranging the sixth pull-up control transistor T81i, the fourth pull-up control transistor T11i, and the fifth pull-up control transistor T12i along the second direction in sequence, the space occupied by the second pull-up control module 321 can be reduced, thereby reducing the frame of the display panel 2.

[0260] In some embodiments, the sixth pull-up control transistor T81i comprises a third pull-up control sub-transistor T81i1 and a fourth pull-up control sub-transistor T81i2, a gate electrode T81i2G of the fourth pull-up control sub-transistor T81i2 and a first electrode T81i2S of the fourth pull-up control sub-transistor T81i2 are electrically connected with the first high potential signal line VGH1, a second electrode T81i2D of the fourth pull-up control sub-transistor T81i2 is electrically connected with a first electrode of the third pull-up control sub-transistor T81i1, a gate electrode T81i1G of the third pull-up control sub-transistor T81i1 is electrically connected with the first high potential signal line VGH1, and a second electrode T81i1D of the third pull-up control sub-transistor T81i1 is electrically connected with a second electrode T11iD of the fourth pull-up control transistor T11i;

[0261] In some embodiments, the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2 are arranged along the second direction. By arranging the sixth pull-up control transistor T81i to comprise the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2, the performance of the sixth pull-up control transistor T81i can be improved, and arranging the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2 along the first direction can reduce the lateral area occupied by the sixth pull-up control transistor T81i and reduce the frame of the display panel 2.

[0262] Specifically, the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2 can be regarded as two independent transistors, or as two sub-transistors of the sixth pull-up control transistor T81i, and the same applies to other sub-transistors. For details, please refer to the above description, which will not be repeated hereinafter.

[0263] Specifically, when a transistor has multiple sub-transistors, the first electrode of the transistor is the electrode connected with the signal line. For example, the sixth pull-up control transistor T81i comprises the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2, and since the first electrode T81i2S of the fourth pull-up control sub-transistor T81i2 is electrically connected with the first high potential signal line VGH1, the first electrode T81iS of the sixth pull-up control transistor T81i is the first electrode T81i2S of the fourth pull-up control sub-transistor T81i2. Similarly, the first electrode of other transistors can be determined.

[0264] Specifically, the multi-stage gate drive circuit 22 comprises a plurality of second-type gate circuits 22b. In the first second-type gate circuit 22b, the gate T11iG of the fourth pull-up control transistor T11i is connected to the start signal line. In other second-type gate circuits 22b, the gate T11iG of the fourth pull-up control transistor T11i and the gate T12iG of the fifth pull-up control transistor T12i are electrically connected to the second signal output end INI[n-2] of the upper two second-type gate circuits 22b, and the first electrode T11iS of the fourth pull-up control transistor T11i and the first electrode T12iS of the fifth pull-up control transistor T12i are electrically connected to the first high-potential signal line VGH1.

[0265] In some embodiments, as shown in FIG. 3, Figure 6 、 Figures 24 to 28 The second pull-down module 323 comprises a fifth pull-down transistor T31i and a sixth pull-down transistor T41i. The gate T31iG of the fifth pull-down transistor T31i is electrically connected to the second pull-down node QB2[n], the first electrode T31iS of the fifth pull-down transistor T31i is electrically connected to the second low-potential signal line VGL2, and the second electrode T31iD of the fifth pull-down transistor T31i is electrically connected to the second signal output end INI[n] of the second-type gate circuit 22b of the current stage. The gate T41iG of the sixth pull-down transistor T41i is electrically connected to the second signal output end INI[n+2] of the second-type gate circuit 22b of the next stage, the first electrode T41iS of the sixth pull-down transistor T41i is electrically connected to the second low-potential signal line VGL2, and the second electrode T41iD of the sixth pull-down transistor T41i is electrically connected to the second pull-up node Q2[n].

[0266] The fifth pull-down transistor T31i and the sixth pull-down transistor T41i are arranged along the second direction. By arranging the fifth pull-down transistor T31i and the sixth pull-down transistor T41i along the second direction, the space occupied by the second pull-down module 323 can be reduced, and the frame of the display panel 2 can be reduced.

[0267] In some embodiments, as shown in FIG. 3, Figure 6 、 Figures 24 to 28As shown, the sixth pull-down transistor T41i includes a third pull-down sub transistor T41i1 and a fourth pull-down sub transistor T41i2, a gate T41i2G of the fourth pull-down sub transistor T41i2 is electrically connected with the second signal output end INI[n+2] of the lower two-stage second-type gate circuit 22b, a first electrode T41i2S of the fourth pull-down sub transistor T41i2 is electrically connected with the second low-potential signal line VGL2, a second electrode T41i2D of the fourth pull-down sub transistor T41i2 is electrically connected with a first electrode T41i1S of the third pull-down sub transistor T41i1 at the second internal node N2[n], a gate T41i1G of the third pull-down sub transistor T41i1 is electrically connected with the second signal output end INI[n+2] of the lower two-stage second-type gate circuit 22b, and a second electrode T41i1D of the third pull-down sub transistor T41i1 is electrically connected with the second pull-up node Q2[n];

[0268] wherein the third pull-down sub transistor T41i1 and the fourth pull-down sub transistor T41i2 are arranged along the second direction. By making the sixth pull-down transistor T41i include the third pull-down sub transistor T41i1 and the fourth pull-down sub transistor T41i2, the performance of the sixth pull-down transistor T41i can be improved, and by arranging the third pull-down sub transistor T41i1 and the fourth pull-down sub transistor T41i2 along the second direction, the lateral area occupied by the sixth pull-down transistor T41i can be reduced, and the frame of the display panel 2 can be reduced.

[0269] In some embodiments, as Figure 6 , Figures 24 to 28As shown, the second inverting module 325 includes a sixth inverting transistor T51i, a seventh inverting transistor T52i, an eighth inverting transistor T53i, a ninth inverting transistor T54i, and a tenth inverting transistor T55i, a gate electrode T51iG of the sixth inverting transistor T51i and a first electrode T51iS of the sixth inverting transistor T51i are electrically connected with the low-frequency signal line LC, a second electrode T51iD of the sixth inverting transistor T51i is electrically connected with a second electrode T52iD of the seventh inverting transistor T52i, a gate electrode T52iG of the seventh inverting transistor T52i is electrically connected with the second pull-up node Q2[n], a first electrode T52iS of the seventh inverting transistor T52i is electrically connected with the second low-potential signal line VGL2, a gate electrode T53iG of the eighth inverting transistor T53i is electrically connected with the second electrode T51iD of the sixth inverting transistor T51i, a first electrode T53iS of the eighth inverting transistor T53i is electrically connected with the low-frequency signal line LC, a second electrode T53iD of the eighth inverting transistor T53i is electrically connected with the second pull-down node QB2[n], a gate electrode T54iG of the ninth inverting transistor T54i is electrically connected with the second pull-up node Q2[n], a first electrode T54iS of the ninth inverting transistor T54i is electrically connected with the second low-potential signal line VGL2, a second electrode T54iD of the ninth inverting transistor T54i is electrically connected with the second pull-down node QB2[n], a gate electrode T55iG of the tenth inverting transistor T55i is electrically connected with the second signal output end INI[n-2] of the upper two-stage second-type gate circuit 22b, a first electrode T55iS of the tenth inverting transistor T55i is electrically connected with the second low-potential signal line VGL2, and a second electrode T55iD of the tenth inverting transistor T55i is electrically connected with the second pull-down node QB2[n].

[0270] In the embodiment, the sixth inverting transistor T51i and the seventh inverting transistor T52i are arranged along the second direction, the eighth inverting transistor T53i, the ninth inverting transistor T54i, and the tenth inverting transistor T55i are arranged along the second direction, and the sixth inverting transistor T51i and the eighth inverting transistor T53i are arranged along the first direction. By arranging the sixth inverting transistor T51i and the seventh inverting transistor T52i along the second direction, the eighth inverting transistor T53i, the ninth inverting transistor T54i, and the tenth inverting transistor T55i along the second direction, and the sixth inverting transistor T51i and the eighth inverting transistor T53i along the first direction, the transverse space occupied by the second inverting module 325 can be reduced, thereby reducing the frame of the display panel 2.

[0271] In some embodiments, as Figure 6 , Figures 24 to 28As shown, the sixth inverting transistor T51i includes a third inverting sub-transistor T51i1 and a fourth inverting sub-transistor T51i2. The gate T51i1G and the first electrode T51i1S of the third inverting sub-transistor T51i1 are electrically connected to the low-frequency signal line LC. The second electrode T51i1D of the third inverting sub-transistor T51i1 is electrically connected to the first electrode of the fourth inverting sub-transistor T51i2. The gate T51i2G of the fourth inverting sub-transistor T51i2 is electrically connected to the low-frequency signal line LC. The second electrode T51i2D of the fourth inverting sub-transistor T51i2 is electrically connected to the second electrode T52iD of the seventh inverting transistor T52i.

[0272] The third inverting sub-transistor T51i1 and the fourth inverting sub-transistor T51i2 are arranged along a first direction. By including the third inverting sub-transistor T51i1 and the fourth inverting sub-transistor T51i2 in the sixth inverting transistor T51i, the performance of the sixth inverting transistor T51i can be improved.

[0273] In some embodiments, such as Figure 6 , Figures 24 to 28 As shown, the eighth inverting transistor T53i and the sixth pull-up control transistor T81i are arranged along the first direction, and the eighth inverting transistor T53i and the fourth pull-up control transistor T11i are arranged along the second direction; thereby reducing the horizontal space occupied by the second inverting module 325 and the second pull-up control module 321, and reducing the bezel of the display panel 2.

[0274] In some embodiments, such as Figure 6 , Figures 24 to 28 As shown, the second pull-down sustaining module 324 includes a second pull-down sustaining transistor T42i. The gate T42iG of the second pull-down sustaining transistor T42i is electrically connected to the second pull-down node QB2[n]. The first electrode T42iS of the second pull-down sustaining transistor T42i is electrically connected to the second low-potential signal line VGL2. The second electrode T42iD of the second pull-down sustaining transistor T42i is electrically connected to the second pull-up node Q2[n].

[0275] In the second direction, the second pull-down holding transistor T42i is disposed between the fifth pull-down transistor T31i and the sixth pull-down transistor T41i. This reduces the lateral space occupied by the second pull-down holding transistor T42i, the fifth pull-down transistor T31i, and the sixth pull-down transistor T41i, thereby reducing the bezel of the display panel 2.

[0276] In some embodiments, such as Figure 6 , Figures 24 to 28As shown, the second pull-down sustaining transistor T42i includes a third pull-down sustaining sub-transistor T42i1 and a fourth pull-down sustaining sub-transistor T42i2. The gate T42i2G of the fourth pull-down sustaining sub-transistor T42i2 is electrically connected to the second pull-down node QB2[n]. The first electrode T42i2S of the fourth pull-down sustaining sub-transistor T42i2 is electrically connected to the second low-potential signal line VGL2. The second electrode T42i2D of the fourth pull-down sustaining sub-transistor T42i2 is electrically connected to the first electrode T42i1S of the third pull-down sustaining sub-transistor T42i1 at the second internal node N2[n]. The gate of the third pull-down sustaining sub-transistor T42i1 is electrically connected to the second pull-down node QB2[n]. The second electrode of the third pull-down sustaining sub-transistor T42i1 is electrically connected to the second pull-up node Q2[n].

[0277] The third pull-down sustaining sub-transistor T42i1 and the fourth pull-down sustaining sub-transistor T42i2 are arranged along the second direction. By including the third pull-down sustaining sub-transistor T42i1 and the fourth pull-down sustaining sub-transistor T42i2 in the second pull-down sustaining transistor T42i, the performance of the second pull-down sustaining transistor T42i can be improved. Furthermore, the arrangement of the third pull-down sustaining sub-transistor T42i1 and the fourth pull-down sustaining sub-transistor T42i2 along the second direction can reduce the lateral space occupied by the second pull-down sustaining transistor T42i, thereby reducing the bezel of the display panel 2.

[0278] In some embodiments, such as Figure 6 , Figures 24 to 28 As shown, the second reset module 327 includes a second reset transistor T43i. The gate T43iG of the second reset transistor T43i is electrically connected to the second reset control line VST2. The first electrode T43iS of the second reset transistor T43i is electrically connected to the second low potential signal line VGL2. The second electrode T43iD of the second reset transistor T43i is electrically connected to the second pull-up node Q2[n].

[0279] The second reset transistor T43i is located on the side of the fifth pull-up control transistor T12i away from the fourth pull-up control transistor T11i. By placing the second reset transistor T43i on the side of the fifth pull-up control transistor T12i away from the fourth pull-up control transistor T11i, the lateral space occupied by the second reset transistor T43i and the second pull-up control module 321 is reduced, thereby reducing the bezel of the display panel 2, and the second reset transistor T43i is easier to connect to the second low-potential signal line VGL2.

[0280] In some embodiments, such as Figure 6 , Figures 24 to 28As shown in the figure, the second reset transistor T43i includes a third reset sub-transistor T43il and a fourth reset sub-transistor T43i2, a gate T43ilG of the fourth reset sub-transistor T43i2 is electrically connected with the second reset control line VST2, a first electrode of the fourth reset sub-transistor T43i2 is electrically connected with the second low potential signal line VGL2, a second electrode T43ilD of the third reset sub-transistor T43il is electrically connected with a first electrode T43ilS of the third reset sub-transistor T43il at the second internal node N2[n], a gate T43ilG of the third reset sub-transistor T43il is electrically connected with the second reset control line VST2, and the second electrode T43ilD of the third reset sub-transistor T43il is electrically connected with the second pull-up node Q2[n];

[0281] Wherein, the third reset sub-transistor T43il and the fourth reset sub-transistor T43i2 are arranged along the second direction. By making the second reset transistor T43i include the third reset sub-transistor T43il and the fourth reset sub-transistor T43i2, the performance of the second reset transistor T43i can be improved, and the third reset sub-transistor T43il and the fourth reset sub-transistor T43i2 are arranged along the second direction, which can reduce the horizontal space occupied by the second reset transistor T43i and reduce the frame of the display panel 2.

[0282] In some embodiments, as shown in the figure, Figure 6 , Figures 24 to 28 As shown in the figure, the second negative bias prevention module 326 includes a second negative bias prevention transistor T61i, a gate T61iG of the second negative bias prevention transistor T61i is electrically connected with the second pull-up node Q2[n], a first electrode T61iS of the second negative bias prevention transistor T61i is electrically connected with the first high potential signal line VGH1, and a second electrode T61iD of the second negative bias prevention transistor T61i is electrically connected with the second internal node N2[n];

[0283] Wherein, the second negative bias prevention transistor T61i is arranged along the first direction between the sixth pull-up control transistor T81i and the eighth inverting transistor T53i, and the second negative bias prevention transistor T61i is arranged along the second direction on a side of the fourth pull-up control transistor Tll i away from the fifth pull-up control transistor T12i. By arranging the second negative bias prevention transistor T61i along the second direction on the side of the fourth pull-up control transistor Tll i away from the fifth pull-up control transistor T12i, the horizontal area occupied by the second negative bias prevention module 326 can be reduced, and the frame of the display panel 2 can be reduced.

[0284] In some embodiments, as shown in the figure, Figure 6 , Figures 24 to 28As shown, the second anti-negative bias transistor T61i includes a third anti-negative bias transistor T61i1 and a fourth anti-negative bias transistor T61i2. The gate T61i2G of the fourth anti-negative bias transistor T61i2 is electrically connected to the second pull-up node Q2[n]. The first electrode T61i2S of the fourth anti-negative bias transistor T61i2 is electrically connected to the first high-potential signal line. The second electrode T61i2D of the fourth anti-negative bias transistor T61i2 is electrically connected to the first electrode of the third anti-negative bias transistor T61i1. The gate T61i1G of the third anti-negative bias transistor T61i1 is electrically connected to the second pull-up node Q2[n]. The second electrode T61i1D of the third anti-negative bias transistor T61i1 is electrically connected to the second internal node N2[n].

[0285] The third anti-negative bias transistor T61i1 and the fourth anti-negative bias transistor T61i2 are arranged along the second direction. By including the third anti-negative bias transistor T61i1 and the fourth anti-negative bias transistor T61i2 in the second anti-negative bias transistor T61i, the performance of the second anti-negative bias transistor T61i can be improved. Furthermore, the arrangement of the third anti-negative bias transistor T61i1 and the fourth anti-negative bias transistor T61i2 along the second direction can reduce the lateral space occupied by the second anti-negative bias transistor T61i, thereby reducing the bezel of the display panel 2.

[0286] In some embodiments, such as Figure 6 , Figures 24 to 28 As shown, the second pull-up module 322 includes a fourth pull-up transistor T21i. The gate T21iG of the fourth pull-up transistor T21i is electrically connected to the second pull-up node Q2[n]. The first electrode T21iS of the fourth pull-up transistor T21i is electrically connected to the third clock signal line CKC. The second electrode T21iD of the fourth pull-up transistor T21i is electrically connected to the second signal output terminal INI[n] of the second type gate circuit 22b of this stage.

[0287] In the first direction, the third clock signal line CKC is arranged adjacent to the fourth pull-up transistor T21i; thus, the third clock signal line CKC does not need to be routed from outside the transistor area to inside the transistor area, and the third clock signal line CKC is arranged adjacent to the transistor it is connected to, with fewer lines, reducing the space occupied by the third clock signal line CKC and reducing the bezel of the display panel 2.

[0288] Specifically, the third clock signal line CKC can include a third clock first line CKC1, a third clock second line CKC2, a third clock third line CKC3 and a third clock fourth line CKC4. Every four second-type gate circuits 22b are connected in a cycle with the four third clock signal lines CKC. For example, the first second-type gate circuit 22b to the fourth second-type gate circuit 22b are connected with the third clock first line CKC1, the third clock second line CKC2, the third clock third line CKC3 and the third clock fourth line CKC4 respectively. The fifth second-type gate circuit 22b to the eighth second-type gate circuit 22b are connected with the third clock first line CKC1, the third clock second line CKC2, the third clock third line CKC3 and the third clock fourth line CKC4 respectively. Similarly, the clock signal lines connected with other second-type gate circuits 22b can be determined.

[0289] Specifically, the above embodiment takes an example of the third clock signal line CKC including four clock lines for illustration, but the embodiment of the present application is not limited thereto. The third clock signal line CKC can include other number of clock lines, for example, eight clock lines.

[0290] In some embodiments, as shown in FIG. 2B, the second-type gate circuit 22b further includes a second capacitor C2. One plate of the second capacitor C2 is electrically connected to the second pull-up node Q2[n], and the other plate of the second capacitor C2 is electrically connected to the second signal output end INI[n] of the second-type gate circuit 22b. Figure 6

[0291] Specifically, the second capacitor C2 includes a first plate C2a and a second plate C2b. The first plate C2a includes a first part C2a1 and a second part C2a2.

[0292] In some embodiments, as shown in FIG. 2B, the second-type gate circuit 22b further includes a second capacitor C2. One plate of the second capacitor C2 is electrically connected to the second pull-up node Q2[n], and the other plate of the second capacitor C2 is electrically connected to the second signal output end INI[n] of the second-type gate circuit 22b. Figure 24 Figure 25 Specifically, as shown in FIG. 2B, the display panel 2 includes a light shielding layer 212. The light shielding layer 212 includes, in sequence along the first direction, a first part VST2a of the second reset control line VST2, the second signal output end INI[n] of the second-type gate circuit 22b, a first part CKCa of the third clock signal line CKC, and a first part C2a1 of the first plate C2a of the second capacitor C2.

[0293] Specifically, as shown in FIG. 2B, the display panel 2 includes a light shielding layer 212. The light shielding layer 212 includes, in sequence along the first direction, a first part VST2a of the second reset control line VST2, the second signal output end INI[n] of the second-type gate circuit 22b, a first part CKCa of the third clock signal line CKC, and a first part C2a1 of the first plate C2a of the second capacitor C2. Figure 25 ​​As shown, the first part CKCa of the third clock signal line CKC includes the first part CKC4a of the fourth clock line CKC4, the first part CKC3a of the third clock line CKC3, the first part CKC2a of the second clock line CKC2, and the first part CKC1a of the first clock line CKC1 arranged in the first direction in sequence.

[0294] In some embodiments, as shown in FIG. 1, the display panel 2 includes a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CKC, a fourth clock signal line CKD, a fifth clock signal line CK5, a sixth clock signal line CK6, a seventh clock signal line CK7, and an eighth clock signal line CK8. Figure 24 、 Figure 26 As shown, the display panel 2 includes an active layer 216, which includes an active part T11iA of a fourth pull-up control transistor T11i, an active part T12iA of a fifth pull-up control transistor T12i, an active part T81iA of a sixth pull-up control transistor T81i, an active part T21iA of a fourth pull-up transistor T21i, an active part T31iA of a fifth pull-up transistor T31i, an active part T41iA of a sixth pull-up transistor T41i, an active part T42iA of a second pull-down maintaining transistor T42i, an active part T51iA of a sixth inverting transistor T51i, an active part T52iA of a seventh inverting transistor T52i, an active part T53iA of an eighth inverting transistor T53i, an active part T54iA of a ninth inverting transistor T54i, an active part T55iA of a tenth inverting transistor T55i, an active part T43iA of a second reset transistor T43i, and an active part T61iA of a second negative bias prevention transistor T61i.

[0295] The active part T81iA of the sixth pull-up control transistor T81i, the active part T11iA of the fourth pull-up control transistor T11i, the active part T12iA of the fifth pull-up control transistor T12i, and the active part T43iA of the second reset transistor T43i are arranged in the second direction in sequence, the active part T51iA of the sixth inverting transistor T51i, the active part T52iA of the seventh inverting transistor T52i, the active part T31iA of the fifth pull-down transistor T31i, the active part T42iA of the second pull-down maintaining transistor T42i, and the active part T41iA of the sixth pull-down transistor T41i are arranged in the second direction in sequence, the active part T53iA of the eighth inverting transistor T53i, the active part T54iA of the ninth inverting transistor T54i, and the active part T55iA of the tenth inverting transistor T55i are arranged in the second direction in sequence, and the active part T81iA of the sixth pull-up control transistor T81i, the active part T61iA of the second negative bias prevention transistor T61i, the active part T53iA of the eighth inverting transistor T53i, the active part T52iA of the seventh inverting transistor T52i, and the active part T21iA of the fourth pull-up transistor T21i are arranged in the first direction in sequence.

[0296] Specifically, as shown in Figure 26 The active part T81iA of the sixth pull-up control transistor T81i includes an active part T81i1A of a third pull-up control sub-transistor T81i1 and an active part T81i2A of a fourth pull-up control sub-transistor T81i2, which are arranged in the second direction in sequence.

[0297] Specifically, as shown in Figure 26 The active part T41iA of the sixth pull-down transistor T41i includes an active part T41i1A of a third pull-down sub-transistor T41i1 and an active part T41i2A of a fourth pull-down sub-transistor T41i2, which are arranged in the second direction.

[0298] Specifically, as shown in Figure 26 The active part T42iA of the second pull-down maintenance transistor T42i includes an active part of a third pull-down maintenance sub-transistor T42i1 and an active part T42i2A of a fourth pull-down maintenance sub-transistor T42i2, which are arranged in the second direction.

[0299] Specifically, as shown in Figure 26 The active part T43iA of the second reset transistor T43i includes an active part T43i1A of a third reset sub-transistor T43i1 and an active part T43i1A of a fourth reset sub-transistor T43i2, which are arranged in the second direction.

[0300] Specifically, as shown in Figure 26 The active part T51iA of the sixth inverter transistor T51i includes an active part T51i1A of a third inverter sub-transistor T51i1 and an active part T51i2A of a fourth inverter sub-transistor T51i2, which are arranged in the first direction.

[0301] Specifically, as shown in Figure 26 The active part T61iA of the second negative bias prevention transistor T61i includes an active part T61i1A of a third negative bias prevention sub-transistor T61i1 and an active part T61i2A of a fourth negative bias prevention sub-transistor T61i2, which are arranged in the second direction.

[0302] In some embodiments, as shown in FIG. 2B, the display panel 2 includes a gate layer 218, which includes a first portion VST2a of the second reset control line VST2, a first portion CKCa of the third clock signal line CKC, a first plate C2a of the second capacitor C2, a gate T11iG of a fourth pull-up control transistor T11i, a gate T12iG of a fifth pull-up control transistor T12i, a gate T81iG of a sixth pull-up control transistor T81i, a gate T21iG of a fourth pull-up transistor T21i, a gate T31iG of a fifth pull-up transistor T31i, a gate T41iG of a sixth pull-up transistor T41i, a gate T42iG of a second pull-down sustain transistor T42i, a gate T51iG of a sixth inverter transistor T51i, a gate T52iG of a seventh inverter transistor T52i, a gate T53iG of an eighth inverter transistor T53i, a gate T54iG of a ninth inverter transistor T54i, a gate T55iG of a tenth inverter transistor T55i, a gate T43iG of a second reset transistor T43i, a gate T61iG of a second negative bias prevention transistor T61i. Figure 24 Figure 27 In some embodiments, as shown in FIG. 2B, the display panel 2 includes a gate layer 218, which includes a first portion VST2a of the second reset control line VST2, a first portion CKCa of the third clock signal line CKC, a first plate C2a of the second capacitor C2, a gate T11iG of a fourth pull-up control transistor T11i, a gate T12iG of a fifth pull-up control transistor T12i, a gate T81iG of a sixth pull-up control transistor T81i, a gate T21iG of a fourth pull-up transistor T21i, a gate T31iG of a fifth pull-up transistor T31i, a gate T41iG of a sixth pull-up transistor T41i, a gate T42iG of a second pull-down sustain transistor T42i, a gate T51iG of a sixth inverter transistor T51i, a gate T52iG of a seventh inverter transistor T52i, a gate T53iG of an eighth inverter transistor T53i, a gate T54iG of a ninth inverter transistor T54i, a gate T55iG of a tenth inverter transistor T55i, a gate T43iG of a second reset transistor T43i, a gate T61iG of a second negative bias prevention transistor T61i.

[0303] In some embodiments, as shown in FIG. 2B, the display panel 2 includes a gate layer 218, which includes a first portion VST2a of the second reset control line VST2, a first portion CKCa of the third clock signal line CKC, a first plate C2a of the second capacitor C2, a gate T11iG of a fourth pull-up control transistor T11i, a gate T12iG of a fifth pull-up control transistor T12i, a gate T81iG of a sixth pull-up control transistor T81i, a gate T21iG of a fourth pull-up transistor T21i, a gate T31iG of a fifth pull-up transistor T31i, a gate T41iG of a sixth pull-up transistor T41i, a gate T42iG of a second pull-down sustain transistor T42i, a gate T51iG of a sixth inverter transistor T51i, a gate T52iG of a seventh inverter transistor T52i, a gate T53iG of an eighth inverter transistor T53i, a gate T54iG of a ninth inverter transistor T54i, a gate T55iG of a tenth inverter transistor T55i, a gate T43iG of a second reset transistor T43i, a gate T61iG of a second negative bias prevention transistor T61i.​

[0304] Specifically, as shown in FIG. 8, the second part CKCb of the third clock signal line CKC includes the second part CKC4b of the third clock fourth line CKC4, the second part CKC3b of the third clock third line CKC3, the second part CKC2b of the third clock second line CKC2, and the second part CKC1b of the third clock first line CKC1 arranged in the first direction in sequence. Figure 27

[0305] Specifically, as shown in FIG. 8, the second part CKCb of the third clock signal line CKC includes the second part CKC4b of the third clock fourth line CKC4, the second part CKC3b of the third clock third line CKC3, the second part CKC2b of the third clock second line CKC2, and the second part CKC1b of the third clock first line CKC1 arranged in the first direction in sequence. Figure 27

[0306] Specifically, as shown in FIG. 8, the second part CKCb of the third clock signal line CKC includes the second part CKC4b of the third clock fourth line CKC4, the second part CKC3b of the third clock third line CKC3, the second part CKC2b of the third clock second line CKC2, and the second part CKC1b of the third clock first line CKC1 arranged in the first direction in sequence. Figure 27

[0307] Specifically, as shown in FIG. 8, the second part CKCb of the third clock signal line CKC includes the second part CKC4b of the third clock fourth line CKC4, the second part CKC3b of the third clock third line CKC3, the second part CKC2b of the third clock second line CKC2, and the second part CKC1b of the third clock first line CKC1 arranged in the first direction in sequence. Figure 27

[0308] Specifically, as shown in FIG. 8, the second part CKCb of the third clock signal line CKC includes the second part CKC4b of the third clock fourth line CKC4, the second part CKC3b of the third clock third line CKC3, the second part CKC2b of the third clock second line CKC2, and the second part CKC1b of the third clock first line CKC1 arranged in the first direction in sequence. Figure 27

[0309] Specifically, as shown in FIG. 8, the second part CKCb of the third clock signal line CKC includes the second part CKC4b of the third clock fourth line CKC4, the second part CKC3b of the third clock third line CKC3, the second part CKC2b of the third clock second line CKC2, and the second part CKC1b of the third clock first line CKC1 arranged in the first direction in sequence. Figure 27 Specifically, as shown in FIG. 8, the second part CKCb of the third clock signal line CKC includes the second part CKC4b of the third clock fourth line CKC4, the second part CKC3b of the third clock third line CKC3, the second part CKC2b of the third clock second line CKC2, and the second part CKC1b of the third clock first line CKC1 arranged in the first direction in sequence.​​​​​

[0310] Specifically, such as Figure 27 As shown, the gate T61iG of the second anti-negative bias transistor T61i includes the gate T61i1G of the third anti-negative bias transistor T61i1 and the gate T61i2G of the fourth anti-negative bias transistor T61i2, and the gate T61i1G of the third anti-negative bias transistor T61i1 and the gate T61i2G of the fourth anti-negative bias transistor T61i2 are arranged along a first direction.

[0311] In some embodiments, such as Figure 24 , Figure 28 As shown, the display panel 2 includes a first source-drain layer 221, which includes a third portion VST2c of the second reset control line VST2, a third portion CKCc of the third clock signal line CKC, a second portion C2a2 of the first plate C2a of the second capacitor C2, a first electrode T11iS of the fourth pull-up control transistor T11i, a first electrode T12iS of the fifth pull-up control transistor T12i, a first electrode T81iS of the sixth pull-up control transistor T81i, and a fourth pull-up transistor T21. The first electrode T21iS of the fifth pull-down transistor T31i, the first electrode T41iS of the sixth pull-down transistor T41i, the first electrode T42iS of the second pull-down holding transistor T42i, the first electrode T51iS of the sixth inverting transistor T51i, the first electrode T52iS of the seventh inverting transistor T52i, the first electrode T53iS of the eighth inverting transistor T53i, the first electrode T54iS of the ninth inverting transistor T54i, and the first electrode T55i of the tenth inverting transistor T55i. T55iS, the first electrode of the second reset transistor T43i, the first electrode of the second anti-negative bias transistor T61i, the second electrode of the fourth pull-up control transistor T11i, the second electrode of the fifth pull-up control transistor T12i, the second electrode of the sixth pull-up control transistor T81i, the second electrode of the fourth pull-up transistor T21i, the second electrode of the fifth pull-down transistor T31i, and the second electrode of the sixth pull-down transistor T41i. 41iD, the second electrode of the second pull-down holding transistor T42i, the second electrode of the sixth inverting transistor T51i, the second electrode of the seventh inverting transistor T52i, the second electrode of the eighth inverting transistor T53i, the second electrode of the ninth inverting transistor T54i, the second electrode of the tenth inverting transistor T55i, the second electrode of the second reset transistor T43i, and the second electrode of the second anti-negative bias transistor T61i.

[0312] The first electrode T81iS of the sixth pull-up control transistor T81i, the first electrode T11iS of the fourth pull-up control transistor T11i, the first electrode T12iS of the fifth pull-up control transistor T12i, and the first electrode T43iS of the second reset transistor T43i are sequentially arranged along the second direction, the first electrode T51iS of the sixth inverter transistor T51i, the first electrode T52iS of the seventh inverter transistor T52i, the first electrode T31iS of the fifth pull-down transistor T31i, the first electrode T42iS of the second pull-down maintenance transistor T42i, and the first electrode T41iS of the sixth pull-down transistor T41i are sequentially arranged along the second direction, the first electrode T53iS of the eighth inverter transistor T53i and the first electrode T54iS of the ninth inverter transistor T54i are sequentially arranged along the second direction, the first electrode T61iS of the second negative bias prevention transistor T61i is arranged on the side of the first electrode T11iS of the fourth pull-up control transistor T11i away from the first electrode T12iS of the fifth pull-up control transistor T12i, the third part VST2c of the second reset control line VST2, the first electrode T81iS of the sixth pull-up control transistor T81i, the first electrode T61iS of the second negative bias prevention transistor T61i, the first electrode T53iS of the eighth inverter transistor T53i, the first electrode T52iS of the seventh inverter transistor T52i, the third part CKCc of the third clock signal line CKC, the first electrode T21iS of the fourth pull-up transistor T21i, and the second part C2a2 of the first plate C2a of the second capacitor C2 are sequentially arranged along the first direction.

[0313] Specifically, in the circuit diagram in the embodiment of the present application, in order to illustrate the connection relationship of each transistor, each transistor will have a gate, a first electrode and a second electrode, but in the actual design process, in order to reduce the occupied space of the transistor, the electrodes of some transistors will be formed by the same structure, for example, the first electrode of the third pull-up control sub-transistor T81i1 and the second electrode T81i2D of the fourth pull-up control sub-transistor T81i2 can be formed by the same structure, therefore, only the second electrode T81i2D of the fourth pull-up control sub-transistor T81i2 is marked in the figure, it can be understood that the structure is also the first electrode of the third pull-up control sub-transistor T81i1. Similarly, the structure of the electrodes of other transistors can be determined.

[0314] Specifically, as shown in Figures 24 to 28 The first part C2a1 of the first plate C2a of the second capacitor C2 is connected with the second part C2a2 of the first plate C2a of the second capacitor C2.

[0315] Specifically, as shown in Figures 24 to 28As shown in the figure, the third part VST2c of the second reset control line VST2 is connected with the second part VST2b of the second reset control line VST2 and the first part VST2a of the second reset control line VST2, and the third part CKCc of the third clock signal line CKC is connected with the second part CKCb of the third clock signal line CKC and the first part CKCa of the third clock signal line CKC.

[0316] Specifically, as shown in the figure, Figure 28 The third part CKCc of the third clock signal line CKC includes the third part CKC4c of the third clock fourth line CKC4, the third part CKC3c of the third clock third line CKC3, the third part CKC2c of the third clock second line CKC2, and the third part CKC1c of the third clock first line CKC1 arranged in the first direction in sequence.

[0317] Specifically, as shown in the figure, Figures 24 to 28 The third part CKC1c of the third clock first line CKC1 is connected with the second part CKC1b of the third clock first line CKC1 and the first part CKC1a of the third clock first line CKC1, the third part CKC2c of the third clock second line CKC2 is connected with the second part CKC2b of the third clock second line CKC2 and the first part CKC2a of the third clock second line CKC2, the third part CKC3c of the third clock third line CKC3 is connected with the second part CKC3b of the third clock third line CKC3 and the first part CKC3a of the third clock third line CKC3, and the third part CKC4c of the third clock fourth line CKC4 is connected with the second part CKC4b of the third clock fourth line CKC4 and the first part CKC4a of the third clock fourth line CKC4.

[0318] Specifically, as shown in the figure, Figure 28 The first source-drain layer 221 includes the first electrode of the third pull-up control sub-tube T81i1, the second electrode T81i1D of the third pull-up control sub-tube T81i1, the first electrode T81i2S of the fourth pull-up control sub-tube T81i2, and the second electrode T81i2D of the fourth pull-up control sub-tube T81i2, and the first electrode T81i2S of the fourth pull-up control sub-tube T81i2, the second electrode T81i2D of the fourth pull-up control sub-tube T81i2, and the second electrode T81i1D of the third pull-up control sub-tube T81i1 are arranged in the second direction in sequence.

[0319] Specifically, as shown in the figure, Figure 28As shown in FIG. 4, the first source-drain layer 221 includes a first electrode T41i1S of the third pull-down sub-tube T41i1, a second electrode T41i1D of the third pull-down sub-tube T41i1, a first electrode T41i2S of the fourth pull-down sub-tube T41i2, a second electrode T41i2D of the fourth pull-down sub-tube T41i2, the second electrode T41i2D of the fourth pull-down sub-tube T41i2, the first electrode T41i2S of the fourth pull-down sub-tube T41i2, and the second electrode T41i1D of the third pull-down sub-tube T41i1 are sequentially arranged along the second direction.

[0320] Specifically, as shown in FIG. 5, the first source-drain layer 221 includes a first electrode T42i1S of the third pull-down maintenance sub-tube T42i1, a second electrode of the third pull-down maintenance sub-tube T42i1, a first electrode T42i2S of the fourth pull-down maintenance sub-tube T42i2, a second electrode T42i2D of the fourth pull-down maintenance sub-tube T42i2, the second electrode T42i2D of the fourth pull-down maintenance sub-tube T42i2, the first electrode T42i2S of the fourth pull-down maintenance sub-tube T42i2, and the first electrode T42i1S of the third pull-down maintenance sub-tube T42i1 are sequentially arranged along the second direction. Figure 28

[0321] Specifically, as shown in FIG. 6, the first source-drain layer 221 includes a first electrode T43i1S of the third reset sub-tube T43i1, a second electrode T43i1D of the third reset sub-tube T43i1, a first electrode of the fourth reset sub-tube T43i2, a second electrode T43i1D of the fourth reset sub-tube T43i2, the second electrode T43i1D of the fourth reset sub-tube T43i2, the first electrode of the fourth reset sub-tube T43i2, and the second electrode T43i1D of the third reset sub-tube T43i1 are sequentially arranged along the second direction. Figure 28

[0322] Specifically, as shown in FIG. 7, the first source-drain layer 221 includes a first electrode T51i1S of the third inverting sub-tube T51i1, a second electrode T51i1D of the third inverting sub-tube T51i1, a first electrode of the fourth inverting sub-tube T51i2, a second electrode T51i2D of the fourth inverting sub-tube T51i2, the first electrode T51i1S of the third inverting sub-tube T51i1, the second electrode T51i1D of the third inverting sub-tube T51i1, and the second electrode T51i2D of the fourth inverting sub-tube T51i2 are sequentially arranged along the first direction. Figure 28

[0323] Specifically, as shown in FIG. 8, the first source-drain layer 221 includes a first electrode T52i1S of the third inverting maintenance sub-tube T52i1, a second electrode of the third inverting maintenance sub-tube T52i1, a first electrode T52i2S of the fourth inverting maintenance sub-tube T52i2, a second electrode T52i2D of the fourth inverting maintenance sub-tube T52i2, the second electrode T52i2D of the fourth inverting maintenance sub-tube T52i2, the first electrode T52i2S of the fourth inverting maintenance sub-tube T52i2, and the second electrode of the third inverting maintenance sub-tube T52i1 are sequentially arranged along the second direction. Figure 28 ​​​As shown, the first source-drain layer 221 includes a first electrode of a third diode T61i1, a second electrode T61i1D of the third diode T61i1, a first electrode T61i2S of a fourth diode T61i2, a second electrode T61i2D of the fourth diode T61i2, and the first electrode T61i2S of the fourth diode T61i2, the second electrode T61i2D of the fourth diode T61i2, and the second electrode T61i1D of the third diode T61i1 are sequentially arranged along the first direction.

[0324] Embodiments of the present application aim at the technical problem that the gate circuit of the reset transistor of the pixel circuit occupies a large space, resulting in a large frame of the display device, and provide some display panels to alleviate the above technical problem.

[0325] Specifically, in some comparative display devices, the gate circuit of the reset transistor of the pixel circuit includes a plurality of transistors, each transistor is arranged along the horizontal direction, resulting in a large space occupied by each transistor, resulting in a large space occupied by the gate circuit of the reset transistor of the pixel circuit, and a large frame of the display panel. Embodiments of the present application provide some embodiments, which are designed in terms of the arrangement of the transistors, the wires, etc. in the third type of gate circuit, to reduce the space occupied by the third type of gate circuit and the frame of the display panel.

[0326] In some embodiments, the display panel 2 includes a plurality of rows of pixels 23, each pixel 23 including a light emitting device LED and a pixel driving circuit 21, the pixel driving circuit 21 including a reset transistor T3, a plurality of gate driving circuits 22 respectively electrically connected to the corresponding pixel driving circuits 21, each gate driving circuit 22 including a first type of gate circuit 22a, a second type of gate circuit 22b, and a third type of gate circuit 22c, a second signal output end of the third type of gate circuit 22c being electrically connected to the reset transistor T3, and the pixel driving circuit 21 and the third type of gate circuit 22c being arranged along a first direction X. In some embodiments, as shown in FIG. 1, the first type of gate circuit 22a includes a first transistor T1 and a second transistor T2, the first transistor T1 being electrically connected to the second transistor T2, the first transistor T1 being electrically connected to a first signal output end of the third type of gate circuit 22c, and the second transistor T2 being electrically connected to a second signal output end of the third type of gate circuit 22c. Figure 7As shown, the third type of gate circuit 22c includes a third pull-up control module 331, a third pull-up module 332, a third pull-down module 333, a third pull-down maintenance module 334, a third inverting module 335, and a third negative bias prevention module 336. The third pull-up control module 331 and the third pull-up module 332 are electrically connected to a third pull-up node Q3[n] of the third type of gate circuit 22c. The third pull-down module 333 is electrically connected to the third pull-up node Q3[n] and a third signal output terminal REF[n] of the third type of gate circuit 22c. The third pull-down maintenance module 334 is electrically connected between the third pull-up node Q3[n] and a second low potential signal line VGL2 of the display panel. The third inverting module 335 is electrically connected to the third pull-up node Q3[n], a first high potential signal line VGH1 of the display panel, the second low potential signal line VGL2, a first signal output terminal Gn[n-1] of an upper first type of gate circuit 22a, a second signal output terminal INI[n] of a current second type of gate circuit 22b, and a second signal output terminal INI[n+1] of a lower second type of gate circuit 22b. The third negative bias prevention module 336 is electrically connected between the first high potential signal line VGH1 and the third pull-up node Q3[n].

[0327] In some embodiments, as shown in Figure 7 , Figure 29 At least two of the third pull-up control module 331, the third pull-up module 332, the third pull-down module 333, the third pull-down maintenance module 334, the third inverting module 335, and the third negative bias prevention module 336 are arranged along a second direction. An included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By arranging at least two of the third pull-up control module 331, the third pull-up module 332, the third pull-down module 333, the third pull-down maintenance module 334, the third inverting module 335, and the third negative bias prevention module 336 along the second direction, the third type of gate circuit 22c can occupy less horizontal space, the gate drive circuit 22 can occupy less horizontal space, and the display panel 2 can have a smaller frame.

[0328] Specifically, compared with the modules in the comparative display device being arranged horizontally, at least two of the third type of gate circuit 22c are arranged along the second direction in the embodiments of the present application, so that the third type of gate circuit 22c can occupy less horizontal space, the gate drive circuit 22 can occupy less horizontal space, and the display panel 2 can have a smaller frame.

[0329] In some embodiments, as shown in Figure 7 , Figure 29As shown, a portion of the third pull-up control module 331, a portion of the third pull-down maintenance module 334, a portion of the third phase inverting module 335, and the third anti-negative bias module 336 are arranged along the second direction, while another portion of the third pull-up control module 331, another portion of the third phase inverting module 335, and a portion of the third pull-down module 333 are arranged along the second direction. By arranging a portion of the third pull-up control module 331, the third pull-down sustaining module 334, a portion of the third inverting module 335, and the third anti-negative bias module 336 along the second direction, and another portion of the third pull-up control module 331, another portion of the third inverting module 335, and a portion of the third pull-down module 333 along the second direction, the lateral space occupied by the third pull-up control module 331, the third pull-down sustaining module 334, the third inverting module 335, the third anti-negative bias module 336, and the third pull-down module 333 can be reduced. This can reduce the lateral space occupied by the third type of gate circuit 22c and the lateral space occupied by the gate driving circuit 22, thereby reducing the bezel of the display panel 2.

[0330] This application provides a display panel in which a portion of a third pull-up control module, a third pull-down sustaining module, a portion of a third inverting module, and a third anti-negative bias module are arranged along a second direction, and another portion of the third pull-up control module, another portion of the third inverting module, and a portion of the third pull-down module are arranged along the second direction. By arranging the modules in a vertical space, the horizontal space occupied by each module is reduced, thereby reducing the horizontal space occupied by the third type of gate circuit, reducing the space occupied by the gate driving circuit, and reducing the bezel of the display panel.

[0331] Specifically, such as Figure 29 As shown, in the second direction, the third pull-up control module 331 is located below the third anti-negative bias module 336, the third anti-negative bias module 336 is located below the third pull-down maintenance module 334, and the third pull-down maintenance module 334 is located below a portion of the third inverting module 335; the third pull-up control module 331 is located below a portion of the third inverting module 335, a portion of the third inverting module 335 is located below a portion of the third pull-down module 333, and a portion of the third inverting module 335 is located above a portion of the third pull-down module 333.

[0332] In some embodiments, such as Figure 7 , Figures 29 to 33As shown, the third inverting module 335 includes an eleventh inverting transistor T51r, a twelfth inverting transistor T52r, a thirteenth inverting transistor T53r, a fourteenth inverting transistor T54r, a fifteenth inverting transistor T55r, and a sixteenth inverting transistor T56r, a gate electrode T51rG of the eleventh inverting transistor T51r and a first electrode T51rS of the eleventh inverting transistor T51r are electrically connected with the first signal output end Gn[n-1] of the upper-stage first-type gate circuit 22a, a second electrode T51rD of the eleventh inverting transistor T51r is electrically connected with a second electrode T52rD of the twelfth inverting transistor T52r, a gate electrode T52rG of the twelfth inverting transistor T52r is electrically connected with the second signal output end INI[n] of the current-stage second-type gate circuit 22b, a first electrode T52rS of the twelfth inverting transistor T52r is electrically connected with the second low-potential signal line VGL2, a gate electrode T53rG of the thirteenth inverting transistor T53r is electrically connected with the second electrode T51rD of the eleventh inverting transistor T51r, a first electrode T53rS of the thirteenth inverting transistor T53r is electrically connected with the first high-potential signal line VGH1, a gate electrode T54rG of the fourteenth inverting transistor T54r is electrically connected with the second electrode T51rD of the eleventh inverting transistor T51r, a first electrode T54rS of the fourteenth inverting transistor T54r is electrically connected with the first high-potential signal line VGH1, a second electrode T54rD of the fourteenth inverting transistor T54r is electrically connected with a third pull-down node QB3[n], a gate electrode T55rG of the fifteenth inverting transistor T55r is electrically connected with the third pull-up node Q3[n], a first electrode T55rS of the fifteenth inverting transistor T55r is electrically connected with the second low-potential signal line VGL2, and a second electrode of the fifteenth inverting transistor T55r is electrically connected with the third pull-down node QB3[n]; a gate electrode T56rG of the sixteenth inverting transistor T56r is electrically connected with the second signal output end INI[n+1] of the lower-stage second-type gate circuit 22b, a first electrode T56rS of the sixteenth inverting transistor T56r is electrically connected with the second low-potential signal line VGL2, and a second electrode T56rD of the sixteenth inverting transistor T56r is electrically connected with the third pull-down node QB3[n];

[0333] The thirteenth inverter transistor T53r, the eleventh inverter transistor T51r and the twelfth inverter transistor T52r are arranged along the first direction, the thirteenth inverter transistor T53r and the fourteenth inverter transistor T54r are arranged along the second direction, and the eleventh inverter transistor T51r, the fifteenth inverter transistor T55r and the sixteenth inverter transistor T56r are arranged along the second direction, so that the third inverting module 335 occupies less horizontal space, thereby reducing the frame of the display panel 2.

[0334] In some embodiments, as shown in Figure 7 、 Figures 29 to 33 The eleventh inverter transistor T51r includes a fifth inverter sub-transistor T51r1 and a sixth inverter sub-transistor T51r2, the gate T51r1G of the fifth inverter sub-transistor T51r1 and the first electrode T51r1S of the fifth inverter sub-transistor T51r1 are electrically connected with the first signal output end Gn[n-1] of the previous stage first type gate circuit 22a, the second electrode T51r1D of the fifth inverter sub-transistor T51r1 is electrically connected with the first electrode of the sixth inverter sub-transistor T51r2, the gate T51r2G of the sixth inverter sub-transistor T51r2 is electrically connected with the first signal output end Gn[n-1] of the previous stage first type gate circuit 22a, and the second electrode T51r2D of the sixth inverter sub-transistor T51r2 is electrically connected with the second electrode T52rD of the twelfth inverter transistor T52r.

[0335] The fifth inverter sub-transistor T51r1 and the sixth inverter sub-transistor T51r2 are arranged along the second direction. By making the eleventh inverter transistor T51r include the fifth inverter sub-transistor T51r1 and the sixth inverter sub-transistor T51r2, the performance of the eleventh inverter transistor T51r can be improved, and the fifth inverter sub-transistor T51r1 and the sixth inverter sub-transistor T51r2 are arranged along the second direction, which can reduce the horizontal space occupied by the eleventh inverter transistor T51r and reduce the frame of the display panel 2.

[0336] In some embodiments, as shown in Figure 7 、 Figures 29 to 33As shown in the figure, the twelfth inverting transistor T52r includes a seventh inverting sub-transistor T52r1 and an eighth inverting sub-transistor T52r2, a gate T52r1G of the seventh inverting sub-transistor T52r1 and a first electrode T52r1S of the seventh inverting sub-transistor T52r1 are electrically connected with the second signal output end INI[n] of the second type gate circuit 22b of the current stage, a second electrode T52r1D of the seventh inverting sub-transistor T52r1 is electrically connected with a first electrode T52r2S of the eighth inverting sub-transistor T52r2, a gate T52r2G of the eighth inverting sub-transistor T52r2 is electrically connected with the second signal output end INI[n] of the second type gate circuit 22b of the current stage, and a second electrode T52r2D of the eighth inverting sub-transistor T52r2 is electrically connected with a second electrode T51rD of the eleventh inverting transistor T51r;

[0337] The seventh inverting sub-transistor T52r1 and the eighth inverting sub-transistor T52r2 are arranged along the second direction. By arranging the seventh inverting sub-transistor T52r1 and the eighth inverting sub-transistor T52r2 along the second direction, the performance of the twelfth inverting transistor T52r can be improved, and the transverse space occupied by the twelfth inverting transistor T52r can be reduced, and the frame of the display panel 2 can be reduced.

[0338] In some embodiments, as shown in the figure, Figure 7 , Figures 29 to 33 The third pull-up control module 331 includes a seventh pull-up control transistor T11r, a gate T11rG of the seventh pull-up control transistor T11r is electrically connected with the second signal output end INI[n+1] of the second type gate circuit 22b of the next stage, a first electrode T11rS of the seventh pull-up control transistor T11r is electrically connected with the first high potential signal line VGH1, and a second electrode T11rD of the seventh pull-up control transistor T11r is electrically connected to the third pull-up node Q3[n].

[0339] The seventh pull-up control transistor T11r and the eleventh inverting transistor T51r are arranged along the second direction. By arranging the seventh pull-up control transistor T11r and the eleventh inverting transistor T51r along the second direction, the transverse space occupied by the third inverting module 335 and the third pull-up control transistor T81j can be reduced, and the frame of the display panel 2 can be reduced.

[0340] In some embodiments, as shown in the figure, Figure 7 , Figures 29 to 33As shown, the third pull-down module 333 includes a seventh pull-down transistor T31r and an eighth pull-down transistor T41r. A gate T31rG of the seventh pull-down transistor T31r is electrically connected with the third pull-down node QB3[n]. A first electrode T31rS of the seventh pull-down transistor T31r is electrically connected with the third low potential signal line VGL3 of the display panel. A second electrode T31rD of the seventh pull-down transistor T31r is electrically connected with the third signal output end REF[n] of the third gate circuit 22c of the current stage. A gate T41rG of the eighth pull-down transistor T41r is electrically connected with the first signal output end of the first gate circuit 22a of the previous stage. A first electrode T41rS of the eighth pull-down transistor T41r is connected with the second low potential signal line VGL2. A second electrode T41rD of the eighth pull-down transistor T41r is electrically connected with the third pull-up node Q3[n].

[0341] The eighth pull-down transistor T41r is arranged between the eleventh inverting transistor T51r and the fifteenth inverting transistor T55r in the second direction. By arranging the eighth pull-down transistor T41r between the eleventh inverting transistor T51r and the fifteenth inverting transistor T55r in the second direction, the space occupied by the third pull-down module 333 and the third inverting module 335 can be reduced, and the frame of the display panel 2 can be reduced.

[0342] In some embodiments, as shown in Figure 7 、 Figures 29 to 33 The eighth pull-down transistor T41r includes a fifth pull-down sub-transistor T41r1 and a sixth pull-down sub-transistor T41r2. A gate T41r1G of the fifth pull-down sub-transistor T41r1 is electrically connected with the first signal output end of the first gate circuit 22a of the previous stage. A first electrode T41r1S of the fifth pull-down sub-transistor T41r1 is electrically connected with the second low potential signal line VGL2. A second electrode T41r1D of the fifth pull-down sub-transistor T41r1 is electrically connected with a first electrode of the sixth pull-down sub-transistor T41r2 at the third internal node N3[n] of the third gate circuit. A gate T41r2G of the sixth pull-down sub-transistor T41r2 is electrically connected with the first signal output end of the first gate circuit 22a of the previous stage. A second electrode T41r2D of the sixth pull-down sub-transistor T41r2 is electrically connected with the third pull-up node Q3[n].

[0343] The fifth pull-down sub-tube T41r1 and the sixth pull-down sub-tube T41r2 are arranged along the second direction. By including the fifth pull-down sub-tube T41r1 and the sixth pull-down sub-tube T41r2 in the eighth pull-down transistor T41r, the performance of the eighth pull-down transistor T41r can be improved, and the fifth pull-down sub-tube T41r1 and the sixth pull-down sub-tube T41r2 are arranged along the second direction, which can reduce the horizontal area occupied by the eighth pull-down transistor T41r and reduce the frame of the display panel 2.

[0344] In some embodiments, as shown in Figure 7 、 Figures 29 to 33 The third pull-down maintaining module 334 includes a third pull-down maintaining transistor T42r, a gate electrode T42rG of the third pull-down maintaining transistor T42r is electrically connected with the third pull-down node QB3[n], a first electrode T42rS of the third pull-down maintaining transistor T42r is electrically connected with the second low potential signal line VGL2, and a second electrode T42rD of the third pull-down maintaining transistor T42r is electrically connected with the third pull-up node Q3[n];

[0345] In the second direction, the third pull-down maintaining transistor T42r is arranged between the twelfth inverting transistor T52r and the seventh pull-up control transistor T11r, so as to reduce the horizontal space occupied by the third pull-down maintaining transistor T42r, the twelfth inverting transistor T52r and the seventh pull-up control transistor T11r, and reduce the frame of the display panel 2.

[0346] In some embodiments, as shown in Figure 7 、 Figures 29 to 33 The third pull-down maintaining transistor T42r includes a fifth pull-down maintaining sub-tube T42r1 and a sixth pull-down maintaining sub-tube T42r2, a gate electrode T42r2G of the sixth pull-down maintaining sub-tube T42r2 is electrically connected with the third pull-down node QB3[n], a first electrode T42r2S of the sixth pull-down maintaining sub-tube T42r2 is electrically connected with the second low potential signal line VGL2, a second electrode T42r2D of the sixth pull-down maintaining sub-tube T42r2 is electrically connected with a first electrode T42r1S of the fifth pull-down maintaining sub-tube T42r1 at a third internal node N3[n], a gate electrode T42r1G of the fifth pull-down maintaining sub-tube T42r1 is electrically connected with the third pull-down node QB3[n], and a second electrode T42r1D of the fifth pull-down maintaining sub-tube T42r1 is electrically connected with the third pull-up node Q3[n];

[0347] The fifth pull-down sustaining sub-transistor T42r1 and the sixth pull-down sustaining sub-transistor T42r2 are arranged along the second direction. By including the fifth pull-down sustaining sub-transistor T42r1 and the sixth pull-down sustaining sub-transistor T42r2 in the third pull-down sustaining transistor T42r, the performance of the third pull-down sustaining transistor T42r can be improved. Furthermore, the arrangement of the fifth pull-down sustaining sub-transistor T42r1 and the sixth pull-down sustaining sub-transistor T42r2 along the second direction can reduce the lateral space occupied by the third pull-down sustaining transistor T42r, thereby reducing the bezel of the display panel 2.

[0348] In some embodiments, such as Figure 7 , Figures 29 to 33 As shown, the third anti-negative bias module 336 includes a third anti-negative bias transistor T61r. The gate T61rG of the third anti-negative bias transistor T61r is electrically connected to the third pull-up node Q3[n]. The first electrode T61rS of the third anti-negative bias transistor T61r is electrically connected to the first high-potential signal line VGH1. The second electrode T61rD of the third anti-negative bias transistor T61r is electrically connected to the third internal node N3[n].

[0349] The third anti-negative bias transistor T61r is disposed along the second direction between the seventh pull-up control transistor T11r and the third pull-down sustaining transistor T42r, and along the first direction on the side of the eighth pull-down transistor T41r away from the fourteenth inverting transistor T54r. By disposing the third anti-negative bias transistor T61r along the second direction between the seventh pull-up control transistor T11r and the third pull-down sustaining transistor T42r, the lateral area occupied by the third anti-negative bias module 336 can be reduced, thus reducing the bezel of the display panel 2.

[0350] In some embodiments, such as Figure 7 , Figures 29 to 33 As shown, the third anti-negative bias transistor T61r includes a fifth anti-negative bias sub-transistor T61r1 and a sixth anti-negative bias sub-transistor T61r2. The gate T61r2G of the sixth anti-negative bias sub-transistor T61r2 is electrically connected to the third pull-up node Q3[n]. The first electrode T61r2S of the sixth anti-negative bias sub-transistor T61r2 is electrically connected to the first high-potential signal line. The second electrode T61r2D of the sixth anti-negative bias sub-transistor T61r2 is electrically connected to the first electrode of the fifth anti-negative bias sub-transistor T61r1. The gate T61r1G of the fifth anti-negative bias sub-transistor T61r1 is electrically connected to the third pull-up node Q3[n]. The second electrode T61r1D of the fifth anti-negative bias sub-transistor T61r1 is electrically connected to the third internal node N3[n].

[0351] The fifth negative bias prevention sub-tube T61r1 and the sixth negative bias prevention sub-tube T61r2 are arranged along the second direction. By arranging the third negative bias prevention transistor T61r to include the fifth negative bias prevention sub-tube T61r1 and the sixth negative bias prevention sub-tube T61r2, the performance of the third negative bias prevention transistor T61r can be improved, and the fifth negative bias prevention sub-tube T61r1 and the sixth negative bias prevention sub-tube T61r2 are arranged along the second direction, so that the horizontal space occupied by the third negative bias prevention transistor T61r can be reduced, and the frame of the display panel 2 can be reduced.

[0352] In some embodiments, the third pull-up module 332 includes a fifth pull-up transistor T21r, a gate electrode T21rG of the fifth pull-up transistor T21r is electrically connected with the third pull-up node Q3[n], a first electrode T21rS of the fifth pull-up transistor T21r is electrically connected with the second high potential signal line VGH2 of the display panel, and a second electrode T21rD of the fifth pull-up transistor T21r is electrically connected with the third signal output end REF[n] of the third gate electrode circuit 22c of the current stage.

[0353] In the first direction, the second high potential signal line VGH2 is arranged adjacent to the fifth pull-up transistor T21r, so that the second high potential signal line VGH2 does not need to be extended from outside the transistor area to inside the transistor area, and the second high potential signal line VGH2 is arranged adjacent to the transistor connected thereto, the cross-line is less, the space occupied by the second high potential signal line VGH2 is reduced, and the frame of the display panel 2 is reduced.

[0354] In some embodiments, as shown in Figure 7 The third gate electrode circuit 22c further includes a third capacitor C3, one plate of the third capacitor C3 is electrically connected to the third pull-up node Q3[n], and the other plate of the third capacitor C3 is electrically connected to the third signal output end REF[n] of the third gate electrode circuit 22c of the current stage.

[0355] Specifically, the third capacitor C3 includes a first plate C3a of the third capacitor C3 and a second plate C3b of the third capacitor C3, and the first plate C3a of the third capacitor C3 includes a first part C3a1 of the first plate C3a of the third capacitor C3 and a second part C3a2 of the first plate C3a of the third capacitor C3.

[0356] In some embodiments, as shown in Figure 7 The third gate electrode circuit 22c further includes a fourth capacitor C4, one plate of the fourth capacitor C4 is electrically connected to the first high potential signal line VGH1, and the other plate of the fourth capacitor C4 is electrically connected to the second electrode T51rD of the eleventh inverting transistor T51r.

[0357] Specifically, the fourth capacitor C4 includes a first plate C4a of the fourth capacitor C4 and a second plate C4b of the fourth capacitor C4.

[0358] In some embodiments, as shown in Figure 29 , Figure 30 The display panel 2 includes a light shielding layer 212, which includes, in the first direction, a first portion VGL2a of the second low potential signal line VGL2, a first portion VGH2a of the second high potential signal line VGH2, a first portion C3a1 of the first plate C3a of the third capacitor C3, and a first portion VGL3a of the third low potential signal line VGL3.

[0359] In some embodiments, as shown in Figure 29 , Figure 31 The display panel 2 includes an active layer 216, which includes an active part T11rA of the seventh pull-up control transistor T11r, an active part T21rA of the fifth pull-up transistor T21r, an active part T31rA of the seventh pull-down transistor T31r, an active part T41rA of the eighth pull-down transistor T41r, an active part T42rA of the third pull-down sustain transistor T42r, an active part T51rA of the eleventh inverting transistor T51r, an active part T52rA of the twelfth inverting transistor T52r, an active part T53rA of the thirteenth inverting transistor T53r, an active part T54rA of the fourteenth inverting transistor T54r, an active part T55rA of the fifteenth inverting transistor T55r, an active part T56rA of the sixteenth inverting transistor T56r, and an active part T61rA of the third negative bias prevention transistor T61r.

[0360] Among them, the active portions T53rA of the thirteenth inverting transistor T53r and the active portions T54rA of the fourteenth inverting transistor T54r are arranged sequentially along the second direction; the active portions T51rA of the eleventh inverting transistor T51r, the active portions T41rA of the eighth pull-down transistor T41r, the active portions T55rA of the fifteenth inverting transistor T55r, the active portions T56rA of the sixteenth inverting transistor T56r, and the active portions T11rA of the seventh pull-up control transistor T11r are arranged sequentially along the second direction; the active portions T52rA of the twelfth inverting transistor T52r, and the active portions T52rA of the eleventh inverting transistor T51r, the active portions T41rA of the eighth pull-down transistor T41r, the active portions T55rA of the fifteenth inverting transistor T55r, the active portions T56rA of the sixteenth inverting transistor T56r, and the active portions T11rA of the seventh pull-up control transistor T11r are arranged sequentially along the second direction; the active portions T52rA of the twelfth inverting transistor T52r, and the active portions T53rA of the eleventh inverting transistor T51r, the active portions T41rA of the eleventh pull-down transistor T41r, the active portions T55rA of the thirteenth inverting transistor T54r, and the active portions T54rA of the thirteenth inverting transistor T54r are arranged sequentially along the second direction; the active portions T53 ... The active portion T42rA of the third pull-down holding transistor T42r, the active portion T61rA of the third anti-negative bias transistor T61r, and the active portion T11rA of the seventh pull-up control transistor T11r are arranged sequentially along the second direction. The active portions T53rA of the thirteenth inverting transistor T53r, the active portions T51rA of the eleventh inverting transistor T51r, the active portions T52rA of the twelfth inverting transistor T52r, the active portions T21rA of the fifth pull-up transistor T21r, and the active portions T31rA of the seventh pull-down transistor T31r are arranged sequentially along the first direction.

[0361] Specifically, such as Figure 31 As shown, the active portion T41rA of the eighth pull-down transistor T41r includes the active portion T41r1A of the fifth pull-down sub-transistor T41r1 and the active portion T41r2A of the sixth pull-down sub-transistor T41r2, which are arranged along the second direction.

[0362] Specifically, such as Figure 31 As shown, the active portion of the fifth pull-down sustaining transistor includes the active portion T42r1A of the fifth pull-down sustaining sub-transistor T42r1 and the active portion T42r2A of the sixth pull-down sustaining sub-transistor T42r2. The active portion T42r1A of the fifth pull-down sustaining sub-transistor T42r1 and the active portion T42r2A of the sixth pull-down sustaining sub-transistor T42r2 are arranged along the second direction.

[0363] Specifically, such as Figure 31 As shown, the active portion T51rA of the eleventh inverting transistor T51r includes the active portion T51r1A of the fifth inverting sub-transistor T51r1 and the active portion T51r2A of the sixth inverting sub-transistor T51r2. The active portion T51r1A of the fifth inverting sub-transistor T51r1 and the active portion T51r2A of the sixth inverting sub-transistor T51r2 are arranged along a second direction.

[0364] Specifically, such as Figure 31As shown, the active part T61rA of the third negative bias prevention transistor T61r includes an active part T61r1A of a fifth negative bias prevention sub-transistor T61r1 and an active part T61r2A of a sixth negative bias prevention sub-transistor T61r2, which are arranged along the second direction.

[0365] In particular, as shown in FIG. 6, the active part T61rA of the third negative bias prevention transistor T61r includes an active part T61r1A of a fifth negative bias prevention sub-transistor T61r1 and an active part T61r2A of a sixth negative bias prevention sub-transistor T61r2, which are arranged along the second direction. Figure 31

[0366] In some embodiments, as shown in FIG. 6, the display panel 2 includes a gate layer 218, which includes a second part VGL2b of the second low potential signal line VGL2, a second part VGH2b of the second high potential signal line VGH2, a second plate C3b of the third capacitor C3, a second plate C4b of the fourth capacitor C4, a second part VGL3b of the third low potential signal line VGL3, a gate T11rG of the seventh pull-up control transistor T11r, a gate T21rG of the fifth pull-up transistor T21r, a gate T31rG of the seventh pull-down transistor T31r, a gate T41rG of the eighth pull-down transistor T41r, a gate T42rG of the third pull-down maintenance transistor T42r, a gate T51rG of the eleventh inverting transistor T51r, a gate T52rG of the twelfth inverting transistor T52r, a gate T53rG of the thirteenth inverting transistor T53r, a gate T54rG of the fourteenth inverting transistor T54r, a gate T55rG of the fifteenth inverting transistor T55r, a gate T56rG of the sixteenth inverting transistor T56r, a gate T61rG of the third negative bias prevention transistor T61r. Figure 29 Figure 32 In particular, as shown in FIG. 6, the active part T61rA of the third negative bias prevention transistor T61r includes an active part T61r1A of a fifth negative bias prevention sub-transistor T61r1 and an active part T61r2A of a sixth negative bias prevention sub-transistor T61r2, which are arranged along the second direction.

[0367] ​​Among them, the gates T53rG of the thirteenth inverting transistor T53r and the fourteenth inverting transistor T54rG are arranged sequentially along the second direction; the gates T51rG of the eleventh inverting transistor T51r, the eighth pull-down transistor T41rG, the fifteenth inverting transistor T55rG, the sixteenth inverting transistor T56rG, and the seventh pull-up control transistor T11rG are arranged sequentially along the second direction; the gates T52rG of the twelfth inverting transistor T52r, the third pull-down sustaining transistor T42rG, the third anti-negative bias transistor T61rG, and the seventh pull-up control transistor T11rG are arranged sequentially along the second direction. The second plate C3b of the third capacitor C3 and the gate T21rG of the fifth pull-up transistor T21r are arranged sequentially along the second direction. The second plate C4b of the fourth capacitor C4, the gate T53rG of the thirteenth inverting transistor T53r, the gate T51rG of the eleventh inverting transistor T51r, the gate T52rG of the twelfth inverting transistor T52r, the second portion VGL2b of the second low-potential signal line VGL2, the second portion VGH2b of the second high-potential signal line VGH2, the gate T21rG of the fifth pull-up transistor T21r, the gate T31rG of the seventh pull-down transistor T31r, and the second portion VGL3b of the third low-potential signal line VGL3 are arranged sequentially along the first direction.

[0368] Specifically, such as Figure 32 As shown, the gate T41rG of the eighth pull-down transistor T41r includes the gate T41r1G of the fifth pull-down sub-transistor T41r1 and the gate T41r2G of the sixth pull-down sub-transistor T41r2, which are arranged along the second direction.

[0369] Specifically, such as Figure 32 As shown, the gate of the fifth pull-down sustaining transistor includes the gate T42r1G of the fifth pull-down sustaining sub-transistor T42r1 and the gate T42r2G of the sixth pull-down sustaining sub-transistor T42r2, which are arranged along the second direction.

[0370] Specifically, such as Figure 32As shown, the gate T51rG of the eleventh inverter transistor T51r includes the gate T51r1G of the fifth inverter sub-transistor T51r1 and the gate T51r2G of the sixth inverter sub-transistor T51r2, the gate T51r1G of the fifth inverter sub-transistor T51r1 being disposed along the second direction from the gate T51r2G of the sixth inverter sub-transistor T51r2.

[0371] In particular, as shown in FIG. 6A, the gate T61rG of the third negative bias protection transistor T61r includes the gate T61r1G of the fifth negative bias protection sub-transistor T61r1 and the gate T61r2G of the sixth negative bias protection sub-transistor T61r2, the gate T61r1G of the fifth negative bias protection sub-transistor T61r1 being disposed along the second direction from the gate T61r2G of the sixth negative bias protection sub-transistor T61r2. Figure 32 In particular, as shown in FIG. 6A, the gate T61rG of the third negative bias protection transistor T61r includes the gate T61r1G of the fifth negative bias protection sub-transistor T61r1 and the gate T61r2G of the sixth negative bias protection sub-transistor T61r2, the gate T61r1G of the fifth negative bias protection sub-transistor T61r1 being disposed along the second direction from the gate T61r2G of the sixth negative bias protection sub-transistor T61r2.

[0372] Figure 32 In particular, as shown in FIG. 6A, the gate T61rG of the third negative bias protection transistor T61r includes the gate T61r1G of the fifth negative bias protection sub-transistor T61r1 and the gate T61r2G of the sixth negative bias protection sub-transistor T61r2, the gate T61r1G of the fifth negative bias protection sub-transistor T61r1 being disposed along the second direction from the gate T61r2G of the sixth negative bias protection sub-transistor T61r2.

[0373] In some embodiments, as shown in FIG. 6A, the gate T61rG of the third negative bias protection transistor T61r includes the gate T61r1G of the fifth negative bias protection sub-transistor T61r1 and the gate T61r2G of the sixth negative bias protection sub-transistor T61r2, the gate T61r1G of the fifth negative bias protection sub-transistor T61r1 being disposed along the second direction from the gate T61r2G of the sixth negative bias protection sub-transistor T61r2. Figure 29 Figure 33 ​​As shown, the display panel 2 includes a first source-drain layer 221 including a third portion VGL2c of the second low potential signal line VGL2, a third portion VGH2c of the second high potential signal line VGH2, a second portion C3a2 of the first plate C3a of the third capacitor C3, a first plate C4a of the fourth capacitor C4, a third portion VGL3c of the third low potential signal line VGL3, a first electrode T11rS of the seventh pull-up control transistor T11r, a first electrode T21rS of the fifth pull-up transistor T21r, a first electrode T31rS of the seventh pull-down transistor T31r, a first electrode T41rS of the eighth pull-down transistor T41r, a first electrode T42rS of the third pull-down sustain transistor T42r, a first electrode T51rS of the eleventh inverting transistor T51r, a first electrode T52rS of the twelfth inverting transistor T52r, a first electrode T53rS of the thirteenth inverting transistor T53r, a first electrode T54rS of the fourteenth inverting transistor T54r, a first electrode T55rS of the fifteenth inverting transistor T55r, a first electrode T56rS of the sixteenth inverting transistor T56r, a first electrode T61rS of the third negative bias prevention transistor T61r, a second electrode T11rD of the seventh pull-up control transistor T11r, a second electrode T21rD of the fifth pull-up transistor T21r, a second electrode T31rD of the seventh pull-down transistor T31r, a second electrode T41rD of the eighth pull-down transistor T41r, a second electrode T42rD of the third pull-down sustain transistor T42r, a second electrode T51rD of the eleventh inverting transistor T51r, a second electrode T52rD of the twelfth inverting transistor T52r, a second electrode T53rD of the thirteenth inverting transistor T53r, a second electrode T54rD of the fourteenth inverting transistor T54r, a second electrode of the fifteenth inverting transistor T55r, a second electrode T56rD of the sixteenth inverting transistor T56r, a second electrode T61rD of the third negative bias prevention transistor T61r;

[0374] The first electrode T53rS of the thirteenth inverter transistor T53r, the first electrode T54rS of the fourteenth inverter transistor T54r, the first electrode T51rS of the eleventh inverter transistor T51r, the first electrode T41rS of the eighth pull-down transistor T41r, the first electrode T55rS of the fifteenth inverter transistor T55r, the first electrode T56rS of the sixteenth inverter transistor T56r, and the first electrode T11rS of the seventh pull-up control transistor T11r are sequentially arranged along the second direction; the first electrode T52rS of the twelfth inverter transistor T52r, the first electrode T42rS of the third pull-down transistor T42r, the first electrode T61rS of the third negative bias prevention transistor T61r, and the first electrode T11rS of the seventh pull-up control transistor T11r are sequentially arranged along the second direction; the second part C3a2 of the first plate C3a of the third capacitor C3 and the first electrode T21rS of the fifth pull-up transistor T21r are arranged along the second direction; the second part C3a2 of the first plate C3a of the third capacitor C3 and the first electrode T21rS of the fifth pull-up transistor T21r are arranged along the second direction; the first plate C4a of the fourth capacitor C4, the first electrode T53rS of the thirteenth inverter transistor T53r, the first electrode T51rS of the eleventh inverter transistor T51r, the first electrode T52rS of the twelfth inverter transistor T52r, the third part VGL2c of the second low potential signal line VGL2, the third part VGH2c of the second high potential signal line VGH2, the first electrode T21rS of the fifth pull-up transistor T21r and the first electrode T31rS of the seventh pull-down transistor T31r, and the third part VGL3c of the third low potential signal line VGL3 are sequentially arranged along the first direction.

[0375] Specifically, in the circuit diagram in the embodiment of the present application, in order to illustrate the connection relationship of each transistor, each transistor will have a gate, a first electrode and a second electrode, but in the actual design process, in order to reduce the occupied space of the transistor, the electrodes of some transistors will adopt the same structure, which can be understood as the electrodes of two transistors. Similarly, the structure of the electrodes of other transistors can be determined.

[0376] Specifically, as shown in Figures 29 to 33 The first part C3a1 of the first plate C3a of the third capacitor C3 is connected with the second part C3a2 of the first plate C3a of the third capacitor C3.

[0377] Specifically, as shown in Figures 29 to 33As shown in FIG. 6, the third part VGL2c of the second low potential signal line VGL2 is connected with the second part VGL2b of the second low potential signal line VGL2 and the first part VGL2a of the second low potential signal line VGL2, the third part VGH2c of the second high potential signal line VGH2 is connected with the second part VGH2b of the second high potential signal line VGH2 and the first part VGH2a of the second high potential signal line VGH2, and the third part VGL3c of the third low potential signal line VGL3 is connected with the second part VGL3b of the third low potential signal line VGL3 and the first part VGL3a of the third low potential signal line VGL3.

[0378] Specifically, as shown in FIG. 5, the first source-drain layer 221 includes the first electrode T41r1S of the fifth pull-down sub-transistor T41r1, the second electrode T41r1D of the fifth pull-down sub-transistor T41r1, the first electrode of the sixth pull-down sub-transistor T41r2, and the second electrode T41r2D of the sixth pull-down sub-transistor T41r2, which are sequentially arranged along the second direction. Figure 33

[0379] Specifically, as shown in FIG. 5, the first source-drain layer 221 includes the first electrode T41r1S of the fifth pull-down sub-transistor T41r1, the second electrode T41r1D of the fifth pull-down sub-transistor T41r1, the first electrode of the sixth pull-down sub-transistor T41r2, and the second electrode T41r2D of the sixth pull-down sub-transistor T41r2, which are sequentially arranged along the second direction. Figure 33

[0380] Specifically, as shown in FIG. 5, the first source-drain layer 221 includes the first electrode T41r1S of the fifth pull-down sub-transistor T41r1, the second electrode T41r1D of the fifth pull-down sub-transistor T41r1, the first electrode of the sixth pull-down sub-transistor T41r2, and the second electrode T41r2D of the sixth pull-down sub-transistor T41r2, which are sequentially arranged along the second direction. Figure 33

[0381] Specifically, as shown in FIG. 5, the first source-drain layer 221 includes the first electrode T41r1S of the fifth pull-down sub-transistor T41r1, the second electrode T41r1D of the fifth pull-down sub-transistor T41r1, the first electrode of the sixth pull-down sub-transistor T41r2, and the second electrode T41r2D of the sixth pull-down sub-transistor T41r2, which are sequentially arranged along the second direction. Figure 33 ​​​As shown, the first source-drain layer 221 includes a first electrode T52r1S of the seventh inverter sub-tube T52r1, a second electrode T52r1D of the seventh inverter sub-tube T52r1, a first electrode T52r2S of the eighth inverter sub-tube T52r2, and a second electrode T52r2D of the eighth inverter sub-tube T52r2, which are sequentially arranged along the second direction.

[0382] Specifically, as shown in FIG. 6, Figure 33 As shown, the first source-drain layer 221 includes a first electrode of the fifth negative bias prevention sub-tube T61r1, a second electrode T61r1D of the fifth negative bias prevention sub-tube T61r1, a first electrode T61r2S of the sixth negative bias prevention sub-tube T61r2, and a second electrode T61r2D of the sixth negative bias prevention sub-tube T61r2, which are sequentially arranged along the second direction.

[0383] In some embodiments, the first type of gate circuit 22a, the second type of gate circuit 22b, and the third type of gate circuit 22c are arranged along the first direction, and the third type of gate circuit 22c is electrically connected with the second low potential signal line VGL2, the third low potential signal line VGL3, and the second high potential signal line VGH2.

[0384] In some embodiments, as shown in FIG. 6, Figure 7 , Figures 8 to 12 , Figures 29 to 33 As shown in FIG. 6, in the first direction, at least one of the second low potential signal line VGL2 and the second high potential signal line VGH2 is arranged between the second type of gate circuit 22b and the third low potential signal line VGL3. By arranging at least one of the second low potential signal line VGL2 and the second high potential signal line VGH2 between the second type of gate circuit 22b and the third low potential signal line VGL3, the length of the connection line required when connecting the signal line and the corresponding transistor can be reduced, and it is not necessary to arrange the signal line outside the transistor region and then extend it into the transistor region, thereby reducing the space occupied by the signal line outside the transistor region and the space occupied by the signal line inside the transistor region, reducing the horizontal space occupied by the signal line connected to the third type of gate circuit 22c, reducing the horizontal space occupied by the third type of gate circuit 22c, and reducing the frame of the display panel 2.

[0385] In some embodiments, as shown in FIG. 6, Figure 7 , Figures 8 to 12 , Figures 29 to 33As shown in FIG. 6, the third type of gate circuit 22c includes a third pull-down maintaining module 334, the third pull-down maintaining module 334 is electrically connected with the second low potential signal line VGL2, and the second low potential signal line VGL2 is arranged between the third pull-down maintaining module 334 and the third low potential signal line VGL3. By arranging the second low potential signal line VGL2 between the third pull-down maintaining module 334 and the third low potential signal line VGL3, the horizontal space occupied by the second low potential signal line VGL2 can be reduced, the horizontal space occupied by the third type of gate circuit 22c can be reduced, and the frame of the display panel 2 can be reduced.

[0386] In some embodiments, as shown in FIG. 6, the third type of gate circuit 22c includes a third pull-down maintaining module 334, the third pull-down maintaining module 334 is electrically connected with the second low potential signal line VGL2, and the second low potential signal line VGL2 is arranged between the third pull-down maintaining module 334 and the third low potential signal line VGL3. By arranging the second low potential signal line VGL2 between the third pull-down maintaining module 334 and the third low potential signal line VGL3, the horizontal space occupied by the second low potential signal line VGL2 can be reduced, the horizontal space occupied by the third type of gate circuit 22c can be reduced, and the frame of the display panel 2 can be reduced. Figure 7 、 Figures 8 to 12 、 Figures 29 to 33 As shown in FIG. 6, the third type of gate circuit 22c includes a third pull-up module 332, and the third pull-up module 332 is electrically connected with the second high potential signal line VGH2.

[0387] In the first direction, the second high potential signal line VGH2 is arranged between the second low potential signal line VGL2 and the third pull-up module 332. By arranging the second high potential signal line VGH2 between the second low potential signal line VGL2 and the third pull-up module 332, the horizontal space occupied by the second high potential signal line VGH2 can be reduced, the horizontal space occupied by the third type of gate circuit 22c can be reduced, and the frame can be reduced.

[0388] In some embodiments, as shown in FIG. 6, the third type of gate circuit 22c includes a third pull-down maintaining module 334, the third pull-down maintaining module 334 is electrically connected with the second low potential signal line VGL2, and the second low potential signal line VGL2 is arranged between the third pull-down maintaining module 334 and the third low potential signal line VGL3. By arranging the second low potential signal line VGL2 between the third pull-down maintaining module 334 and the third low potential signal line VGL3, the horizontal space occupied by the second low potential signal line VGL2 can be reduced, the horizontal space occupied by the third type of gate circuit 22c can be reduced, and the frame of the display panel 2 can be reduced. Figure 7 、 Figures 8 to 12 、 Figures 29 to 33 As shown in FIG. 6, the third type of gate circuit 22c includes a third pull-down module 333, and the third pull-down module 333 is electrically connected with the third low potential signal line VGL3.

[0389] In the first direction, the third low potential signal line VGL3 is arranged on the side of the third pull-down module 333 away from the third pull-up module 332. By arranging the third low potential signal line VGL3 on the side of the third pull-down module 333 away from the third pull-up module 332, the horizontal space occupied by the third low potential signal line VGL3 can be reduced, the horizontal space occupied by the third type of gate circuit 22c can be reduced, and the frame can be reduced.

[0390] Specifically, the signals output on the first low potential signal line VGL1, the second low potential signal line VGL2, and the third low potential signal line VGL3 can be different.

[0391] Specifically, the signals output on the first high potential signal line VGH1 and the second high potential signal line VGH2 can be different.

[0392] Specifically, in the embodiment of the present application, the first signal output end Gn[m] of the another stage of the first type of gate circuit 22a can be the first signal output end of the next stage of the first type of gate circuit 22a, for example, the first signal output end Gn[m] of the another stage of the first type of gate circuit 22a can be the first signal output end of the next stage of the first type of gate circuit 22a, and taking n as 3 for example, m can be 4; but the embodiment of the present application is not limited to this, the first signal output end Gn[m] of the another stage of the first type of gate circuit 22a can be the first signal output end of the next two stages of the first type of gate circuit 22a or the first signal output end of other stages of the first type of gate circuit 22a.

[0393] Specifically, the above embodiment takes some transistors including two sub-transistors as an example for description, but the embodiment of the present application is not limited to this, each transistor can only include one sub-transistor.

[0394] Specifically, as shown in Figure 4 Figure 4 A pixel driving circuit 21 of a display panel 2 is provided, the pixel driving circuit 21 comprising a driving transistor T1, a switching transistor T2, a reset transistor T3 and an initialization transistor T4, the driving transistor T1, the switching transistor T2 and the reset transistor T3 being connected to a first pixel node g, the driving transistor T1 and the initialization transistor T4 being connected to a second pixel node s;

[0395] The gate of the switching transistor T2 is electrically connected to the first signal output end Gn[n] of the first type of gate circuit 22a of the current stage, the gate of the initialization transistor T4 is electrically connected to the second signal output end INI[n] of the second type of gate circuit 22b of the current stage, and the gate of the reset transistor T3 is electrically connected to the third signal output end REF[n] of the third type of gate circuit 22c of the current stage. By electrically connecting the gate of the switching transistor, the gate of the initialization transistor and the gate of the reset transistor to the first signal output end Gn[n] of the first type of gate circuit 22a of the current stage, the second signal output end INI[n] of the second type of gate circuit 22b of the current stage and the third signal output end REF[n] of the third type of gate circuit 22c of the current stage respectively, the gate driving circuit 22 can input signals to the pixel driving circuit 21, so that the pixel driving circuit 21 can work normally.

[0396] Specifically, as shown in Figure 2 ​As shown, the display panel 2 further includes a light emitting device LED, a gate of a driving transistor T1 is connected to a first node g, a first electrode of the driving transistor T1 is connected to a high potential power line VDD, a second electrode of the driving transistor T1 is connected to a second node s, a first electrode of a switching transistor T2 is connected to a data line Vdata, a second electrode of the switching transistor T2 is connected to the first node g, a first electrode of a reset transistor T3 is connected to a reference line Vref, a second electrode of the reset transistor T3 is connected to the first node g, a first electrode of an initialization transistor T4 is connected to an initialization signal line Vini, a second electrode of the initialization transistor T4 is connected to a positive electrode of the light emitting device LED, and a negative electrode of the light emitting device LED is connected to a low potential power line VSS.

[0397] Specifically, it can be understood that the display panel 2 includes a plurality of rows of sub-pixel units, and a plurality of stages of pixel driving circuits 21 are correspondingly arranged to drive the sub-pixel units, and a plurality of stages of gate driving circuits 22 are correspondingly arranged, and each stage of the gate driving circuit 22 can be connected to a corresponding one or two rows of pixel driving circuits 21.

[0398] Specifically, the type of each transistor in the gate driving circuit 22 in the embodiment of the present application can be an N-type transistor or a P-type transistor. The type of each transistor in the pixel driving circuit 21 in the embodiment of the present application can be an N-type transistor or a P-type transistor.

[0399] Specifically, the active part of each transistor in the gate driving circuit 22 in the embodiment of the present application can be formed by using the active layer 216. The active part of each transistor in the pixel driving circuit 21 in the embodiment of the present application can be formed by using the semiconductor layer 214, or partially formed by using the semiconductor layer 214 and partially formed by using the active layer 216.

[0400] Specifically, the first electrode can be the source electrode and the second electrode can be the drain electrode, or the first electrode can be the drain electrode and the second electrode can be the source electrode.

[0401] Specifically, the above embodiments have been described in detail from the aspects of the circuit, timing, transistor design, etc. of the display panel 2. It can be understood that the embodiments can be combined when there is no conflict between the embodiments, for example, in the first direction, the second reset control line is arranged between the first reset control line and the third low potential signal line, and the low frequency signal line is arranged between the first reset control line and the third low potential signal line.

[0402] Meanwhile, the embodiment of the present application provides a display device, which includes the display panel 2 as described in any of the above embodiments.

[0403] In the description of the application, the terms "first", "second", "third" and the like are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0404] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0405] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.

[0406] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present application without departing from the technical solution content of the present application still falls within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that, include: Multiple rows of pixels, each pixel including a light-emitting device and a pixel driving circuit, the pixel driving circuit including a reset transistor; A multi-stage gate driving circuit is electrically connected to the corresponding pixel driving circuit. Each stage of the gate driving circuit includes a first type of gate circuit, a second type of gate circuit, and a third type of gate circuit. The third signal output terminal of the third type of gate circuit is electrically connected to the reset transistor. The third type of gate circuit includes a third pull-up control module, a third pull-up module, a third pull-down module, a third pull-down sustaining module, a third inverting module, and a third negative bias protection module. The third pull-up control module and the third pull-up module are electrically connected to the third pull-up node of the third type of gate circuit. The third pull-down module and the third pull-up node are electrically connected to the third pull-up node. The third signal output terminal of the third type gate circuit of this stage is electrically connected to the third pull-up node; the third pull-down sustaining module is electrically connected between the third pull-up node and the second low-potential signal line of the display panel; the third inverting module is electrically connected to the third pull-up node, the first high-potential signal line of the display panel, the second low-potential signal line, the first signal output terminal of the previous first type gate circuit, the second signal output terminal of the current second type gate circuit, and the second signal output terminal of the next second type gate circuit; the third anti-negative bias module is electrically connected between the first high-potential signal line and the third pull-up node; The pixel driving circuit and the third type of gate circuit are arranged along a first direction, a part of the third pull-up control module, the third pull-down sustaining module, a part of the third inverting module, and the third anti-negative bias module are arranged along a second direction, and another part of the third pull-up control module, another part of the third inverting module, and a part of the third pull-down module are arranged along the second direction. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. The third inverting module is electrically connected to the third pull-down sustaining module at the third pull-down node. The third inverting module is configured to invert the potentials of the third pull-up node and the third pull-down node. The third negative bias protection module is electrically connected to the third pull-down module and the third pull-down sustaining module at the third internal node. The third negative bias protection module is configured to be controlled by the signal of the third pull-up node and output the signal of the first high-potential signal line to the third internal node. The third internal node acts on the transistors in the third pull-down module and the third pull-down sustaining module to prevent leakage when the threshold voltage of the transistors is negatively biased.

2. The display panel according to claim 1, characterized in that, The third inverting module includes an eleventh, twelfth, thirteenth, fourteenth, fifteenth, and sixteenth inverting transistors. The gate and first electrode of the eleventh inverting transistor are electrically connected to the first signal output terminal of the previous stage's first-type gate circuit. The second electrode of the eleventh inverting transistor is electrically connected to the second electrode of the twelfth inverting transistor. The gate of the twelfth inverting transistor is electrically connected to the second signal output terminal of the current stage's second-type gate circuit. The first electrode of the twelfth inverting transistor is electrically connected to the second low-potential signal line. The gate of the thirteenth inverting transistor is electrically connected to the second electrode of the eleventh inverting transistor. The first electrode of the thirteenth inverting transistor is electrically connected to the first high-potential signal line. The gate of the fourteenth inverting transistor is electrically connected to the second electrode of the eleventh inverting transistor; the first electrode of the fourteenth inverting transistor is electrically connected to the first high-potential signal line; the second electrode of the fourteenth inverting transistor is electrically connected to the third pull-down node; the gate of the fifteenth inverting transistor is electrically connected to the third pull-up node; the first electrode of the fifteenth inverting transistor is electrically connected to the second low-potential signal line; and the second electrode of the fifteenth inverting transistor is electrically connected to the third pull-down node. The gate of the sixteenth inverting transistor is electrically connected to the second signal output terminal of the next-stage second-type gate circuit; the first electrode of the sixteenth inverting transistor is electrically connected to the second low-potential signal line; and the second electrode of the sixteenth inverting transistor is electrically connected to the third pull-down node. The thirteenth, eleventh, and twelfth inverting transistors are arranged along the first direction, the thirteenth and fourteenth inverting transistors are arranged along the second direction, and the eleventh, fifteenth, and sixteenth inverting transistors are arranged along the second direction.

3. The display panel according to claim 2, characterized in that, The eleventh inverting transistor includes a fifth inverting sub-transistor and a sixth inverting sub-transistor. The gate and first electrode of the fifth inverting sub-transistor are electrically connected to the first signal output terminal of the previous stage first type gate circuit. The second electrode of the fifth inverting sub-transistor is electrically connected to the first electrode of the sixth inverting sub-transistor. The gate of the sixth inverting sub-transistor is electrically connected to the first signal output terminal of the previous stage first type gate circuit. The second electrode of the sixth inverting sub-transistor is electrically connected to the second electrode of the twelfth inverting transistor. The fifth and sixth inverting sub-tubes are arranged along the second direction.

4. The display panel according to claim 2, characterized in that, The twelfth inverting transistor includes a seventh inverting sub-transistor and an eighth inverting sub-transistor. The gate and first electrode of the seventh inverting sub-transistor are electrically connected to the second signal output terminal of the second type gate circuit of this stage. The second electrode of the seventh inverting sub-transistor is electrically connected to the first electrode of the eighth inverting sub-transistor. The gate of the eighth inverting sub-transistor is electrically connected to the second signal output terminal of the second type gate circuit of this stage. The second electrode of the eighth inverting sub-transistor is electrically connected to the second electrode of the eleventh inverting transistor. The seventh and eighth inverting sub-tubes are arranged along the second direction.

5. The display panel according to claim 2, characterized in that, The third pull-up control module includes a seventh pull-up control transistor. The gate of the seventh pull-up control transistor is electrically connected to the second signal output terminal of the next-stage second-type gate circuit. The first electrode of the seventh pull-up control transistor is electrically connected to the first high-potential signal line. The second electrode of the seventh pull-up control transistor is electrically connected to the third pull-up node. The seventh pull-up control transistor and the eleventh inverting transistor are arranged along the second direction.

6. The display panel according to claim 5, characterized in that, The third pull-down module includes a seventh pull-down transistor and an eighth pull-down transistor. The gate of the seventh pull-down transistor is electrically connected to the third pull-down node. The first electrode of the seventh pull-down transistor is electrically connected to the third low-potential signal line of the display panel. The second electrode of the seventh pull-down transistor is electrically connected to the third signal output terminal of the third type gate circuit of this stage. The gate of the eighth pull-down transistor is electrically connected to the first signal output terminal of the first type gate circuit of the previous stage. The first electrode of the eighth pull-down transistor is electrically connected to the second low-potential signal line. The second electrode of the eighth pull-down transistor is electrically connected to the third pull-up node. The eighth pull-down transistor is disposed between the eleventh inverting transistor and the fifteenth inverting transistor along the second direction.

7. The display panel according to claim 6, characterized in that, The eighth pull-down transistor includes a fifth pull-down sub-transistor and a sixth pull-down sub-transistor. The gate of the fifth pull-down sub-transistor is electrically connected to the first signal output terminal of the previous stage first type gate circuit. The first electrode of the fifth pull-down sub-transistor is electrically connected to the second low-potential signal line. The second electrode of the fifth pull-down sub-transistor and the first electrode of the sixth pull-down sub-transistor are electrically connected to the third internal node of the third type gate circuit. The gate of the sixth pull-down sub-transistor is electrically connected to the first signal output terminal of the previous stage first type gate circuit. The second electrode of the sixth pull-down sub-transistor is electrically connected to the third pull-up node. The fifth and sixth pull-down sub-tubes are arranged along the second direction.

8. The display panel according to claim 6, characterized in that, The third pull-down sustaining module includes a third pull-down sustaining transistor, the gate of which is electrically connected to the third pull-down node, the first electrode of which is electrically connected to the second low-potential signal line, and the second electrode of which is electrically connected to the third pull-up node. In the second direction, the third pull-down holding transistor is disposed between the twelfth inverting transistor and the seventh pull-up control transistor.

9. The display panel according to claim 8, characterized in that, The third pull-down sustaining transistor includes a fifth pull-down sustaining sub-transistor and a sixth pull-down sustaining sub-transistor. The gate of the sixth pull-down sustaining sub-transistor is electrically connected to the third pull-down node. The first electrode of the sixth pull-down sustaining sub-transistor is electrically connected to the second low-potential signal line. The second electrode of the sixth pull-down sustaining sub-transistor and the first electrode of the fifth pull-down sustaining sub-transistor are electrically connected to the third internal node. The gate of the fifth pull-down sustaining sub-transistor is electrically connected to the third pull-down node. The second electrode of the fifth pull-down sustaining sub-transistor is electrically connected to the third pull-up node. The fifth pull-down support sub-tube and the sixth pull-down support sub-tube are arranged along the second direction.

10. The display panel according to claim 8, characterized in that, The third anti-negative bias module includes a third anti-negative bias transistor, the gate of which is electrically connected to the third pull-up node, the first electrode of which is electrically connected to the first high-potential signal line, and the second electrode of which is electrically connected to the third internal node. The third anti-negative bias transistor is disposed between the seventh pull-up control transistor and the third pull-down sustaining transistor along the second direction, and the third anti-negative bias transistor is disposed on the side of the eighth pull-down transistor away from the fourteenth inverting transistor along the first direction.

11. The display panel according to claim 10, characterized in that, The third anti-negative bias transistor includes a fifth anti-negative bias sub-transistor and a sixth anti-negative bias sub-transistor. The gate of the sixth anti-negative bias sub-transistor is electrically connected to the third pull-up node. The first electrode of the sixth anti-negative bias sub-transistor is electrically connected to the first high-potential signal line. The second electrode of the sixth anti-negative bias sub-transistor is electrically connected to the first electrode of the fifth anti-negative bias sub-transistor. The gate of the fifth anti-negative bias sub-transistor is electrically connected to the third pull-up node. The second electrode of the fifth anti-negative bias sub-transistor is electrically connected to the third internal node. The fifth anti-negative deviation tube and the sixth anti-negative deviation tube are arranged along the second direction.

12. The display panel according to claim 11, characterized in that, The third pull-up module includes a fifth pull-up transistor, the gate of the fifth pull-up transistor is electrically connected to the third pull-up node, the first electrode of the fifth pull-up transistor is electrically connected to the second high-potential signal line of the display panel, and the second electrode of the fifth pull-up transistor is electrically connected to the third signal output terminal of the third type gate circuit of this stage. In the first direction, the second high-potential signal line is disposed adjacent to the fifth pull-up transistor.

13. The display panel according to claim 12, characterized in that, The third type of gate circuit also includes a third capacitor. One plate of the third capacitor is electrically connected to the third pull-up node, and the other plate of the third capacitor is electrically connected to the third signal output terminal of the third type of gate circuit in this stage.

14. The display panel according to claim 13, characterized in that, The third type of gate circuit also includes a fourth capacitor, one plate of which is electrically connected to the first high-potential signal line, and the other plate of which is electrically connected to the second electrode of the eleventh inverting transistor.

15. The display panel according to claim 14, characterized in that, The display panel includes a light-shielding layer, which includes a first portion of a second low-potential signal line, a first portion of a second high-potential signal line, a first portion of a first electrode of a third capacitor, and a first portion of a third low-potential signal line arranged sequentially along the first direction.

16. The display panel according to claim 15, characterized in that, The display panel includes an active layer, which includes the active portion of a seventh pull-up control transistor, the active portion of a fifth pull-up transistor, the active portion of a seventh pull-down transistor, the active portion of an eighth pull-down transistor, the active portion of a third pull-down sustaining transistor, the active portion of an eleventh inverting transistor, the active portion of a twelfth inverting transistor, the active portion of a thirteenth inverting transistor, the active portion of a fourteenth inverting transistor, the active portion of a fifteenth inverting transistor, the active portion of a sixteenth inverting transistor, and the active portion of a third anti-negative bias transistor. The active portions of the thirteenth and fourteenth inverting transistors are arranged sequentially along the second direction. The active portions of the eleventh inverting transistor, the eighth pull-down transistor, the fifteenth inverting transistor, the sixteenth inverting transistor, and the seventh pull-up control transistor are arranged sequentially along the second direction. The active portions of the twelfth inverting transistor, the third pull-down sustaining transistor, the third anti-negative bias transistor, and the seventh pull-up control transistor are arranged sequentially along the second direction. The active portions of the thirteenth inverting transistor, the eleventh inverting transistor, the twelfth inverting transistor, the fifth pull-up transistor, and the seventh pull-down transistor are arranged sequentially along the first direction.

17. The display panel according to claim 16, characterized in that, The display panel includes a gate layer, which includes a second portion of a second low-potential signal line, a second portion of a second high-potential signal line, a second plate of a third capacitor, a second plate of a fourth capacitor, a second portion of a third low-potential signal line, the gate of a seventh pull-up control transistor, the gate of a fifth pull-up transistor, the gate of a seventh pull-down transistor, the gate of an eighth pull-down transistor, the gate of a third pull-down sustaining transistor, the gate of an eleventh inverting transistor, the gate of a twelfth inverting transistor, the gate of a thirteenth inverting transistor, the gate of a fourteenth inverting transistor, the gate of a fifteenth inverting transistor, the gate of a sixteenth inverting transistor, and the gate of a third anti-negative bias transistor. In this configuration, the gates of the thirteenth and fourteenth inverting transistors are sequentially arranged along the second direction; the gates of the eleventh inverting transistor, the eighth pull-down transistor, the fifteenth inverting transistor, the sixteenth inverting transistor, and the seventh pull-up control transistor are sequentially arranged along the second direction; the gates of the twelfth inverting transistor, the third pull-down sustaining transistor, the third anti-negative bias transistor, and the seventh pull-up control transistor are sequentially arranged along the second direction; the second plate of the third capacitor and the gate of the fifth pull-up transistor are arranged along the second direction; and the second plate of the fourth capacitor, the gate of the thirteenth inverting transistor, the gate of the eleventh inverting transistor, the gate of the twelfth inverting transistor, the second portion of the second low-potential signal line, the second portion of the second high-potential signal line, the gate of the fifth pull-up transistor, the gate of the seventh pull-down transistor, and the second portion of the third low-potential signal line are sequentially arranged along the first direction.

18. The display panel according to claim 17, characterized in that, The display panel includes a first source-drain layer, which includes a third portion of a second low-potential signal line, a third portion of a second high-potential signal line, a second portion of a first electrode of a third capacitor, a first electrode of a fourth capacitor, a third portion of a third low-potential signal line, a first electrode of a seventh pull-up control transistor, a first electrode of a fifth pull-up transistor, a first electrode of a seventh pull-down transistor, a first electrode of an eighth pull-down transistor, a first electrode of a third pull-down sustaining transistor, a first electrode of an eleventh inverting transistor, a first electrode of a twelfth inverting transistor, a first electrode of a thirteenth inverting transistor, a first electrode of a fourteenth inverting transistor, a first electrode of a fifteenth inverting transistor, a first electrode of a sixteenth inverting transistor, a first electrode of a third anti-negative bias transistor, a second electrode of a seventh pull-up control transistor, a second electrode of a fifth pull-up transistor, a second electrode of a seventh pull-down transistor, a second electrode of an eighth pull-down transistor, a second electrode of a third pull-down sustaining transistor, a second electrode of an eleventh inverting transistor, a second electrode of a twelfth inverting transistor, a second electrode of a thirteenth inverting transistor, a second electrode of a fourteenth inverting transistor, a second electrode of a fifteenth inverting transistor, a second electrode of a sixteenth inverting transistor, and a second electrode of a third anti-negative bias transistor. The first electrodes of the thirteenth and fourteenth inverting transistors are arranged sequentially along the second direction. The first electrodes of the eleventh inverting transistor, the eighth pull-down transistor, the fifteenth inverting transistor, the sixteenth inverting transistor, and the seventh pull-up control transistor are arranged sequentially along the second direction. The first electrodes of the twelfth inverting transistor, the third pull-down holding transistor, the third anti-negative bias transistor, and the seventh pull-up control transistor are arranged sequentially along the second direction. The second portion of the first plate of the third capacitor and the first electrode of the fifth pull-up transistor are arranged along the second direction. The first plate of the fourth capacitor, the first electrode of the thirteenth inverting transistor, the first electrode of the eleventh inverting transistor, the first electrode of the twelfth inverting transistor, the third portion of the second low-potential signal line, the third portion of the second high-potential signal line, the first electrode of the fifth pull-up transistor, the first electrode of the seventh pull-down transistor, and the third portion of the third low-potential signal line are arranged sequentially along the first direction.

19. The display panel according to any one of claims 1 to 18, characterized in that, The first type of gate circuit, the second type of gate circuit, and the third type of gate circuit are arranged along the first direction. The third type of gate circuit is electrically connected to the second low-potential signal line, the third low-potential signal line, and the second high-potential signal line. In the first direction, at least one of the second low-potential signal line and the second high-potential signal line is disposed between the second type of gate circuit and the third low-potential signal line.

20. The display panel according to claim 19, characterized in that, The third type of gate circuit includes a third pull-down sustaining module, which is electrically connected to the second low-potential signal line; In the first direction, the second low-potential signal line is disposed between the third pull-down sustaining module and the third low-potential signal line.

21. The display panel according to claim 19, characterized in that, The third type of gate circuit includes a third pull-up module, which is electrically connected to the second high-potential signal line; In the first direction, the second high-potential signal line is disposed between the second low-potential signal line and the third pull-up module.

22. The display panel according to claim 19, characterized in that, The third type of gate circuit includes a third pull-down module, which is electrically connected to a third low-potential signal line; In the first direction, the third low-potential signal line is located on the side of the third pull-down module away from the third pull-up module.

23. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 22.

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