Circuit implementation method for improving read-write speed of SRAM (Static Random Access Memory)

Abstract

The invention provides a circuit implementation method for improving the read-write speed of an SRAM (Static Random Access Memory), which belongs to the technical field of circuit design and comprises an SRAM storage unit, the SRAM storage unit comprises a transistor component and an inverter component, the transistor component comprises a transistor I, a transistor II, a transistor III, a transistor IV, a transistor V and a transistor VI, and the inverter component comprises a transistor I, a transistor II, a transistor III, a transistor IV and a transistor IV; the inverter assembly comprises a first inverter and a second inverter. The invention has the beneficial effects that through the improved design of the architecture and the connection mode, the storage units in the same row are enabled during reading and writing, and the storage units in the same column share the data transmission line, so that the control logic of the circuit is simplified, redundant links on a signal transmission path are reduced, and the data transmission efficiency can be effectively improved; and meanwhile, the read-write operation is divided into a plurality of stages, so that different operation stages of different storage units can be simultaneously carried out in one clock period, time resources are fully utilized, and the read-write speed is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and more particularly, to a circuit implementation method for improving the read and write speed of SRAM. Background Art

[0002] With the continuous progress of the times, the demand for storage in applications is also increasing. As a commonly used storage device, SRAM (static random access memory) is widely used in various fields. As the amount of data that applications need to process continues to increase, the read and write speed of storage devices such as SRAM will directly affect the data processing speed.

[0003] In the prior art, in the SRAM read mode, the BL / BLB is pre-charged to the VDD voltage by the peripheral control part. Since one of the two nodes Q / QB in the bitcell (the smallest unit in SRAM that stores 0 / 1 information) is logic high and the other is logic low, when the WL signal is pulled high, one side of the BL / BLB will start to discharge. When a sufficient voltage difference is generated between the BL and BLB, the signal stored in the bitcell can be determined to be logic high or logic low through the subsequent circuit. In the SRAM write mode, the peripheral control part first pulls one side of the BL / BLB low and the other side high. For example, BL is pulled low and BLB is pulled high. Then, after the WL signal is pulled high, the Q node is written with logic low and the QB node is written with logic high, and vice versa. Therefore, in the traditional SRAM architecture, limited by specific process nodes and traditional read and write control timings, it may not be possible to further improve the read and write speed of SRAM. How to invent a circuit implementation method for improving the read and write speed of SRAM to solve these problems has become an urgent problem for those skilled in the art. Summary of the Invention

[0004] To make up for the above deficiencies, the present invention provides a circuit implementation method for improving the read and write speed of SRAM, aiming to solve the problem that in the traditional SRAM architecture, limited by specific process nodes and traditional read and write control timings, it may not be possible to further improve the read and write speed of SRAM.

[0005] The present invention is implemented as follows: The present invention provides a circuit implementation method for improving the read and write speed of SRAM, including: an SRAM storage unit, where the SRAM storage unit includes a transistor component and an inverter component. The transistor component includes transistor one, transistor two, transistor three, transistor four, transistor five, and transistor six. The inverter component includes inverter one and inverter two. Transistor two is connected to RWL1, and RWL1 is connected to RBL1. Transistor three is connected to BL, WWL, and the Q node. Transistor four is connected to BLB and the QB node. Transistor five is connected to RWL2, and RWL2 is connected to RBL2. There are several SRAM storage units, and several SRAM storage units are distributed in an n-row and m-column array. Several SRAM storage units contain multiple memory cells bitcell; In the circuit, RWL1 is the first read word line, RBL1 is the first read bit line, BL is the bit line, WWL is the write word line, BLB is the reverse bit line, RWL2 is the second read word line, and RBL2 is the second read bit line; The specific steps are as follows: S1: During the high-level time of the SRAM input clock, perform the decoding of address 1, select one path to open from RWL11 - RWL1n, and the selected RWL1x is pulled high at the moment when the SRAM input clock changes from high to low. At this time, the address decoding circuit adopts a decoding method that combines parallel and segmented methods to quickly convert the address signal into a row strobe signal; S2: During the low-level time of the SRAM input clock, perform read and write operations on the selected bitcell, read the corresponding data through RBL11 - RBL1m. At the same time, perform the decoding of address 2, select one path to open from RWL21 - RWL2n, and the selected RWL2x is pulled high at the moment when the SRAM input clock changes from low to high; S3: During the time when the SRAM input clock is switched to high level again, perform read and write operations on the currently selected bitcell, read the corresponding data through RBL21 - RBL2m. At the same time, perform the decoding of address 3, select one path to open from RWL11 - RWL1n, and the selected RWL1x is pulled high at the moment when the SRAM input clock changes from high to low; S4: Continuously implement according to the above S1 - S3 pipeline algorithm implementation method until the last address is read, and complete the read and write operations of the entire SRAM.

[0006] Preferably, the source of transistor one is grounded, the drain of transistor one is connected to the source of transistor two, and the gate of transistor one is connected to inverter one, inverter two, and the Q node respectively.

[0007] Preferably, the drain of the second transistor is connected to the first read bit line, and the gate of the second transistor is connected to the first read word line.

[0008] Preferably, the source of the third transistor is connected to the bit line, the gate of the third transistor is connected to the write word line, the drain of the third transistor is connected to the Q node, and the Q node is respectively connected to the output terminal of the first inverter and the input terminal of the second inverter.

[0009] Preferably, the source of the sixth transistor is grounded, the gate of the sixth transistor is respectively connected to the first inverter, the second inverter and the QB node, and the drain of the sixth transistor is connected to the source of the fifth transistor.

[0010] Preferably, the gate of the fifth transistor is connected to the second read word line, and the drain of the fifth transistor is connected to the second read bit line.

[0011] Preferably, the source of the fourth transistor is connected to the inverted bit line, the gate of the fourth transistor is connected to the write word line, the drain of the fourth transistor is connected to the QB node, and the QB node is respectively connected to the input terminal of the first inverter and the output terminal of the second inverter.

[0012] The beneficial effects of the present invention are as follows: Through the improved design of the architecture and connection method, the write word line, the first read word line and the second read word line are short-circuited row by row in the horizontal direction, and the bit line, the inverted bit line, the first read bit line and the second read bit line are short-circuited column by column in the vertical direction. This design allows the storage units in the same row to be enabled simultaneously during reading and writing, and the storage units in the same column share the data transmission line. This not only simplifies the control logic of the circuit, reduces the redundant links on the signal transmission path, but also effectively reduces the signal transmission delay, improves the efficiency of data transmission, and thus speeds up the overall reading and writing speed. At the same time, the pipeline operation mode is adopted, and the reading and writing operations are divided into multiple stages, so that each stage is processed in parallel in different clock cycles. This enables different operation stages of different storage units to be carried out simultaneously in one clock cycle, greatly improving the overall data throughput rate of the SRAM, making full use of time resources, and significantly enhancing the reading and writing speed. Compared with the traditional bitcell unit structure, by using the SRAM bitcell suitable for pipeline as the storage unit and combining the algorithm and timing proposed by the present invention, the reading and writing speed of the SRAM can be effectively improved. Description of the Drawings

[0013] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0014] Figure 1 It is a schematic structural diagram of the SRAM bitcell architecture of a circuit implementation method for improving the read / write speed of SRAM provided by the embodiments of the present invention; Figure 2 It is a schematic structural diagram of the improved structure of the storage unit of a traditional SRAM in a circuit implementation method for improving the read / write speed of SRAM provided by the embodiments of the present invention.

[0015] In the figure: 1, Transistor One; 2, Transistor Two; 3, Transistor Three; 4, Inverter One; 5, Inverter Two; 6, Transistor Four; 7, Transistor Five; 8, Transistor Six. Specific Embodiments

[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0017] Example, referring to Figure 1 - Figure 2 , a circuit implementation method for improving the read / write speed of SRAM, including: an SRAM storage unit, the SRAM storage unit includes a transistor component and an inverter component, the transistor component includes Transistor One 1, Transistor Two 2, Transistor Three 3, Transistor Four 6, Transistor Five 7, and Transistor Six 8, the inverter component includes Inverter One 4 and Inverter Two 5, Transistor Two 2 is connected to RWL1, RWL1 is connected to RBL1, Transistor Three 3 is connected to BL, WWL, and the Q node, Transistor Four 6 is connected to BLB and the QB node, Transistor Five 7 is connected to RWL2, RWL2 is connected to RBL2, there are several SRAM storage units, and several SRAM storage units are arranged in an n-row and m-column array distribution, and several SRAM storage units include multiple storage unit bitcells; In the circuit, RWL1 is the first read word line, RBL1 is the first read bit line, BL is the bit line, WWL is the write word line, BLB is the reverse bit line, RWL2 is the second read word line, and RBL2 is the second read bit line.

[0018] Further, the source of transistor 1 is grounded, the drain of transistor 1 is connected to the source of transistor 2, and the gate of transistor 1 is connected to inverter 1 4, inverter 2 5, and the Q node respectively; the drain of transistor 2 is connected to the first read bit line, and the gate of transistor 2 is connected to the first read word line; the source of transistor 3 is connected to the bit line, the gate of transistor 3 is connected to the write word line, and the drain of transistor 3 is connected to the Q node. The Q node is connected to the output terminal of inverter 1 4 and the input terminal of inverter 2 5 respectively; the source of transistor 3 is connected to the bit line, the gate of transistor 3 is connected to the write word line, and the drain of transistor 3 is connected to the Q node. The Q node is connected to the output terminal of inverter 1 4 and the input terminal of inverter 2 5 respectively; the gate of transistor 7 is connected to the second read word line, and the drain of transistor 7 is connected to the second read bit line; the source of transistor 6 is connected to the inverted bit line, the gate of transistor 6 is connected to the write word line, and the drain of transistor 6 is connected to the QB node. The QB node is connected to the input terminal of inverter 1 4 and the output terminal of inverter 2 5 respectively.

[0019] It should be noted that each memory cell in the memory cell structure is composed of at least a pair of complementary inverters and multiple transistors, and is used to store 1-bit binary data. The transistors include a select transistor for controlling data transmission and a storage transistor for maintaining the data state; the signal lines are connected in the vertical direction. The bit lines (BLx), inverted bit lines (BLBx), first read bit lines (RBL1x), and second read bit lines (RBL2x) of all memory cells are short-circuited by column respectively, and are realized by low-impedance metal wiring to reduce signal transmission delay; the signal lines are connected in the horizontal direction. All write word lines (WWLx), first read word lines (RWL1x), and second read word lines (RWL2x) are short-circuited by row respectively to realize unified read and write control of a row of memory cells. In addition, in terms of the architecture and connection method, the advantages of the row-column shared signal design are as follows: Horizontally, the word write lines (WWLx), the first read word lines (RWL1x), and the second read word lines (RWL2x) are short-circuited by row, and vertically, the bit lines (BLx), the inverted phase lines (BLBx), the first read bit lines (RBL1x), and the second read bit lines (RBL2x) are short-circuited by column. This design allows the storage units in the same row to be enabled simultaneously during read and write operations, and the storage units in the same column share the data transmission lines. This not only simplifies the control logic of the circuit, reduces the redundant links in the signal transmission path, but also effectively reduces the signal transmission delay, improves the efficiency of data transmission, and thus speeds up the overall read and write speed; Using low-impedance metal wires for signal line connection can significantly reduce the resistance and capacitance effects of the signal during transmission. The resistance effect will cause a voltage drop in the signal during transmission, and the capacitance effect will cause signal delay and distortion. By reducing the influence of these effects, the integrity and fast transmission of the signal are ensured, providing a basic guarantee for high-speed read and write operations.

[0020] Refer to Figure 2 , further; within the high-level time of the SRAM input clock, the decoding of address 1 is performed, and one path is selected and opened from RWL11 - RWL1n, and the selected RWL1x is pulled high at the moment when the SRAM input clock changes from high to low. At this time, the address decoding circuit adopts a decoding method that combines parallel and segmented decoding to quickly convert the address signal into a row strobe signal; within the low-level time of the SRAM input clock, read and write operations are performed on the selected bitcell, and the corresponding data is read out through RBL11 - RBL1m. At the same time, the decoding of address 2 is performed, and one path is selected and opened from RWL21 - RWL2n, and the selected RWL2x is pulled high at the moment when the SRAM input clock changes from low to high; within the time when the SRAM input clock changes back to high level again, read and write operations are performed on the currently selected bitcell, and the corresponding data is read out through RBL21 - RBL2m. At the same time, the decoding of address 3 is performed, and one path is selected and opened from RWL11 - RWL1n, and the selected RWL1x is pulled high at the moment when the SRAM input clock changes from high to low; The above S1 - S3 pipeline algorithm implementation method is continuously carried out until the last address is read out, and the entire SRAM read and write operation is completed.

[0021] It should be noted that: By adopting the pipeline operation mode, the read and write operations are divided into multiple stages, such as address decoding, data reading, data writing, etc. Each stage is processed in parallel in different clock cycles, which enables different operation stages of different storage units to be carried out simultaneously within one clock cycle, greatly improving the overall data throughput rate of the SRAM. For example, while reading data from one storage unit, operations such as address decoding can be performed on another storage unit, making full use of the time resource and significantly enhancing the read and write speed; Advantages of address decoding and read / write control: The address decoding circuit adopts a decoding method combining parallel and segmented methods, which can quickly and accurately convert the address signal into a row select signal, reducing the time delay of address decoding. During the read and write operations, the sense amplifier is equipped with a dynamic threshold adjustment circuit, which can dynamically adjust the threshold voltage according to the amplitude of the read bit line signal and the noise level, improving the detection accuracy and response speed. The sense amplifier has a high-speed differential amplification structure and a dynamic threshold adjustment circuit, which can quickly detect and amplify the weak read bit line signal and accurately judge the data state of the storage unit. The write data driver circuit has sufficient driving ability and is equipped with a write equalization circuit to ensure the signal consistency between the bit line and the anti-phase line. All of these ensure that the read and write operations can be carried out quickly and reliably; In addition, the inverters in the storage unit can adopt a high-speed and low-power structure. The transistor size and threshold voltage are precisely optimized, and the internal signal transmission path is optimized in layout to shorten the signal transmission distance and reduce the influence of parasitic parameters. The transistors in the storage unit can adopt new transistor structures such as Fin-FET or GAA-FET to improve the transistor switching speed and driving ability and reduce the parasitic capacitance and leakage current. The advanced transistor structure and precisely optimized inverters are adopted in the storage unit. The new transistor structure has a faster switching speed and a stronger driving ability, which can complete the data storage and transmission operations in a shorter time. At the same time, the transistor size and threshold voltage of the inverter are optimized, reducing the power consumption while ensuring sufficient driving ability, achieving a good balance between speed and power consumption, enabling the storage unit to quickly respond to the read and write signals and enhancing the read and write performance of the SRAM. The internal signal transmission path of the storage unit is carefully optimized in layout, minimizing the signal transmission distance and reducing the influence of parasitic capacitance and inductance. Parasitic parameters will increase the signal transmission delay and power consumption. By reducing these parasitic effects, the propagation speed of the signal inside the storage unit can be effectively increased, further accelerating the execution of the read and write operations.

[0022] It should be noted that the specific model specifications need to be selected and determined according to the actual specifications of the device, etc. The specific selection calculation method adopts the existing technology in this field, so it will not be elaborated in detail.

[0023] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A circuit implementation method for improving the read and write speed of SRAM, comprising: An SRAM storage unit, characterized in that the SRAM storage unit comprises a transistor component and an inverter component, the transistor component comprises a transistor 1 (1), a transistor 2 (2), a transistor 3 (3), a transistor 4 (6), a transistor 5 (7) and a transistor 6 (8), the inverter component comprises an inverter 1 (4) and an inverter 2 (5), the transistor 2 (2) is connected to RWL1, the RWL1 is connected to RBL1, the transistor 3 (3) is connected to BL, WWL and Q nodes, the transistor 4 (6) is connected to BLB and QB nodes, the transistor 5 (7) is connected to RWL2, the RWL2 is connected to RBL2, a plurality of the SRAM storage units are provided, the plurality of the SRAM storage units are distributed in an array of n rows and m columns, and the plurality of the SRAM storage units contain a plurality of storage unit bitcells; In the circuit, RWL1 is the first read word line, RBL1 is the first read bit line, BL is the bit line, WWL is the write word line, BLB is the reverse bit line, RWL2 is the second read word line, and RBL2 is the second read bit line; The specific steps are as follows: S1: During the high level time of the SRAM input clock, address 1 is decoded, one channel is selected from RWL11-RWL1n to be turned on, and the selected RWL1x is pulled high when the SRAM input clock switches from high to low. At this time, the address decoding circuit adopts a decoding method combining parallel and segmented decoding to quickly convert the address signal into a row selection signal; S2: During the low level time of the SRAM input clock, the selected bitcell is read and written, and the corresponding data is read out through RBL11-RBL1m. At the same time, address 2 is decoded and one channel is selected from RWL21-RWL2n to be opened. The selected RWL2x is pulled high when the SRAM input clock switches from low to high; S3: During the time when the SRAM input clock switches to high level again, the currently selected bitcell is read and written, and the corresponding data is read out through RBL21-RBL2m. At the same time, address 3 is decoded, and one channel is selected from RWL11-RWL1n to be opened. The selected RWL1x is pulled high when the SRAM input clock switches from high to low; S4: Continue according to the above S1-S3 pipeline algorithm implementation method until the last address is read, completing the read and write operations of the entire SRAM.

2. A circuit implementation method for improving SRAM read and write speed according to claim 1, characterized in that: The source of the transistor one (1) is grounded, the drain of the transistor one (1) is connected to the source of the transistor two (2), and the gate of the transistor one (1) is connected to the inverter one (4), the inverter two (5) and the Q node respectively.

3. A circuit implementation method for improving SRAM read and write speed according to claim 1, characterized in that: The drain of the transistor 2 (2) is connected to the first read bit line, and the gate of the transistor 2 (2) is connected to the first read word line.

4. A circuit implementation method for improving SRAM read and write speed according to claim 1, characterized in that: The source of the transistor three (3) is connected to the bit line, the gate of the transistor three (3) is connected to the write word line, the drain of the transistor three (3) is connected to the Q node, and the Q node is respectively connected to the output end of the inverter one (4) and the input end of the inverter two (5).

5. A circuit implementation method for improving SRAM read and write speed according to claim 1, characterized in that: The source of the transistor six (8) is grounded, the gate of the transistor six (8) is connected to the inverter one (4), the inverter two (5) and the QB node respectively, and the drain of the transistor six (8) is connected to the source of the transistor five (7).

6. A circuit implementation method for improving SRAM read and write speed according to claim 1, characterized in that: The gate of the transistor five (7) is connected to the second read word line, and the drain of the transistor five (7) is connected to the second read bit line.

7. A circuit implementation method for improving SRAM read and write speed according to claim 1, characterized in that: The source of the transistor four (6) is connected to the inverting bit line, the gate of the transistor four (6) is connected to the write word line, the drain of the transistor four (6) is connected to the QB node, and the QB node is respectively connected to the input end of the inverter one (4) and the output end of the inverter two (5).

Images