Memory and electronic equipment

Abstract

The invention discloses a memory and an electronic device, the memory comprises a digital line, a local bit line, a memory cell, a bit line and a word line connected with the memory cell, a first gate transistor and a second gate transistor, at least one of the first gate transistor and the second gate transistor is configured to be a P-channel transistor, and the first gate transistor and the second gate transistor are configured to be P-channel transistors. Compared with the first gating transistor and the second gating transistor which are both N-channel transistors, the equivalent parasitic capacitance of the bit line can be reduced at the moment of conduction of the memory unit, so that the duration time of overshoot current is shortened.

Description

Technical Field

[0001] This application relates to the field of storage technologies, and in particular, to a memory and an electronic device. Background Art

[0002] Phase change memory (PCM) utilizes the reversible conversion characteristics between the crystalline state and the amorphous state of phase change materials under different heat amounts to achieve data storage. For example, when the storage cell is in the crystalline state, the data stored in it is "1"; when the storage cell is in the amorphous state, the data stored in it is "0".

[0003] However, since the turn-on time of the storage cell cannot be predicted, it is difficult to suppress the overshoot energy brought about by the moment when the storage cell is turned on, which increases the interference factors of the operation and thus affects the performance of the memory. Summary of the Invention

[0004] This application provides a memory and an electronic device to alleviate the technical problem of the long duration of the overshoot current when the storage cell is turned on.

[0005] In a first aspect, this application provides a memory, which includes a digital line, a local bit line, storage cells distributed in an array, a bit line and a word line connected to each storage cell, a first select transistor, and a second select transistor. The first pole of the first select transistor is connected to the bit line, the second pole of the first select transistor is connected to the local bit line, and the gate of the first select transistor is connected to the first select line; the first pole of the second select transistor is connected to the local bit line, the second pole of the second select transistor is connected to the digital line, and the gate of the second select transistor is connected to the second select line; wherein, at least one of the first select transistor and the second select transistor is a P-channel transistor.

[0006] In a second aspect, this application provides an electronic device, which includes the above-mentioned memory.

[0007] For the memory and the electronic device provided in this application, by configuring at least one of the first select transistor and the second select transistor as a P-channel transistor, compared with the case where both the first select transistor and the second select transistor are N-channel transistors, the equivalent parasitic capacitance of the bit line can be reduced at the moment when the storage cell is turned on, thereby shortening the duration of the overshoot current. Description of the Drawings

[0008] The following will make the technical solutions and other beneficial effects of this application obvious by describing the specific embodiments of this application in detail in conjunction with the drawings.

[0009] Figure 1 It is a first structural schematic diagram of a memory in the related art.

[0010] Figure 2 It is a schematic diagram of the equivalent circuit of a memory cell in the related art.

[0011] Figure 3 It is a schematic diagram of the threshold voltage distribution of a memory cell in the related art.

[0012] Figure 4 It is a schematic diagram of the change in the threshold voltage of a memory cell in the related art.

[0013] Figure 5 It is a schematic diagram of the comparative change in the threshold voltage of a memory cell in the related art.

[0014] Figure 6 It is a schematic diagram of the comparative distribution of the threshold voltage of a memory cell in the related art.

[0015] Figure 7 It is a schematic diagram of the compensation of time current in the related art.

[0016] Figure 8 It is a schematic diagram of the second structure of a memory in the related art.

[0017] Figure 9 It is a schematic diagram of the first structure of the memory provided by the embodiments of the present application.

[0018] Figure 10 It is a schematic diagram of the second structure of the memory provided by the embodiments of the present application.

[0019] Figure 11 It is a schematic diagram of the third structure of the memory provided by the embodiments of the present application. Detailed implementation manners

[0020] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application.

[0021] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0022] Figure 1It is a schematic diagram of the first structure of a memory in the related art. The memory includes a bit line BL, a word line WL, a memory array, a word line gating circuit 20, and a bit line gating circuit 10. The memory array includes memory cells Mcell distributed in an array. The bit line BL includes, for example, a first bit line BL1, a second bit line BL2, and a third bit line BL3, etc. The word line WL includes, for example, a first word line WL1, a second word line W2L, and a third word line WL3, etc. Each memory cell Mcell is connected to the bit line gating circuit 10 through the bit line BL, and each memory cell Mcell is connected to the word line gating circuit 20 through the word line WL.

[0023] Figure 2 It is a schematic diagram of the equivalent circuit of the memory cell Mcell in the related art. Among them, the first parasitic resistance Rwl is the parasitic resistance of the word line WL. The second parasitic resistance Rbl is the parasitic resistance of the bit line BL. The first parasitic capacitance Cwl is the parasitic capacitance of the word line WL. The second parasitic capacitance Cbl is the parasitic capacitance of the bit line BL. Vwl represents the voltage of the word line WL, and Vwl` represents the voltage of the word line WL considering the parasitic capacitance impedance. Vbl represents the voltage of the bit line BL, and Vbl` represents the voltage of the bit line BL considering the parasitic capacitance impedance.

[0024] As Figure 3 shown, Coutner represents the number of memory cells Mcell in the memory, and Vth represents the threshold voltage of the memory cell Mcell. When the memory cell Mcell in the phase change memory is in the crystalline state and the non-crystalline state, it corresponds to different threshold voltages. Among them, the threshold voltage (Vth_SET) of the memory cell Mcell in the crystalline state is less than the threshold voltage (Vth_RESET) of the memory cell Mcell in the non-crystalline state.

[0025] By applying different forms of heat, the conversion of the memory cell Mcell between the crystalline state and the non-crystalline state can be achieved. Among them, the programming operation of writing "1" to the memory cell Mcell is defined as the set (SET) operation, and the programming operation of writing "0" to the memory cell Mcell is defined as the reset (RESET) operation. By applying a read voltage (Vread) greater than Vth_SET and less than Vth_RESET to the selected memory cell Mcell, the memory cell Mcell in the crystalline state can be opened, but the memory cell Mcell in the non-crystalline state cannot be opened, and thus the data reading operation of the memory cell Mcell can be completed.

[0026] The memory cell Mcell includes a bidirectional threshold switch (Ovonic Threshold Switch, OTS), which is made of a volatile non-linear resistive switching material. This material can suddenly switch from a high-resistance state to a low-resistance state under the action of a threshold voltage. In order to maintain its low-resistance state characteristics, it is necessary to satisfy that its conduction voltage (current) is greater than a certain specific value, which is generally defined as Vhold (Ihold). Due to the above characteristics of this material, its easy integration, and the fact that these characteristics do not change as the process node continues to shrink, it has become the core device of three-dimensional phase change memory.

[0027] Three-dimensional phase change memory generally refers to the 3D Cross point PCM or 3D X-point PCM storage where planar cross arrays are stacked in multiple layers. Its memory cell Mcell is a 1T1R structure achieved by integrating a phase change material and a bidirectional threshold switch in layers, and it has characteristics such as scalability and stackability.

[0028] Due to the characteristic that the threshold voltage of the bidirectional threshold switch shifts with the applied voltage polarity, subsequently, the storage based on the selector only memory (OTS-only memory) with a dual threshold switch has also become another technical direction of storage.

[0029] After the wafer on which the memory array is located is shipped out of the factory (Fab-out), excluding the influence of the underlying complementary metal oxide semiconductor (CMOS) used as a driver and the flatness that may be introduced by operations such as via holes in the lower layer, the threshold voltages of all memory cells Mcell are uniformly distributed. In other words, the normal distribution curve of the threshold voltage of the initial memory cell Mcell should only be related to each production step during its production process, and there will be no situation where the threshold voltage is inconsistent due to different physical positions. This physical position refers to the distance position between the memory cell Mcell and the word line selection circuit 20 and / or the bit line selection circuit 10.

[0030] As Figure 4 shown, the threshold voltage (Vth_inital) of the initial memory cell Mcell is too high to be directly used and needs to go through a seasoning (forming / first fire) process for a period of time to reach the relatively saturated and stable Vth_SET and Vth_RESET that can be normally programmed and read / written. This seasoning process is usually achieved by applying a certain number of reset (RESET) voltages, currents, and times that are much higher than normal operations to the memory cell Mcell. In some cases, a small amount of set (SET) operations may also be superimposed to quickly saturate Vth_SET and Vth_RESET.

[0031] The material properties of current phase change memories determine that the threshold voltage after seasoning is only relatively saturated, and the threshold voltage (Vth) of the memory cell Mcell will still slowly decrease as the number of operations (Cycle) increases. This process will continue throughout the entire cycle of the memory cell Mcell, and the rate of decrease of its threshold voltage will gradually slow down.

[0032] The energy (E) generated during the programming process of the memory cell Mcell consists of two parts. One part comes from the inrush current at the moment when the memory cell Mcell is turned on, and the other part comes from the set DC current. The calculation method of E is shown in Equation 1-1:

[0033]

[0034] Among them, R on represents the on-resistance of the memory cell Mcell. I inrush represents the inrush current, and t inrush represents the duration of the inrush current. I DC represents the DC current, and t DC represents the duration of the DC current.

[0035] The inrush current at time 0 can be approximately expressed by Equation 1-2 as follows:

[0036]

[0037] Among them, V` wlt0- represents the word line WL voltage at time 0 negative. V` blt0- represents the bit line BL voltage at time 0 negative. V` wlt0 represents the word line WL voltage at time 0. V` blt0 represents the bit line BL voltage at time 0. λ is a constant.

[0038] The inrush current at time t can be approximately expressed by Equation 1-3 as follows:

[0039]

[0040] By transforming Equation 1-3, the approximate formula 1-4 for the duration of the inrush current is obtained as follows:

[0041]

[0042] Among them,

[0043] Among them, since both the DC current and its duration are determined by different chips TBD (Trim by die). From the above expressions, it can be seen that the overshoot energy is directly related to the equivalent parasitic resistance capacitance of the word line WL and the bit line BL. For the memory cell Mcell far from the bit line strobe circuit 10 or the word line strobe circuit 20, the parasitic resistance is small, so the overshoot current is small. If the same DC current and its duration are adopted, the energy will necessarily be different.

[0044] As Figure 5 shown, this will cause the decreasing trend of the threshold voltage of the memory cell Mcell far from the bit line strobe circuit 10 or the word line strobe circuit 20 in the memory array to be as shown by the first curve S1, while the decreasing trend of the threshold voltage of the memory cell Mcell close to the bit line strobe circuit 10 or the word line strobe circuit 20 is as shown by the second curve S2.

[0045] As Figure 6 shown, Vth_near on the left side of the read voltage (Vread) represents the normal distribution curve of the threshold voltage of the memory cell Mcell in the set state close to the bit line strobe circuit 10 or the word line strobe circuit 20. Vth_far on the left side of the read voltage (Vread) represents the normal distribution curve of the threshold voltage of the memory cell Mcell in the set state far from the bit line strobe circuit 10 or the word line strobe circuit 20. Vth_near on the right side of the read voltage (Vread) represents the normal distribution curve of the threshold voltage of the memory cell Mcell in the reset state close to the bit line strobe circuit 10 or the word line strobe circuit 20. Vth_far on the right side of the read voltage (Vread) represents the normal distribution curve of the threshold voltage of the memory cell Mcell in the reset state far from the bit line strobe circuit 10 or the word line strobe circuit 20.

[0046] Figure 5 The different decreasing trends of the threshold voltage of the memory cell Mcell shown in Figure 6 will cause the read window loss shown, that is, RWM-loss, which will further affect the read accuracy. Therefore, to ensure that the total operation energy remains unchanged, it is necessary to perform position compensation on the memory cell Mcell to ensure that the operation energy of the memory cells Mcell at each position is as equal as possible.

[0047] Since seasoning is also a programming operation with stronger energy, it is also necessary to keep the energy of the far end and the near end as consistent as possible during the seasoning stage, otherwise it will also introduce different threshold voltages at different positions similar to the programming stage.

[0048] The energy of the overshoot current is large, so the DC current in the reset state of TBD can be reduced somewhat, which seems to be beneficial from the perspective of power consumption. However, an excessive overshoot current will cause a higher energy to be generated instantaneously, which will in turn cause read disturb and write disturb, thus affecting the memory performance.

[0049] The energy of the overshoot current is large, and the excessive instantaneous heat will also cause the crystallization time to increase during the crystallization operation. The programming time is determined by the crystallization time, which will in turn cause a write delay.

[0050] In addition, continuously impacting the memory cell Mcell with a large current density will also cause segregation of elements in the OTS. For example, it has been observed in Ge-Se compounds that as the number of operations increases, the concentration of the Se element that inhibits crystallization will decrease, resulting in a continuous decrease in the threshold voltage as the number of operations increases, and the endurance decreases, and this effect is irreversible.

[0051] Figure 7 It is a schematic diagram of time-current compensation in the related art. Among them, the third curve S3 represents the change curve of the current pulse received by the memory cell Mcell closer to the bit line selection circuit 10 or the word line selection circuit 20, and the fourth curve S4 represents the change curve of the current pulse received by the memory cell Mcell farther from the bit line selection circuit 10 or the word line selection circuit 20. Among them, △I represents the current difference between the third curve S3 and the fourth curve S4, and △t represents the time difference between the third curve S3 and the fourth curve S4.

[0052] In order to balance the current pulses received by the memory cells Mcell at each position, it can be achieved by at least one of the above current difference and time difference.

[0053] Figure 8 It is a schematic diagram of the second structure of the memory in the related art. The memory includes a digital line DL, a local bit line LBL, a memory cell Mcell, a bit line BL and a word line WL connected to the memory cell Mcell, a first selection transistor T1 and a second selection transistor T2. The first pole of the first selection transistor T1 is connected to the bit line BL, the second pole of the first selection transistor T1 is connected to the local bit line LBL, the first pole of the second selection transistor T2 is connected to the local bit line LBL, the second pole of the second selection transistor T2 is connected to the digital line DL, and both the first selection transistor T1 and the second selection transistor T2 are N-channel transistors.

[0054] It should be noted that Figure 8 The working process of the shown memory is as follows:

[0055] Before a certain memory cell Mcell is selected, the voltage of bit line BL is exemplarily V1, and the voltages of local bit line LBL and digital line DL are both exemplarily V1 or V2, where V1 is greater than V2, V2 is a negative voltage, and the gate voltages of first select transistor T1 and second select transistor T2 are both exemplarily V1 or V2. Then, the gate-source voltage differences (Vgs) of first select transistor T1 and second select transistor T2 are both less than or equal to V1. Since the threshold voltage (Vth_N) of an N-channel transistor is positive and Vth_N is greater than V1, the gate-source voltage differences (Vgs) of first select transistor T1 and second select transistor T2 are both less than their own threshold voltages and thus in an off state.

[0056] After the memory cell Mcell is selected, the gate voltages of first select transistor T1 and second select transistor T2 are both exemplarily V1 (indicating that the corresponding memory cell Mcell is selected). At this time, the voltage of digital line DL is Vneg (V2). Then, the Vgs of second select transistor T2 is greater than its own Vth_N, so second select transistor T2 conducts, and the drain voltage of second select transistor T2 is pulled to the same voltage as its source voltage, i.e., Vneg. Similarly, first select transistor T1 conducts, and the drain voltage of first select transistor T1 is pulled to the same voltage as its source voltage, i.e., Vneg.

[0057] Thereafter, the voltage of word line WL rises to reach the threshold voltage of memory cell Mcell, and memory cell Mcell is turned on, and the read and write operations on memory cell Mcell start. During this process, since first select transistor T1 and second select transistor T2 are conducting after memory cell Mcell is selected, the equivalent parasitic capacitance of bit line BL is equivalent to the equivalent series capacitance of Cbl, Clbl, and Cdl, which increases the equivalent parasitic capacitance of bit line BL, so that the duration of the overshoot energy is longer when memory cell Mcell is turned on instantaneously.

[0058] This embodiment provides a memory, please refer to Figures 9 to 11, the memory includes a digital line DL, a local bit line LBL, memory cells Mcell distributed in an array, a bit line BL and a word line WL connected to each memory cell Mcell, a first select transistor T1, and a second select transistor T2. A first pole of the first select transistor T1 is connected to the bit line BL, a second pole of the first select transistor T1 is connected to the local bit line LBL, and a gate of the first select transistor T1 is connected to a first select line SL1; A first pole of the second select transistor T2 is connected to the local bit line LBL, a second pole of the second select transistor T2 is connected to the digital line DL, and a gate of the second select transistor T2 is connected to a second select line SL2; Wherein, at least one of the first select transistor T1 and the second select transistor T2 is a P-channel transistor.

[0059] It can be understood that, for the memory provided in this embodiment, by configuring at least one of the first select transistor T1 and the second select transistor T2 as a P-channel transistor, compared with the case where both the first select transistor T1 and the second select transistor T2 are N-channel transistors, the equivalent parasitic capacitance of the bit line BL can be reduced at the moment when the memory cell Mcell is turned on, thereby shortening the duration of the overshoot current.

[0060] In some embodiments, such as Figure 9 , Figure 10 shown, the channel type of the first select transistor T1 is different from the channel type of the second select transistor T2.

[0061] It should be noted that by configuring the channel type of the first select transistor T1 to be different from the channel type of the second select transistor T2, compared with the case where both the first select transistor T1 and the second select transistor T2 are N-channel transistors, the equivalent parasitic capacitance of the bit line BL can be reduced at the moment when the memory cell Mcell is turned on, thereby shortening the duration of the overshoot current.

[0062] In some embodiments, such as Figure 9 shown, the first select transistor T1 is an N-channel transistor, and the second select transistor T2 is a P-channel transistor; The drain of the first select transistor T1 is connected to the bit line BL, and the source of the first select transistor T1 is connected to the local bit line LBL; The source of the second select transistor T2 is connected to the local bit line LBL, and the drain of the second select transistor T2 is connected to the digital line DL.

[0063] It should be noted that before a certain memory cell Mcell is selected, the Vgs of the second select transistor T2 is less than the absolute value of its own threshold voltage and is in an off state. The Vgs of the first select transistor T1 is less than its own threshold voltage. Therefore, the first select transistor T1 is in an off state.

[0064] After the storage cell Mcell is selected, the gate voltage of the second select transistor T2 is Vneg(V2), the source voltage of the second select transistor T2 is V1, and |Vgs| of the second select transistor T2 = |V2 - V1|, which is greater than the absolute value of its own threshold voltage. Therefore, the second select transistor T2 conducts. Since the voltage of the digital line DL is Vneg, the voltage of the local bit line LBL, i.e., the source voltage of the second select transistor T2, is pulled to Vneg + |Vth_P|. |Vgs| of the second select transistor T2 = |V2 - (Vneg + |Vth_P|)|, which is equal to the absolute value of its own threshold voltage, and the second select transistor T2 is almost in an off state.

[0065] The gate voltage of the first select transistor T1 is V1, the source voltage of the first select transistor T1 is Vneg + |Vth_P|, then Vgs of the first select transistor T1 = V1 - (Vneg + |Vth_P|), which is greater than its own threshold voltage, and the first select transistor T1 conducts. The voltage of the bit line BL, i.e., the drain voltage of the first select transistor T1, is pulled to the same source voltage, i.e., Vneg + |Vth_P|. This makes Cbl not connected in series with Cdl, and the equivalent parasitic capacitance of the bit line BL is Cbl + Clbl. Compared with the equivalent parasitic capacitance Figure 8 in, the equivalent parasitic capacitance is reduced, and thus the duration of the overshoot current is also shortened.

[0066] As the voltage of the word line WL rises, when it reaches the threshold voltage of the storage cell Mcell, the storage cell Mcell turns on, and the voltage of the bit line BL will rise rapidly. As a result, the source voltage of the second select transistor T2 also starts to rise. When |Vgs| of the second select transistor T2 is greater than |Vth_P| of the second select transistor T2, the second select transistor T2 automatically conducts and starts to read and write the storage cell Mcell. This shows that although the channel type of the corresponding transistor is changed, its normal operation is not affected.

[0067] In some of these embodiments, as Figure 10 shown, the first select transistor T1 is a P-channel transistor, and the second select transistor T2 is an N-channel transistor; the source of the first select transistor T1 is connected to the bit line BL, and the drain of the first select transistor T1 is connected to the local bit line LBL; the drain of the second select transistor T2 is connected to the local bit line LBL, and the source of the second select transistor T2 is connected to the digital line DL.

[0068] It should be noted that, before a certain memory cell Mcell is selected, the voltage of the bit line BL is exemplarily V1, the source voltage of the first select transistor T1 is also V1, the gate voltage of the first select transistor T1 is V1, and the Vgs of the first select transistor T1 is less than the absolute value of its own threshold voltage, that is, |Vth_P|. Therefore, the first select transistor T1 is in an off state. The gate voltage of the second select transistor T2 is Vneg(V2). The voltage of the digital line DL is Vneg, and the source voltage of the second select transistor T2 is also Vneg. Therefore, the Vgs of the second select transistor T2 is less than its own threshold voltage and is in an off state.

[0069] After the memory cell Mcell is selected, the gate voltage of the second select transistor T2 is V1, the voltage of the digital line DL is Vneg, and the source voltage of the second select transistor T2 is also Vneg(V2). The Vgs of the second select transistor T2 = V1 - V2, which is greater than its own threshold voltage. Therefore, the second select transistor T2 conducts, and the voltage of the local bit line LBL, that is, the drain voltage of the second select transistor T2, is pulled to Vneg. The gate voltage of the first select transistor T1 is V2, and the source voltage of the first select transistor T1 is V1. Then, |Vgs| of the first select transistor T1 = |V2 - V1|, which is greater than the absolute value of its own threshold voltage. The first select transistor T1 conducts, and the voltage of the bit line BL, that is, the source voltage of the first select transistor T1, is pulled down to Vneg + |Vth_P|. At this time, |Vgs| of the first select transistor T1 = |V2 - (Vneg + |Vth_P|)|, which is equal to the absolute value of its own threshold voltage. The first select transistor T1 is almost in an off state. This makes Cbl not connected in series with Clbl and Cdl, and the equivalent parasitic capacitance of the bit line BL is Cbl, compared with the equivalent parasitic capacitance Figure 8 in, the equivalent parasitic capacitance is reduced, and thus the duration of the overshoot current is also shortened.

[0070] As the voltage of the word line WL rises, when it reaches the threshold voltage of the memory cell Mcell, the memory cell Mcell is turned on, and the voltage of the bit line BL will rise rapidly. Consequently, the source voltage of the first select transistor T1 also starts to surge. When |Vgs| of the first select transistor T1 is greater than |Vth_P| of the first select transistor T1, the first select transistor T1 automatically conducts and starts the read / write operation on the memory cell Mcell. This shows that although the channel type of the corresponding transistor is changed, its normal operation is not affected.

[0071] In some of these embodiments, such as Figure 10As shown, the memory further includes a third transistor T3. The first pole of the third transistor T3 is connected to the bit line BL. The second pole of the third transistor T3 is connected to the initialization voltage line VSS. The gate of the third transistor T3 is connected to the third select line SL3.

[0072] It should be noted that before a certain memory cell Mcell is selected, the voltage of the initialization voltage line VSS can be exemplarily V1. The source voltage of the third transistor T3 is V1, and the gate voltage of the third transistor T3 is Vneg(V2). Then, |Vgs| of the third transistor T3 = |V2 - V1|, which is greater than |Vth_P| of the third transistor T3. The third transistor T3 is turned on, and the voltage of the bit line BL is V1. In this way, an initial state voltage can be provided for the bit line BL through the third transistor T3 to ensure that the unselected memory cell Mcell will not be mis-conducted due to the floating voltage of the bit line BL.

[0073] After the memory cell Mcell is selected, the gate voltage of the third transistor T3 is V1. Then, |Vgs| of the third transistor T3 is less than |Vth_P| = 0.7V of the third transistor T3, and the third transistor T3 is turned off.

[0074] The conduction time of the third transistor T3 is earlier than that of the first select transistor T1. Optionally, the channel type of the third transistor T3 is the same as that of the first select transistor T1. For example, both are P-channel transistors.

[0075] In some embodiments, as Figure 11 shown, the first select transistor T1 is a P-channel transistor, and the second select transistor T2 is a P-channel transistor. The source of the first select transistor T1 is connected to the bit line BL, and the drain of the first select transistor T1 is connected to the local bit line LBL. The source of the second select transistor T2 is connected to the local bit line LBL, and the drain of the second select transistor T2 is connected to the digital line DL.

[0076] It should be noted that before selecting a certain memory cell Mcell, the voltage of the initialization voltage line VSS can be exemplarily V1. The source voltage of the third transistor T3 is V1, and the gate voltage of the third transistor T3 is Vneg(V2). Then, |Vgs| of the third transistor T3 = |V2 - V1|, which is greater than |Vth_P| of the third transistor T3. The third transistor T3 is turned on, and the voltage of the bit line BL is V1. The source voltage of the first select transistor T1 is also V1, and the gate voltage of the first select transistor T1 is V1. The Vgs of the first select transistor T1 is less than the absolute value of its own threshold voltage, that is, |Vth_P|. Therefore, the first select transistor T1 is in an off state. The gate voltage of the second select transistor T2 is V1, and the source voltage of the second select transistor T2 is V1. Therefore, the Vgs of the second select transistor T2 is less than the absolute value of its own threshold voltage and is in an off state.

[0077] After the memory cell Mcell is selected, the gate voltage of the third transistor T3 is V1. Then, |Vgs| of the third transistor T3 is less than |Vth_P| of the third transistor T3, and the third transistor T3 is turned off.

[0078] The gate voltage of the second select transistor T2 is Vneg(V2), and the source voltage of the second select transistor T2 is V1. |Vgs| of the second select transistor T2 = |V2 - V1|, which is greater than its own threshold voltage, that is, |Vth_P|. Therefore, the second select transistor T2 is turned on. Since the voltage of the digital line DL is Vneg, the voltage of the local bit line LBL, that is, the source voltage of the second select transistor T2, is pulled to Vneg + |Vth_P|. At this time, |Vgs| of the second select transistor T2 = |V2 - (Vneg + |Vth_P|)|, which is equal to the absolute value of its own threshold voltage. The second select transistor T2 is almost in an off state. This makes Cbl not connected in series with Cdl, and the equivalent parasitic capacitance of the bit line BL is Cbl + Clbl, compared with the equivalent parasitic capacitance Figure 8 in [reference], the equivalent parasitic capacitance is reduced, so the duration of the overshoot current is also shortened.

[0079] The gate voltage of the first select transistor T1 is V2, and the source voltage of the first select transistor T1 is V1. Then, for the first select transistor T1, |Vgs| = |V2 - V1|, which is greater than the absolute value of its own threshold voltage. The first select transistor T1 conducts. Since the drain voltage of the first select transistor T1 is Vneg + |Vth_P|, the voltage of the bit line BL, i.e., the source voltage of the first select transistor T1, is pulled down to Vneg + |Vth_P| + |Vth_P| = Vneg + 2|Vth_P|. At this time, for the first select transistor T1, |Vgs| = |V2 - (Vneg + 2|Vth_P|)| = 1.4V, which is greater than the absolute value of its own threshold voltage, and the first select transistor conducts.

[0080] As the voltage of the word line WL rises, when it reaches the threshold voltage of the memory cell Mcell, the memory cell Mcell is turned on, and the voltage of the bit line BL will rise rapidly. Consequently, the source voltage of the first select transistor T1 also starts to increase. When |Vgs| of the first select transistor T1 is greater than |Vth_P| of the first select transistor T1, the first select transistor T1 automatically conducts. Then, the source voltage of the second select transistor T2 starts to increase. When |Vgs| of the second select transistor T2 is greater than |Vth_P| of the second select transistor T2, the second select transistor T2 automatically conducts, and the read / write operation of the memory cell Mcell starts. This shows that although the channel type of the corresponding transistor is changed, its normal operation is not affected.

[0081] In some of these embodiments, as Figure 11 shown, the memory further includes a control module 30, and the control module 30 is connected to the digital line DL. The control module 30 is configured to have the control logic of the digital line DL to perform corresponding compensation in terms of current and / or time.

[0082] It should be noted that in Figures 8 to 11 , Cbl is the parasitic capacitance of the bit line BL. Clbl is the parasitic capacitance of the local bit line LBL. Cdl is the parasitic capacitance of the digital line DL.

[0083] In summary, the present application shortens the duration of the overshoot current and minimizes the energy of the overshoot current as much as possible, thereby ensuring the uniformity of the operations of the memory cells Mcell at various positions and the consistent decrease in the threshold voltage of the memory cells Mcell. For example, if the energy caused by the overshoot current is negligible, the overshoot energy for operating the memory cells Mcell at different distances is only determined by the designed DC current (the change in this DC current is almost negligible) and the duration of this DC current, which can effectively reduce the design difficulty and the compensation difficulty for achieving the uniformity of the threshold voltage of the memory cells Mcell.

[0084] In some of these embodiments, this embodiment provides an electronic device, and the electronic device includes the above-mentioned memory.

[0085] It can be understood that since the electronic device provided in this embodiment includes the above-mentioned memory, at least one of the first select transistor T1 and the second select transistor T2 can also be configured as a P-channel transistor. Compared with the case where both the first select transistor T1 and the second select transistor T2 are N-channel transistors, the equivalent parasitic capacitance of the bit line BL can be reduced at the moment when the memory cell Mcell is turned on, thereby shortening the duration of the overshoot current.

[0086] It should be noted that the memory can be, but is not limited to, a phase change memory or a three-dimensional phase change memory, and can also be other applicable memory chips.

[0087] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0088] The memory and the electronic device provided in the embodiments of the present application have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The descriptions of the above embodiments are only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory, characterized in that: The memory comprises: Digital lines, local bit lines, memory cells distributed in an array, and bit lines and word lines connected to each of the memory cells; a first gating transistor, wherein a first electrode of the first gating transistor is connected to the bit line, a second electrode of the first gating transistor is connected to the local bit line, and a gate of the first gating transistor is connected to a first gating line; a second gating transistor, wherein a first electrode of the second gating transistor is connected to the local bit line, a second electrode of the second gating transistor is connected to the digit line, and a gate of the second gating transistor is connected to a second gating line; Wherein, at least one of the first selection transistor and the second selection transistor is a P-channel transistor.

2. The memory according to claim 1, characterized in that: A channel type of the first pass transistor is different from a channel type of the second pass transistor.

3. The memory according to claim 2, characterized in that: The first gating transistor is an N-channel transistor, and the second gating transistor is a P-channel transistor; The drain of the first gating transistor is connected to the bit line, and the source of the first gating transistor is connected to the local bit line; A source of the second gate transistor is connected to the local bit line, and a drain of the second gate transistor is connected to the digit line.

4. The memory according to claim 2, characterized in that: The first gating transistor is a P-channel transistor, and the second gating transistor is an N-channel transistor; A source of the first gating transistor is connected to the bit line, and a drain of the first gating transistor is connected to the local bit line; A drain of the second selection transistor is connected to the local bit line, and a source of the second selection transistor is connected to the digit line.

5. The memory according to claim 4, characterized in that: The memory further includes a third transistor, a first electrode of the third transistor is connected to the bit line, a second electrode of the third transistor is connected to an initialization voltage line, and a gate of the third transistor is connected to a third selection line.

6. The memory according to claim 5, characterized in that: A channel type of the third transistor is the same as a channel type of the first gate transistor.

7. The memory according to claim 6, characterized in that: The turn-on time of the third transistor is earlier than the turn-on time of the first gate transistor.

8. The memory according to claim 1, characterized in that: The first gating transistor is a P-channel type transistor, and the second gating transistor is a P-channel type transistor; A source of the first gating transistor is connected to the bit line, and a drain of the first gating transistor is connected to the local bit line; A source of the second gate transistor is connected to the local bit line, and a drain of the second gate transistor is connected to the digit line.

9. The memory according to any one of claims 1 to 8, characterized in that: The memory further comprises a control module connected with the digital line.

10. An electronic device, characterized in that: The electronic device comprises the memory according to any one of claims 1-9.

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