Preparation method of semiconductor device

Abstract

The invention provides a preparation method of a semiconductor device, which is applied to the technical field of semiconductors. The method comprises the following steps: firstly, providing a stress release structure in the shape of a groove structure, and then placing one or more stress release structures in scribing grooves in the periphery of the outer side of each chip on a wafer, so that the stress of each minimum photoetching unit, namely the chip, on the wafer is fully released; therefore, the warping of the wafer is reduced, the stress is fully released, and the probability that the wafer is broken and cracked in the subsequent process is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for manufacturing a semiconductor device. Background Art

[0002] To meet the requirements of application scenarios such as driverless, face recognition, and intelligent robots, the development of high-capacity, high-reliability, and high-energy-efficiency memory chips is an inevitable trend. New memory technologies such as phase change memory, resistive random access memory, and spin device memory can significantly improve the energy efficiency and data processing scale of chips. Some of these new memories contain special material thin films such as chalcogenide alloy thin films, magnetic metal thin films, and metal oxide thin films. These special thin films are not compatible with standard logic processes and require special manufacturing processes.

[0003] Currently, during the manufacturing process of advanced memory devices with metal thin film layers, the special metal-containing thin films on the wafer can cause excessive stress on the wafer. In particular, the stress generated by multiple metal thin film layers can lead to peeling of the formed thin films, deterioration of the wafer warpage, and ultimately result in a decrease in wafer yield and device performance deterioration. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for manufacturing a semiconductor device to reduce the warpage of the wafer, release stress, reduce the probability of wafer breakage and cracking in subsequent processes, and improve the production rate and device performance of semiconductor devices.

[0005] To solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, including:

[0006] Providing a wafer, the wafer including a plurality of chips and scribe grooves provided between adjacent chips;

[0007] Etching the wafer to form at least one alignment mark on at least one chip and at least one stress relief structure in the scribe grooves around the outside of the chip; and

[0008] Forming a metal thin film layer on the chip.

[0009] In some alternative examples, the stress relief structure is provided in the scribe groove outside the vertex angle of a chip, or is provided in the scribe groove outside the side of a chip.

[0010] In some alternative examples, the stress relief structure is a first groove structure, and the first groove structure includes at least one of a semi-circular ring groove structure, an arc-shaped groove structure, or a strip-shaped groove structure.

[0011] In some alternative examples, the stress release structure in the scribing groove provided outside the top corner of the chip has a cross-sectional shape of at least one of an arc shape or a semi-circular ring shape in a direction parallel to the chip surface.

[0012] In some alternative examples, the stress release structure in the scribing groove provided outside the side of the chip has a cross-sectional shape of at least one of a rectangle or a square in a direction parallel to the chip surface.

[0013] In some alternative examples, the width of the first groove structure in a direction parallel to the chip surface is: 1 μm to 20 μm.

[0014] In some alternative examples, the depth of the first groove structure in a direction perpendicular to the chip surface is n times the thickness of the metal thin film layer, and 1.5 ≤ n ≤ 3.

[0015] In some alternative examples, the alignment mark is a second groove structure, and the second groove structure includes a strip-shaped groove structure.

[0016] In some alternative examples, the step of forming a metal thin film layer on the chip includes:

[0017] Depositing a metal material layer, where the metal material layer covers the surface of a chip, the inner surface of the second groove structure located inside the chip, and the inner surface of the first groove structure located around the outside of the chip;

[0018] Etching the metal material layer to form a metal thin film layer on the chip surface while removing the metal material layer on the inner surfaces of the first groove structure and the second groove structure.

[0019] In some alternative examples, the material of the metal thin film layer is at least one of a chalcogenide alloy, a magnetic metal, a metal oxide, and a metal nitride.

[0020] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects:

[0021] The present invention first proposes a stress release structure in the shape of a groove structure, and then places one or more of the stress release structures in the scribing grooves around the outside of each chip on the wafer, so that the stress of each minimum lithography unit on the wafer, that is, the chip, is fully released, thereby achieving the purpose of reducing the warping of the wafer and releasing stress, and reducing the probability of chip breakage and cracking in subsequent processes.

[0022] Furthermore, since the stress relief structure proposed in the embodiments of the present invention is completed synchronously during alignment mark lithography and etching, that is, one or more stress relief structures can be efficiently fabricated without adding new lithography, etching process and other manufacturing processes. Thus, without affecting the layout design of a single chip, increasing the number of photomasks for a single chip, and other semiconductor manufacturing process steps, the stress of each chip and the wafer containing multiple chips is fully and evenly released. Description of the Drawings

[0023] Figure 1 It is a schematic flow chart of a method for manufacturing a semiconductor device provided in some embodiments of the present invention;

[0024] Figure 2 It is a top view showing the positional relationship between multiple chips 11 and scribing grooves 12 in a wafer provided in some embodiments of the present invention;

[0025] Figure 3 It is a cross-sectional view of etching a chip 11 on a wafer 10 in some embodiments of the present invention to synchronously form an alignment mark 101 as a second groove structure on the chip 11 and a stress relief structure 102 as a first groove structure in the scribing groove 12 around the outside of the chip 11;

[0026] Figure 4 It is a top view of a stress relief structure in which three semi-circular groove structures are respectively formed in multiple scribing grooves 12 outside the four top corners of a chip 11 provided in some embodiments of the present invention;

[0027] Figure 5 It is a top view of a stress relief structure in which one strip-shaped groove structure is respectively formed in the scribing grooves 12 outside the two sides of a chip 11 provided in some embodiments of the present invention;

[0028] Figure 6 It is a cross-sectional view of depositing a metal material layer on a chip 11 provided in some embodiments of the present invention;

[0029] Figure 7 It is a cross-sectional view of etching the metal material layer to form a metal thin film layer provided in some embodiments of the present invention.

[0030] Among them, the reference numerals are:

[0031] 10 - Wafer;

[0032] 11 - Chip;

[0033] 12 - Scribing groove;

[0034] 101 - Alignment mark;

[0035] 102 - Stress relief structure;

[0036] 111 - Metal material layer;

[0037] 111’ - Metal thin film layer. Specific embodiments

[0038] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further elaborated in detail below in conjunction with the drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided to enable a more thorough understanding of the present invention and to be able to fully convey the scope of the present invention to those skilled in the art.

[0039] In the following paragraphs, the present invention will be described more specifically by way of example with reference to the drawings. The advantages and features of the present invention will be clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. It can be understood that the meanings of "on...", "above...", and "overhead..." in the present invention should be interpreted in the broadest way, so that "on..." not only means "on" something "without any intermediate features or layers (i.e., directly on something)", but also includes the meaning of "on" something "with intermediate features or layers".

[0040] In addition, for the convenience of description, spatial relative terms such as "on...", "above...", "overhead...", "upper", "upper part", etc. can be used in this article to describe the relationship between one element or feature and another element or feature as shown in the figure. Except for the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive words used herein can be interpreted accordingly.

[0041] In the embodiments of the present invention, terms such as "first", "second", etc. are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be noted that the technical solutions recorded in the embodiments of the present invention can be combined arbitrarily without conflict.

[0042] At present, for the special metal-containing thin film on the wafer, it will cause excessive stress on the wafer. In particular, the stress generated by the multi-layer metal thin film will cause the formed metal thin film to peel off, the warpage of the wafer to deteriorate, and ultimately lead to a decrease in the wafer yield and the deterioration of device performance. There are two common solutions in the prior art. Solution 1: Remove the metal thin film at the edge of 3mm - 5mm of the entire wafer or silicon wafer, so as to release the stress of the wafer. Solution 2: Adopt the method of annealing the wafer after depositing the metal thin film to release the stress.

[0043] However, for a 12-inch wafer, its diameter is usually 30cm. Therefore, using the method of removing the metal thin film in the edge area of the wafer as described in Solution 1 above can only release the stress of some chips near the edge of the wafer, while the stress of many other chips located at the center position of the wafer cannot be released or cannot be fully released, and multiple additional photolithography and etching processes are required. When annealing the wafer after depositing the metal thin film as described in Solution 2, since some metal thin films are very sensitive to heat, the annealing process will change the characteristics of the metal thin film, resulting in the failure of semiconductor devices.

[0044] Obviously, the stress release method currently adopted in the prior art is a local small-area stress release method, which will inevitably lead to problems such as an increase in the warpage of the wafer, the peeling off of the metal thin film formed on the wafer, the occurrence of broken chips and cracked chips in the subsequent processes of the wafer, and the impact on other subsequent manufacturing processes.

[0045] Based on this, the present invention proposes a stress release structure in the shape of a groove structure and disposes it in the dicing groove outside the chip on the wafer, so as to realize stress release for each chip on the wafer without affecting the internal device design of the chip, without changing the chip layout design, and without adding additional photolithography and etching process steps, thereby achieving the purpose of reducing the warpage of the wafer and reducing the probability of broken chips and cracked chips in its subsequent processes.

[0046] The following will introduce the formation position, preparation process, etc. of the groove structure-shaped stress release structure provided by the present invention in combination with the process description of the preparation method of forming a metal thin film layer on at least one chip on the wafer.

[0047] For the convenience of understanding, the horizontal direction and the vertical direction are defined below. The horizontal direction is the direction parallel to the surface of the wafer 10; the vertical direction is the direction perpendicular to the surface of the wafer 10; and in Figures 2 to 7 the X direction and the Y direction are also specifically defined, where the X direction corresponds to the horizontal direction, the Y direction corresponds to the vertical direction, and the X direction and the Y direction are perpendicular to each other.

[0048] Refer to Figure 1 and in combination withFigures 2 to 7 , the Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor device provided in some embodiments of the present invention. The Figure 2 is a top view for showing the positional relationship between a plurality of chips 11 and scribe grooves 12 in a wafer provided in some embodiments of the present invention. The Figures 3 to 7 is provided in some embodiments of the present invention Figure 1 is a schematic structural view during the manufacturing process of the manufacturing method in Figure 3 and Figure 4 are top views of different structures of the stress relief structure provided by the present invention.

[0049] As Figure 1 shown, the method for manufacturing a semiconductor device includes at least the following steps:

[0050] Step S101: Provide a wafer, the wafer including a plurality of chips arranged in an array and scribe grooves provided between adjacent chips;

[0051] Step S102: Etch the wafer to form alignment marks on at least one chip and form at least one stress relief structure in the scribe grooves around the outside of the chip;

[0052] Step S103: Form a metal thin film layer on the chip.

[0053] Referring to Figure 2 , Figure 2 is a top view for showing the positional relationship between a plurality of chips and scribe grooves in a wafer provided in some embodiments of the present invention. As Figure 2 shown, in step S101 of the manufacturing method provided by the present invention, it is necessary to first provide a wafer 10, where the wafer 10 specifically may include a plurality of chips 11 and scribe grooves 12 provided between adjacent chips 11; as an example, the Figure 1 only exemplifies a partial number of chips 11 on the wafer 10.

[0054] In this embodiment, since scribe grooves 12 are provided around the outside of each chip 11, therefore, the stress relief structure proposed by the present invention can surround each chip 11 at different positions in the corresponding scribe groove 12 along the outside of each chip 11, thereby achieving the purpose of taking each chip 11 as the minimum stress unit, that is, fully releasing the stress of each chip 11 on the wafer 10.

[0055] It should be noted that multiple chips 11 on the wafer 10 can form semiconductor devices with the same structure in subsequent semiconductor manufacturing processes. For example, a metal thin film layer that affects the curvature, stress, etc. of the chips described in the background art of the present invention can be formed on each of the multiple chips 11 on the wafer 10. To simplify the drawing of the specification drawings, in the embodiments of the present invention, Figures 3 to 7 only by showing the preparation of the stress release structure and alignment marks on one of the chips 11 on the wafer 10, and in other embodiments, the Figures 3 to 7 preparation process can be performed on multiple chips 11 on the wafer 10, and the present invention will not repeat it here.

[0056] Refer to Figure 3 , Figure 3 which is a cross-sectional view of etching a chip 11 on a wafer 10 to synchronously form alignment marks 101 on the chip 11 and stress release structures 102 in scribe grooves 12 around the outside of the chip 11 in some embodiments of the present invention.

[0057] As Figure 3 shown, in step S102 of the preparation method provided by the present invention, for one chip 11 in the wafer 10, an etching process, such as a dry etching process or a wet etching process, can be used to synchronously form multiple alignment marks 101 on the chip 11 and multiple stress release structures 102 on the scribe grooves 12 (which is an area) around the outside of the chip 11.

[0058] Among them, the chip 11 described in the embodiments of the present invention is specifically a substrate, and the material of the substrate can specifically include semiconductor materials, such as silicon substrates, gallium arsenide substrates, germanium substrates, germanium-silicon substrates, fully depleted silicon-on-insulator (FDSOI) substrates. And the substrate of the chip 11 can also be an integrated circuit, such as a triode, a diode, a dielectric, but not limited thereto. Preferably, the chip 11 in this embodiment can specifically be a dielectric substrate integrated with a triode and a bottom electrode.

[0059] It should be noted that in the present invention, the alignment mark 101 and the stress relief structure 102 can both be exemplarily groove structures. That is, the alignment mark 101 is a second groove structure, and the stress relief structure 102 is a first groove structure. The groove structure (the first groove structure and / or the second groove structure) can be, for example, one or a combination of a semi-circular ring groove structure, an arc-shaped groove structure, or a strip-shaped groove structure. The alignment mark 101 is specifically formed in the substrate corresponding to the chip 11, such as the edge region of the substrate, and the stress relief structure 102 can be placed in the dicing groove 12 outside the apex angle of the chip 11, or can also be placed in the dicing groove 12 outside the side of the chip 11.

[0060] As a preferred example, the stress relief structure 102 provided by the present invention is specifically placed in the dicing groove 12 outside the apex angle of the chip 11, and the number of stress relief structures 102 that can be provided for each outside the apex angle of the chip 11 can be 0 to 4, preferably 3. For details, please refer to Figure 4 , Figure 4 FIG. is a top view of the stress relief structure formed by 3 semi-circular ring groove structures in the dicing grooves 12 outside the four apex angles of the chip 11 provided in some embodiments of the present invention; as Figure 4 shown, the cross-sectional shape of the stress relief structure 102 placed in the dicing groove 12 outside the apex angle of the chip 11 in the direction parallel to the surface of the chip 11 (simply referred to as the horizontal direction, also the X direction) is specifically at least one of an arc shape or a semi-circular ring shape.

[0061] It can be understood that Figure 4 the stress relief structure 102 shown is formed outside each apex angle of the chip 11. In other examples, it can also be formed only outside some apex angles of the chip 11, and the number of stress relief structures 102 formed outside each apex angle can be the same or different. The present invention does not make specific limitations on this.

[0062] As another preferred example, the stress relief structure 102 provided by the present invention is specifically placed in the dicing groove 12 outside one or more sides of the chip 11, and the number of stress relief structures 102 that can be provided for each outside the side of the chip 11 can be 0 to 3. For details, please refer to Figure 5 , Figure 5 FIG. is a top view of the stress relief structure formed by 1 strip-shaped groove structure in the dicing grooves 12 outside the two sides of the chip 11 provided in some embodiments of the present invention. As Figure 5 shown, the cross-sectional shape of the stress relief structure 102 placed in the dicing groove 12 outside the side of the chip 11 in the direction parallel to the surface of the chip 11 is specifically at least one of a rectangle or a square.

[0063] It is understandable that Figure 5 the stress release structures shown are formed on the outer sides of the two side edges of the chip 11 respectively. In other examples, they can also be formed on the outer sides of all the side edges of the chip 11, and the number of stress release structures 102 formed on the outer side of each side edge can be the same or different. The present invention does not make specific limitations on this.

[0064] As other preferred examples, the stress release structures 102 provided by the present invention can be placed in the scribing grooves 12 on one or more outer side edges of the chip 11 and at the same time in the scribing grooves 12 on the outer sides of one or more top corners of the chip 11. The present invention does not make specific limitations on this.

[0065] Furthermore, regardless of whether the stress release structures 102 provided in the embodiments of the present invention are specifically set or placed in the scribing grooves 12 on the outer sides of the top corners of the chip 11 or in the scribing grooves 12 on the outer sides of the side edges of the chip 11, the width of the stress release structures 101 in the direction parallel to the surface of the chip 11 (the horizontal direction) can be: 1 μm to 20 μm, that is, specifically can be 1 μm, 2 μm, 3 μm, 5 μm, 10 μm, 15 μm, 20 μm, etc. Exemplarily, the groove width of each stress release structure 102 is 5 μm; and its depth in the direction perpendicular to the surface of the chip 11 (the vertical direction) is specifically n times the thickness of the metal thin film layer, and 1.5 ≤ n ≤ 3. Exemplarily, the groove depth of each stress release structure 102 is 150 μm to 200 μm.

[0066] Obviously, in the embodiments of the present invention, the photomask when forming the alignment marks 101 and the stress release structures 102 can be the same photomask. Therefore, the photolithography and etching processes for forming the alignment marks 101 and the stress release structures 102 can both be the same semiconductor manufacturing process, that is, the present invention cannot add additional photomask design, photolithography, etching and other process steps. Under the condition of device cost, multiple stress release structures can be formed.

[0067] The following will take the stress release structure of the strip-shaped groove structure shown placed on the side edge of a chip 11 as an example to introduce the subsequent formation process of the metal thin film layer on the chip 11. Figure 5 shown to introduce the subsequent formation process of the metal thin film layer on the chip 11.

[0068] Refer to Figures 6 to 7 , Figure 6 is a cross-sectional view of depositing a metal material layer on a chip 11 provided in some embodiments of the present invention, Figure 7 is a cross-sectional view of etching the metal material layer to form a metal thin film layer provided in some embodiments of the present invention. As Figure 6As shown, in step S103 of the preparation method provided by the present invention, a metal material layer 111 can be formed on the chip 11 by using a deposition process, such as chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, etc. Among them, the material of the metal material layer 111 can specifically be at least one of chalcogenide alloy, magnetic metal, metal oxide, and metal nitride. The metal material layer 111 specifically covers the surface of the chip 11, the inner surface of the alignment mark 101 located inside the chip 11, and the inner surface of the stress release structure 102 located outside the chip 11; Exemplarily, if the formed metal material layer 111 is a chalcogenide alloy material layer, it can be GeSbTe with a thickness of 60 nm. Or, if the formed metal material layer 111 is a metal nitride thin film, it can be TiN with a thickness of 30 nm.

[0069] As Figure 7 As shown, in step S103 of the preparation method provided by the present invention, the metal material layer 111 can be further etched subsequently to form a metal thin film layer 111 on the surface of the chip 11 while removing the metal material layer on the inner surfaces of the stress release structure 102 and the alignment mark 101, so as to form a metal thin film layer 111' only on the target area of the chip 11, that is, the metal material layers in the groove structures corresponding to the alignment mark 101 and the stress release structure 102 need to be completely removed finally.

[0070] In summary, the present invention first proposes a stress release structure in the shape of a groove structure, and then places one or more of the stress release structures in the scribing grooves around the outside of each chip on the wafer, so that the stress of each minimum lithography unit on the wafer, that is, the chip, can be fully released, thereby achieving the purpose of reducing the warping of the wafer, releasing stress, and reducing the probability of chip breakage and cracking in subsequent processes.

[0071] Furthermore, since the stress release structure proposed in the embodiment of the present invention is completed synchronously during alignment mark lithography and etching, that is, one or more stress release structures can be efficiently fabricated without adding new lithography, etching processes and other manufacturing processes, so as to achieve the full and uniform release of stress of each chip and the wafer containing multiple chips without affecting the layout design of a single chip, increasing the number of photomasks of a single chip, and other semiconductor manufacturing process steps.

[0072] The above description is only a description of the preferred embodiment of the present invention, and does not limit the protection scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure belong to the protection scope of the present invention.

[0073] It should be noted that although the present invention has been disclosed above in preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or it can be modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0074] In this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element.

[0075] The above are only the preferred embodiments of the present invention, and are not used to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are all included in the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, comprising: providing a wafer, the wafer including a plurality of chips and scribe grooves disposed between adjacent chips; etching the wafer to form at least one alignment mark on at least one of the chips and at least one stress relief structure in the scribe grooves around the outer periphery of the chip; and forming a metal thin film layer on the chip.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, the stress relief structure is disposed in the scribe groove outside the apex of one of the chips, or is disposed in the scribe groove outside the side of one of the chips.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, the stress relief structure is a first groove structure, and the first groove structure includes at least one of a semi-circular ring groove structure, an arc-shaped groove structure, or a strip-shaped groove structure.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, the cross-sectional shape of the stress relief structure disposed in the scribe groove outside the apex of the chip in a direction parallel to the surface of the chip is at least one of an arc shape or a semi-circular ring shape.

5. The method for manufacturing a semiconductor device according to claim 3, characterized in that, the cross-sectional shape of the stress relief structure disposed in the scribe groove outside the side of the chip in a direction parallel to the surface of the chip is at least one of a rectangle or a square.

6. The method for manufacturing a semiconductor device according to claim 4 or 5, characterized in that, the width of the first groove structure in a direction parallel to the surface of the chip is: 1 μm to 20 μm.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, the depth of the first groove structure in a direction perpendicular to the surface of the chip is n times the thickness of the metal thin film layer, and 1.5 ≤ n ≤ 3.

8. The method for manufacturing a semiconductor device according to claim 3, characterized in that, the alignment mark is a second groove structure, and the second groove structure includes a strip-shaped groove structure.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, the step of forming a metal thin film layer on the chip includes: depositing a metal material layer, the metal material layer covering the surface of one of the chips, the inner surface of the second groove structure located inside the chip, and the inner surface of the first groove structure located around the outer periphery of the chip; etching the metal material layer to form a metal thin film layer on the surface of the chip while removing the metal material layer on the inner surfaces of the first groove structure and the second groove structure.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, the material of the metal thin film layer is at least one of a chalcogenide alloy, a magnetic metal, a metal oxide, or a metal nitride.

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