Wafer-free interposer manufacturing method

Abstract

A method for manufacturing a wafer-free interposer includes the steps of: providing a carrier wafer; forming a first redistribution layer on the carrier wafer, wherein at least the first redistribution layer forms a wire pattern; forming a protective layer to protect the wire pattern; the bearing wafer is turned over and attached to the supporting base material, so that the protection layer makes contact with the supporting base material and is attached to the supporting base material; and removing the carrier wafer to form a wafer-free interposer attached to the support substrate. Wherein the bearing wafer is only used as a bearing tool, so that the bearing wafer can be repeatedly used. In addition, an expensive through-silicon-via process is not needed, the risk of chip pre-arrangement derivation is avoided, and the interposer can be delivered independently.

Description

Technical Field

[0001] The present invention relates to a manufacturing method, and particularly to a method for manufacturing a waferless interposer suitable for advanced manufacturing processes. Background Art

[0002] Advanced packaging is a technology used in semiconductor manufacturing, which involves packaging integrated circuit chips (ICs) in smaller, thinner, more efficient, or more feature-rich packages to meet the requirements of modern electronic devices. Facing the trend of the increasing number of input / output ports of chips, the demand for advanced packaging has been increasingly emphasized. For example, the demand for chips currently used in the field of artificial intelligence (AI) has increased significantly, and the requirements for the specifications, production capacity, and yield of advanced packaging have become crucial.

[0003] In the current semiconductor manufacturing technology, there are only two production technologies that can meet the actual requirements of advanced packaging, namely CoWoS (Chip on Wafer on Substrate) and InFO (Integrated Fan-Out). Among them, the CoWoS technology stacks chips on a wafer through the CoW (Chip on Wafer) manufacturing process, and then connects the aforementioned CoW part to the substrate through the WoS (Wafer on Substrate) manufacturing process to package multiple chips together, so as to achieve the technical effects of reducing volume and power consumption and maintaining high performance; while the InFO technology, that is, the integrated fan-out technology, allows the number of pins to exceed the chip, can support more pins, making the pin density higher, and can also improve the heat dissipation effect.

[0004] However, in the InFO technology, since it is a chip-first packaging technology that requires the chips to be fixed and arranged at the bottom first and then subsequent manufacturing processes are carried out, if there are yield problems during the manufacturing process, it will lead to chip scrapping and cause serious losses; while in the CoWoS technology, although it is a chip-last packaging technology, because it requires wafers as materials, manufacturing processes such as wafer grinding and thinning and through-silicon via (TSV) must be carried out, which requires a large amount of cost and time in terms of materials and manufacturing processes. During the grinding process, defects such as local or overall thickness non-uniformity or wafer edge damage may also occur, resulting in a low yield. In addition, an ultrathin wafer handling system is required during the production process of the interposer, which also increases the complexity and cost of the manufacturing process.

[0005] In addition, in the advanced packaging using either CoWoS technology or InFO technology, there will be problems of stress residue and stress accumulation during its manufacturing process, resulting in poor quality of the interposer and the final product.

[0006] Therefore, it is necessary to provide a method for manufacturing a waferless interposer to solve the problems existing in the prior art. Summary of the Invention

[0007] The motivation of the present invention is to provide a method for manufacturing a waferless interposer, aiming to solve and improve the problems and disadvantages of the aforementioned prior art.

[0008] The main object of the present invention is to provide a method for manufacturing a waferless interposer. By flipping the carrier wafer and bonding it to the support substrate and then removing the carrier wafer to form a waferless interposer, the carrier wafer only serves as a carrier tool and can be reused. At the same time, since the wafer does not belong to the material itself and there is no need to arrange the chips at the bottom first, it is possible to avoid the expensive through-silicon via (TSV) process and the risks derived from chip first, and the interposer can be shipped separately, etc.

[0009] Furthermore, since the method for manufacturing the waferless interposer of the present invention does not require wafer grinding and thinning in any of its steps, it is possible to provide a high-quality waferless interposer with low stress and low deformation.

[0010] According to one aspect of the present invention, it aims to provide a method for manufacturing a waferless interposer, including the steps of: (a) providing a carrier wafer; (b) forming a first redistribution layer on the carrier wafer, wherein at least the first redistribution layer forms a wire pattern; (c) forming a protective layer to protect the wire pattern; (d) flipping the carrier wafer and bonding it to a support substrate so that the protective layer contacts and bonds to the support substrate; and (e) removing the carrier wafer to form a waferless interposer bonded to the support substrate.

[0011] In an embodiment of the present invention, in the step (b), the first redistribution layer forms the wire pattern, and in the step (c), the protective layer is formed on the first redistribution layer.

[0012] In an embodiment of the present invention, between the step (b) and the step (c), there is further included the step of: (b1) forming a second redistribution layer on the first redistribution layer, wherein in the step (b1), the first redistribution layer and the second redistribution layer form the wire pattern, and in the step (c), the protective layer is formed on the second redistribution layer.

[0013] In an embodiment of the present invention, after the step (e), the method further includes the steps of: (f) bonding a plurality of chips to the waferless interposer; (g) packaging the plurality of chips and the waferless interposer into an advanced package; and (h) removing the support substrate.

[0014] In an embodiment of the present invention, the first redistribution layer has a plurality of conductive contacts. In the step (e), the plurality of conductive contacts are exposed on a first surface of the waferless interposer, and in the step (f), the plurality of chips are connected to the plurality of conductive contacts so that the plurality of chips are electrically connected to the waferless interposer.

[0015] In an embodiment of the present invention, between the step (c) and the step (d), the method further includes the step of: (c1) forming a plurality of vias in the protective layer, wherein in the step (e), the plurality of vias are located on a second surface of the waferless interposer.

[0016] In an embodiment of the present invention, the step (g) is to perform packaging in a direction from the first surface of the waferless interposer away from the second surface of the waferless interposer.

[0017] In an embodiment of the present invention, after the step (h), the method further includes the step of: (i) assembling the advanced package with a circuit board so that a plurality of solder balls on the circuit board are connected to the conductive pattern through the plurality of vias, thereby electrically connecting the circuit board to the waferless interposer.

[0018] In an embodiment of the present invention, in the step (d), the bonding of the protective layer and the support substrate is achieved by using a tape, and the step (h) is achieved by performing a debonding operation.

[0019] In an embodiment of the present invention, the carrier wafer includes a light-transmissive substrate and a carrier layer formed on the light-transmissive substrate, and the step (e) is achieved by using a laser to penetrate the light-transmissive substrate and irradiate the carrier layer to vaporize and dissociate the carrier layer.

[0020] Therefore, the manufacturing method of the waferless interposer provided by the present invention has at least the following beneficial effects compared with the prior art:

[0021] First, the carrier wafer is only used as a carrier tool and can be reused, which can effectively reduce the material cost;

[0022] Second, in the manufacturing process, there is no need to perform through-silicon via (TSV) and wafer grinding and thinning processes, which can effectively reduce the manufacturing cost and time consumed;

[0023] III. Avoiding risks derived from chip first; and

[0024] IV. The waferless interposer can be shipped separately by attaching it to a support substrate, shipped after being packaged with chips and removing the support substrate, or shipped after being assembled with a circuit board after debonding, which has sufficient flexibility and can be manufactured according to actual requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A flowchart showing a method for manufacturing a waferless interposer according to a preferred embodiment of the present case.

[0026] Figure 2 A flowchart showing a method for manufacturing a waferless interposer according to another preferred embodiment of the present case.

[0027] Figure 3 A flowchart showing a method for manufacturing a waferless interposer according to another preferred embodiment of the present case.

[0028] Figure 4 A flowchart showing a method for manufacturing a waferless interposer according to another preferred embodiment of the present case.

[0029] Figure 5 A flowchart showing a method for manufacturing a waferless interposer according to another preferred embodiment of the present case.

[0030] Figure 6 A flowchart showing a method for manufacturing a waferless interposer according to another preferred embodiment of the present case.

[0031] Figure 7 Showing Figure 6 A schematic diagram of step S10 of the method for manufacturing the waferless interposer shown.

[0032] Figure 8 Showing Figure 6 A schematic diagram of step S20 of the method for manufacturing the waferless interposer shown.

[0033] Figure 9 Showing Figure 6 A schematic diagram of step S25 of the method for manufacturing the waferless interposer shown.

[0034] Figure 10 Showing Figure 6 A schematic diagram of steps S30 and S35 of the method for manufacturing the waferless interposer shown.

[0035] Figure 11 Showing Figure 6 A schematic diagram of step S40 of the method for manufacturing the waferless interposer shown.

[0036] Figure 12Display Figure 6 Schematic diagram of step S50 of the method for manufacturing the shown waferless interposer.

[0037] Figure 13 Display Figure 6 Schematic diagram of step S60 of the method for manufacturing the shown waferless interposer.

[0038] Figure 14 Display Figure 6 Schematic diagram of step S70 of the method for manufacturing the shown waferless interposer.

[0039] Figure 15 Display Figure 6 Schematic diagram of step S80 of the method for manufacturing the shown waferless interposer.

[0040] Figure 16 Display Figure 6 Schematic diagram of step S90 of the method for manufacturing the shown waferless interposer. Detailed implementation mode

[0041] To make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following will specifically present the preferred embodiments of the present invention and, in conjunction with the accompanying drawings, make a detailed description as follows. Furthermore, the directional terms mentioned in the present invention, such as up, down, top, bottom, front, back, left, right, inside, outside, side, surrounding, center, horizontal, transverse, vertical, longitudinal, axial, radial, the uppermost layer or the lowermost layer, etc., are only the directions referring to the accompanying drawings. Therefore, the directional terms used are for explaining and understanding the present invention, rather than for limiting the present invention.

[0042] Please refer to Figure 1 , which shows a flowchart of a method for manufacturing a waferless interposer according to a preferred embodiment of this case. As Figure 1As shown, according to a preferred embodiment of the present case, a method for manufacturing a waferless interposer applicable to an advanced manufacturing process is provided, including the following steps. First, as shown in step S10, a carrier wafer is provided. Secondly, as shown in step S20, a first redistribution layer (RDL) is formed on the carrier wafer, wherein at least the first redistribution layer forms a wire pattern, for example, the first redistribution layer forms the wire pattern. Then, as shown in step S30, a passivation layer is formed to protect the wire pattern, for example, the passivation layer is formed on the first redistribution layer. Next, as shown in step S40, the carrier wafer is flipped and bonded to a support substrate so that the passivation layer contacts and bonds to the support substrate. In some embodiments, the support substrate can be a jig, for example, a dedicated board designed for support, but not limited thereto. Then, as shown in step S50, the carrier wafer is removed to form a waferless interposer bonded to the support substrate. In other words, the waferless interposer includes at least the first redistribution layer and the passivation layer, wherein the support substrate, the passivation layer, and the first redistribution layer are stacked in sequence from bottom to top, and the passivation layer is in direct contact with the support substrate. Since the support substrate provides sufficient strength and support, the waferless interposer can be shipped separately bonded to the support substrate to meet actual requirements. From the above description, it can be seen that the carrier wafer is only a carrier tool rather than the material itself, so the carrier wafer can be reused. At the same time, since the carrier wafer does not belong to the material itself, there is no need to perform an expensive through-silicon via (TSV) process. In addition, the method for manufacturing the waferless interposer in the present case does not require arranging the chips at the bottom first, so the risks derived from the chip-first manufacturing process can be avoided.

[0043] In some embodiments, the carrier wafer includes a light-transmitting substrate and a carrier layer formed on the light-transmitting substrate. For step S50 above, i.e., the step of removing the carrier wafer, it is preferably achieved by irradiating the carrier layer with a laser that penetrates the light-transmitting substrate to vaporize and dissociate the carrier layer. Specifically, the light-transmitting substrate can be made of quartz glass, borosilicate glass, sodium silicate glass, or sapphire glass; the carrier layer can be a buffer layer and can be a ceramic optical film, a metal thin film, or a non-metal thin film, such as ceramic optical films like gallium nitride (GaN), aluminum nitride (AlN), aluminum oxide (AlO), or zinc oxide (ZnO), metal thin films like gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), titanium (Ti), or titanium tungsten (TiW), or non-metal thin films like silicon nitride (SixNx), silicon oxide (SixOx), silicon (Si), or silicon carbide (SiC), but not limited thereto. In addition, in step S50, the laser used can be an infrared laser (IR Laser), a visible light laser, an ultraviolet laser (UV Laser), or a deep ultraviolet laser (DUV Laser), etc., and an appropriate laser is selected in combination with the materials of the light-transmitting carrier and the carrier layer to achieve the technical effect of penetrating the light-transmitting carrier and irradiating the carrier layer to vaporize and dissociate the carrier layer.

[0044] In some embodiments, the method for manufacturing the waferless interposer of the present invention can form two or more redistribution layers according to the requirements of the circuit layout (Layout) to form a three-dimensional wire pattern.

[0045] Embodiments of the method for manufacturing the waferless interposer of the present invention including the steps of forming a first redistribution layer and forming a second redistribution layer will be described below. Please refer to Figure 2 , which shows a flowchart of a method for manufacturing a waferless interposer according to another preferred embodiment of the present case. As Figure 2 shown, the method for manufacturing the waferless interposer of the present invention may further include step S25 between step S20 and step S30, forming a second redistribution layer on the first redistribution layer. In addition, in step S25, the first redistribution layer and the second redistribution layer form a wire pattern, and in step S30, a protective layer is formed on the second redistribution layer to protect the wire pattern. In other words, the waferless interposer in step S50 of this embodiment includes a first redistribution layer, a second redistribution layer, and a protective layer, where the support substrate, the protective layer, the second redistribution layer, and the first redistribution layer are stacked in sequence from bottom to top.

[0046] Embodiments of the method for manufacturing the waferless interposer of the present invention including the steps of forming a first redistribution layer, forming a second redistribution layer, and forming a third redistribution layer will be described below. Please refer to Figure 3 , which shows a flowchart of a method for manufacturing a waferless interposer according to another preferred embodiment of the present case. As Figure 3As shown, the method for manufacturing a waferless interposer of the present invention includes step S25 between step S20 and step S30, forming a second rewiring layer on the first rewiring layer, and further includes step S28 between step S25 and step S30, forming a third rewiring layer on the second rewiring layer. In this embodiment, in step S28, the first rewiring layer, the second rewiring layer, and the third rewiring layer form a wire pattern, and in step S30, a protective layer is formed on the third rewiring layer to protect the wire pattern. That is to say, the waferless interposer in step S50 of this embodiment includes a first rewiring layer, a second rewiring layer, a third rewiring layer, and a protective layer, wherein the support substrate, the protective layer, the third rewiring layer, the second rewiring layer, and the first rewiring layer are stacked in sequence from bottom to top.

[0047] In some embodiments, the waferless interposer manufactured by the method for manufacturing a waferless interposer of this case, in addition to being attached to the support substrate in the manner described above and shipped as a product separately, can also be packaged with chips and shipped as a product after removing the support substrate. The following will be further described.

[0048] Please refer to Figure 4 , which shows a flowchart of a method for manufacturing a waferless interposer according to another preferred embodiment of this case. As Figure 4 shown, the method for manufacturing a waferless interposer of the present invention may further include step S60, step S70, and step S80 after step S50. After step S50 is completed, as shown in step S60, a plurality of chips are bonded to the waferless interposer. Then, as shown in step S70, a plurality of chips and the waferless interposer are packaged into an advanced package (Advanced Package), such as 2.5D or 3D package, but not limited thereto. Then, as shown in step S80, the support substrate is removed. In some embodiments, in step S40 of the method for manufacturing a waferless interposer of the present invention, the bonding of the protective layer of the waferless interposer and the support substrate is achieved by a tape, and in step S80, the removal of the support substrate is achieved by performing a debonding action, such as directly removing the tape and separating the support substrate from the waferless interposer, but not limited thereto. After step S80 is completed, the waferless interposer and the advanced package can be shipped as a product.

[0049] In some embodiments, the waferless interposer manufactured by the method for manufacturing a waferless interposer of this case, in addition to being attached to the support substrate in the manner described above or packaged with chips and shipped as a product after removing the support substrate, can also be assembled with a circuit board after debonding and shipped as a product, having sufficient flexibility and can be manufactured according to actual needs. The following will be further described.

[0050] Please refer to Figure 5, which shows a flowchart of a method for manufacturing a waferless interposer according to another preferred embodiment of the present case. As Figure 5 shown, the method for manufacturing the waferless interposer of the present invention further includes step S35 between step S30 and step S40, that is, the step of forming a plurality of through holes in the protective layer, wherein the positions where the plurality of through holes are formed can be designed in accordance with the wire pattern according to actual requirements. In addition, further includes step S90 after step S80, that is, the step of assembling the advanced package and the circuit board, so that a plurality of solder balls on the circuit board are connected to the conductive pattern through the plurality of through holes, thereby electrically connecting the circuit board and the waferless interposer. After step S90 is completed, that is, after the electrical connection between the waferless interposer and the circuit board is completed, it can be shipped as a product.

[0051] Please refer to Figure 6 and cooperate with Figures 7 to 16 , wherein Figure 6 shows a flowchart of a method for manufacturing a waferless interposer according to another preferred embodiment of the present case, Figure 7 shows Figure 6 a schematic diagram of step S10 of the method for manufacturing the waferless interposer shown, Figure 8 shows Figure 6 a schematic diagram of step S20 of the method for manufacturing the waferless interposer shown, Figure 9 shows Figure 6 a schematic diagram of step S25 of the method for manufacturing the waferless interposer shown, Figure 10 shows Figure 6 a schematic diagram of steps S30 and S35 of the method for manufacturing the waferless interposer shown, Figure 11 shows Figure 6 a schematic diagram of step S40 of the method for manufacturing the waferless interposer shown, Figure 12 shows Figure 6 a schematic diagram of step S50 of the method for manufacturing the waferless interposer shown, Figure 13 shows Figure 6 a schematic diagram of step S60 of the method for manufacturing the waferless interposer shown, Figure 14 shows Figure 6 a schematic diagram of step S70 of the method for manufacturing the waferless interposer shown, Figure 15 shows Figure 6 a schematic diagram of step S80 of the method for manufacturing the waferless interposer shown, and Figure 16 shows Figure 6 a schematic diagram of step S90 of the method for manufacturing the waferless interposer shown.

[0052] As Figures 6 to 16As shown, the manufacturing method of the waferless interposer of a preferred embodiment of this case includes the following steps. First, as shown in step S10, a carrier wafer 1 is provided. Secondly, as shown in step S20, a first redistribution layer 21 is formed on the carrier wafer 1, and the first redistribution layer 21 has a plurality of conductive contacts 211, and the plurality of conductive contacts 211 are formed in step S20. Then, as shown in step S25, a second redistribution layer 22 is formed on the first redistribution layer 21, wherein the first redistribution layer 21 and the second redistribution layer 22 form a wire pattern. Then, as shown in step S30, a protective layer 23 is formed to protect the wire pattern, wherein the protective layer 23 is formed on the second redistribution layer 22. Then, as shown in step S35, a plurality of vias 230 are formed in the protective layer 23. Then, as shown in step S40, the carrier wafer 1 is turned over and bonded to the support substrate 3 so that the protective layer 23 contacts and bonds to the support substrate 3, wherein the support substrate 3 can be a jig, but is not limited thereto. Then, as shown in step S50, the carrier wafer 1 is removed to form a waferless interposer 2 bonded to the support substrate 3. In this step S50, a plurality of conductive contacts 211 are exposed on the first surface of the waferless interposer 2, that is, the surface of the waferless interposer 2 farthest from the support substrate 3, and the plurality of vias 230 are located on the second surface of the waferless interposer 2, that is, the surface of the waferless interposer 2 that contacts and bonds to the support substrate 3. Then, as shown in step S60, a plurality of chips 4 are bonded to the waferless interposer 2. In this step S60, the plurality of chips 4 are connected to the plurality of conductive contacts 211 so that the plurality of chips 4 are electrically connected to the waferless interposer 2. Then, as shown in step S70, the plurality of chips 4 and the waferless interposer 2 are encapsulated into an advanced package 5, specifically by encapsulating from the first surface of the waferless interposer 2 in a direction away from the second surface of the waferless interposer 2. Next, as shown in step S80, the support substrate 3 is removed. Finally, as shown in step S90, the advanced package 5 is assembled with the circuit board 6 so that a plurality of solder balls 61 on the circuit board 6 are connected to the conductive pattern through the plurality of vias 230, thereby electrically connecting the circuit board 6 to the waferless interposer 2.

[0053] In summary, the present invention provides a manufacturing method of a waferless interposer. By turning over the carrier wafer and bonding it to the support substrate and then removing the carrier wafer to form the waferless interposer, the carrier wafer only serves as a carrier tool and can be reused. At the same time, since the wafer does not belong to the material itself and there is no need to arrange the chips at the bottom first, it is possible to avoid the expensive through-silicon via (TSV) process and the risks derived from chip first, and the interposer can be shipped separately, etc. Further, since the manufacturing method of the waferless interposer of the present invention does not require wafer grinding and thinning in any of its steps, a high-quality waferless interposer with low stress and low deformation can be provided.

[0054] Although the present invention has been disclosed in preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the claims.

Claims

1. A manufacturing method of a waferless interposer, characterized in that, it includes the steps of: (a) Providing a carrier wafer; (b) Forming a first redistribution layer on the carrier wafer, wherein at least the first redistribution layer forms a wire pattern; (c) Forming a protective layer to protect the wire pattern; (d) Flipping the carrier wafer and bonding it to a support substrate so that the protective layer contacts and bonds with the support substrate; and (e) Removing the carrier wafer to form a waferless interposer bonded to the support substrate.

2. The manufacturing method of the waferless interposer as claimed in claim 1, characterized in that, in the step (b), the first redistribution layer forms the wire pattern, and in the step (c), the protective layer is formed on the first redistribution layer.

3. The manufacturing method of the waferless interposer as claimed in claim 1, characterized in that, between the step (b) and the step (c), it further includes the step: (b1) Forming a second redistribution layer on the first redistribution layer, wherein in the step (b1), the first redistribution layer and the second redistribution layer form the wire pattern, and in the step (c), the protective layer is formed on the second redistribution layer.

4. The manufacturing method of the waferless interposer as claimed in claim 1, characterized in that, after the step (e), it further includes the steps: (f) Bonding a plurality of chips to the waferless interposer; (g) Encapsulating the plurality of chips and the waferless interposer into an advanced package; and (h) Removing the support substrate.

5. The manufacturing method of the waferless interposer as claimed in claim 4, characterized in that, the first redistribution layer has a plurality of conductive contacts, in the step (e), the plurality of conductive contacts are exposed on a first surface of the waferless interposer, and in the step (f), the plurality of chips are connected to the plurality of conductive contacts so that the plurality of chips are electrically connected to the waferless interposer.

6. The manufacturing method of the waferless interposer as claimed in claim 5, characterized in that, between the step (c) and the step (d), it further includes the step: (c1) Forming a plurality of through holes in the protective layer, wherein in the step (e), the plurality of through holes are located on a second surface of the waferless interposer.

7. The manufacturing method of the waferless interposer as claimed in claim 6, characterized in that, the step (g) is to perform encapsulation from the first surface of the waferless interposer in a direction away from the second surface of the waferless interposer.

8. The manufacturing method of the waferless interposer as claimed in claim 6, characterized in that, after the step (h), it further includes the step: (i) Assembling the advanced package with a circuit board so that a plurality of solder balls on the circuit board are connected to the conductive pattern through the plurality of through holes, thereby electrically connecting the circuit board to the waferless interposer.

9. The manufacturing method of the waferless interposer as claimed in claim 4, characterized in that, In the step (d), the bonding of the protective layer and the support substrate is achieved by a tape, and the step (h) is achieved by performing a debonding operation.

10. The method for manufacturing a waferless interposer according to claim 1, wherein, the carrier wafer includes a light-transmissive substrate and a carrier layer formed on the light-transmissive substrate, and the step (e) is achieved by a laser penetrating the light-transmissive substrate to irradiate the carrier layer to vaporize and dissociate the carrier layer.

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