Interposer with MIM capacitor and manufacturing method thereof

Abstract

An interposer having an MIM capacitor includes a substrate, a redistribution layer disposed on the substrate, a first copper pillar, a second copper pillar, and a third copper pillar disposed on the redistribution layer, the first copper pillar and the third copper pillar being electrically connected to the redistribution layer, respectively, and the first copper pillar, the second copper pillar, and the third copper pillar being electrically connected to the redistribution layer. An MIM capacitor covers and contacts the first copper pillar and the second copper pillar, a first bonding bump is disposed right above the third copper pillar and electrically connected to the third copper pillar, and a second bonding bump is disposed right above the second copper pillar and electrically connected to the MIM capacitor.

Description

Technical Field

[0001] The present invention relates to an interposer, and more particularly to an interposer having a metal-insulator-metal (MIM) capacitor and a method for manufacturing the same. Background Art

[0002] With the vigorous development of the electronics industry, electronic products tend to be thinner, lighter, shorter, and smaller in form. Therefore, their semiconductor chips are gradually moving towards the research and development direction of high performance, high functionality, and high speed in terms of functions. Generally speaking, the most direct method for miniaturizing semiconductor chips relies on the improvement of lithography technology. However, today's lithography technology has gradually approached its physical limit. Therefore, the solution needs to shift from the lateral scale to the vertical scale.

[0003] Compared with the early method of fixing the substrate and the chip with pins, in order to increase the number of I / Os and meet reliable heat dissipation, many new packaging technologies have been developed to achieve the reduction of the chip volume and the increase of the number of solder joints. The currently developed and mature ball grid array packaging can be bonded by wire bonding or by using the flip chip method. The flip chip method is a technology with the tin ball facing down, which can directly reduce materials and costs.

[0004] As the circuit pattern of semiconductor chips is reduced to a size of dozens of nanometers, the fabricated chips integrate more computing functions and a larger number of transistor elements, resulting in a rapid doubling of the number of signal pins (I / Os). This has also brought extremely severe challenges to traditional chip packaging technologies. Summary of the Invention

[0005] In view of this, the present invention provides an interposer for a stacked type package of three-dimensional integrated circuits, thereby increasing the efficiency of semiconductor chips.

[0006] According to a preferred embodiment of the present invention, an interposer having an MIM capacitor includes a substrate, a redistribution wiring layer disposed on the substrate, a first copper pillar, a second copper pillar, and a third copper pillar disposed on the redistribution wiring layer, wherein the first copper pillar and the third copper pillar are each electrically connected to the redistribution wiring layer, an MIM capacitor covers and contacts the first copper pillar and the second copper pillar, a first bonding bump is disposed directly above the third copper pillar and electrically connected to the third copper pillar, and a second bonding bump is disposed directly above the second copper pillar and electrically connected to the MIM capacitor.

[0007] According to another preferred embodiment of the present invention, a method for manufacturing an interposer having a MIM capacitor includes providing a substrate, then forming a redistribution line layer on the substrate, and then simultaneously forming a first copper pillar, a second copper pillar, and a third copper pillar on the redistribution line layer, wherein the first copper pillar and the third copper pillar are each electrically connected to the redistribution line layer. After that, a first conductive layer, an insulating layer, and a second conductive layer are sequentially formed, and the first conductive layer, the insulating layer, and the second conductive layer cover the first copper pillar, the second copper pillar, and the third copper pillar from bottom to top. Subsequently, the first conductive layer, the insulating layer, and the second conductive layer are truncated to form a gap between the first copper pillar and the third copper pillar, so that the first conductive layer, the insulating layer, and the second conductive layer covering the first copper pillar and the second copper pillar form a MIM capacitor, and the first conductive layer, the insulating layer, and the second conductive layer covering the third copper pillar form a stacked structure. Finally, a first bonding bump and a second bonding bump are formed. The first bonding bump is disposed directly above the third copper pillar and is electrically connected to the third copper pillar, and the second bonding bump is disposed directly above the second copper pillar and is electrically connected to the MIM capacitor.

[0008] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically illustrates preferred embodiments and is accompanied by the attached drawings in detail as follows. However, the following preferred embodiments and the drawings are only for reference and illustration, and are not used to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 6 A schematic diagram of a method for manufacturing an interposer having a MIM capacitor shown in a preferred embodiment of the present invention.

[0010] MAIN ELEMENT SYMBOL DESCRIPTION

[0011] 10: Substrate

[0012] 12: Through-hole conductor

[0013] 14: Dielectric layer

[0014] 14a: Opening

[0015] 16: Redistribution line layer

[0016] 18: Dielectric layer

[0017] 18a: Opening

[0018] 18b: Opening

[0019] 20: Bump underfill metal layer

[0020] 22: First conductive layer

[0021] 24: Insulating layer

[0022] 26: Second conductive layer

[0023] 28: Spacing

[0024] 30a: First bonding bump

[0025] 30b: Second bonding bump

[0026] 32a: First nickel layer

[0027] 32b: Second nickel layer

[0028] 34a: First solder paste

[0029] 34b: Second solder paste

[0030] 36a: First solder ball

[0031] 36b: Second solder ball

[0032] 38a: First inter-metal layer

[0033] 38b: Second inter-metal layer

[0034] 100: Interposer with MIM capacitor

[0035] A: MIM capacitor

[0036] B: Stacked structure

[0037] C: Capacitor region

[0038] D: Capacitor dielectric layer

[0039] E1: Lower electrode

[0040] E2: Upper electrode

[0041] I / O: Output / input region

[0042] P1: First copper pillar

[0043] P2: Second copper pillar

[0044] P3: Third copper pillar

[0045] P4: Fourth copper pillar Detailed implementation manner

[0046] Figures 1 to 6 It is a manufacturing method of an interposer with an MIM capacitor shown according to a preferred embodiment of the present invention.

[0047] As Figure 1As shown, first, a substrate 10 is provided. The substrate 10 can be silicon, glass, or a dielectric layer. A plurality of perforated wires 12 penetrate the substrate 10. Then, a dielectric layer 14 is formed to cover the substrate 20. Then, the dielectric layer 14 is etched to form several openings 14a to expose the perforated wires 12. Then, one or more redistribution layers 16 are formed on the substrate 10 and filled into the openings 14a to contact and electrically connect to the perforated wires 12. After that, a dielectric layer 18 is formed to cover the redistribution layer 16 and the dielectric layer 14.

[0048] As Figure 2 shown, a first copper pillar P1, a second copper pillar P2, a third copper pillar P3, and a fourth copper pillar P4 are simultaneously formed on the redistribution layer 16. Among them, the first copper pillar P1 and the third copper pillar P3 are each electrically connected to the redistribution layer 16. Specifically, the manufacturing process of the copper pillar preferably includes first etching the dielectric layer 18 to form openings 18a / 18b, exposing the redistribution layer 16 from the openings 18a / 18b. Then, an under-bump metallization (UBM) material layer is formed to cover the dielectric layer 18 and filled into the openings 18a / 18b. Then, a patterned photoresist (not shown in the figure) is formed. There are four openings on the patterned photoresist to define the positions of the copper pillars. The openings on the patterned photoresist expose the UBM material layer. Then, an electroplating manufacturing process is carried out to respectively form the first copper pillar P1, the second copper pillar P2, the third copper pillar P3, and the fourth copper pillar P4 in the openings of the patterned photoresist. Finally, the patterned photoresist is removed, and then the UBM material layer not covered by the first copper pillar P1, the second copper pillar P2, the third copper pillar P3, and the fourth copper pillar P4 is removed to form four UBM layers 20. According to a preferred embodiment of the present invention, the first copper pillar P1, the second copper pillar P2, and the fourth copper pillar P4 are located in the same area, such as the capacitance area C, while the third copper pillar P3 is located in the input / output area I / O. In addition, according to different requirements, the number of the above copper pillars and the UBM layers 20 can be adjusted. Additionally, the material of the UBM layer 20 includes copper, chromium, nickel, aluminum, gold, silver, tungsten, titanium, tantalum, tin, platinum, palladium, titanium nitride (TiN), titanium tungsten (TiW), tantalum nitride (TaN), nickel vanadium (NiV), or chromium copper (CrCu). The redistribution layer 16 includes a conductive material such as aluminum, gold, or nickel.

[0049] As Figure 3As shown, a first conductive layer 22, an insulating layer 24, and a second conductive layer 26 are sequentially formed. The first conductive layer 22, the insulating layer 24, and the second conductive layer 26 conformally cover the first copper pillar P1, the second copper pillar P2, the third copper pillar P3, and the fourth copper pillar P4 from bottom to top. The first conductive layer 22 includes titanium nitride or tantalum nitride, the second conductive layer 26 includes nickel, cobalt, or cobalt tungsten alloy, and the insulating layer 24 includes aluminum oxide, zirconium oxide, barium strontium titanate (BST), lead zirconate titanate (PZT), zirconium silicate (ZrSiO 4 ), hafnium silicon oxide (HfSiO 2 ), hafnium silicon oxynitride (HfSiON), tantalum oxide, or a combination of the above materials.

[0050] As Figure 4 shown, the first conductive layer 22, the insulating layer 24, and the second conductive layer 26 are patterned to form a MIM capacitor A and a stacked structure B. Specifically, the first conductive layer 22, the insulating layer 24, and the second conductive layer 26 are truncated to form an interval 28 between the first copper pillar P1 and the third copper pillar P3. The interval 28 is used to separate the first conductive layer 22, the insulating layer 24, and the second conductive layer 26 in the capacitor region C and the output / input region I / O, so that the first conductive layer 22, the insulating layer 24, and the second conductive layer 26 covering the first copper pillar P1, the second copper pillar P2, and the fourth copper pillar P4 in the capacitor region C form a MIM capacitor A. The first conductive layer 22 serves as the lower electrode E1, the insulating layer 24 serves as the capacitor dielectric layer D, and the second conductive layer 26 serves as the upper electrode E2. The first conductive layer 22, the insulating layer 24, and the second conductive layer 26 covering the third copper pillar P3 in the output / input region I / O form a stacked structure B. The first conductive layer 22, the insulating layer 24, and the second conductive layer 26 can be truncated by etching, and during the etching process, the first conductive layer 22, the insulating layer 24, and the second conductive layer 26 covering the upper surface of the third copper pillar P3 are also removed simultaneously.

[0051] As Figure 5 and Figure 6 shown, a first bonding bump 30a and a second bonding bump 30b are formed simultaneously. The first bonding bump 30a is disposed directly above the third copper pillar P3 and is electrically connected to the third copper pillar P3. The second bonding bump 30b is disposed directly above the second copper pillar P2 and is electrically connected to the MIM capacitor A. Specifically, as Figure 5As shown, the manufacturing process steps of the first bonding bump 30a and the second bonding bump 30 include first forming a first nickel layer 32a and a second nickel layer 32b. The first nickel layer 32a covers and contacts the upper surface of the third copper pillar P3, and the second nickel layer 32b covers and contacts the MIM capacitor A on the second copper pillar P2. After that, a first solder paste 34a and a second solder paste 34b are formed to cover the first nickel layer 32a and the second nickel layer 32b respectively. As Figure 6 shown, a reflow manufacturing process is performed so that the first solder paste 34a and the second solder paste 34a are transformed into a first solder ball 36a and a second solder ball 36b. The first nickel layer 32a and the second nickel layer 32b react with the tin to form a first intermetallic compound layer 38a and a second intermetallic compound layer 38b. The first intermetallic compound layer 38a and the second intermetallic compound layer 38b preferably include a nickel-silicon alloy or a nickel-silicon-copper alloy. Thus, an interposer 100 with an MIM capacitor of the present invention is completed. The interposer 100 with an MIM capacitor of the present invention can be used to bond with a chip, a substrate, or a circuit board to improve the packaging density of the product.

[0052] As Figure 6 shown, an interposer 100 with an MIM capacitor includes a substrate 10, and the substrate 10 can be silicon, glass, or a dielectric layer. A plurality of through vias 12 penetrate the substrate 10. Preferably, there are no active components, such as transistors, in the substrate 10. In addition to using the through vias 12 as connection lines in the interposer, a redistribution line layer can also be buried in the substrate 10 as a connection line. In the present invention, several through vias 12 are taken as an example. A redistribution line layer 16 is disposed on the substrate 10. A first copper pillar P1, a second copper pillar P2, a third copper pillar P3, and a fourth copper pillar P4 are disposed on the redistribution line layer 16. The first copper pillar P1, the second copper pillar P2, and the fourth copper pillar P4 are located in the capacitor region C, and the third copper pillar P3 is located in the input / output region I / O. The first copper pillar P1 and the third copper pillar P3 are each electrically connected to the redistribution line layer 16. The second copper pillar P2 and the fourth copper pillar P4 are both insulated from the redistribution line layer 16. Under the first copper pillar P1, the second copper pillar P2, the third copper pillar P3, and the fourth copper pillar P4, a bump under-bump metal layer 20 is respectively disposed. An MIM capacitor A covers and contacts the first copper pillar P1, the second copper pillar P2, and the fourth copper pillar P4. A stacked structure B covers and contacts the sidewall of the third copper pillar P3. The MIM capacitor A does not contact the third copper pillar P3. A first bonding bump 30a is disposed directly above the third copper pillar P3 and is electrically connected to the third copper pillar P3. A second bonding bump 30b is disposed directly above the second copper pillar P2 and is electrically connected to the MIM capacitor A.

[0053] The MIM capacitor A includes a lower electrode E1, a capacitor dielectric layer D, and an upper electrode E2 stacked in sequence from bottom to top. The lower electrode E1 contacts the first copper pillar P1, the second copper pillar P2, and the fourth copper pillar P4. The upper electrode E2 contacts the second bonding bump 30b. The second copper pillar P2 and the fourth copper pillar P4 are not used to connect to other circuits, but are used to increase the surface area of the MIM capacitor A, thereby increasing the capacitance value. According to different requirements, the numbers of the first copper pillar P1, the second copper pillar P2, and the fourth copper pillar P4 can be adjusted. In principle, the more copper pillars in the capacitor region C, the higher the capacitance value of the finally formed MIM capacitor A. The stacked structure B is formed by stacking a first conductive layer 22, an insulating layer 24, and a second conductive layer 26. The first conductive layer 22 contacts the third copper pillar P3. The insulating layer 24 is sandwiched between the first conductive layer 22 and the second conductive layer 26. As described in the previous manufacturing process, since the lower electrode E1 is formed by truncating the first conductive layer 22, the material of the first conductive layer 22 is the same as that of the lower electrode E1. The capacitor dielectric layer D is formed by truncating the insulating layer 24, so the material of the insulating layer 24 is the same as that of the capacitor dielectric layer D. The upper electrode E2 is formed by truncating the second conductive layer 26, so the material of the second conductive layer 26 is the same as that of the upper electrode E2. The first bonding bump 30a and the second bonding bump 30b contain tin. The lower electrode E1 contains titanium nitride or tantalum nitride, and the upper electrode E2 contains nickel, cobalt, or cobalt-tungsten alloy.

[0054] The third copper pillar P3 and the first bonding bump 30a are interlayers used to connect to the endpoints of another chip or substrate. The first copper pillar P1 is used to electrically connect the lower electrode E1 and the redistribution line layer 16. In addition, the first copper pillar P1, the second copper pillar P2, and the fourth copper pillar P4 all have a convex profile, so they can all increase the surface area of the MIM capacitor A. And because the first copper pillar P1, the second copper pillar P2, the third copper pillar P3, and the fourth copper pillar P4 are fabricated in the same manufacturing process, no additional manufacturing process steps are added. Generally speaking, a micro-bump is composed of a copper pillar and a bonding bump. For example, the third copper pillar P3 and the first bonding bump 30a are combined into a micro-bump. In the present invention, the MIM capacitor A is disposed in the micro-bump, that is, between the second copper pillar P2 and the second bonding bump 30b, and the MIM capacitor A is outside the redistribution line layer 16 and does not contact the redistribution line layer 16 at all.

[0055] In the present invention, MIM capacitors are disposed on the interposer layer, such that while the interposer layer connects chips (chip on chip) and a chip and a substrate (chip on wafer), electrical signals between chips on both sides of the interposer layer or between the chip and the substrate can be separated. Furthermore, in the present invention, a first conductive layer contacts the copper pillar, and the first conductive layer is titanium nitride or tantalum nitride. The first conductive layer not only serves as a lower electrode, but also, because titanium nitride or tantalum nitride is used, the situation of copper pillar protrusion or copper pillar fracture caused by copper atom migration can be avoided. In addition, in the present invention, a second conductive layer serves as an upper electrode and the second conductive layer contacts the inter-metal. Since the second conductive layer is nickel, cobalt or cobalt tungsten alloy, the second conductive layer can serve as a buffer layer to prevent tin atom diffusion. Additionally, because nickel, cobalt or cobalt tungsten alloy has a relatively high work function, a relatively large energy gap (band gap) drop can be caused to the capacitor dielectric layer. Therefore, the leakage of the MIM capacitor can be reduced.

[0056] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. An interposer with a metal-insulator-metal (MIM) capacitor, comprising: A substrate; A redistribution layer disposed on the substrate; A first copper pillar, a second copper pillar, and a third copper pillar disposed on the redistribution layer, wherein the first copper pillar and the third copper pillar are each electrically connected to the redistribution layer; A metal-insulator-metal capacitor covering and contacting the first copper pillar and the second copper pillar; A first bonding bump disposed directly above the third copper pillar and electrically connected to the third copper pillar; and A second bonding bump disposed directly above the second copper pillar and electrically connected to the metal-insulator-metal capacitor.

2. The interposer with a metal-insulator-metal capacitor according to claim 1, further comprising a fourth copper pillar disposed between the first copper pillar and the second copper pillar, wherein the metal-insulator-metal capacitor covers and contacts the fourth copper pillar.

3. The interposer with a metal-insulator-metal capacitor according to claim 1, wherein the metal-insulator-metal capacitor includes a lower electrode, a capacitive dielectric layer, and an upper electrode stacked in sequence from bottom to top, the lower electrode contacts the first copper pillar, and the upper electrode contacts the second bonding bump.

4. The interposer with a metal-insulator-metal capacitor according to claim 3, wherein the lower electrode includes titanium nitride or tantalum nitride, and the upper electrode includes nickel, cobalt, or cobalt tungsten alloy.

5. The interposer with a metal-insulator-metal capacitor according to claim 3, further comprising a stacked structure covering and contacting the sidewall of the third copper pillar, wherein the stacked structure is formed by stacking a first conductive layer, an insulating layer, and a second conductive layer, the first conductive layer contacts the third copper pillar, the material of the first conductive layer is the same as the material of the lower electrode, the material of the insulating layer is the same as the material of the capacitive dielectric layer, and the material of the second conductive layer is the same as the material of the upper electrode.

6. The interposer with a metal-insulator-metal capacitor according to claim 1, wherein the metal-insulator-metal capacitor does not contact the third copper pillar.

7. The interposer with a metal-insulator-metal capacitor according to claim 1, further comprising a via wire penetrating the substrate, the via wire being electrically connected to the redistribution layer.

8. The interposer with a metal-insulator-metal capacitor according to claim 1, wherein the first bonding bump includes tin.

9. The interposer with a metal-insulator-metal capacitor according to claim 1, wherein the second copper pillar is insulated from the redistribution layer.

10. A method for manufacturing an interposer with a metal-insulator-metal (MIM) capacitor, comprising: Providing a substrate; Forming a redistribution layer on the substrate; Form a first copper pillar, a second copper pillar, and a third copper pillar on the redistribution line layer, wherein the first copper pillar and the third copper pillar are each electrically connected to the redistribution line layer; Form a first conductive layer, an insulating layer, and a second conductive layer in sequence, and the first conductive layer, the insulating layer, and the second conductive layer cover the first copper pillar, the second copper pillar, and the third copper pillar from bottom to top; Cut off the first conductive layer, the insulating layer, and the second conductive layer to form an interval between the first copper pillar and the third copper pillar, such that the first conductive layer, the insulating layer, and the second conductive layer covering the first copper pillar and the second copper pillar form a metal-insulating layer-metal capacitor, and the first conductive layer, the insulating layer, and the second conductive layer covering the third copper pillar form a stacked structure; and Form a first bonding bump and a second bonding bump, the first bonding bump is disposed directly above the third copper pillar and electrically connected to the third copper pillar, and the second bonding bump is disposed directly above the second copper pillar and electrically connected to the metal-insulating layer-metal capacitor.

11. The method for manufacturing an interposer having a metal-insulating layer-metal capacitor as claimed in claim 10, further comprising forming a fourth copper pillar between the first copper pillar and the second copper pillar when forming the first copper pillar, the second copper pillar, and the third copper pillar, wherein the metal-insulating layer-metal capacitor covers and contacts the fourth copper pillar.

12. The method for manufacturing an interposer having a metal-insulating layer-metal capacitor as claimed in claim 10, wherein the first conductive layer comprises titanium nitride or tantalum nitride, and the second conductive layer comprises nickel, cobalt, or cobalt tungsten alloy.

13. The method for manufacturing an interposer having a metal-insulating layer-metal capacitor as claimed in claim 10, further comprising forming a via wire penetrating the substrate, and the via wire is electrically connected to the redistribution line layer.

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