Broadband silicon-based su-8 dielectric resonant antenna array and method of manufacturing the same

Abstract

A broadband silicon-based SU-8 dielectric resonant antenna array and its fabrication method are disclosed, comprising: a feeding substrate, an SU-8 layer disposed thereon, and a dielectric resonator located in the SU-8 layer, wherein: the dielectric resonator includes a dielectric body and a first metal layer; the feeding substrate includes: a second metal layer, a dielectric layer, and a third metal layer. This invention uses high-resistivity silicon as the main dielectric resonator and employs a coupled feeding method to fabricate a template with cavities on the feeding substrate using SU-8 photoresist, achieving high-precision manufacturing and array assembly of the dielectric resonant antenna, as well as rapid assembly and precise positioning; simultaneously, it has a wider operating bandwidth and advantages such as simple process steps, low cost, and rapid mass production.

Description

Technical Field

[0001] This invention relates to a technology in the field of radio frequency semiconductor devices, specifically a broadband silicon-based SU-8 dielectric resonant antenna array and its fabrication method. Background Technology

[0002] Dielectric resonant antennas utilize dielectric resonators as radiating elements, eliminating the need for metal radiating patches and avoiding conductor losses. Compared to printed metal antennas such as patch antennas using printed circuit board technology, they exhibit higher radiation efficiency and hold significant application value in the millimeter-wave band. Dielectric resonant antenna arrays, after being assembled, have higher gain, which helps overcome atmospheric attenuation in the millimeter-wave band and compensate for path losses. However, the inherent processing precision of current PCB technology and the assembly precision of dielectric resonators are difficult to meet technical requirements, resulting in lower antenna performance. Summary of the Invention

[0003] This invention addresses numerous shortcomings in existing dielectric resonant antenna manufacturing processes, including poor precision, large alignment errors, narrow operating bandwidth of silicon-based semiconductor processes, time-consuming etching due to time / size lag, and poor array uniformity. It proposes a broadband silicon-based SU-8 dielectric resonant antenna array and its fabrication method. The method utilizes high-resistivity silicon as the main dielectric resonator and employs a coupled feeding approach to fabricate a cavity-containing template on a feeding substrate using SU-8 photoresist. This enables high-precision manufacturing and array assembly of the dielectric resonant antenna, along with rapid assembly and precise positioning. Furthermore, it offers a wider operating bandwidth and boasts advantages such as simple process steps, low cost, and rapid mass production capability.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a broadband silicon-based SU-8 dielectric resonant antenna array, comprising: a feed substrate, an SU-8 layer disposed thereon, and a dielectric resonator located in the SU-8 layer, wherein: the dielectric resonator comprises a dielectric body and a first metal layer; the feed substrate comprises: a second metal layer, a dielectric layer, and a third metal layer.

[0006] The medium body is located on the second metal layer and spaced apart from the first metal layer.

[0007] The first metal layer has metal slots for adjusting the impedance matching and excitation mode of the dielectric resonant antenna array.

[0008] The dielectric layer is provided with metal vias that connect the second metal layer and the third metal layer respectively. The power feeding substrate is fed in the form of a microstrip line, the third metal layer serves as a conductor, and the second metal layer is connected to the ground potential.

[0009] Technical effect

[0010] This invention utilizes ultraviolet lithography to fabricate an SU-8 layer. SU-8 material has a low dielectric constant, and while the SU-8 layer incorporates a cavity structure, an additional metal layer with gaps is fabricated beneath the dielectric body of the dielectric resonator. Compared to existing technologies, this invention effectively reduces the equivalent dielectric constant of the dielectric resonator without altering its core structure, improving impedance matching of the antenna array and increasing efficiency. The SU-8 cavity structure provides constraint, enabling rapid and high-precision bonding and assembly of dielectric resonators of various shapes. The additional metal layer with gaps beneath the dielectric resonator effectively avoids the impact of air gaps caused by bonding on the coupling feed, further reducing the area and difficulty of applying conductive silver paste. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view of the silicon-based SU-8 dielectric resonant antenna array of the present invention;

[0012] Figure 2 This is a schematic diagram of the silicon-based SU-8 dielectric resonant antenna array of the present invention;

[0013] Figure 3 The diagram illustrates the bandwidth and gain performance of the antenna array in this invention.

[0014] Figure 4 This is a result diagram illustrating the antenna pattern of the present invention.

[0015] Figure 5 This is a result diagram illustrating the effects of different SU-8 thicknesses in this invention;

[0016] Figure 6 This is a flowchart of the preparation process of the present invention;

[0017] Figure 7 This is a schematic diagram illustrating the effect of the example;

[0018] In the figure: 1 dielectric substrate, 2 SU-8 layer, 3 first metal layer, 4 second metal layer, 5 metal via, 6 feed substrate dielectric layer, 7 third metal layer. Detailed Implementation

[0019] like Figure 1 As shown, this embodiment relates to a broadband silicon-based SU-8 dielectric resonant antenna array, including: a feed substrate, an SU-8 layer 2 disposed thereon, and a dielectric resonator located in the SU-8 layer 2. The dielectric resonator includes a dielectric body 1 and a first metal layer 3. The feed substrate includes: a second metal layer 4, a dielectric layer 6, and a third metal layer 7, wherein: the dielectric body 1 is located on the second metal layer 4 and is spaced apart from it by the first metal layer 3.

[0020] The first metal layer 3 is provided with metal gaps for adjusting the impedance matching and excitation mode of the dielectric resonant antenna array. The first metal layer 3 is fabricated on a high-resistivity silicon wafer using MEMS technology.

[0021] The dielectric layer 6 is provided with metal vias 5 that connect the second metal layer 4 and the third metal layer 7 respectively. The power feeding substrate is fed in the form of a microstrip line, the third metal layer 7 serves as a conductor, and the second metal layer 4 is connected to the ground potential.

[0022] The second metal layer 4 has a plurality of metal slots, the pattern of which is completely consistent with the metal slots on the first metal layer 3. These metal slots are used to adjust the impedance matching and excitation mode of the dielectric resonant antenna array.

[0023] The number of slots in the second metal layer 4 is consistent with the size of the antenna array. In this embodiment, there are 4 metal slots.

[0024] The aforementioned metal via 5 is a silicon via, fabricated using conventional TSV electroplating technology and filled with copper. Metal via 5 is used to form a GSG structure, facilitating RF probe feeding and providing only ground signals. It offers very high process freedom without affecting the overall impedance matching of the antenna. It can be fabricated directly using a 200μm thick high-resistivity silicon wafer, or by thinning a thicker silicon wafer.

[0025] The dielectric layer 6 has a thickness of 200μm and is fabricated using high-resistivity silicon.

[0026] The third metal layer 7 is a microstrip power divider pattern, used to efficiently transfer externally fed energy to each radiating element, and also has a significant impact on the overall operating bandwidth of the antenna array. The fabrication method can employ conventional MEMS processes such as sputtering-photolithography-electroplating-resor removal-etching. The microstrip power divider pattern can be adjusted according to actual needs. This embodiment is a 1-to-4 microstrip power divider, constructed using a cascaded T-type network.

[0027] The shape and size of the dielectric body 1 can be adjusted according to the operating frequency and operating mode. In this embodiment, a quadrangular prism with a thickness of 1mm and a side length of 3mm is selected, operating in TE111 mode. It can be fabricated by cutting a high-resistivity silicon wafer with a thickness of 1mm.

[0028] The SU-8 layer 2 is fabricated by spin-coating liquid SU-8 photoresist and then processing a cavity structure using ultraviolet lithography. The shape of the cavity structure is consistent with the cross-sectional shape of the dielectric body 1, and the number of cavities is consistent with the size of the antenna array. The thickness of the SU-8 photoresist is 400 μm, obtained through multiple spin-coating processes to ensure the flatness of the SU-8. A thicker SU-8 layer is beneficial for improving the overall matching of the antenna array.

[0029] The connection between the dielectric body 1 and the first metal layer 3 and the power supply substrate can be achieved by wafer bonding, manual bonding, or other methods; the SU-8 layer 2 can assist in assembly and alignment.

[0030] like Figure 6 As shown, the method for preparing the broadband silicon-based SU-8 dielectric resonant antenna array in this embodiment includes:

[0031] Step 1, the feed substrate fabrication stage, specifically includes:

[0032] 1.1 A layer of photoresist is spin-coated on the substrate, and a photoresist mask required for deep silicon etching is prepared by photolithography. The silicon wafer with the photoresist mask is then subjected to deep silicon etching using an NMC ICP reactive ion etching machine. The etching thickness is greater than the thickness of the final feed substrate.

[0033] The substrate is a 4-inch, 445μm thick double-polished high-resistivity silicon substrate with a resistivity of 10000Ω·cm.

[0034] 1.2 The substrate is processed with through-silicon vias using the Damascus through-silicon via process, and the surface copper is ground and polished.

[0035] 1.3 The silicon wafer is thinned on the back side to obtain the required dielectric substrate thickness and expose the copper.

[0036] 1.4 A metal pattern with a thickness of 4 μm was prepared by a process sequence of sputtering-photolithography-electroplating-resist stripping-etching, which is the third metal layer 7.

[0037] 1.5 A metal pattern with a thickness of 4 μm is prepared by a process sequence of sputtering-photolithography-electroplating-resist stripping-etching, which is the second metal layer 4; before electroplating, the third metal layer 7 needs to be masked with protective adhesive.

[0038] 1.6 The feed substrate is processed by spin-coating SU-8 photoresist multiple times and combining it with ultraviolet lithography.

[0039] Step 2, the dielectric resonator fabrication stage, specifically includes:

[0040] 2.1 A metal pattern with a thickness of 4 μm was prepared on a high-resistivity silicon substrate with a thickness of 1 mm by a process sequence of sputtering-photolithography-electroplating-resist stripping-etching. This is the first metal layer 3.

[0041] 2.2 A separated dielectric resonator is obtained by diamond dicing, specifically comprising a dielectric body 1 and a first metal layer 3;

[0042] 2.3 The dielectric resonator and the feed substrate are artificially bonded by applying conductive silver paste to complete the fabrication of the overall antenna array.

[0043] This embodiment first verifies, using the full-wave simulation software HFSS, that the addition of the first metal layer 3 significantly reduces the impact of the air gap on the slot-coupled feed. Figure 7 As shown, a dielectric resonator is excited in a typical linear slot coupling within a single antenna element; further verification of the improvement effect of SU-8 layer 2 on the impedance matching of the antenna array is performed using the full-wave simulation software HFSS. Figure 5 The figure shows the reflection coefficient of a 1×4 antenna array excited by a dumbbell-shaped slot coupling under SU-8 layers of different thicknesses.

[0044] like Figure 3 As shown in the figure, through specific practical experiments, the reflection coefficient is less than -10dB and the gain is greater than 8.7dBi in the 24-33GHz frequency band. Using dumbbell-shaped slot coupling excitation, the normalized radiation pattern of this antenna array is as follows. Figure 4 As shown.

[0045] Compared with the prior art, the present invention achieves high-precision assembly of dielectric resonant antenna array and improved impedance matching within the frequency band through the SU-8 layer, and the first metal layer avoids the influence of air gaps on the dielectric resonator.

[0046] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A broadband silicon-based SU-8 dielectric resonant antenna array, characterized in that, include: A power feeding substrate, an SU-8 layer disposed thereon, and a dielectric resonator located in the SU-8 layer, wherein: the dielectric resonator includes a dielectric body and a first metal layer; the power feeding substrate includes: a second metal layer, a dielectric layer, and a third metal layer; The dielectric body is located on the second metal layer, and the first metal layer is located between the dielectric body and the second metal layer; The first metal layer is provided with metal slots for adjusting the impedance matching and excitation mode of the dielectric resonant antenna array. The dielectric layer is provided with metal vias that connect the second metal layer and the third metal layer respectively. The power feeding substrate is fed in the form of a microstrip line, the third metal layer serves as a conductor, and the second metal layer is connected to the ground potential. The second metal layer has a plurality of metal slots, the pattern of which is completely consistent with the metal slots on the first metal layer. These metal slots are used to adjust the impedance matching and excitation mode of the dielectric resonant antenna array. The number of slots in the second metal layer is consistent with the size of the antenna array.

2. The broadband silicon-based SU-8 dielectric resonant antenna array according to claim 1, characterized in that, The third metal layer is a microstrip power divider pattern.

3. The broadband silicon-based SU-8 dielectric resonant antenna array according to claim 1, characterized in that, The connection between the dielectric substrate and the first metal layer as a whole and the power supply substrate is achieved by wafer bonding or manual bonding.

4. A method for preparing a broadband silicon-based SU-8 dielectric resonant antenna array according to any one of claims 1-3, characterized in that, include: Step 1, the feed substrate fabrication stage, specifically includes: 1.1 A layer of photoresist is spin-coated on the substrate, and a photoresist mask required for deep silicon etching is prepared by photolithography. The silicon wafer with the photoresist mask is then subjected to deep silicon etching using an NMC ICP reactive ion etching machine. The etching thickness is greater than the thickness of the final feed substrate. 1.2 The substrate is processed with through-silicon vias using the Damascus through-silicon via process, and the surface copper is ground and polished. 1.3 The silicon wafer is thinned on the back side to obtain the required dielectric substrate thickness and expose the copper. 1.4 A metal pattern, namely the third metal layer, is prepared by a process sequence of sputtering-photolithography-electroplating-resist stripping-etching; 1.5 A metal pattern, namely the second metal layer, is prepared by a process sequence of sputtering-photolithography-electroplating-resist stripping-etching; a third metal layer needs to be masked with protective adhesive before electroplating. 1.6 The feed substrate is processed by spin-coating SU-8 photoresist multiple times and combining it with ultraviolet lithography; Step 2, the dielectric resonator fabrication stage, specifically includes: 2.1 A metal pattern, namely the first metal layer, is prepared on high-resistivity silicon using a process sequence of sputtering-photolithography-electroplating-resist stripping-etching; 2.2 A separated dielectric resonator, consisting of a dielectric substrate and a first metal layer, is obtained by diamond dicing. 2.3 The dielectric resonator and the feed substrate are artificially bonded by applying conductive silver paste to complete the fabrication of the overall antenna array.

Images