Analog front-end amplifier based on hybrid architecture direct current offset suppression loop

Abstract

The invention discloses an analog front-end amplifier based on a hybrid architecture direct-current offset suppression loop. The analog front-end amplifier comprises a capacitive coupling instrument amplifier with a chopper and a hybrid architecture DSL, wherein the hybrid architecture DSL comprises a digital DSL module and an analog DSL module. The digital DSL detects an output signal in real time in a compensation mode, generates different compensation currents according to different DC imbalance, and switches to a holding mode after the output is stable; the analog DSL is high in compensation precision and good in noise performance, and is used for compensating residual electrode direct current imbalance; under the combined action of the hybrid architecture DSL, the direct current offset suppression range of the electrode is widened, the compensation precision is improved, and the useful signal loss is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and particularly relates to an analog front-end amplifier based on a hybrid architecture DC offset suppression loop. Background Art

[0002] The real-time recording and monitoring of electroencephalogram (EEG) signals are the basis and prerequisite for the treatment of brain diseases such as epilepsy. Traditional invasive EEG signal acquisition devices can no longer meet people's needs, and current EEG signal acquisition systems are developing in the direction of non-invasive, low-power, and small-area. The amplitude of EEG signals is between 1 - 100 μV, and the frequency is between 1 - 100 Hz, which is easily affected by external environmental interference and circuit noise.

[0003] Due to its high noise efficiency, the chopper capacitor-coupled amplifier has become the mainstream architecture of analog front-end amplifiers for biological signal acquisition. Compared with traditional capacitor-coupled amplifiers, this structure introduces chopper modulation technology, improving the common-mode rejection ratio of the system, but losing the ability to suppress electrode DC offset. For non-invasive EEG signal acquisition systems, differences in electrodes and different skin contact effects can cause electrode DC offset to reach ±300 mV in the worst case, seriously affecting the normal operation of the analog front-end amplifier. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides an analog front-end amplifier based on a hybrid architecture DC offset suppression loop.

[0005] The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] In a first aspect, the present invention provides an analog front-end amplifier based on a hybrid architecture DC offset suppression loop, including: a capacitor-coupled instrumentation amplifier with a chopper and a hybrid architecture DSL; wherein, the hybrid architecture DSL includes: a digital DSL module and an analog DSL module;

[0007] The capacitor-coupled instrumentation amplifier with a chopper is used to amplify the input signal and separate the circuit noise in the input signal by using the chopper to obtain an output signal;

[0008] The digital DSL module is used to switch to a compensation mode when the output signal is greater than or equal to a threshold signal to generate a compensation current and obtain a compensated output signal; it is also used to switch to a hold mode when the output signal is less than the threshold signal;

[0009] The analog DSL module is used to eliminate the DC offset voltage in the compensated output signal to obtain a target EEG signal.

[0010] Optionally, the capacitive-coupled instrumentation amplifier with a chopper includes: an input chopper switch CH1, an input capacitor Cin1, an input capacitor Cin2, an operational amplifier GM1, an operational amplifier GM2, a feedback capacitor Cfb1, a feedback capacitor Cfb2, a positive feedback capacitor Cpf1, a positive feedback capacitor Cpf2, a feedback chopper switch CH3, a DC feedback resistor Rb1, and a DC feedback resistor Rb2; the input terminal of the input chopper switch CH1 is connected to the input signal, the output terminal of the input chopper switch CH1 is respectively connected to the lower plates of the input capacitor Cin1, the input capacitor Cin2, the positive feedback capacitor Cpf1, and the positive feedback capacitor Cpf2, the non-inverting input terminal VDSL+ of the operational amplifier GM1 is respectively connected to the lower plate of the input capacitor Cin1, the lower plate of the feedback capacitor Cfb1, and the first terminal of the DC feedback resistor Rb1, the inverting input terminal VDSL- of the operational amplifier GM1 is connected to the lower plate of the input capacitor Cin2, the lower plate of the feedback capacitor Cfb2, and the first terminal of the DC feedback resistor Rb2, the inverting output terminal Vout- of the operational amplifier GM2 is connected to the first output terminal of the feedback chopper switch CH3, the non-inverting output terminal Vout+ of the operational amplifier GM2 is connected to the second output terminal of the feedback chopper switch CH3, and the input terminal of the feedback chopper switch CH3 is respectively connected to the upper plates of the feedback capacitor Cfb1, the feedback capacitor Cfb2, the positive feedback capacitor Cpf1, and the positive feedback capacitor Cpf2.

[0011] Optionally, the capacitive-coupled instrumentation amplifier with a chopper further includes: a ripple suppression module; the ripple suppression module includes: a filter capacitor Cr1, a filter capacitor Cr2, an output chopper switch CH2, a bias resistor Rb3, and a bias resistor Rb4; the inverting output terminal of the operational amplifier GM1 is respectively connected to the second terminal of the bias resistor Rb1 and the upper plate of the filter capacitor Cr1, the non-inverting output terminal of the operational amplifier GM1 is respectively connected to the second terminal of the DC feedback resistor Rb2 and the upper plate of the filter capacitor Cr2, the lower plates of the filter capacitor Cr1 and the filter capacitor Cr2 are both connected to the input terminal of the output chopper switch CH2, and the output terminal of the output chopper switch CH2 is respectively connected to the first terminal of the bias resistor Rb3, the first terminal of the bias resistor Rb4, the non-inverting input terminal of the operational amplifier GM2, and the inverting input terminal of the operational amplifier GM2.

[0012] Optionally, the digital DSL module includes: a comparator Comp1, a comparator Comp2, a logic control circuit, an n Bit counter, and a compensation capacitor array; the non-inverting input terminal of the comparator Comp1 is connected to the non-inverting output terminal Vout+ of the operational amplifier GM2, the non-inverting input terminal of the comparator Comp2 is connected to the inverting output terminal Vout- of the operational amplifier GM2, the inverting input terminals of both the comparator Comp1 and the comparator Comp2 are connected to the threshold voltage VTH, the output terminal of the comparator Comp1 is connected to the first input terminal of the logic control circuit, the output terminal of the comparator Comp2 is connected to the second input terminal of the logic control circuit, the first output terminal of the logic control circuit is connected to the first input terminal of the n Bit counter, the second output terminal of the logic control circuit is connected to the second input terminal of the n Bit counter, and the third output terminal of the logic control circuit is connected to the input terminal of the compensation capacitor array.

[0013] Optionally, the analog DSL module includes: switch S1, switch S2, switch S3, switch S4, switch S5, switch S6, switch S7, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, chopper switch CH5, chopper switch CH6, and integrator operational amplifier GM3; the first end of switch S1 is connected to the non-inverting output terminal Vout+ of operational amplifier GM2, the first end of switch S2 is connected to the inverting output terminal Vout- of operational amplifier GM2, the second end of switch S1 is connected to the first end of switch S3, the second end of switch S2 is connected to the second end of switch S3, the first end of switch S3 is connected to the upper plate of capacitor C1, the second end of switch S3 is connected to the upper plate of capacitor C2, the lower plate of capacitor C1 is connected to the first input terminal of chopper switch CH5, the lower plate of capacitor C2 is connected to the second input terminal of chopper switch CH5, the first output terminal of chopper switch CH5 is connected to the non-inverting input terminal of integrator operational amplifier GM3, the second output terminal of chopper switch CH5 is connected to the inverting input terminal of integrator operational amplifier GM3, chopper switch CH6 is embedded in integrator operational amplifier GM3, the first output terminal of chopper switch CH6 is connected to the non-inverting input terminal of integrator operational amplifier GM3, the second output terminal of chopper switch CH6 is connected to the inverting input terminal of integrator operational amplifier GM3, the upper plate of capacitor C5 is connected to the first input terminal of the chopper switch, the lower plate of capacitor C5 is connected to the non-inverting output terminal of integrator operational amplifier GM3, the upper plate of capacitor C6 is connected to the second input terminal of the chopper switch, the lower plate of capacitor C6 is connected to the inverting output terminal of integrator operational amplifier GM3, the first end of switch S4 is connected to the first input terminal of chopper switch CH5, the second end of switch S4 is respectively connected to the upper plate of capacitor C3 and the first end of switch S6, the lower plate of capacitor C3 is connected to the non-inverting output terminal of integrator operational amplifier GM3, the second end of switch S6 is connected to the fixed level Vcm, the first end of switch S5 is connected to the second input terminal of chopper switch CH5, the second end of switch S5 is respectively connected to the upper plate of capacitor C4 and the first end of switch S7, the lower plate of capacitor C4 is connected to the inverting output terminal of integrator operational amplifier GM3, and the second end of switch S7 is connected to the fixed level Vcm.

[0014] Optionally, the analog DSL module further includes: a switched-capacitor integrator; the switched-capacitor integrator includes: a chopper switch CH4, an analog DSL capacitor CA_DSL1, and an analog DSL capacitor CA_DSL2; a first output terminal of the chopper switch CH4 is connected to an upper plate of the analog DSL capacitor CA_DSL1, a lower plate of the analog DSL capacitor CA_DSL1 is connected to a non-inverting input terminal VDSL+ of the operational amplifier GM1, a second output terminal of the chopper switch CH4 is connected to an upper plate of the analog DSL capacitor CA_DSL2, and a lower plate of the analog DSL capacitor CA_DSL2 is connected to an inverting input terminal VDSL- of the operational amplifier GM1.

[0015] Optionally, the bandwidth of the switched-capacitor integrator is expressed as follows:

[0016]

[0017] where f integ represents the bandwidth of the switched-capacitor integrator, f chop represents the chopping clock, C 1，2 represents the capacitance value of capacitor C1 or capacitor C2, C 5，6 represents the capacitance value of capacitor C5 or capacitor C6, C 3，4 represents the capacitance value of capacitor C3 or capacitor C4.

[0018] Optionally, the relationship between the bandwidth of the switched-capacitor integrator and the loop high-pass cut-off frequency is expressed as follows:

[0019]

[0020] where f hp represents the high-pass cut-off frequency introduced by the switched-capacitor integrator in the entire analog front-end circuit, C A_DSL represents the capacitance value of the analog DSL capacitor CA_DSL1 or the analog DSL capacitor CA_DSL2, C fb1，2 represents the capacitance value of the feedback capacitor Cfb1 or the feedback capacitor Cfb2.

[0021] Optionally, the maximum value of the DC offset voltage eliminated by the analog DSL is expressed as follows:

[0022]

[0023] where V EOV represents the maximum value of the DC offset voltage eliminated by the analog DSL, C in1，2 represents the capacitance value of the input capacitor Cin1 or the input capacitor Cin2, V out-max represents the maximum output amplitude of the integrator operational amplifier GM3.

[0024] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects:

[0025] In the above technical solution, an analog front-end amplifier based on a hybrid architecture DC offset suppression loop is proposed. The analog DSL module and the digital DSL module in it work together to ensure that the signal can be amplified normally. The digital DSL module can generate different compensation currents in real time according to different output DC offsets, and will not affect the noise performance of the entire analog front end; the analog DSL module has high compensation accuracy, can eliminate the remaining DC offset voltage, and avoids the subsequent circuit being affected.

[0026] The following will further elaborate on the present invention in detail with reference to the drawings and embodiments. Description of the Drawings

[0027] Figure 1 is a schematic structural diagram of an analog front-end amplifier based on a hybrid architecture DC offset suppression loop provided by an embodiment of the present invention;

[0028] Figure 2 is a schematic structural diagram of a digital DSL module provided by an embodiment of the present invention;

[0029] Figure 3 is a flowchart of the operation of a digital DSL module proposed by the present invention;

[0030] Figure 4 is a schematic structural diagram of an analog DSL module provided by an embodiment of the invention;

[0031] Figure 5 is a schematic diagram of the waveform change of the electrode DC offset provided by an embodiment of the present invention;

[0032] Figure 6 is a schematic diagram of the suppression effect of DC offset provided by an embodiment of the present invention. Detailed Embodiments

[0033] To facilitate the understanding of the solution of the present invention, the relevant situation of the prior art and the inventive concept of the present invention will be briefly described first.

[0034] In the prior art, in order to solve the problems of poor PVT characteristics, noise performance and DC offset suppression ability of the analog integrator composed of traditional pseudo-resistors and capacitors, a new type of GMCI was proposed based on the GM-C integrator structure 2- DSL (DC Servo Loop, a hybrid architecture DC offset suppression loop). This loop uses a GM-C integrator to integrate the output signal. After passing through a chopper switch, the offset signal modulated to a high frequency is fed back between the cascode transistors of the main operational amplifier of the instrumentation amplifier, canceling out the offset signal of the main channel and achieving DC offset suppression for the electrodes. Among them, the cascode transistor is shared by the instrumentation amplifier and the analog DSL feedback amplifier, avoiding the introduction of analog DSL capacitors and improving the integration of the entire analog front-end chip.

[0035] Although Document 1 eliminates the compensation capacitor and improves the integration of the entire chip, limited by the linearity of the GM-C integrator, the DC offset suppression ability of the electrodes in the entire front-end is only 20 mV, far lower than the index requirements of non-invasive EEG devices.

[0036] Document 2 abandons the traditional analog DC offset suppression loop and eliminates most of the DC offset signals only through the operation of the digital DC offset suppression loop, enabling the front-end amplifier to return to the normal operating state. The digital DSL in this invention uses four comparators to monitor the output signal and generates a calibration signal through a control logic circuit to control the output voltage in the offset calibration circuit. A bandgap reference circuit is used to generate a reference voltage, and this reference voltage is divided by a resistor string to generate calibration voltages of different magnitudes. According to different calibration signals, the corresponding output voltage is adjusted to achieve offset calibration.

[0037] The compensation voltage in the digital DSL of Document 2 is generated by a bandgap reference circuit and a resistor string network. The compensation accuracy of the circuit is determined by the voltage division of the control circuit and the bandgap reference circuit. The higher the accuracy, the worse the matching accuracy of the resistor string. The limited accuracy of this digital DSL results in a DC offset in the output signal, which may interfere with the normal operation of the subsequent circuit. In addition, the thermal noise of the bandgap reference circuit and the resistor string will be introduced into the input of the operational amplifier through the compensation capacitor, deteriorating the noise performance.

[0038] A high-precision instrumentation amplifier based on hybrid architecture offset calibration is designed in Document 3. The digital calibration circuit consists of a SAR ADC (Successive Approximation Register), a latch, and a DAC (Digital-to-Analog Converter) array. The analog calibration circuit is designed based on an integrator composed of traditional pseudo-resistors and capacitors, and is fed back to the input of the operational amplifier through a chopper switch and a compensation capacitor. The working principle of this invention is as follows: when the instrumentation amplifier starts to work, the closed-loop gain is set to 1. The SAR ADC starts to work, converts the output analog signal into a digital signal and inputs it into the latch for latching. After the enable signal flips, the latch transmits the nBit digital code to the DAC array to control the operation of the DAC unit. At this time, the SAR ADC does not work, and the instrumentation amplifier works under normal gain conditions. The electrode DC offset is suppressed by the compensation current generated by the DAC array, and the entire instrumentation amplifier can amplify the signal normally.

[0039] The hybrid architecture DSL in Document 3 uses a SAR ADC to quantize the output signal, increasing the complexity and cost of the circuit. In addition, this digital DSL only works when the gain of the instrumentation amplifier is 1 and cannot monitor the circuit output in real time. The integrator of the analog DSL has poor frequency characteristics and noise performance under different conditions, which will affect the linearity of the EEG signal.

[0040] Figure 1 It is a schematic structural diagram of an analog front-end amplifier based on a hybrid architecture DC offset suppression loop provided by an embodiment of the present invention, as Figure 1 shown, including: a capacitive-coupled instrumentation amplifier with a chopper and a hybrid architecture DSL; wherein, the hybrid architecture DSL includes: a digital DSL module and an analog DSL module.

[0041] The capacitive-coupled instrumentation amplifier with a chopper is used to amplify the input signal and separate the circuit noise in the input signal by using the chopper to obtain the output signal.

[0042] Optionally, the capacitive-coupled instrumentation amplifier with a chopper includes: an input chopper switch CH1, an input capacitor Cin1, an input capacitor Cin2, operational amplifiers GM1 and GM2, feedback capacitors Cfb1 and Cfb2, positive feedback capacitors Cpf1 and Cpf2, a feedback chopper switch CH3, a DC feedback resistor Rb1, and a DC feedback resistor Rb2; the input terminal of the input chopper switch CH1 is connected to an input signal, and the output terminal of the input chopper switch CH1 is respectively connected to the lower plates of the input capacitor Cin1, the input capacitor Cin2, the positive feedback capacitor Cpf1, and the positive feedback capacitor Cpf2. The non-inverting input terminal VDSL+ of the operational amplifier GM1 is respectively connected to the lower plate of the input capacitor Cin1, the lower plate of the feedback capacitor Cfb1, and the first terminal of the DC feedback resistor Rb1. The inverting input terminal VDSL- of the operational amplifier GM1 is connected to the lower plate of the input capacitor Cin2, the lower plate of the feedback capacitor Cfb2, and the first terminal of the DC feedback resistor Rb2. The inverting output terminal Vout- of the operational amplifier GM2 is connected to the first output terminal of the feedback chopper switch CH3, and the non-inverting output terminal Vout+ of the operational amplifier GM2 is connected to the second output terminal of the feedback chopper switch CH3. The input terminal of the feedback chopper switch CH3 is respectively connected to the upper plates of the feedback capacitor Cfb1, the feedback capacitor Cfb2, the positive feedback capacitor Cpf1, and the positive feedback capacitor Cpf2.

[0043] Optionally, the capacitive-coupled instrumentation amplifier with a chopper further includes: a ripple suppression module; the ripple suppression module includes: a filter capacitor Cr1, a filter capacitor Cr2, an output chopper switch CH2, a bias resistor Rb3, and a bias resistor Rb4; the inverting output terminal of the operational amplifier GM1 is respectively connected to the second terminal of the bias resistor Rb1 and the upper plate of the filter capacitor Cr1, and the non-inverting output terminal of the operational amplifier GM1 is respectively connected to the second terminal of the DC feedback resistor Rb2 and the upper plate of the filter capacitor Cr2. The lower plates of the filter capacitor Cr1 and the filter capacitor Cr2 are both connected to the input terminal of the value output chopper switch CH2, and the output terminal of the output chopper switch CH2 is respectively connected to the first terminal of the bias resistor Rb3, the first terminal of the bias resistor Rb4, the non-inverting input terminal of the operational amplifier GM2, and the inverting input terminal of the operational amplifier GM2.

[0044] It can be understood that operational amplifiers GM1 and GM2 form the main operational amplifiers of a chopper-stabilized capacitive-coupled instrumentation amplifier, meeting the requirements of gain and large output swing. The ratio of the capacitance values of input capacitor Cin1, input capacitor Cin2, feedback capacitor Cfb1, and feedback capacitor Cfb2 determines the gain of the entire instrumentation amplifier. The pseudo-resistors Rb1 and Rb2 formed by PMOS are respectively biased at each input terminal and the output terminal of operational amplifier GM1, forming a DC feedback path to determine the input common-mode level of the operational amplifier. CH1, CH2, and CH3 are the input chopper switch, output chopper switch, and feedback chopper switch respectively. The output chopper switch CH2 modulates the low-frequency 1 / f noise of operational amplifier GM1 to the chopping frequency and its harmonics, isolates it from the input signal that has returned to the original frequency after two chopping modulations, and then filters it through the subsequent filter, reducing the system noise. The feedback chopper switch CH3 ensures the correctness of the feedback polarity. Filter capacitors Cr1 and Cr2, together with pseudo-resistors Rb3 and Rb4, form a high-pass filter to filter out the offset and low-frequency noise in operational amplifier GM1 and attenuate the ripple at the output terminal of the instrumentation amplifier. A positive feedback is introduced between the output and input capacitors of the instrumentation amplifier. After the output signal is modulated by the feedback chopper switch CH3, it is converted into a current through positive feedback capacitors Cpf1 and Cpf2 and injected into the input capacitor, reducing the current injected from the electrode input terminal and increasing the equivalent input impedance.

[0045] The digital DSL module is used to switch to the compensation mode to generate a compensation current and obtain a compensated output signal when the output signal is greater than or equal to the threshold signal; it is also used to switch to the hold mode when the output signal is less than the threshold signal.

[0046] Optionally, Figure 2 is a schematic structural diagram of a digital DSL module provided by an embodiment of the present invention, as Figure 2 shown, the digital DSL module includes: comparator Comp1, comparator Comp2, logic control circuit, n Bit counter, and compensation capacitor array; the non-inverting input terminal of comparator Comp1 is connected to the non-inverting output terminal Vout+ of operational amplifier GM2, the non-inverting input terminal of comparator Comp2 is connected to the inverting output terminal Vout- of operational amplifier GM2, the inverting input terminals of comparator Comp1 and comparator Comp2 are both connected to the threshold voltage VTH, the output terminal of comparator Comp1 is connected to the first input terminal of the logic control circuit, the output terminal of comparator Comp2 is connected to the second input terminal of the logic control circuit, the first output terminal of the logic control circuit is connected to the first input terminal of the n Bit counter, the second output terminal of the logic control circuit is connected to the second input terminal of the n Bit counter, and the third output terminal of the logic control circuit is connected to the input terminal of the compensation capacitor array.

[0047] It can be understood that in the digital DSL module, the comparators Comp1 and Comp2 respectively output signals Flag_p and Flag_n to the input terminals of the logic control circuit. The logic control module outputs the enable signal COMP of the n-bit counter and the clear signal RST of the n-bit counter to control the operation of the n-bit counter, and outputs the chopping clock phase control signal S_chop to the compensation capacitor array to control the chopping switch clock phase. The n-bit counter outputs an n-bit control code Q under the action of the logic control circuit and the clock CLK <n-1:0>and its inverted signal QN <n-1:0>The compensation capacitor array is composed of n groups of switched capacitors and chopper switches. Two groups of n-bit control signals output by the counter are respectively the control signals for the switches of the corresponding compensation capacitor units. The power supply voltages VDD and VSS are connected to the input terminals of the chopper switches of the compensation capacitor units. The output terminals of the chopper switches are connected to the switched capacitors, and then are respectively connected to the non-inverting input terminal VDSL+ and the inverting input terminal VDSL- of the operational amplifier GM1.

[0048] The digital DSL module has two operating modes: compensation mode and hold mode. Two comparators respectively detect the non-inverting output terminal Vout+ and the inverting output terminal Vout- of the capacitive-coupled instrumentation amplifier with a chopper, and determine whether the output exceeds the normal range, so as to determine the operating state of the digital DSL module. If the output signal of the non-inverting output terminal Vout+ or the inverting output terminal Vout- is greater than the threshold signal VTH, a flag Flag_p = 1 or Flag_n = 1 is sent to the control logic, and the digital DSL module enters the compensation mode. The logic control circuit generates an enable signal COMP, a clear signal RST, and a phase control signal S_chop according to the received flag bits. The enable signal COMP is used to control the counting of the n Bit counter. The clear signal RST is a signal that controls the counter to be cleared when the contact state of the bioelectrode changes, resulting in a change in the DC offset polarity. When the DC offset polarity changes, the entire digital DSL module needs to be restored to the initial state, RST = 1, and the n Bit counter is cleared. S_chop becomes 0, controlling the clock phase change of the chopper switch of the compensation capacitor array to ensure the correct DC offset compensation polarity. The control signal COMP controls the counting of the n Bit counter and outputs a control code Q <n-1:0>Control the operation of the compensation capacitor array. The compensation capacitor array is composed of n groups of chopper switches and switched capacitors. During operation, the compensation current is output to the input terminals VDSL+ and VDSL- of the operational amplifier GM1. When not working, the compensation capacitor array of the digital DSL module is connected to the ground. It is worth mentioning that the capacitance values of the capacitors in the compensation capacitor array are configured according to the binary rule, and the unit capacitor is C d_DSL . In theory, the maximum DC offset of the electrodes that can be eliminated by the compensation capacitor array of the n-bit counter is:

[0049]

[0050] For example, when the unit capacitor C d_DSL = 23 fF, the power supply voltage is 1.8 V, and the counter bit number is 6 bits, the maximum DC offset of the electrodes that can be eliminated by this digital DSL module is 523 mV, meeting the requirements of the non-invasive system.

[0051] In one implementation, taking a 6-bit counter as an example, Figure 3 is the flowchart of the operation of a digital DSL module proposed by the present invention. For example, if there is a DC offset of dozens of mV at the input electrode, the output signal of the non-inverting output terminal Vout+ is greater than the threshold signal VTH, and the comparator Comp1 outputs Flag_p = 1. After passing through the logic control circuit, COMP = 1, RST = 0, and S_chop = 1 are output. The clock phase of the chopper switch remains unchanged, and the n-bit counter counts under the control of the rising edge of CLK. The 6-bit control signal Q<5:0> output controls the corresponding compensation capacitor array to be connected to the non-inverting input terminal of the operational amplifier GM1. After the next clock rising edge arrives, the comparator Comp1 continues to compare the amplitude of the output signal. If Flag_p = 1, it means that the generated compensation current is not enough, and the counter continues to count. If Flag_p = 0, it means that the DC offset of the electrode is suppressed, and the output signal returns to the normal operating range. At this time, the n-bit counter stops counting, and the entire digital DSL module operates in the hold mode. If the polarity of the DC offset suddenly reverses at a certain moment, the comparator outputs Flag_p = 0 and Flag_n = 1. After passing through the logic control circuit, COMP = 1, RST = 1, and S_chop = 0 are output. The n-bit counter will be cleared for a period of time and then start counting again. The chopper switch clock of the compensation capacitor array operates in reverse, and the n-bit counter starts counting again under the control of the clock, generating an inverted compensation current to the input terminal of the operational amplifier GM1.

[0052] The analog DSL module is used to eliminate the DC offset voltage in the compensated output signal to obtain the target EEG signal.

[0053] Optionally, Figure 4 It is a schematic structural diagram of an analog DSL module provided by an invention embodiment. As Figure 4 shown, the analog DSL module includes: switch S1, switch S2, switch S3, switch S4, switch S5, switch S6, switch S7, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, chopper switch CH5, chopper switch CH6, and integrator operational amplifier GM3. The first terminal of switch S1 is connected to the non-inverting output terminal Vout+ of operational amplifier GM2. The first terminal of switch S2 is connected to the inverting output terminal Vout- of operational amplifier GM2. The second terminal of switch S1 is connected to the first terminal of switch S3. The second terminal of switch S2 is connected to the second terminal of switch S3. The first terminal of switch S3 is connected to the upper plate of capacitor C1. The second terminal of switch S3 is connected to the upper plate of capacitor C2. The lower plate of capacitor C1 is connected to the first input terminal of chopper switch CH5. The lower plate of capacitor C2 is connected to the second input terminal of chopper switch CH5. The first output terminal of chopper switch CH5 is connected to the non-inverting input terminal of integrator operational amplifier GM3. The second output terminal of chopper switch CH5 is connected to the inverting input terminal of integrator operational amplifier GM3. Chopper switch CH6 is embedded in integrator operational amplifier GM3. The first output terminal of chopper switch CH6 is connected to the non-inverting input terminal of integrator operational amplifier GM3. The second output terminal of chopper switch CH6 is connected to the inverting input terminal of integrator operational amplifier GM3. The upper plate of capacitor C5 is connected to the first input terminal of the chopper switch. The lower plate of capacitor C5 is connected to the non-inverting output terminal of integrator operational amplifier GM3. The upper plate of capacitor C6 is connected to the second input terminal of the chopper switch. The lower plate of capacitor C6 is connected to the inverting output terminal of integrator operational amplifier GM3. The first terminal of switch S4 is connected to the first input terminal of chopper switch CH5. The second terminal of switch S4 is respectively connected to the upper plate of capacitor C3 and the first terminal of switch S6. The lower plate of capacitor C3 is connected to the non-inverting output terminal of integrator operational amplifier GM3. The second terminal of switch S6 is connected to the fixed level Vcm. The first terminal of switch S5 is connected to the second input terminal of chopper switch CH5. The second terminal of switch S5 is respectively connected to the upper plate of capacitor C4 and the first terminal of switch S7. The lower plate of capacitor C4 is connected to the inverting output terminal of integrator operational amplifier GM3. The second terminal of switch S7 is connected to the fixed level Vcm.

[0054] Optionally, the analog DSL module further includes: a switched-capacitor integrator. The switched-capacitor integrator includes: chopper switch CH4, analog DSL capacitor CA_DSL1, and analog DSL capacitor CA_DSL2. The first output terminal of chopper switch CH4 is connected to the upper plate of analog DSL capacitor CA_DSL1. The lower plate of analog DSL capacitor CA_DSL1 is connected to the non-inverting input terminal VDSL+ of operational amplifier GM1. The second output terminal of chopper switch CH4 is connected to the upper plate of analog DSL capacitor CA_DSL2. The lower plate of analog DSL capacitor CA_DSL2 is connected to the inverting input terminal VDSL- of operational amplifier GM1.

[0055] It is understandable that, in order to further improve the compensation accuracy, the present invention adopts an analog DSL module to assist the digital DSL module to work. In the analog DSL module, the conduction of switches S1, S2, S6, and S7 is controlled by clock Φ1, and the conduction of switches S3, S4, and S5 is controlled by clock Φ2. The capacitance values of capacitor C1 and capacitor C2 are the same, the capacitance values of capacitor C3 and capacitor C4 are the same, and the capacitance values of capacitor C5 and capacitor C6 are the same. Clock Φ1 and clock Φ2 are a pair of complementary clocks, and the transfer of charge is achieved by controlling the conduction of switches through the clocks.

[0056] The bandwidth of the switched-capacitor integrator is expressed as follows:

[0057]

[0058] where f integ represents the bandwidth of the switched-capacitor integrator, f chop represents the chopping clock, C 1，2 represents the capacitance value of capacitor C1 or capacitor C2, C 5，6 represents the capacitance value of capacitor C5 or capacitor C6, C 3，4 represents the capacitance value of capacitor C3 or capacitor C4.

[0059] The relationship between the bandwidth of the switched-capacitor integrator and the loop high-pass cut-off frequency is expressed as follows:

[0060]

[0061] where f hp represents the high-pass cut-off frequency introduced by the switched-capacitor integrator in the entire analog front-end circuit, C A_DSL represents the capacitance value of analog DSL capacitor CA_DSL1 or analog DSL capacitor CA_DSL2, C fb1，2 represents the capacitance value of feedback capacitor Cfb1 or feedback capacitor Cfb2.

[0062] The maximum value of the DC offset voltage eliminated by the analog DSL is expressed as follows:

[0063]

[0064] where V EOV represents the maximum value of the DC offset voltage eliminated by the analog DSL, C in1，2 represents the capacitance value of input capacitor Cin1 or input capacitor Cin2, V out-max represents the maximum output amplitude of integrator op amp GM3.

[0065] Exemplarily, when the bandwidth of the integrator operational amplifier GM3 is 0.12 Hz and the tail capacitance Chp is 0.1 pF, the theoretically introduced high-pass pole frequency is around 0.3 Hz, and the EEG signal can be transmitted to the output end almost without loss. Assume that the maximum output dynamic range of the integrator operational amplifier GM3 is 1.2 V, and the maximum offset voltage that the circuit can suppress is 24 mV. The maximum electrode DC offset voltage that the entire hybrid architecture analog DSL can eliminate is 547 mV, meeting the requirements of non-invasive EEG acquisition devices.

[0066] In addition, in order to further reduce the equivalent noise introduced by the analog integrator at the input of the front-end amplifier, chopper switches CH5 and CH6 are embedded in the operational amplifier of the analog integrator. The input chopper switch CH5 is located before the integrator operational amplifier GM3, and the output chopper switch CH6 is embedded in the operational amplifier, modulating the low-frequency noise and offset signal of the integrator operational amplifier GM3 to the chopping frequency, reducing the output noise of the integrator operational amplifier GM3, and improving the noise performance of the entire analog front end. The chopping frequency of the two chopper switches here is 1 / 2 of the chopping frequency of the instrumentation amplifier. It can be generated by simply dividing the chopping frequency of the instrumentation amplifier with a frequency divider circuit. The digital DSL module introduces a compensation capacitor at the operational amplifier input node, increasing the equivalent input noise. However, since the requirement for suppressing the electrode DC offset of the analog DSL module is reduced, the noise contributed by the analog integrator is reduced. Therefore, compared with the traditional analog DSL, the noise performance of this hybrid architecture DSL is not severely affected, lifting the limitation between the noise performance and the electrode DC offset suppression range.

[0067] Taking a 6-bit counter as an example, Figure 5 is a schematic diagram of the waveform change of the electrode DC offset provided by the embodiment of the present invention, as Figure 5 As shown, the change in the output waveform is simulated when the DC offset of the electrode suddenly changes from 500 mV to -500 mV. The power supply voltage is 1.8 V, the input signal frequency is 100 Hz, and the amplitude is 2 mVpp. Initially, the 500 mV DC offset saturates the output. Starting from 5 ms, the digital DSL module enters the compensation mode. The counter operates at a frequency of 100 Hz, leaving enough working time for each compensation. After 62 cycles, the output waveform returns to the normal operating range. The compensation time of the digital DSL module is less than 630 ms, while the DC offset suppression ability of traditional analog DSL electrodes is generally less than 50 mV, and it takes up to several seconds of integration to completely eliminate the DC offset. At 1 s, the electrode DC offset suddenly changes to -500 mV, and the IA output waveform saturates. The chopper switch control signal S_chop is inverted, and the counter is cleared. After that, the counter starts counting again, generating an inverted compensation current to be compensated to the input of GM1. The output waveform returns to normal around 1.63 s, and then the digital DSL enters the hold mode. Due to the limited compensation accuracy, there is a common-mode offset of about 700 mV in the final output waveform of the CCIA.

[0068] Figure 6 It is a schematic diagram showing the suppression effect of DC offset provided by an embodiment of the present invention. As Figure 6 shown, Figure 6 shows the suppression effect of the hybrid architecture DSL on the ±100 mV electrode DC offset. The compensation time of the digital DSL module is 130 ms, eliminating 91 mV of the electrode offset. The integrator of the analog DSL module keeps working until all the DC offset is completely eliminated. For a 100 mV electrode DC offset, the hybrid architecture DSL shortens the compensation time to about 2 s. The analog DSL module works slowly, eliminating the remaining 8.8 mV of DC offset. At 3 s, the electrode DC offset suddenly changes to -100 mV, and S_chop becomes 0. The integrator of the analog DSL starts to integrate in the reverse direction, and the counter in the digital DSL starts counting again. After 2 s, all the electrode DC offset is eliminated, and the output signal waveform returns to normal.

[0069] Through the above technical solution, the analog DSL module and the digital DSL module work together to ensure that the input EEG signal can be amplified normally. The digital DSL module eliminates the trade-off limitation between the noise performance and the EDO suppression range of the analog DSL module, broadens the electrode DC offset suppression range, shortens the compensation time, and enables the circuit to quickly return to the normal working range. Moreover, the circuit structure and timing of the digital DSL module are simple, and the compensation accuracy of the analog DSL is high, which is used to eliminate the remaining offset, avoid affecting the subsequent circuit, reduce the loss of the EEG signal, and the state of the output signal of the instrumentation amplifier can be monitored in real time through the digital DSL module. In addition, it reduces the circuit design difficulty and implementation cost, and can optimize the noise characteristics of the analog DSL module through the frequency stability of the analog DSL module. Moreover, a chopper switch is embedded at the input of the integrator op-amp of the analog DSL module, which reduces the noise introduced at the input of the analog front-end amplifier and optimizes the noise index.

[0070] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0071] Although the present invention has been described in connection with various embodiments herein, however, in the process of implementing the claimed invention, those skilled in the art can understand and achieve other variations of the disclosed embodiments by viewing the accompanying drawings and the disclosure. In the description of the present invention, the term "including" does not exclude other components or steps, the word "a" or "one" does not exclude a plurality of cases, and the meaning of "a plurality" is two or more, unless otherwise specifically defined. In addition, certain measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0072] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. An analog front-end amplifier based on a hybrid architecture DC offset suppression loop, characterized in that: include: A capacitive coupled instrumentation amplifier with a chopper and a hybrid architecture DSL; wherein the hybrid architecture DSL includes: a digital DSL module and an analog DSL module; The capacitive coupled instrument amplifier with chopper is used to amplify the input signal and separate the circuit noise in the input signal by using the chopper to obtain the output signal; The digital DSL module is used to switch to a compensation mode when the output signal is greater than or equal to a threshold signal to generate a compensation current and obtain a compensated output signal; and is also used to switch to a holding mode when the output signal is less than the threshold signal; The analog DSL module is used to eliminate the DC offset voltage in the compensated output signal to obtain the target EEG signal.

2. The analog front-end amplifier based on a hybrid architecture DC offset suppression loop according to claim 1, characterized in that: The capacitive coupling instrument amplifier with chopper comprises: an input chopping switch CH1, an input capacitor Cin1, an input capacitor Cin2, an operational amplifier GM1, an operational amplifier GM2, a feedback capacitor Cfb1, a feedback capacitor Cfb2, a positive feedback capacitor Cpf1, a positive feedback capacitor Cpf2, a feedback chopping switch CH3, a DC feedback resistor Rb1 and a DC feedback resistor Rb2; the input end of the input chopping switch CH1 is connected to the input signal, the output end of the input chopping switch CH1 is respectively connected to the lower plates of the input capacitor Cin1, the input capacitor Cin2, the positive feedback capacitor Cpf1 and the positive feedback capacitor Cpf2, the in-phase input end VDSL+ of the operational amplifier GM1 is respectively connected to the input capacitors Cin1 and Cin2, the positive feedback capacitor Cpf1 and the positive feedback capacitor Cpf2, the in-phase input end VDSL+ of the operational amplifier GM1 is respectively connected to the input capacitors Cin1 and Cin2, the positive feedback capacitor Cpf1 and the positive feedback capacitor Cpf2, the positive feedback capacitor Cpf2 and the positive feedback capacitor Cpf2, the positive feedback capacitor Cpf1 ... Cin1, the lower plate of the feedback capacitor Cfb1 and the first end of the DC feedback resistor Rb1, the inverting input terminal VDSL- of the operational amplifier GM1 is connected to the input capacitor Cin2, the lower plate of the feedback capacitor Cfb2 and the first end of the DC feedback resistor Rb2, the inverting output terminal Vout- of the operational amplifier GM2 is connected to the first output end of the feedback chopper switch CH3, the in-phase output terminal Vout+ of the operational amplifier GM2 is connected to the second output end of the feedback chopper switch CH3, and the input end of the feedback chopper switch CH3 is respectively connected to the upper plates of the feedback capacitor Cfb1, the feedback capacitor Cfb2, the positive feedback capacitor Cpf1 and the positive feedback capacitor Cpf2.

3. The analog front-end amplifier based on the hybrid architecture DC offset suppression loop according to claim 2, characterized in that: The capacitive coupling instrument amplifier with chopper also includes: a ripple suppression module; the ripple suppression module includes: a filter capacitor Cr1, a filter capacitor Cr2, an output chopper switch CH2, a bias resistor Rb3 and a bias resistor Rb4; the inverting output end of the operational amplifier GM1 is respectively connected to the second end of the bias resistor Rb1 and the upper plate of the filter capacitor Cr1, the inverting output end of the operational amplifier GM1 is respectively connected to the second end of the DC feedback resistor Rb2 and the upper plate of the filter capacitor Cr2, the lower plates of the filter capacitor Cr1 and the filter capacitor Cr2 are both connected to the input end of the output chopper switch CH2, and the output end of the output chopper switch CH2 is respectively connected to the first end of the bias resistor Rb3, the first end of the bias resistor Rb4, the inverting input end of the operational amplifier GM2 and the inverting input end of the operational amplifier GM2.

4. The analog front-end amplifier based on a hybrid architecture DC offset suppression loop according to claim 2, characterized in that: The digital DSL module includes: a comparator Comp1, a comparator Comp2, a logic control circuit, an n-bit counter and a compensation capacitor array; the non-inverting input terminal of the comparator Comp1 is connected to the non-inverting output terminal Vout+ of the operational amplifier GM2, the non-inverting input terminal of the comparator Comp2 is connected to the inverting output terminal Vout- of the operational amplifier GM2, the inverting input terminal of the comparator Comp1 and the inverting input terminal of the comparator Comp2 are both connected to a threshold voltage VTH, the output terminal of the comparator Comp1 is connected to the first input terminal of the logic control circuit, the output terminal of the comparator Comp2 is connected to the second input terminal of the logic control circuit, the first output terminal of the logic control circuit is connected to the first input terminal of the n-bit counter, the second output terminal of the logic control circuit is connected to the second input terminal of the n-bit counter, and the third output terminal of the logic control circuit is connected to the input terminal of the compensation capacitor array.

5. The analog front-end amplifier based on a hybrid architecture DC offset suppression loop according to claim 2, characterized in that: The analog DSL module includes: a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6, a switch S7, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a chopper switch CH5, a chopper switch CH6 and an integrator amplifier GM3; a first end of the switch S1 is connected to a non-inverting output terminal Vout+ of the operational amplifier GM2, a first end of the switch S2 is connected to an inverting output terminal Vout- of the operational amplifier GM2, a second end of the switch S1 is connected to a first end of the switch S3, and a second end of the switch S2 is connected to a first end of the switch S3. The second end of the switch S3 is connected to the upper plate of the capacitor C1, the second end of the switch S3 is connected to the upper plate of the capacitor C2, the lower plate of the capacitor C1 is connected to the first input end of the chopper switch CH5, the lower plate of the capacitor C2 is connected to the second input end of the chopper switch CH5, the first output end of the chopper switch CH5 is connected to the non-inverting input end of the integrator amplifier GM3, the second output end of the chopper switch CH5 is connected to the inverting input end of the integrator amplifier GM3, and the chopper switch CH6 is embedded in the integrator amplifier G In M3, the first output end of the chopper switch CH6 is connected to the non-inverting input end of the integrator amplifier GM3, the second output end of the chopper switch CH6 is connected to the inverting input end of the integrator amplifier GM3, the upper plate of the capacitor C5 is connected to the first input end of the chopper switch, the lower plate of the capacitor C5 is connected to the non-inverting output end of the integrator amplifier GM3, the upper plate of the capacitor C6 is connected to the second input end of the chopper switch, the lower plate of the capacitor C6 is connected to the inverting output end of the integrator amplifier GM3, the first end of the switch S4 is connected to the first input end of the chopper switch CH5 The first end of the switch S5 is connected to the second input end of the chopper switch CH5, the second end of the switch S5 is connected to the upper plate of the capacitor C4 and the first end of the switch S7, the lower plate of the capacitor C4 is connected to the inverting output end of the integrator amplifier GM3, and the second end of the switch S7 is connected to the fixed level Vcm.

6. The analog front-end amplifier based on a hybrid architecture DC offset suppression loop according to claim 5, characterized in that: The analog DSL module further includes: a switched capacitor integrator; the switched capacitor integrator includes: a chopping switch CH4, an analog DSL capacitor CA_DSL1 and an analog DSL capacitor CA_DSL2; a first output end of the chopping switch CH4 is connected to an upper plate of the analog DSL capacitor CA_DSL1, a lower plate of the analog DSL capacitor CA_DSL1 is connected to a non-inverting input end VDSL+ of the operational amplifier GM1, a second output end of the chopping switch CH4 is connected to an upper plate of the analog DSL capacitor CA_DSL2, and a lower plate of the analog DSL capacitor CA_DSL2 is connected to an inverting input end VDSL- of the operational amplifier GM1.

7. The analog front-end amplifier based on a hybrid architecture DC offset suppression loop according to claim 6, characterized in that: The bandwidth of the switched capacitor integrator is expressed as follows: Among them, f integ represents the bandwidth of the switched capacitor integrator, f chop represents the chopping clock, C 1,2 Indicates the capacitance value of capacitor C1 or capacitor C2, C 5,6 Indicates the capacitance value of capacitor C5 or capacitor C6, C 3,4 Indicates the capacitance value of capacitor C3 or capacitor C4.

8. The analog front-end amplifier based on a hybrid architecture DC offset suppression loop according to claim 7, characterized in that: The relationship between the bandwidth of the switched capacitor integrator and the loop high-pass cutoff frequency is expressed as follows: Among them, f hp represents the high-pass cutoff frequency introduced by the switched capacitor integrator in the entire analog front-end circuit, C A_DSL represents the capacitance value of the analog DSL capacitor CA_DSL1 or the analog DSL capacitor CA_DSL2, C fb1,2 represents the capacitance value of the feedback capacitor Cfb1 or the feedback capacitor Cfb2.

9. The analog front-end amplifier based on a hybrid architecture DC offset suppression loop according to claim 8, characterized in that: The maximum value of the DC offset voltage eliminated by the analog DSL is expressed as follows: Among them, V EOV The maximum value of the DC offset voltage eliminated by the analog DSL is C in1,2 represents the capacitance value of the input capacitor Cin1 or the input capacitor Cin2, V out-max Represents the maximum output amplitude of the integrator operational amplifier GM3.

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