Analog-to-digital converter with embedded filter, driver chip and electronic device

Abstract

The present disclosure relates to an embedded filter analog-to-digital converter, a driving chip and an electronic device, the analog-to-digital converter comprising: a first analog-to-digital conversion module, the first analog-to-digital conversion module being a successive approximation analog-to-digital converter with a plurality of sampling capacitors and a plurality of sampling periods, the first analog-to-digital conversion module achieving a finite impulse response (FIR) filtering effect on an input sampling signal through charge sharing between the respective sampling capacitors; and starting a successive approximation quantization process on the signal on the sampling capacitors that have completed sampling while part of the sampling capacitors are still in the process of sampling the input signal. The analog-to-digital converter of the present disclosure has filtering characteristics, and at the same time has the characteristics of high bandwidth, low power consumption and low area.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to an analog-to-digital converter with embedded filter, a driving chip and an electronic device. BACKGROUND

[0002] An analog-to-digital converter (ADC) is a key bridge connecting a digital system and a physical world, and it plays an indispensable and important role in advanced electronic systems in the fields of communication, signal acquisition, and even national defense and aerospace. The ADC is usually implemented by an integrated circuit (chip).

[0003] In many current applications of wireless receivers, the ADC chip is usually an independent optimal design, which is disconnected with the front and rear modules in the signal chain. Therefore, from the perspective of the complete signal chain system, the global optimization has not been achieved. In order to pursue lower overall energy consumption of the system and better overall architecture of the system, the joint optimization technology of the front end of the signal chain is particularly important. It develops a new idea for the research and development of analog-to-digital conversion and signal chain fields.

[0004] As shown in FIG. 1, the current mainstream analog front end (AFE) solution includes the following types: 1. independent filter and independent ADC; 2. continuous-time delta-sigma (CTDSM) type; and 3. successive approximation register (SAR) type with embedded switched-capacitor filter. Figure 1

[0005] Figure 1 In FIG. 1(a), an AFE is composed of an independent filter and an independent ADC. This is a traditional AFE architecture widely used in wireless receivers. Figure 1 In FIG. 1(b), an AFE architecture based on a continuous-time delta-sigma modulator (CTDSM) is shown. The CTDSM is a classic high-precision ADC architecture. Since it has an anti-aliasing characteristic, it is usually used as an AFE architecture to replace the independent filter and the independent ADC in many wireless receivers in the industry. It can achieve higher power consumption and smaller area in a bandwidth of tens of megahertz. Figure 1 In FIG. 1(c), a SAR ADC architecture with embedded switched-capacitor filter is shown. It multiplexes the sampling and quantization capacitors in the SAR ADC to the switched-capacitor filter capacitors, so that the filtered signal can be directly generated on the sampling and quantization capacitors, avoiding an additional independent filter stage. Therefore, it can achieve smaller area, lower power consumption, and lower noise.

[0006] ​In the AFE using independent filter and independent ADC architecture, the ADC chip is a separate design for local optimization, and is cut off from the front and rear modules in the signal chain. Therefore, from the perspective of the complete signal chain system, the global optimization is not achieved. The additional filter will introduce additional noise and area consumption. Taking CTDSM as the AFE architecture, although a higher bandwidth can be achieved by a high-order quantizer, and at the same time, the area is lower, but it is difficult to achieve lower power consumption in the high bandwidth mode. This is because the CTDSM is limited by its internal closed-loop structure, so that the CTDSM must pay a higher power consumption at a higher bandwidth. The SAR ADC with embedded switched-capacitor filter has lower power consumption and area, but its bandwidth is very limited, usually less than 10 MHz, and can only be used for filtering and quantization of very low-speed signals. This is because the SAR ADC with embedded switched-capacitor filter must first complete the multi-cycle switched-capacitor sampling filtering operation before the SAR quantization starts. This greatly prolongs the time required in the sampling stage of the ADC, slowing down the overall conversion rate of the ADC.

[0007] It can be seen that the ADC architecture of these traditional schemes is difficult to simultaneously achieve low area, low power consumption and high bandwidth requirements. SUMMARY

[0008] According to an aspect of the present disclosure, an analog-to-digital converter with embedded filter is provided, comprising a first analog-to-digital conversion module, the first analog-to-digital conversion module being a successive approximation register (SAR) analog-to-digital converter (ADC) with a plurality of sampling capacitors and a plurality of sampling periods, the first analog-to-digital conversion module achieving a finite impulse response (FIR) filtering effect on an input sampling signal through charge sharing between the sampling capacitors; and starting a successive approximation quantization process on a signal on a part of the sampling capacitors that have completed sampling while the part of the sampling capacitors are still sampling the input signal.

[0009] In a possible implementation, the analog-to-digital converter further comprises one or more filter capacitors; any one of the sampling capacitors is connected to each of the filter capacitors one by one after sampling the input signal, and an infinite impulse response (IIR) filtering effect on the input sampling signal is achieved through charge sharing between the sampling capacitors and the filter capacitors; and a successive approximation quantization process is started on a signal on a part of the sampling capacitors that have completed sampling and filtering while the part of the sampling capacitors are still sampling the input signal or performing IIR filtering.

[0010] In a possible implementation, the analog-to-digital converter further comprises an amplifier and a second analog-to-digital conversion module, and the first analog-to-digital conversion module, the amplifier and the second analog-to-digital conversion module constitute a pipeline SAR ADC.

[0011] In a possible implementation, the first analog-to-digital conversion module further includes a plurality of analog-to-digital conversion units, the analog-to-digital conversion units are in a time domain interleaving relationship, and after all sampling capacitors of one analog-to-digital conversion unit complete sampling, a next analog-to-digital conversion unit starts a sampling process.

[0012] In a possible implementation, all analog-to-digital conversion units in the first analog-to-digital conversion module include a plurality of switch sampling components, an amplification control switch, a first comparator, and a first successive approximation logic circuit unit, the switch sampling component includes a first sampling capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and one or more filter control switches, wherein,

[0013] a first end of the first sampling capacitor is connected to a first end of the first switch, a first end of the second switch, and a first end of the third switch,

[0014] a second end of the first sampling capacitor is connected to a first end of the fourth switch, a first end of the fifth switch, a second end of the third switch, and a first end of each filter control switch,

[0015] a second end of the second switch is connected to a common-mode voltage, a second end of the first switch of each switch sampling component is connected to a first end of the amplification control switch and a first input end of the first comparator, a second input end of the first comparator is configured to receive a preset voltage, a second end of the amplification control switch is connected to an input end of the amplifier, and an output end of the first comparator is connected to the first successive approximation logic circuit unit,

[0016] a second end of the fourth switch of each switch sampling component is connected to an output end of the input buffer,

[0017] a second end of the fifth switch of each switch sampling component is connected to the first successive approximation logic circuit unit,

[0018] a second end of each filter control switch is connected to a corresponding filter capacitor.

[0019] In a possible implementation, each switch sampling component is configured to sequentially be in a reset phase, a sampling phase, a filtering phase, a quantization phase, and a residual error amplification phase, wherein, for any one switch sampling component:

[0020] in the reset phase, the second switch and the third switch are turned on, and the first sampling capacitor is in a reset state;

[0021] In the sampling phase, the second switch and the fourth switch are turned on, the first sampling capacitor performs charge sampling, after a first sampling duration, the fourth switch is turned off, and after a second delay duration, the second switch is turned off;

[0022] In the filtering phase, the second switch is turned on, each filtering control switch is turned on in turn, and each filtering control switch is turned on for a preset duration.

[0023] In the quantization phase, the first switch and the fifth switch are turned on.

[0024] In the residual error amplification phase, the amplification control switch is turned on.

[0025] In a possible implementation, the ith switch sampling assembly is sequentially configured to be in a reset phase, a sampling phase, a filtering phase, a quantization phase, and a residual error amplification phase from the ith clock cycle, where i is a positive integer.

[0026] According to an aspect of the present disclosure, a driving chip is provided, which comprises the embedded filter ADC.

[0027] According to an aspect of the present disclosure, an electronic device is provided, which comprises the driving chip.

[0028] In a possible implementation, the electronic device comprises any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an all-in-one computer, an access control device, and an electronic door lock.

[0029] The present disclosure achieves the finite impulse response (FIR) filtering effect on the input sampling signal by sharing the charges among the sampling capacitors, and starts the successive approximation quantization process on the signals of the sampling capacitors that have completed sampling while the other sampling capacitors are still sampling the input signal, so that the sampling and quantization processes are parallel, the conversion rate of the ADC is accelerated, the system bandwidth is improved, and the ADC of the present disclosure has no closed-loop feedback loop, so that the power consumption is not deteriorated sharply at high bandwidth. It can be seen that the ADC of the present disclosure has the characteristics of high bandwidth, low power consumption, and low area.

[0030] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, but not limiting the present disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0031] The drawings incorporated in and forming a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure.

[0032] Figure 1 A schematic diagram of a current analog front end (AFE) solution is shown.

[0033] Figure 2a A schematic diagram of an analog-to-digital converter with an embedded filter according to embodiments of the present disclosure is shown, Figure 2b A schematic diagram of an analog-to-digital converter with an embedded filter is shown. Figure 2a A schematic diagram of an analog-to-digital converter with an embedded filter is shown.

[0034] Figure 3a A schematic diagram of an analog-to-digital converter with an embedded filter according to embodiments of the present disclosure is shown.

[0035] Figure 3b A schematic diagram of an analog-to-digital converter with an embedded filter according to embodiments of the present disclosure is shown.

[0036] Figure 4 A timing diagram of a first analog-to-digital conversion module according to embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0037] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numbers in different drawings represent the same or similar elements. Although various aspects of embodiments are illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0038] In the description of the present disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0039] In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0040] In this disclosure, unless specifically defined otherwise, the terms "mounting", "connected", "connection", "fixed", and the like, should be construed broadly, for example, can be fixed connection, can also be detachable connection, or integral; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication of two elements or interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in this disclosure can be understood according to the specific circumstances.

[0041] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0042] The term "and / or", only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, and C, which can mean including any one or more elements selected from the set consisting of A, B, and C.

[0043] In addition, in order to better illustrate the present disclosure, a large number of specific details are given in the specific embodiments below. Those skilled in the art should understand that without certain specific details, the present disclosure can also be implemented. In some examples, methods, means, elements and circuits well known to those skilled in the art are not described in detail, in order to highlight the main idea of the present disclosure.

[0044] The embodiment of the present disclosure provides an analog-to-digital converter with an embedded filter, comprising a first analog-to-digital conversion module, the first analog-to-digital conversion module is a successive approximation analog-to-digital converter with a plurality of sampling capacitors and a plurality of sampling periods, the first analog-to-digital conversion module realizes a finite impulse response (FIR) filtering effect on an input sampling signal through charge sharing between each sampling capacitor; and while part of the sampling capacitors are still sampling the input signal, the successive approximation quantization process of the signal on the part of the sampling capacitors that have completed sampling is started.

[0045] The present disclosure sets up charge sharing between each sampling capacitor to achieve a finite-length unit impulse response (FIR) filtering effect on the input sampling signal; and while some sampling capacitors are still sampling the input signal, the successive approximation quantization process on the signals on the sampling capacitors that have completed sampling is started, which can realize parallel sampling and quantization, speed up the conversion rate of the ADC, improve the system bandwidth, and the ADC of the present disclosure does not have a closed-loop feedback loop, thus avoiding the sharp deterioration of power consumption at high bandwidth. In addition, no additional filtering circuit is needed to save circuit area overhead. It can be seen that the ADC of the present disclosure has the characteristics of high bandwidth, low power consumption and low area.

[0046] The present disclosure does not limit the number of sampling capacitors in the first ADC module and the specific implementation of the SAR ADC, and the person skilled in the art can set them according to the actual situation and needs. The present disclosure does not limit the specific timing of sampling some sampling capacitors and starting successive approximation quantization on some sampling capacitors that have completed sampling, and the specific division method of the number of capacitors in each part, and the person skilled in the art can set them according to the actual situation and needs. The following exemplary describes each possible implementation of the first ADC module.

[0047] Please refer to Figure 2a , Figure 2a The schematic diagram of the ADC with the embedded filter is shown.

[0048] Please refer to Figure 2b , Figure 2b The working schematic diagram of the ADC with the embedded filter in Figure 2a is shown.

[0049] Exemplarily, as shown in Figure 2a , the first ADC module can include a switched capacitor array module (including each sampling capacitor (C S1 ~ C SN ), each switch (φ1~φ N )), a comparator, and a successive approximation logic circuit.

[0050] Exemplarily, as shown in Figure 2a , the first end of the switched capacitor array module is connected with the input analog signal V IN (also referred to as input signal below), and the second end of the switched capacitor array module is connected with the first input terminal of the comparator. Figure 2bAs shown, the N sampling capacitors in the switched capacitor array module sample the input signal in turn in the sampling stage; the second end of the switched capacitor array module is connected with the comparator, and the N sampling capacitors in the switched capacitor array module are connected with the comparator in turn through the switch after the sampling is completed, and the filtering effect is realized through charge sharing; while part of the capacitors are still in the sampling process, the comparator is started to compare and input the output result into the successive approximation logic circuit, and the successive approximation quantization process of the signal on part of the capacitors that have completed sampling is started, and the output result of the successive approximation logic circuit is fed back to the first end of the capacitor array module, and the output result of the successive approximation logic circuit is fed back to the first sampling capacitor C S1 to the N sampling capacitor C SN .

[0051] Of course, it should be noted that, Figure 2a the circuit structure in the above is an exemplary structure given for introducing the analog-to-digital converter of the embodiment of the present disclosure to perform the analog-to-digital conversion process, and should not be regarded as a limitation on the embodiment of the present disclosure, and the implementation mode of the first analog-to-digital conversion module can be set according to the actual situation and needs.

[0052] For example, in a possible implementation, the analog-to-digital converter can further include one or more filter capacitors; after any sampling capacitor samples the input signal, the sampling capacitor can be connected with each filter capacitor one by one, and the infinite impulse response (IIR) filtering effect of the input sampling signal is realized through charge sharing between the sampling capacitor and each filter capacitor; and while part of the sampling capacitors are still in the input signal sampling process or IIR filtering process, the successive approximation quantization process of the signal on part of the sampling capacitors that have completed sampling and filtering can be started, and the specific timing of starting can be set according to the actual situation and needs, and the embodiment of the present disclosure is not limited.

[0053] The embodiment of the present disclosure does not limit the specific number of filter capacitors, and does not limit the specific size of each filter capacitor, and the skilled in the art can set according to the actual situation and needs.

[0054] In a possible implementation, the analog-to-digital converter can further include an input buffer Buf, wherein the input buffer Buf is used to buffer the input analog signal (V IN ).

[0055] The embodiment of the present disclosure does not limit the specific implementation mode of the input buffer Buf, and the skilled in the art can realize it by using a suitable device according to the actual situation and needs.

[0056] In a possible implementation, the first analog-digital conversion module can further include a plurality of analog-digital conversion units (such as two or more than two), and the analog-digital conversion units are in a time domain interleaving relationship, and after all the sampling capacitors of one analog-digital conversion unit complete sampling, the next analog-digital conversion unit starts the sampling process.

[0057] The analog-digital converter is further described below.

[0058] Please refer to Figure 3a , Figure 3a A schematic diagram of the analog-digital converter with an embedded filter according to an embodiment of the present disclosure is shown.

[0059] Please refer to Figure 3b , Figure 3b A schematic diagram of the analog-digital converter with an embedded filter according to an embodiment of the present disclosure is shown.

[0060] In a possible implementation, as shown in Figure 3a and Figure 3b , the analog-digital converter can further include an amplifier Amp and a second analog-digital conversion module 20, and the first analog-digital conversion module 10, the amplifier Amp and the second analog-digital conversion module 20 form a pipeline type successive approximation analog-digital converter.

[0061] The present embodiment does not limit the specific implementation of the amplifier Amp and the second analog-digital conversion module 20, and a person skilled in the art can implement it by using related technologies. For example, the second analog-digital conversion module 20 can include a two-channel time interleaving 10-bit SAR ADC. The preferred implementation of the first analog-digital conversion module 10 is described below.

[0062] In a possible implementation, as shown in Figure 3a , the first analog-digital conversion module 10 can include a first analog-digital conversion unit CH1 and a second analog-digital conversion unit CH2, and each analog-digital conversion unit can include a plurality of switch sampling components, an amplification control switch Sc1, a first comparator Cmp1 and a first successive approximation logic circuit unit SAR Logic1. The switch sampling component can include a first sampling capacitor (such as C S1 ~C S8 ), a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5 and a plurality of filter control switches (for example, three filter control switches Sf1-Sf3 in the present example), wherein,

[0063] The first end of the first sampling capacitor (hereinafter referred to as C S1 ) is connected to the first end of the first switch S1, the first end of the second switch S2 and the first end of the third switch S3,

[0064] The first sampling capacitor C S1 The second end is connected to the first end of the fourth switch S4, the first end of the fifth switch S5, the second end of the third switch S3, and the first end of each filter control switch (Sf1~Sf3).

[0065] The second terminal of the second switch S2 is connected to a common-mode voltage (such as ground voltage). The second terminal of the first switch S1 of each switch sampling component is connected to the first terminal of the amplification control switch Sc1 and the first input terminal of the first comparator Cmp1. The second input terminal of the first comparator Cmp1 is used to receive a preset voltage (the magnitude of which is not limited in this embodiment, but can be set by those skilled in the art according to actual conditions and needs). The amplification control switch Sc1...

[0066] The second terminal is connected to the input terminal of the amplifier Amp (i.e., the second terminal of the amplification control switch Sc1 serves as the output terminal of the analog-to-digital conversion unit), and the output terminal of the first comparator Cmp1 is connected to the first successive approximation logic circuit unit.

[0067] The second terminal of the fourth switch S4 of each switching sampling component is connected to the output terminal of the input buffer Buf to receive the analog signal V output by the input buffer Buf. IN ,

[0068] The second terminal of the fifth switch S5 of each switching sampling component is connected to the first successive approximation logic circuit unit SAR Logic1.

[0069] The second terminal of each filter control switch is connected to the corresponding filter capacitor (for example, this example includes three filter capacitors C). IIR1 C IIR2 C IIR3 ).

[0070] For example, such as Figure 3a As shown, the second terminals of the filter control switch Sf1 of the first analog-to-digital converter CH1 and the filter control switch Sf1 of the second analog-to-digital converter CH2 are both connected to the filter capacitor C. IIR1 The first terminal, the second terminal of the filter control switch Sf2 of the first analog-to-digital converter CH1 and the second terminal of the filter control switch Sf2 of the second analog-to-digital converter CH2 are both connected to the filter capacitor C. IIR2 The first terminal, the second terminal of the filter control switch Sf3 of the first analog-to-digital converter CH1 and the second terminal of the filter control switch Sf3 of the second analog-to-digital converter CH2 are both connected to the filter capacitor C. IIR3 First end.

[0071] The embodiments of the present disclosure do not limit the switch types of the amplification control switch Sc1, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and each filter control switch (Sf1-Sf3), which can be set according to actual conditions and needs by those skilled in the art, for example, the switches can be any one of a relay, a reed switch, a thyristor, a switching diode, a switching triode, an electronic double switch, an optoelectronic coupler, and a transistor, and the transistor can be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT), which can be implemented based on silicon carbide (SiC) or gallium nitride (GaN) to improve performance.

[0072] For example, the fourth switch S4 and the amplification control switch Sc1 can be designed as bootstrapped switches, and the embodiments of the present disclosure do not limit the specific implementation of the bootstrapped switches, which can be implemented by related technologies according to actual conditions and needs by those skilled in the art. By setting the fourth switch S4 and the amplification control switch Sc1 as bootstrapped switches, the on-resistance of the fourth switch S4 and the amplification control switch Sc1 does not change significantly with the input signal level (the gate-source voltage of the bootstrapped switch is the power supply voltage, and the on-resistance is a fixed small resistance value), which greatly improves the linearity of sampling and further improves the performance of the ADC such as the spurious-free dynamic range (SFDR).

[0073] The embodiments of the present disclosure do not limit the specific implementation of the first successive approximation logic circuit unit SAR Logic1, which can be implemented by related technologies according to actual conditions and needs by those skilled in the art. The first successive approximation logic circuit unit SAR Logic1 can implement the initialization control, start conversion, successive approximation control, comparison control, data storage and update, bit switching control, conversion end judgment and output of the SAR ADC, and the specific working content of the first successive approximation logic circuit unit SAR Logic1 is described in related technologies, which is not repeated here.

[0074] In a possible implementation, as shown in FIG. 1, Figure 3a The first analog-to-digital conversion unit CH1 and the second analog-to-digital conversion unit CH2 can each include eight switch sampling components, and each switch sampling component includes three filter control switches (Sf1-Sf3), and the number of filter capacitors is three (C IIR1 , C IIR2 , C IIR3, of course, the number of switch sampling components, filter control switches, filter capacitors can also be other, the present disclosure embodiments do not limit this.

[0075] Exemplary, the capacitance size of each first sampling capacitor in the switch sampling component can be equal or not equal, the capacitance size of each filter capacitor can be set according to actual situation and need, which is not limited here.

[0076] In a possible implementation, in the 8 switch sampling components: the first sampling capacitor (such as C S7 ) of one switch sampling component is two capacitors with a capacitance of 2C in parallel, the first sampling capacitor (such as C S8 ) of one switch sampling component is one capacitor with a capacitance of 2C, two capacitors with a capacitance of C in parallel, and the first sampling capacitor (such as C S1 ~C S6 ) of the remaining switch sampling components is a capacitor with a capacitance of 4C, wherein C represents the size of a unit capacitor. Of course, each capacitor can also have other setting methods, and those skilled in the art can set according to actual situation and need.

[0077] The present disclosure embodiments do not limit the specific size of the unit capacitor, and those skilled in the art can set according to actual situation and need.

[0078] The present disclosure embodiments can save the area of the circuit by multiplexing a large number of circuit structures in the signal filtering stage and the quantization stage. In the present disclosure embodiments, the conversion of the first analog-digital conversion module 10 can be quantized by a step-by-step conversion method. The conversion of the second analog-digital conversion module 20 can be a normal asynchronous SAR conversion. The step-by-step conversion method of the first analog-digital conversion module 10 is exemplarily introduced below. The asynchronous SAR conversion method adopted by the second analog-digital conversion module 20 is described in the related art, which is not described here.

[0079] In a possible implementation, each switch sampling component is configured to be in a reset stage, a sampling stage, a filtering stage, a quantization stage, and a residual error amplification stage in sequence, wherein for any one switch sampling component:

[0080] In the reset stage, the second switch S2 and the third switch S3 are turned on, and the first sampling capacitor C S1 is in a reset state, in which case the switches at both ends of the first sampling capacitor C S1 are connected to the common mode voltage, and the charge is cleared, waiting to be awakened by the start instruction signal. This stage lasts for half or one clock cycle;

[0081] In the sampling stage, the second switch S2 and the fourth switch S4 are turned on, and the first sampling capacitor CS1 Charge sampling is performed, after a first time duration, the fourth switch S4 is turned off, after a second time duration, the second switch S2 is turned off; in the sampling stage, the top plate (first end) of the first sampling capacitor C S1 is still connected to the common mode voltage, the bottom plate (second end) of the first sampling capacitor C S1 is connected to the input signal through the bootstrap switch (φS) to perform sampling. At the end of sampling, the bottom plate switch is first turned off, after a short delay, the top plate switch is turned off, completing the high linearity backplane sampling of the input signal. This stage lasts for one clock cycle, for example, and the first time duration and the second time duration are both less than one clock cycle.

[0082] In the filtering stage, the second switch S2 is turned on, and each filter control switch (Sf1-Sf3) is turned on in turn, and each filter control switch is turned on for a preset time duration; in the three clock cycles after sampling, the top plate of the first sampling capacitor C S1 is kept connected to the common mode voltage, and the bottom plate is connected to the filter capacitor C IIR1 -C IIR3 in turn through the filter control switch (which can be a transmission gate) (at this time the other end of the filter capacitor is kept grounded), forming a third-order IIR filter of the input signal.

[0083] In the quantization stage, the first switch S1 and the fifth switch S5 are turned on; after the first sampling capacitor C S1 completes IIR filtering, the first end of the first sampling capacitor C S1 will be connected to the first comparator Cmp1 immediately, the second end of the first sampling capacitor C S1 is connected to the first successive approximation logic circuit unit SAR Logic1, converted into part of the quantization capacitor (C DAC , not shown) and participates in the SAR quantization process of this cycle. This stage will continue until all quantization is complete.

[0084] In the residual error amplification stage, the amplification control switch Sc1 is turned on. After the quantization stage is completed, the top plate of C DAC forms the residual error voltage after the first stage of quantization. All first sampling capacitors at this time are connected to the residual error amplifier Amp as part of the quantization capacitor C DAC to perform residual error amplification.

[0085] Compared with SAR ADCs with embedded switched capacitors in related technologies, the ADC of this disclosure adopts a step-by-step conversion method, that is, while performing switched capacitor filtering on some sampling capacitors, quantization of the voltage on another part of the sampling capacitors is performed, realizing the parallelism of the filtering process and the quantization process, accelerating the conversion rate of the ADC and improving the system bandwidth.

[0086] The embodiments disclosed herein do not limit the switching control methods of the amplification control switch Sc1, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and each filter control switch (Sf1 to Sf3). Those skilled in the art can implement these methods using relevant technologies according to actual conditions and needs. For example, each switch can be controlled by setting a processing component to output a pre-prepared switch control signal.

[0087] This disclosure does not limit the specific implementation of the processing component. In one example, the processing component includes, but is not limited to, a standalone processor, discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device with instruction execution capabilities. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions can be executed through hardware circuits such as logic gates, switches, ASICs, programmable logic controllers, and embedded microcontrollers.

[0088] For example, such as Figure 3a As shown, the switch control signal may include φ RA φ QTZ φ VCM φ R φ S φ T1 φ T2 φ T3 The processing component controls the analog-to-digital conversion process by outputting corresponding switch control signals at different time periods to activate the corresponding switches. For example, during the reset phase, the processing component can control the analog-to-digital conversion process via the switch control signal φ. VCM φ R The control unit turns on the second switch S2 and the third switch S3, and controls the remaining switches to turn off via the control signals of the other switches; during the sampling phase, the processing component controls the other switches to turn off via the switch control signal φ. VCM φ Scontrolling the second switch S2 and the fourth switch S4 to be turned on; in the filtering stage, the processing assembly turns on the switches through the switch control signal φ VCM controlling the second switch S2 to be turned on and turning on the switches through the switch control signal φ T1 T2 T3 controlling the filtering control switches Sf1-Sf3 to be turned on in sequence; in the quantization stage, the processing assembly turns on the switches through the switch control signal φ QTZ controlling the first switch S1 and the fifth switch S5 to be turned on; in the residual error amplification stage, the processing assembly turns on the switches through the switch control signal φ RA controlling the amplification control switch Sc1 to be turned on.

[0089] In a possible implementation, the i-th switch sampling assembly C Si is configured to be in a reset stage, a sampling stage, a filtering stage, a quantization stage, and a residual error amplification stage in sequence from the i-th clock cycle, where i is a positive integer. For example, the first switch sampling assembly is configured to be in a reset stage, a sampling stage, a filtering stage, a quantization stage, and a residual error amplification stage in sequence from the first clock cycle, the second switch sampling assembly is configured to be in a reset stage, a sampling stage, a filtering stage, a quantization stage, and a residual error amplification stage in sequence from the second clock cycle, the third switch sampling assembly is configured to be in a reset stage, a sampling stage, a filtering stage, a quantization stage, and a residual error amplification stage in sequence from the third clock cycle, and so on.

[0090] In this way, the eight switch sampling assemblies start the above five steps (a reset stage, a sampling stage, a filtering stage, a quantization stage, and a residual error amplification stage) in sequence in eight clock cycles. The first sampling capacitor with an IIR filtered signal is gradually converted into a part of the quantization capacitor C DAC in the SAR control unit and added to the SAR conversion process. The charge sharing process accompanied by the merging into the quantization capacitor C DAC naturally has the effect of FIR filtering. The SAR quantization process is step by step performed with the gradual addition of the first sampling capacitor. Through the above step-by-step conversion strategy, the filtering process and the quantization process can be maximally overlapped, and the speed loss caused by the filtering operation can be weakened.

[0091] Please refer to Figure 4 , Figure 4 a timing diagram of a first analog-to-digital conversion module 10 of an embodiment of the present disclosure is shown.

[0092] For example, Figure 4 ​​As shown, during the first clock cycle, the first sampling capacitor CS1 samples the input analog signal V. IN .

[0093] For example, such as Figure 4 As shown, during the second to fourth cycles, the first sampling capacitor C... S1 and IIR filter capacitor C IIR1 -C IIR3 Charge sharing is performed sequentially to complete the third-order IIR filtering operation. Simultaneously, the second first-sampling capacitor C... S2 The input analog signal V is sampled during the second cycle. IN C S2 The first sampling capacitor C will be repeated. S1 Every step of the operation.

[0094] For example, such as Figure 4 As shown, during the fifth cycle, the first sampling capacitor C... S1 The three-step IIR filtering operation has been completed and immediately connected to the comparator, converting it into a quantization capacitor C. DAC Part of it.

[0095] For example, such as Figure 4 As shown, during the sixth cycle, the second first sampling capacitor C... S2 The three-step IIR filtering operation has been completed and immediately connected to the first comparator, and the first sampling capacitor C. S1 Together they form the quantization capacitor C DAC Part of it. At this time, the second first sampling capacitor C S2 and the first sampling capacitor C S1 The charge sharing that occurs between them introduces a first-order FIR filter effect. Once the charge sharing is fully established, the first comparator is immediately activated, initiating the first quantization process. Subsequently, the first sampling capacitor C is adjusted based on the result of the first quantization process. S1 The base plate is flipped over to complete the quantization of this cycle.

[0096] For example, such as Figure 4 As shown, in the seventh to twelfth cycles, a new first sampling capacitor will be converted into a quantization capacitor C in each cycle. DAC With the filtered signal charge and quantization capacitor C DAC Charge sharing is performed to achieve a higher-order FIR filtering effect. Once charge sharing is fully established, the comparator will be activated immediately to begin the quantization process for this cycle.

[0097] For example, such as Figure 4As shown, the first analog-to-digital conversion unit CH1 and the second analog-to-digital conversion unit CH2 of the embodiment of the present disclosure are configured in a time domain interleaving relationship, after all the sampling capacitances of the first analog-to-digital conversion unit CH1 complete sampling, the second analog-to-digital conversion unit CH2 starts the sampling process and performs the response operations of sampling, filtering and quantization.

[0098] The above process is a step-by-step conversion strategy. As can be seen from the above process, in the first analog-to-digital conversion module 10 of the embodiment of the present disclosure, the quantization accuracy of 5 bits is redistributed in 10 SAR conversion periods and is distributed in 7 clock periods. In the first five clock periods, only 1-bit SAR quantization is performed, in the subsequent one period, 2-bit SAR quantization is performed, and in the last period, 3-bit SAR quantization is performed. The weight design of SAR quantization contains sufficient redundancy to digest the signal charge of the additional quantization capacitance C DAC in each clock period.

[0099] The above takes the first analog-to-digital conversion module 10 as an example of a two-channel time-interleaved 5-bit SAR ADC with embedded filtering function, and the second analog-to-digital conversion module 20 as a two-channel time-interleaved 10-bit SAR ADC. However, the above exemplary introduction should not be regarded as a limitation of the embodiments of the present disclosure. In other embodiments, the first analog-to-digital conversion module 10 and the second analog-to-digital conversion module 20 can also be other implementations, and the analog-to-digital conversion accuracy can also be set according to actual conditions and needs.

[0100] The ADC scheme of the embodiment of the present disclosure has two main advantages:

[0101] 1. High bandwidth. The analog-to-digital converter of the embodiment of the present disclosure has higher bandwidth than the SAR ADC with embedded switched-capacitor filter. The analog-to-digital converter of the embodiment of the present disclosure adopts a two-way time-interleaved two-stage pipeline structure, which improves the bandwidth of the circuit. At the same time, the step-by-step conversion method is introduced in the first analog-to-digital conversion module, so that the filtering sampling and quantization processes can be performed at the same time, thereby improving the conversion rate of the ADC and weakening the speed loss problem introduced by the filtering sampling.

[0102] 2. Low power consumption. The analog-to-digital converter of the embodiment of the present disclosure has lower power consumption than the CTDSM. Since there is no closed-loop feedback loop in the analog-to-digital converter of the embodiment of the present disclosure, the power consumption is not deteriorated sharply at high bandwidth. The analog-to-digital converter of the embodiment of the present disclosure combines the high energy efficiency of the SAR ADC structure and the low power consumption of the switched-capacitor passive filter, and realizes a high-bandwidth ADC with an embedded filter with low power consumption. The low power consumption makes it more suitable for application in large-scale integrated receiver systems or Internet of Things application scenarios.

[0103] 3. Low area. Compared with the AFE design with independent filter and independent ADC, the analog-to-digital converter of the embodiment of the present disclosure adopts the architecture of joint design of filter and ADC, and the capacitance is multiplexed as filter sampling capacitance and quantization capacitance C in the filter stage and the quantization stage respectively DAC , thus greatly saving the area of the chip.

[0104] In practical applications, the ADC with embedded filter proposed in the present application can solve the overall optimization problem of the analog front end which is difficult to achieve in the traditional architecture, and realize the design of the analog front end with high bandwidth, low power consumption and low area. The low-power high-bandwidth ADC with embedded filter has a wider application scenario, and is expected to replace CTDSM in the next generation of wireless communication systems, becoming a mainstream analog front end design architecture under high bandwidth. This overall optimization of the analog front end also makes it possible to integrate a chip for the Internet of Things, smart sensors, etc., i.e. to realize the design of the analog front end with lower power consumption and smaller area, greatly improving the compactness of related products and reducing material costs.

[0105] According to an aspect of the present disclosure, a driving chip is provided, and the chip comprises the analog-to-digital converter with embedded filter.

[0106] According to an aspect of the present disclosure, an electronic device is provided, and the electronic device comprises the driving chip.

[0107] In a possible implementation, the electronic device comprises any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an all-in-one computer, an access control device, and an electronic door lock.

[0108] Of course, the electronic device can also be other terminal devices, and the terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device, or a vehicle-mounted device, etc. For example, some terminals include a mobile phone, a tablet computer, a notebook computer, a palm computer, a mobile Internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, a wireless terminal in Internet of Vehicles, etc. For example, the server can be a local server or a cloud server.

[0109] The above has described various embodiments of the present disclosure, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other ordinary skilled persons in the art to understand the disclosed embodiments.

Claims

1. An analog-to-digital converter with an embedded filter, characterized by, The first analog-digital conversion module is a successive approximation analog-digital converter with multiple sampling capacitors and multiple sampling periods, and the first analog-digital conversion module realizes a finite-length unit impulse response (FIR) filtering effect on an input sampling signal through charge sharing between the sampling capacitors; and while some sampling capacitors are still sampling the input signal, a successive approximation quantization process is started on the signals on the sampling capacitors that have completed sampling, The analog-digital conversion unit in the first analog-digital conversion module comprises multiple switch sampling components, an amplification control switch, a first comparator, and a first successive approximation logic circuit unit, and the switch sampling component comprises a first sampling capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and one or more filter control switches, wherein The first end of the first sampling capacitor is connected to the first end of the first switch, the first end of the second switch, and the first end of the third switch, The second end of the first sampling capacitor is connected to the first end of the fourth switch, the first end of the fifth switch, the second end of the third switch, and the first end of each filter control switch, The second end of the second switch is connected to a common-mode voltage, the second end of the first switch of each switch sampling component is connected to the first end of the amplification control switch and the first input end of the first comparator, the second input end of the first comparator is configured to receive a preset voltage, the second end of the amplification control switch is connected to the input end of an amplifier, and the output end of the first comparator is connected to the first successive approximation logic circuit unit, The second end of the fourth switch of each switch sampling component is connected to the output end of an input buffer, The second end of the fifth switch of each switch sampling component is connected to the first successive approximation logic circuit unit, The second end of each filter control switch is connected to a corresponding filter capacitor.

2. The analog-to-digital converter of claim 1, wherein, The analog-digital converter further comprises one or more filter capacitors; after any sampling capacitor samples an input signal, the sampling capacitor is connected to each filter capacitor one by one, and an infinite-length unit impulse response IIR filtering effect on the input sampling signal is realized through charge sharing between the sampling capacitor and each filter capacitor; and while some sampling capacitors are still sampling the input signal or performing IIR filtering, a successive approximation quantization process is started on the signals on the sampling capacitors that have completed sampling and filtering.

3. The analog-to-digital converter of claim 2, wherein, The analog-digital converter further comprises an amplifier and a second analog-digital conversion module, and the first analog-digital conversion module, the amplifier, and the second analog-digital conversion module constitute a pipeline successive approximation analog-digital converter.

4. The analog-to-digital converter of claim 3, wherein, The first analog-digital conversion module further comprises multiple analog-digital conversion units, and a time-domain interleaving relationship is formed between the analog-digital conversion units; after all the sampling capacitors in one analog-digital conversion unit complete sampling, the next analog-digital conversion unit starts the sampling process.

5. The analog-to-digital converter of claim 1, wherein, Each switch sampling component is configured to sequentially enter a reset stage, a sampling stage, a filtering stage, a quantization stage, and a residual error amplification stage, wherein, for any switch sampling component: In the reset stage, the second switch and the third switch are turned on, and the first sampling capacitor is in a reset state; In the sampling stage, the second switch and the fourth switch are turned on, the first sampling capacitor samples charges, after a first sampling duration, the fourth switch is turned off, and after a second delay duration, the second switch is turned off; In the filtering stage, the second switch is turned on, and each filtering control switch is turned on in turn and for a preset duration; In the quantization stage, the first switch and the fifth switch are turned on; In the residual error amplification stage, the amplification control switch is turned on.

6. The analog-to-digital converter of claim 5, wherein, The ith switch sampling assembly is sequentially configured to be in a reset stage, a sampling stage, a filtering stage, a quantization stage, and a residual error amplification stage from an ith clock cycle, where i is a positive integer.

7. A driving chip, characterized by comprising: The chip comprises the embedded filter ADC of any one of claims 1-6.

8. An electronic device, comprising: The electronic device comprises the driving chip of claim 7.

9. The electronic device of claim 8, wherein, The electronic device comprises any one of a display, a smartphone, a smartwatch, a smart bracelet, a tablet computer, a notebook computer, an all-in-one computer, an access control device, and an electronic door lock.

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