Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes: a bit line disposed on a substrate and extending in a first horizontal direction; a word line disposed at a higher vertical height than the bit line above the top surface of the substrate, and extending in a second horizontal direction crossing the first horizontal direction; a channel layer extending in a vertical direction on sidewalls of the word line and including a first sidewall facing the word line and a second sidewall opposite the first sidewall; a first cover pad disposed on a second sidewall of the channel layer and including silicon nitride or a high-k dielectric material; and a first buried insulating layer disposed on a sidewall of the first cover pad.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0176774, filed with the Korean Intellectual Property Office on December 7, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to semiconductor devices, and more particularly, to semiconductor devices including vertical channel transistors. Background Art

[0003] As the size of semiconductor devices is reduced, the size of dynamic random access memory (DRAM) devices is also decreased. In a DRAM device having a 1T-1C structure in which one capacitor is connected to one transistor, there is a limitation in that the smaller the device becomes, the more the current leakage through the channel region increases. To reduce the current leakage, a vertical channel transistor using an oxide semiconductor material as a channel layer has been proposed. Summary of the Invention

[0004] Aspects of the inventive concept provide a semiconductor device having improved electrical performance.

[0005] According to an aspect of the inventive concept, a semiconductor device includes: a bit line located above a substrate and extending in a first horizontal direction; a word line located at a vertical height higher than the bit line above a top surface of the substrate and extending in a second horizontal direction intersecting the first horizontal direction; a channel layer extending vertically on sidewalls of the word line and including a first sidewall facing the word line and a second sidewall opposite to the first sidewall; a first capping liner located on the second sidewall of the channel layer and including silicon nitride or a high-k dielectric material; and a first buried insulating layer located on sidewalls of the first capping liner.

[0006] According to another aspect of the inventive concept, a semiconductor device includes: a bit line located above a substrate and extending in a first horizontal direction; a word line located at a vertical height higher than the bit line above a top surface of the substrate and extending in a second horizontal direction intersecting the first horizontal direction; a gate insulating layer located on sidewalls of the word line; a channel layer extending vertically on sidewalls of the gate insulating layer and including a first sidewall facing the gate insulating layer, a second sidewall opposite to the first sidewall, and third and fourth sidewalls spaced apart from each other in the second horizontal direction; a first capping liner located on the second sidewall of the channel layer and including silicon nitride or a high-k dielectric material; and a second capping liner located on the third and fourth sidewalls of the channel layer and including silicon nitride or a high-k dielectric material.

[0007] According to another aspect of the inventive concept, a semiconductor device includes: a peripheral circuit region located above a substrate; bit lines located in the peripheral circuit region and extending in a first horizontal direction; word lines located at a vertical height above a top surface of the substrate higher than the bit lines and extending in a second horizontal direction crossing the first horizontal direction; a channel layer extending vertically on sidewalls of the word lines and including a first sidewall facing the word lines, a second sidewall opposite to the first sidewall, and a third sidewall and a fourth sidewall spaced apart from each other in the second horizontal direction; a first capping liner located on the second sidewall of the channel layer and including silicon nitride or a high-k dielectric material; a first buried insulating layer located on sidewalls of the first capping liner; a second capping liner located on the third sidewall of the channel layer and sidewalls of the first buried insulating layer and including silicon nitride or a high-k dielectric material; and a second buried insulating layer located on sidewalls of the first buried insulating layer, wherein the second capping liner is disposed between the first buried insulating layer and the second buried insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be understood more clearly from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a layout view showing a semiconductor device according to an embodiment.

[0010] Figure 2 is Figure 1 an enlarged layout view of a part of a cell array region MCA of

[0011] Figure 3 is a cross-sectional view taken along line A1-A1' of Figure 2

[0012] Figure 4 is a cross-sectional view taken along line A2-A2' of Figure 2

[0013] Figure 5 is a horizontal cross-sectional view at a first vertical height LV1 of Figure 3

[0014] Figure 6 is a horizontal cross-sectional view at a second vertical height LV2 of Figure 3

[0015] Figure 7 is a horizontal cross-sectional view at a third vertical height LV3 of Figure 3

[0016] Figure 8 is Figure 3 an enlarged view of region B of

[0017] Figure 9 ​​​​​is a cross-sectional view showing a semiconductor device according to an embodiment.

[0018] Figure 10 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0019] Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B and Figure 22C is a schematic diagram illustrating a method of manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0020] Figure 1 is a layout diagram showing a semiconductor device 100 according to an embodiment. Figure 2 yes Figure 1 An enlarged layout diagram of a portion of the cell array area MCA. Figure 3 It is along Figure 2 A cross-sectional view taken along line A1-A1'. Figure 4 It is along Figure 2 A cross-sectional view taken along line A2-A2'. Figure 5 is Figure 3 A horizontal cross-sectional view at a first vertical height LV1. Figure 6 is Figure 3 A horizontal cross-sectional view at a second vertical height LV2. Figure 7 is Figure 3 A horizontal cross-sectional view at a third vertical height LV3. Figure 8 yes Figure 3An enlarged view of region B. The semiconductor device 100 can be, for example, a semiconductor chip (e.g., a semiconductor memory chip), or a semiconductor package including one or more semiconductor chips.

[0021] Referring to Figures 1 to 8 , the semiconductor device 100 can include a peripheral circuit area PCA and a cell array area MCA located at a vertical height higher than the peripheral circuit area PCA. In some embodiments, the cell array area MCA can include a memory cell area of a dynamic random access memory (DRAM) device, and the peripheral circuit area PCA can include a core area or a peripheral circuit area of the DRAM device. For example, the peripheral circuit area PCA can include peripheral circuit transistors PC for transmitting signals and / or power to a memory cell array included in the cell array area MCA. In some embodiments, the peripheral circuit transistors PC can constitute various circuits, such as a command decoder, control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input / output circuit.

[0022] As Figure 2 shown, in the cell array area MCA, a plurality of word lines WL extend in a first horizontal direction X, and a plurality of bit lines BL extend in a second horizontal direction Y. An item, layer, or part of an item or layer described as extending in a particular direction can be further described as extending "longitudinally" in the particular direction, which indicates that the item, layer, or part of the item or layer has a length in the particular direction and a width perpendicular to that direction, where the length is greater than the width, unless the context indicates otherwise. A plurality of cell transistors CTR can be located at intersections between the plurality of word lines WL and the plurality of bit lines BL. A plurality of storage nodes SN can be respectively located above the plurality of cell transistors CTR.

[0023] The plurality of word lines WL can include a first word line WL1 and a second word line WL2 alternately arranged in the second horizontal direction Y, and the plurality of cell transistors CTR can include a first cell transistor CTR1 and a second cell transistor CTR2 alternately arranged in the second horizontal direction Y. The first cell transistor CTR1 can be located adjacent to the first word line WL1, and the second cell transistor CTR2 can be located adjacent to the second word line WL2. The first word line WL1 can be one of the plurality of first word lines, and the second word line WL2 can be one of the plurality of second word lines such that the plurality of first word lines and the plurality of second word lines are alternately arranged in the second horizontal direction Y. Similarly, the first cell transistor CTR1 can be one of the plurality of first cell transistors, and the second cell transistor CTR2 can be one of the plurality of second cell transistors such that the plurality of first cell transistors and the plurality of second cell transistors are alternately arranged in the second horizontal direction Y.

[0024] The first unit transistor CTR1 and the second unit transistor CTR2 may have a structure that is mirror-symmetric with respect to each other. For example, the first unit transistor CTR1 and the second unit transistor CTR2 may have a structure that is mirror-symmetric with respect to a center line extending between the first unit transistor CTR1 and the second unit transistor CTR2 and in the first horizontal direction X.

[0025] In some embodiments, the plurality of word lines WL may have a width of 1F (e.g., in the second horizontal direction Y), the plurality of word lines WL may have a pitch of 2F (i.e., in the second horizontal direction Y, the sum of the width and the pitch), the plurality of bit lines BL may have a width of 1F (e.g., in the first horizontal direction X), the plurality of bit lines BL may have a pitch of 2F (i.e., in the first horizontal direction X, the sum of the width and the pitch), and the unit area for forming one unit transistor CTR may be 4F. 2 . Thus, the unit transistor CTR may be a cross-point type that requires a relatively small unit area, which may be beneficial for improving the integration degree of the semiconductor device 100. The unit transistor CTR may be a vertical unit transistor, such as a DRAM vertical unit transistor.

[0026] The substrate 110 may include silicon (e.g., single-crystalline silicon, polycrystalline silicon, or amorphous silicon), or may be formed of silicon (e.g., single-crystalline silicon, polycrystalline silicon, or amorphous silicon). In some embodiments, the substrate 110 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP, or may be formed of at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate 110 may include a conductive region, such as a well doped with impurities or a structure doped with impurities.

[0027] The device isolation layer 110I that defines the active region may be located on the substrate 110, and the peripheral circuit transistors PC may be located on the substrate 110. Each of the peripheral circuit transistors PC may include a gate electrode 112, a gate insulating layer 114, and source / drain regions 116, and may be electrically connected to the bit line BL or the word line WL through, for example, the peripheral circuit wiring PCL and the peripheral circuit contact PCT.

[0028] On the substrate 110, the peripheral circuit insulating layer 118 may cover the peripheral circuit transistors PC, the peripheral circuit wiring PCL, and the peripheral circuit contact PCT. The peripheral circuit insulating layer 118 may include an oxide film, a nitride film, a low-k dielectric film, or a combination thereof, or may be formed of an oxide film, a nitride film, a low-k dielectric film, or a combination thereof, and the peripheral circuit insulating layer 118 may have a stacked structure of a plurality of insulating layers.

[0029] The bit line BL extending in the second horizontal direction Y may be located on the peripheral circuit insulating layer 118. In some embodiments, the bit line BL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, polysilicon, or a combination thereof, or may be formed of Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, polysilicon, or a combination thereof.

[0030] The bit line separation insulating layer 122 may be located between the plurality of bit lines BL. The bit line separation insulating layer 122 may include an oxide film, a nitride film, a low-k dielectric film, or a combination thereof, or may be formed of an oxide film, a nitride film, a low-k dielectric film, or a combination thereof.

[0031] In some embodiments, a shielding structure extending in the second horizontal direction Y may further be located between the plurality of bit lines BL. The shielding structure may include a conductive material, such as a metal. In some embodiments, the shielding structure may be formed of a conductive material and may include an air gap or void therein, or in other embodiments, an air gap may be defined in the bit line separation insulating layer 122 instead of the shielding structure.

[0032] The etch stop film 124 extending in the first horizontal direction X may be located on the plurality of bit lines BL and the bit line separation insulating layer 122. In some embodiments, the etch stop film 124 may include silicon nitride, or may be silicon nitride.

[0033] Pairs of gate electrodes 132 may be spaced apart from each other on the etch stop film 124. In some embodiments, the pairs of gate electrodes 132 may be spaced apart from each other in the second horizontal direction Y, and each of the pairs of gate electrodes 132 may correspond to a respective one of the plurality of word lines WL. In some embodiments, the pairs of gate electrodes 132 may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, polysilicon, or a combination thereof, or may be formed of Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, polysilicon, or a combination thereof.

[0034] In some embodiments, the pair of gate electrodes 132 may have a strip shape or a line pattern shape extending in a first horizontal direction X. For example, the pair of gate electrodes 132 may be formed by forming a mask pattern having a line pattern shape on a gate electrode layer and patterning the gate electrode layer using the mask pattern as an etching mask. Thus, the pair of gate electrodes 132 may have a flat shape in the form of a strip or a line.

[0035] In some embodiments, as Figure 3 shown, the pair of gate electrodes 132 may have vertical or substantially vertical sidewalls and may have a width that is constant in a second horizontal direction Y over its total height. In other embodiments, the pair of gate electrodes 132 may have slanted sidewalls, and the width of the upper portion of the pair of gate electrodes 132 in the second horizontal direction Y may be less than the width of the lower portion of the pair of gate electrodes 132 in the second horizontal direction Y. Terms such as "same", "equal", "flat", "coplanar", "parallel", and "perpendicular" as used herein include equality or approximate equality, which includes, for example, variations that may occur due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning.

[0036] Each of the pair of gate electrodes 132 may have a sidewall on which the gate insulating layer 134 is located. The gate insulating layer 134 may be located on both sidewalls of the pair of gate electrodes 132 and may extend, for example, from the sidewalls of the pair of gate electrodes 132 facing each other to the upper surface of the etch stop film 124 located between the pair of gate electrodes 132.

[0037] In some embodiments, the gate insulating layer 134 may include or be formed of at least one selected from high-k dielectric materials and ferroelectric materials having a dielectric constant higher than that of silicon oxide. In some embodiments, the gate insulating layer 134 may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), lead zirconate titanate (PbZrTiO), strontium bismuth tantalate (StTaBiO), bismuth iron oxide (BiFeO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO), or be formed of at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), lead zirconate titanate (PbZrTiO), strontium bismuth tantalate (StTaBiO), bismuth iron oxide (BiFeO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0038] In the space between the paired gate electrodes 132, a molded insulating layer 136 may be located on the gate insulating layer 134. The molded insulating layer 136 may have an upper surface at the same height as the upper surfaces of the paired gate electrodes 132, and may fill the space between the paired gate electrodes 132 while extending in a first horizontal direction X. A molded covering layer 138 may be located on the upper surfaces of the paired gate electrodes 132 and the molded insulating layer 136. In some embodiments, the molded insulating layer 136 may include or be formed of silicon oxide or a low-k dielectric material, and the molded covering layer 138 may include or be formed of silicon nitride.

[0039] The paired gate electrodes 132, the gate insulating layer 134 on the sidewalls of the paired gate electrodes 132, the molded insulating layer 136 filling the space between the paired gate electrodes 132, and the molded cover layer 138 may be referred to as a molded line pattern. The molded line pattern may extend in the first horizontal direction X, and a molded opening H1 (see Figure 14B ) may be defined between one molded line pattern and another adjacent molded line pattern. The molded opening H1 may have a bottom portion exposing the upper surface of the bit line BL and the bit line isolation insulating layer 122.

[0040] The channel layer 140 may be located in the molded opening H1. The channel layer 140 may have a U-shaped vertical cross-section and may include a first vertical portion P1, a second vertical portion P2, and a connecting portion P3. The first vertical portion P1 may be located on the first sidewall of the molded opening H1 and may extend in the vertical direction Z, and the second vertical portion P2 may be located on the second sidewall of the molded opening H1 and may extend in the vertical direction Z. The second vertical portion P2 may be spaced apart from the first vertical portion P1 in the second horizontal direction Y. The connecting portion P3 may be connected to the bottom portions of the first vertical portion P1 and the second vertical portion P2 and may be located on the upper surface of the bit line BL.

[0041] Relative to one channel layer 140 located between two molded line patterns, the first vertical portion P1 may be positioned to face the gate electrode 132 within one molded line pattern, and the second vertical portion P2 may be positioned to face the gate electrode 132 within the other molded line pattern. The gate electrode 132 within one molded line pattern and facing the first vertical portion P1 may correspond to the first word line WL1 (see Figure 2 ), and the first vertical portion P1, the first word line WL1, and the gate insulating layer 134 therebetween may form a first unit transistor CTR1 (see Figure 2 ). The gate electrode 132 within one molded line pattern and facing the second vertical portion P2 may correspond to the second word line WL2 (see Figure 2 ), and the second vertical portion P2, the second word line WL2, and the gate insulating layer 134 therebetween may form a second unit transistor CTR2 (see Figure 2 ). Accordingly, the first unit transistor CTR1 and the second unit transistor CTR2 may have a structure that is mirror-symmetric with respect to each other.

[0042] In some embodiments, the channel layer 140 may include zinc tin oxide (Zn x Sn y O), indium zinc oxide (In x Zn y O), zinc oxide (ZnO x ), indium gallium zinc oxide (In x Ga y Zn zO), indium gallium silicon (In x Ga y Si z O), indium tungsten (In x W y O), indium (In x O), tin oxide (Sn x O), titanium oxide (Ti x O), zinc oxide nitride (Zn x ON z ), magnesium zinc oxide (Mg x Zn y O), zirconium indium zinc oxide (Zr x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn x In y Zn z O) (or indium tin zinc oxide (In x Sn y Zn z O)), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O), silicon indium zinc oxide (Si x In y Zn z O), aluminum zinc tin oxide (Al x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), indium tin gallium oxide (In x Sn y Ga z O), indium aluminum zinc oxide (In x Al y Zn z O), indium gallium oxide (In x Ga y O), magnesium aluminum zinc oxide (Mg x Al y Zn z O) and zirconium zinc tin oxide (Zr x Zn y Sn z O) or more, or composed of zinc tin oxide (Zn x Sn y O), indium zinc oxide (Inx Zn y O), zinc oxide (ZnO x ), indium gallium zinc oxide (In x Ga y Zn z O), indium gallium silicon oxide (In x Ga y Si z O), indium tungsten oxide (In x W y O), indium oxide (In x O), tin oxide (Sn x O), titanium oxide (Ti x O), zinc oxynitride (Zn x ON z ), magnesium zinc oxide (Mg x Zn y O), zirconium indium zinc oxide (Zr x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn x In y Zn z O) (or indium tin zinc oxide (In x Sn y Zn z O)), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O), silicon indium zinc oxide (Si x In y Zn z O), aluminum zinc tin oxide (Al x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), indium tin gallium oxide (In x Sn y Ga z O), indium aluminum zinc oxide (In x Al y Zn z O), indium gallium oxide (In x Ga y O), magnesium aluminum zinc oxide (Mg x Al y Zn z O) and zirconium zinc tin oxide (Zrx Zn y Sn z is formed of at least one of (O).

[0043] In some embodiments, the upper portions of the first vertical portion P1 and the second vertical portion P2 of the channel layer 140 may be further doped with impurity ions, and the connecting portion P3 of the channel layer 140 may be further doped with impurity ions. The connecting portion P3 of the channel layer 140 may be used as a source contact, and the upper portions of the first vertical portion P1 and the second vertical portion P2 of the channel layer 140 may be used as drain contacts.

[0044] In a molding opening H1, a plurality of channel layers 140 may be spaced apart from each other in the first horizontal direction X. The plurality of channel layers 140 may be positioned to be vertically stacked with each of a plurality of bit lines BL, and each connecting portion P3 of the plurality of channel layers 140 may be located on each upper surface of the plurality of bit lines BL.

[0045] As Figure 6 shown, in an exemplary embodiment, the first vertical portion P1 and the second vertical portion P2 of the channel layer 140 may have a horizontally rectangular cross-section. The first vertical portion P1 of the channel layer 140 may include a first sidewall S1 facing the gate electrode 132 (e.g., word line WL) and a second sidewall S2 opposite and spaced apart from the first sidewall S1 in the second horizontal direction Y. In addition, the first vertical portion P1 of the channel layer 140 may include a third sidewall S3 and a fourth sidewall S4 spaced apart from each other in the first horizontal direction X. The first sidewall S1 of the first vertical portion P1 may be in contact with the gate insulating layer 134. It will be understood that when an element is referred to as being "connected" or "coupled" to another element or "on" another element, the element may be directly connected or coupled to the other element or directly on the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, or as "contacting" another element or "in contact with" another element (or using any form of the word "contact"), there are no intervening elements at the point of contact.

[0046] The first capping liner 152 may be located on the second sidewall S2 of the first vertical portion P1 of the channel layer 140, the second sidewall S2 of the second vertical portion P2, and the upper surface of the connecting portion P3. The first capping liner 152 may extend from the upper surface of the connecting portion P3 to the upper surface of the bit line isolation insulating layer 122. The first capping liner 152 may be located on the entire second sidewall S2 of the first vertical portion P1 and the entire second sidewall S2 of the second vertical portion P2. The first capping liner 152 may include or be formed of silicon nitride or a high-k dielectric material. In some embodiments, the high-k dielectric material may be at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconium titanate (PbZrTiO), strontium bismuth tantalate (StTaBiO), bismuth iron oxide (BiFeO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0047] The first buried insulating layer 154 may be located on the first capping liner 152 and may fill the space between the second sidewall S2 of the first vertical portion P1 and the second sidewall S2 of the second vertical portion P2. For example, the first buried insulating layer 154 may be located on the sidewall of the portion of the first capping liner 152 located on the second sidewall S2 of the first vertical portion P1 and on the upper surface of the portion of the first capping liner 152 located on the upper surface of the connecting portion P3. The upper surface of the first buried insulating layer 154 may be at a height lower than the upper surface of the channel layer 140 (e.g., the upper surface of the first vertical portion P1).

[0048] The first buried insulating layer 154 may be spaced apart from the second sidewall S2 of the first vertical portion P1 of the channel layer 140 in the second horizontal direction Y, and due to the first capping liner 152 provided between the first buried insulating layer 154 and the second sidewall S2, the first buried insulating layer 154 may not contact the second sidewall S2 of the first vertical portion P1 of the channel layer 140.

[0049] In some embodiments, the first vertical portion P1 of the channel layer 140 may have a first width w1 in the first horizontal direction X, the first buried insulating layer 154 may have a second width w2 equal to the first width w1 in the first horizontal direction X, and the first capping liner 152 may have a third width w3 equal to the first width w1 in the first horizontal direction X.

[0050] In a molding opening H1, a plurality of first buried insulating layers 154 may be spaced apart from each other in a first horizontal direction X. The plurality of first buried insulating layers 154 may be at positions corresponding to each of the plurality of channel layers 140 and may be positioned to be vertically stacked with each of the plurality of bit lines BL.

[0051] A second capping liner 156 may be located on third sidewalls S3 and fourth sidewalls S4 of the first vertical portion P1, on sidewalls of the gate insulating layer 134, and on sidewalls of the first buried insulating layer 154. In some embodiments, the second capping liner 156 may include silicon nitride or a high-k dielectric material.

[0052] In some embodiments, the gate insulating layer 134 may include a first portion 134P1 and a second portion 134P2. The first portion 134P1 of the gate insulating layer 134 may be located between the gate electrode 132 and the channel layer 140 and may be in contact with the channel layer 140. The second portion 134P2 of the gate insulating layer 134 may be located between the gate electrode 132 and the second capping liner 156 and may be in contact with the second capping liner 156.

[0053] A second buried insulating layer 158 may be located on sidewalls of the first buried insulating layer 154. For example, in a molding opening H1, the second buried insulating layer 158 may fill a space between the plurality of first buried insulating layers 154, and the second capping liner 156 may be disposed between the first buried insulating layer 154 and the second buried insulating layer 158. For example, as Figure 7 shown, at a third vertical height LV3 higher than an upper surface of the gate electrode 132, an upper portion of the second buried insulating layer 158 may have a horizontal cross-sectional shape that fills the molding opening H1 and extends in the first horizontal direction X. As Figure 6 shown, at a second vertical height LV2 lower than the upper surface of the gate electrode 132 and higher than a bottom surface of the gate electrode 132, a lower portion of the second buried insulating layer 158 may fill the space between the plurality of first buried insulating layers 154.

[0054] In some embodiments, the first buried insulating layer 154 and the second buried insulating layer 158 may include silicon oxide or a low-k dielectric material or may be formed of silicon oxide or a low-k dielectric material.

[0055] A second sidewall S2 of the channel layer 140 may be covered by a first capping liner 152, and third sidewalls S3 and fourth sidewalls S4 of the channel layer 140 may be covered by the second capping liner 156. Accordingly, the channel layer 140 may not be in contact with the first buried insulating layer 154 or the second buried insulating layer 158. Accordingly, when the semiconductor device 100 is used, an oxygen path to the channel layer 140 may be blocked, and reliability of the unit transistor CTR may be improved.

[0056] The upper insulating layer 162 may be located on the second buried insulating layer 158 and the molded cover layer 138. The bonding pad 164 may be located in the bonding pad opening 164H passing through the upper insulating layer 162. The bonding pad 164 may be in contact with the upper surface of the channel layer 140 (e.g., the upper surface of the first vertical portion P1 and the upper surface of the second vertical portion P2). In some embodiments, the bonding pad 164 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof, or may be formed of Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0057] The storage node SN may be located on the bonding pad 164. In some embodiments, the storage node SN may include or be a capacitor having a metal-insulator-metal (MIM) structure. In other embodiments, the storage node SN may include or be a variable resistance memory component, a phase change memory component, a magnetic memory component, etc., thereby generating, for example, a capacitorless memory such as a capacitorless DRAM.

[0058] According to the above embodiments, the second sidewall S2 of the channel layer 140 may be covered by the first cover liner 152, and the third sidewall S3 and the fourth sidewall S4 of the channel layer 140 may be covered by the second cover liner 156. Therefore, the channel layer 140 may not be in contact with the first buried insulating layer 154 or the second buried insulating layer 158. Therefore, when the semiconductor device 100 is used, the oxygen path to the channel layer 140 may be blocked, and the reliability of the unit transistor CTR may be improved. During annealing, the oxygen supply to the connection portion P3 of the channel layer 140 in contact with the bit line BL may be blocked, thereby improving the performance of the unit transistor CTR, such as increasing the on-current.

[0059] Figure 9 is a cross-sectional view showing a semiconductor device 100A according to an embodiment.

[0060] Refer to Figure 9, the molded insulating layer 136A located between the pair of gate electrodes 132 may include an air space. For example, the molded insulating layer 136A may include a space defined by a portion of the gate insulating layer 134 on the sidewalls of the pair of gate electrodes 132 and a portion of the gate insulating layer 134 on the upper surface of the etch stop film 124, and the space may be filled with air rather than any material layer. In other embodiments, the molded insulating layer 136A may include an insulating material layer that includes voids or gaps therein. For example, the insulating material layer may be formed on the sidewalls and the upper surface of the gate insulating layer 134, and the voids or gaps may be located within the insulating material layer. The term "air" as discussed herein may refer to atmospheric air or other gases that may be present during the manufacturing process. The voids or gaps may refer to gaps in which a vacuum is formed, or may also include air.

[0061] Figure 10 is a cross-sectional view showing a semiconductor device 100B according to an embodiment.

[0062] Referring to Figure 10 , the upper surface (e.g., the uppermost surface or the top surface) of the first buried insulating layer 154 may be at a height higher than the upper surface (e.g., the uppermost surface or the top surface) of the gate electrode 132 and at a height lower than the upper surface (e.g., the uppermost surface or the top surface) of the channel layer 140 (e.g., the upper surface of the first vertical portion P1 or the upper surface of the second vertical portion P2). The bottom surface (e.g., the lowermost surface) of the second buried insulating layer 158 may also be at a height higher than the upper surface of the gate electrode 132 and at a height lower than the upper surface of the channel layer 140 (e.g., the upper surface of the first vertical portion P1 or the upper surface of the second vertical portion P2). For example, the term "height" as discussed herein may refer to the vertical height or vertical position in the Z direction above the top surface of the substrate 110.

[0063] In some embodiments, a portion of the channel layer 140 at a vertical height higher than the upper surface of the first buried insulating layer 154 (e.g., a portion of the first vertical portion P1 at a vertical height higher than the upper surface of the first buried insulating layer 154 or a portion of the second vertical portion P2 at a vertical height higher than the upper surface of the first buried insulating layer 154) may be doped with impurity ions, and this portion of the channel layer 140 may be used as a drain contact electrically connected to the bonding pad 164.

[0064] Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B ,Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B and Figure 22C are schematic views showing a method of manufacturing a semiconductor device according to an embodiment.

[0065] Specifically, Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A and Figure 22A are horizontal cross-sectional views at a second vertical height LV2 of Figure 3 according to the process sequence, Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B and Figure 22B are cross-sectional views taken along line A1 - A1' of Figure 2 , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C , Figure 20C , Figure 21C and Figure 22C are cross-sectional views taken along line A2 - A2' of Figure 2 .

[0066] Refer to Figure 11A and Figure 11B, an external circuit transistor PC, an external circuit wiring PCL, an external circuit contact PCT, and an external circuit insulating layer 118 can be formed on the substrate 110. Each of the external circuit transistors PC may include a gate electrode 112, a gate insulating layer 114, and source / drain regions 116. On the substrate 110, the external circuit insulating layer 118 can cover the external circuit transistor PC, the external circuit wiring PCL, and the external circuit contact PCT.

[0067] Thereafter, on the external circuit insulating layer 118, a plurality of bit lines BL extending in the second horizontal direction Y and a bit line separation insulating layer 122 filling the space between the plurality of bit lines BL are formed.

[0068] In some embodiments, to form the bit line separation insulating layer 122 on the external circuit insulating layer 118, a bit line formation space (not shown) can be formed by patterning the bit line separation insulating layer 122 with a mask pattern (not shown), a conductive layer can be formed in the bit line formation space, and an upper portion of the conductive layer can be removed such that the upper surface of the bit line separation insulating layer 122 is exposed, thereby forming a plurality of bit lines BL.

[0069] Referring to Figure 12A and 12B , an etch stop film 124 is formed on the plurality of bit lines BL and the bit line separation insulating layer 122. Thereafter, a gate electrode 132 extending in the first horizontal direction X is formed on the etch stop film 124.

[0070] In some embodiments, to form the etch stop film 124 on the plurality of bit lines BL and the bit line separation insulating layer 122, a gate electrode layer is formed on the etch stop film 124 with a conductive material, a mask pattern is formed on the gate electrode layer, and then the gate electrode layer is patterned to form the gate electrode 132.

[0071] In some embodiments, the gate electrodes 132 can be positioned at a predetermined pitch in the second horizontal direction Y. For example, as shown in Figure 12A , the odd-numbered gate electrodes 132 can be positioned at equal intervals (or at the same pitch), and the even-numbered gate electrodes 132 can be positioned at equal intervals (or at the same pitch). The space between two adjacent gate electrodes 132 can be different from the space between any other two adjacent gate electrodes 132.

[0072] In other embodiments, different from the illustration in Figure 12A , the space between two adjacent gate electrodes 132 can be the same as the space between any other two adjacent gate electrodes 132.

[0073] Referring to Figure 13A and Figure 13B, a gate insulating layer 134 covering the gate electrode 132 is formed on the etch stop film 124. The gate insulating layer 134 can conformally cover the upper surface and two sidewalls of the gate electrode 132.

[0074] In some embodiments, at least one of a chemical vapor deposition (CVD) process, a low-pressure CVD process, a plasma-enhanced CVD process, a MOCVD process, and an atomic layer deposition process can be used to form the gate insulating layer 134.

[0075] Referring to Figure 14A and Figure 14B , a molded insulating layer 136 is formed on the gate insulating layer 134, and the upper portion of the molded insulating layer 136 can be planarized such that the upper surface of the gate electrode 132 is exposed. Thereafter, a molded cover layer 138 covering the pair of gate electrodes 132 and the molded insulating layer 136 therebetween can be formed, and portions of the molded insulating layer 136 not covered by the molded cover layer 138, portions of the gate insulating layer 134 not covered by the molded cover layer 138, and portions of the etch stop film 124 not covered by the molded cover layer 138 can be removed such that the upper surfaces of the bit line BL and the bit line separation insulating layer 122 are exposed.

[0076] For example, the molded cover layer 138 can extend in a first horizontal direction X and can have a line pattern shape covering the pair of gate electrodes 132. The pair of gate electrodes 132, the gate insulating layer 134 on two sidewalls of the pair of gate electrodes 132, the molded insulating layer 136 between the pair of gate electrodes 132, and the molded cover layer 138 can be referred to as a molded line pattern. A molded opening H1 can be defined between one molded line pattern and another adjacent molded line pattern. The molded opening H1 can have a bottom portion exposing the upper surfaces of the bit line BL and the bit line separation insulating layer 122.

[0077] Referring to Figures 15A to 15C , a channel layer 140 is formed on the inner wall of the molded opening H1.

[0078] In some embodiments, the channel layer 140 includes indium gallium zinc oxide (In x Ga y Zn z O), indium tungsten oxide (In x W y O), indium tin gallium oxide (In x Sn y Ga z O), indium aluminum zinc oxide (In x Al y Zn z O), indium gallium oxide (In x Ga y O), indium tin zinc oxide (Inx Sn y Zn z O), indium gallium silicon (In x Ga y Si z O), indium zinc oxide (In x Zn y O), indium oxide (In x O), magnesium aluminum zinc oxide (Mg x Al y Zn z O), zinc tin oxide (Zn x Sn y O), zirconium zinc tin oxide (Zr x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), aluminum zinc tin oxide (Al x Zn y Sn z O) and tin oxide (Sn x O), or indium gallium zinc oxide (In x Ga y Zn z O), indium tungsten oxide (In x W y O), indium tin gallium oxide (In x Sn y Ga z O), indium aluminum zinc oxide (In x Al y Zn z O), indium gallium oxide (In x Ga y O), indium tin zinc oxide (In x Sn y Zn z O), indium gallium silicon oxide (In x Ga y Si z O), indium zinc oxide (In x Zn y O), indium oxide (In x O), magnesium aluminum zinc oxide (Mg x Al y Zn z O), zinc tin oxide (Zn x Sn y O), zirconium zinc tin oxide (Zr x Zn y Sn zO), zinc tin gallate (Ga x Zn y Sn z O), aluminum zinc tin oxide (Al x Zn y Sn z O) and tin oxide (Sn x O) and is formed of at least one of them.

[0079] In some embodiments, at least one of a CVD process, a low-pressure CVD process, a plasma-enhanced CVD process, a MOCVD process, and an atomic layer deposition process may be used to form the channel layer 140.

[0080] In some embodiments, the channel layer 140 may have a U-shaped vertical cross-section and may include a first vertical portion P1, a second vertical portion P2, and a connecting portion P3. The first vertical portion P1 may be located on the first sidewall of the molding opening H1 and may extend in the vertical direction Z, and the second vertical portion P2 may be located on the second sidewall of the molding opening H1 and may extend in the vertical direction Z. The second vertical portion P2 may be spaced apart from the first vertical portion P1 in the second horizontal direction Y. The connecting portion P3 may be connected to the bottom portions of the first vertical portion P1 and the second vertical portion P2 and may be located on the upper surfaces of the bit line BL and the bit line isolation insulating layer 122. The channel layer 140 may be formed on the inner wall of the molding opening H1 with a relatively small thickness, and thus, the inside of the molding opening H1 may be retained without being completely filled.

[0081] Referring to Figures 16A to 16C , a protective layer (not shown) that fills the molding opening H1 may be formed on the channel layer 140, and a portion of the protective layer (not shown) may be removed by an etch-back process. A portion of the channel layer 140 may also be removed in the etch-back process for the protective layer, and a plurality of channel layers 140 may be retained in the molding opening H1. Each of the plurality of channel layers 140 may be located at a position vertically stacked with each of the plurality of bit lines BL.

[0082] Referring to Figures 17A to 17C , a first capping liner 152 and a first buried insulating layer 154 are sequentially formed on the inner wall of the molding opening H1.

[0083] In some embodiments, the first capping liner 152 may be formed of silicon nitride or a high-k dielectric material, and the first buried insulating layer 154 may be formed of silicon oxide or a low-k dielectric material.

[0084] The first capping liner 152 may cover the surface of the channel layer 140 located on the inner wall of the molding opening H1 and may be located on the second sidewall S2 of the first vertical portion P1 of the channel layer 140 (see Figure 6), on the upper surface of the connection part P3 and the second side wall S2 of the second vertical part P2.

[0085] Referring to Figures 18A to 18C , a mask pattern may be formed on the first capping liner 152 and the first buried insulating layer 154, and the mask pattern may be used as an etching mask to remove a part of the first capping liner 152 and a part of the first buried insulating layer 154, thereby forming a tunnel opening H2.

[0086] In some embodiments, the tunnel opening H2 may be positioned to expose the third side wall S3 and the fourth side wall S4 of the channel layer 140. When the tunnel opening H2 is formed, the first capping liner 152 and the first buried insulating layer 154 may be formed to have a width equal to the horizontal direction width of the first vertical part P1 of the channel layer 140.

[0087] In some embodiments, in the process of forming the tunnel opening H2, the part of the first capping liner 152 located at the bottom part of the tunnel opening H2 may be left without being removed. Accordingly, the side walls of the connection part P3 of the channel layer 140 may be covered by the first capping liner 152 and may not be exposed in the inner space of the tunnel opening H2.

[0088] Referring to Figures 19A to 19C , the upper part of the first buried insulating layer 154 may be removed such that the upper surface of the first buried insulating layer 154 is at a height lower than the upper surface of the gate electrode 132 and / or the upper surface of the first capping liner 152.

[0089] An oxygen source layer 210 may be formed in the tunnel opening H2. The oxygen source layer 210 may have an upper surface located at the same height as the upper surface of the first buried insulating layer 154. When the oxygen source layer 210 fills the inner space of the tunnel opening H2, the third side wall S3 and the fourth side wall S4 of the first vertical part P1 of the channel layer 140 may be in contact with the oxygen source layer 210.

[0090] In some embodiments, the oxygen source layer 210 may be formed of silicon oxide using at least one of a CVD process, a low-pressure CVD process, a plasma-enhanced CVD process, a MOCVD process, and an atomic layer deposition process.

[0091] Thereafter, an annealing process may be performed on the structure in which the oxygen source layer 210 is formed. In some embodiments, the annealing process may be performed at a temperature of about 100°C to about 400°C for several minutes to several hours. In some embodiments, the annealing process may be performed at atmospheric pressure or under reduced pressure.

[0092] In some embodiments, through an annealing process, oxygen atoms included in the oxygen source layer 210 can diffuse through the third sidewall S3 and the fourth sidewall S4 of the first vertical portion P1 of the channel layer 140 and move into the first vertical portion P1. In addition, through the annealing process, oxygen atoms included in the oxygen source layer 210 can diffuse through the third sidewall S3 and the fourth sidewall S4 of the second vertical portion P2 of the channel layer 140 and move into the second vertical portion P2.

[0093] According to some embodiments, oxygen atoms can diffuse from the oxygen source layer 210 filled in the tunnel opening H2 and move into the channel layer 140, and thus oxygen atoms can be supplemented into oxygen vacancies within the channel layer 140, thereby reducing the trap density within the channel layer 140.

[0094] In addition, the connecting portion P3 of the channel layer 140 can be covered by the first cover liner 152 and can be not in contact with the oxygen source layer 210. Therefore, during the annealing process, oxygen can be prevented from being supplied into the connecting portion P3 of the channel layer 140.

[0095] Referring to Figures 20A to 20C , the oxygen source layer 210 can be removed, and the inner wall of the tunnel opening H2 can be exposed again. For example, the third sidewall S3 and the fourth sidewall S4 of the channel layer 140 located on the inner wall of the tunnel opening H2 and the sidewalls of the first buried insulating layer 154 can be exposed again without being covered by the oxygen source layer 210.

[0096] Referring to Figures 21A to 21C , a second cover liner 156 and a second buried insulating layer 158 are sequentially formed on the inner wall of the tunnel opening H2. On the inner wall of the tunnel opening H2, the second cover liner 156 can be conformally formed to cover the third sidewall S3 and the fourth sidewall S4 of the channel layer 140 and the sidewalls of the first buried insulating layer 154.

[0097] In some embodiments, the second cover liner 156 can be formed of silicon nitride or a high-k dielectric material, and the second buried insulating layer 158 can be formed of silicon oxide or a low-k dielectric material.

[0098] As Figure 21B shown, the second cover liner 156 can extend to the upper surface of the first buried insulating layer 154 and the sidewalls of the first cover liner 152 located at the upper portion of the molding opening H1 (e.g., at a height higher than the upper surface of the first buried insulating layer 154). The lower portion of the second buried insulating layer 158 can fill the space between two adjacent first buried insulating layers 154 (e.g., the second buried insulating layer 158 can fill the inner space of the tunnel opening H2), and the upper portion of the second buried insulating layer 158 can extend in the first horizontal direction X at a vertical height higher than the upper surface of the first buried insulating layer 154.

[0099] Referring to Figures 22A to 22C , an upper insulating layer 162 may be formed on the molded cover layer 138 and the second buried insulating layer 158. Thereafter, a part of the upper insulating layer 162 may be removed, and a bonding pad opening 164H exposing the upper surface of the channel layer 140 may be formed. A bonding pad 164 may be formed in the bonding pad opening 164H. In some embodiments, the bonding pad 164 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof, or may be formed of Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0100] In some embodiments, after the bonding pad opening 164H is formed, an upper portion (e.g., an upper portion of the first vertical portion P1 and an upper portion of the second vertical portion P2) of the channel layer 140 exposed through the bottom portion of the bonding pad opening 164H may be removed, and a bottom portion of the bonding pad 164 may extend into a space from which the upper portion of the channel layer 140 has been removed. Here, the bonding pad 164 may have a T-shaped vertical cross-section.

[0101] Returning to the reference Figure 3 and Figure 4 , a storage node SN may be formed on the bonding pad 164.

[0102] The semiconductor device 100 may be completed by performing the above-described processes and performing additional steps (such as a dicing process and a packaging process for fabricating a semiconductor chip).

[0103] According to some embodiments, oxygen atoms may be supplied from an oxygen source layer 210 located in the tunnel opening H2 to the channel layer 140 through a third sidewall S3 and a fourth sidewall S4 of the channel layer 140. Accordingly, the trap density in the channel layer 140 may be reduced, and the semiconductor device 100 may have excellent electrical properties. In addition, oxygen supply to a connection portion P3 of the channel layer 140 that contacts the bit line BL may be blocked during annealing, thereby improving the performance of the unit transistor CTR, such as increasing the on-current.

[0104] In addition, the second sidewall S2 of the channel layer 140 may be covered by a first cover liner 152, and the third sidewall S3 and the fourth sidewall S4 of the channel layer 140 may be covered by a second cover liner 156. Accordingly, the channel layer 140 may not contact the first buried insulating layer 154 or the second buried insulating layer 158. Therefore, when the semiconductor device 100 is used, an oxygen path to the channel layer 140 may be blocked, and the reliability of the unit transistor CTR may be improved.

[0105] According to an aspect of the inventive concept, sidewalls of the channel layer may be covered by a first capping liner and a second capping liner, and the channel layer may not be in contact with a first buried insulating layer or a second buried insulating layer. Accordingly, when a semiconductor device is used, an oxygen path to the channel layer may be blocked, and reliability of a unit transistor may be improved. In addition, during annealing, oxygen supply to a portion of the channel layer in contact with a bit line may be blocked, thereby improving performance of the unit transistor, such as increasing an on-current.

[0106] Ordinal numbers such as "first", "second", "third", etc. may simply be used as labels for certain elements, steps, etc. to distinguish such elements, steps, etc. from each other. Terms not described with "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. Additionally, a term referred to by a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere by a different ordinal number (e.g., "second" in the specification or another claim).

[0107] Embodiments described herein will be described with reference to plan views and / or cross-sectional views in the form of ideal schematic diagrams. Accordingly, the exemplary diagrams may be modified according to manufacturing techniques and / or tolerances. Therefore, the disclosed embodiments are not limited to the embodiments shown in the figures, but include modifications of configurations formed based on manufacturing processes. Accordingly, regions exemplified in the figures may have a schematic nature, and the shapes of the regions shown in the figures may exemplify aspects of the invention not limited to the specific shapes of regions of elements.

[0108] For ease of description, spatial relative terms such as "beneath", "below", "lower", "above", "upper", "top", "bottom", etc. may be used herein to describe a relationship of one element or feature shown in the figures to another (other) element or feature. It will be understood that, in addition to the orientation depicted in the figures, spatial relative terms are also intended to encompass different orientations of a device during use or operation. For example, if the device in the figures is flipped, an element described as "beneath" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the term "below" may encompass both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0109] In addition, these spatial relative terms such as "above" and "below" as used herein have their ordinary broad meanings - for example, element A may be above element B, even when there is no superposition between them when looking down at the two elements (just as something in the sky is typically above something on the ground, even if not directly above).

[0110] While the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: a bit line on the substrate and extending in a first horizontal direction; a word line disposed above a top surface of the substrate at a higher vertical height than the bit line and extending in a second horizontal direction intersecting the first horizontal direction; a channel layer extending in a vertical direction on a sidewall of the word line and including a first sidewall facing the word line and a second sidewall opposite to the first sidewall; a first capping liner on the second sidewall of the channel layer and comprising silicon nitride or a high-k dielectric material; as well as The first buried insulating layer is located on the sidewall of the first cover pad.

2. The semiconductor device according to claim 1, wherein: The first buried insulating layer is spaced apart from the second sidewall of the channel layer in a first horizontal direction, and The second sidewall of the channel layer does not contact the first buried insulating layer.

3. The semiconductor device according to claim 1, wherein An upper surface of the first buried insulating layer is at a lower height than an upper surface of the channel layer relative to a top surface of the substrate.

4. The semiconductor device according to claim 1, wherein: The channel layer has a first width in a second horizontal direction, The first covering pad has a second width in a second horizontal direction, and The second width is equal to the first width.

5. The semiconductor device according to claim 4, wherein: The first buried insulating layer has a third width in the second horizontal direction, and The third width is equal to the first width.

6. The semiconductor device according to claim 1, wherein: The channel layer further includes a third sidewall and a fourth sidewall spaced apart from each other in the second horizontal direction, and The semiconductor device further includes a second capping liner disposed on the third sidewall of the channel layer and the sidewall of the first buried insulating layer and including silicon nitride or a high-k dielectric material.

7. The semiconductor device according to claim 6, further comprising a second buried insulating layer, the second buried insulating layer being disposed on a side wall of the first buried insulating layer, in, The second capping pad is disposed between the first buried insulating layer and the second buried insulating layer.

8. The semiconductor device according to claim 7, wherein: Each of the first buried insulating layer and the second buried insulating layer includes silicon oxide or a low-k dielectric material.

9. The semiconductor device according to claim 7, wherein: The second capping pad extends onto the upper surface of the first buried insulating layer.

10. The semiconductor device according to claim 7, further comprising a gate insulating layer, the gate insulating layer being disposed on a side wall of the word line, in: A first portion of the gate insulating layer is disposed between the word line and the channel layer, and A second portion of the gate insulating layer is disposed between the word line and the second capping pad.

11. The semiconductor device according to claim 7, wherein: The channel layer includes at least one of indium gallium zinc oxide, indium tungsten oxide, indium tin gallium oxide, indium aluminum zinc oxide, indium gallium oxide, indium tin zinc oxide, indium gallium silicon oxide, indium zinc oxide, indium oxide, magnesium aluminum zinc oxide, zinc tin oxide, zirconium zinc tin oxide, gallium zinc tin oxide, aluminum zinc tin oxide and tin oxide.

12. The semiconductor device according to claim 1, wherein The channel layer forms part of a vertical channel transistor of a dynamic random access memory.

13. A semiconductor device comprising: A bit line disposed on the substrate and extending in a first horizontal direction; a word line disposed above a top surface of the substrate at a higher vertical height than the bit line and extending in a second horizontal direction intersecting the first horizontal direction; A gate insulating layer is disposed on the sidewall of the word line; a channel layer extending in a vertical direction on a sidewall of the gate insulating layer to form a portion of a vertical channel transistor, the channel layer comprising a first sidewall facing the gate insulating layer, a second sidewall opposite to the first sidewall, and a third sidewall and a fourth sidewall spaced apart from each other in a second horizontal direction; a first capping liner disposed on the second sidewall of the channel layer and comprising silicon nitride or a high-k dielectric material; as well as The second capping liner is disposed on the third sidewall and the fourth sidewall of the channel layer and includes silicon nitride or a high-k dielectric material.

14. The semiconductor device according to claim 13, wherein: A first portion of the gate insulating layer is disposed between the word line and the channel layer, and A second portion of the gate insulating layer is disposed between the word line and the second capping pad.

15. The semiconductor device according to claim 13, further comprising: a first buried insulating layer disposed on a sidewall of the first cover liner, wherein the first cover liner is disposed between the channel layer and the first buried insulating layer; and The second buried insulating layer is disposed on the sidewall of the second cover pad.

16. The semiconductor device according to claim 15, wherein: The first buried insulating layer is spaced apart from the second sidewall of the channel layer in a first horizontal direction, and The second sidewall of the channel layer does not contact the first buried insulating layer.

17. The semiconductor device according to claim 15, wherein: With respect to a top surface of the substrate, an upper surface of the first buried insulating layer is at a height lower than an upper surface of the channel layer, and A portion of the second capping pad is disposed on an upper surface of the first buried insulating layer.

18. The semiconductor device according to claim 17, wherein: A portion of the second buried insulating layer is disposed on the portion of the second cover liner, and The second capping pad is disposed between the second buried insulating layer and the first buried insulating layer.

19. A semiconductor device comprising: A peripheral circuit region is arranged on the substrate; A bit line disposed on the peripheral circuit region and extending in a first horizontal direction; a word line disposed above a top surface of the substrate at a higher vertical height than the bit line and extending in a second horizontal direction intersecting the first horizontal direction; a channel layer extending in a vertical direction on a sidewall of the word line and including a first sidewall facing the word line, a second sidewall opposite to the first sidewall, and third and fourth sidewalls spaced apart from each other in a second horizontal direction; a first capping liner disposed on the second sidewall of the channel layer and comprising silicon nitride or a high-k dielectric material; a first buried insulating layer disposed on a sidewall of the first cover liner; a second capping liner disposed on the third sidewall of the channel layer and the sidewall of the first buried insulating layer and comprising silicon nitride or a high-k dielectric material; as well as The second buried insulating layer is disposed on the sidewall of the first buried insulating layer, wherein the second covering pad is disposed between the first buried insulating layer and the second buried insulating layer.

20. The semiconductor device according to claim 19, wherein The first buried insulating layer and the second buried insulating layer each include silicon oxide or a low-k dielectric material.

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