Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes: a substrate; a bit line on the substrate, the bit line extending in a first direction parallel to a top surface of the substrate, and including a metal layer; an insulating cap structure on the bit line, the insulating cap structure including a first insulating cap pattern, a second cover insulating pattern on the first insulating cap pattern, a third insulating cap pattern on the second insulating cap pattern, and a fourth insulating cap pattern on the third insulating cap pattern; a contact plug disposed adjacent to the bit line; a bonding pad disposed on the contact plug and extending over the insulating cover structure, the bonding pad including a first portion and a second portion on the first portion; and a bit line spacer disposed between the bit line and the contact plug and extending on one side of the insulating cover structure. A bottom surface of a first insulating cap pattern of the insulating cap structure contacts the metal layer of the bit line, and a top surface of a fourth insulating cap pattern of the insulating cap structure contacts a bottom surface of the second portion of the bond pad.

Description

[0001] This application is a divisional application of an invention patent application with an application date of April 21, 2020, application number "202010315963.6", and invention name "Integrated circuit device and method for manufacturing the same". Technical Field

[0002] The inventive concept relates to an integrated circuit device and a method of manufacturing the same, and more particularly, to an integrated circuit device including a bit line. Background Art

[0003] As integrated circuit devices have been rapidly reduced, the spacing between multiple wirings has decreased, and the area occupied by multiple wirings and multiple conductive structures placed between the multiple wirings has also decreased. Therefore, it is difficult to ensure sufficient contact area among the multiple wirings and the multiple conductive structures. Therefore, it is desirable to develop a structure capable of suppressing the increase in resistance of wirings densely arranged in a limited area and a method for realizing the structure. Summary of the invention

[0004] According to aspects of the inventive concept, there is provided an integrated circuit device having a structure capable of suppressing an increase in resistance of wirings densely arranged in a limited area in an integrated circuit device having a fine unit cell size according to shrinkage of the integrated circuit device.

[0005] According to another aspect of the inventive concept, there is provided a method of manufacturing an integrated circuit device having a structure capable of suppressing an increase in resistance of wirings densely arranged in a limited area in an integrated circuit device having a fine unit cell size according to shrinkage of the integrated circuit device.

[0006] According to an embodiment, an integrated circuit device is provided, the integrated circuit device comprising: a conductive line formed on a substrate, the conductive line comprising a metal layer and extending in a first horizontal direction relative to an upper surface of the substrate; and an insulating cover structure covering the conductive line. The insulating cover structure comprises: a first insulating cover pattern having a first density, the first insulating cover pattern being adjacent to the metal layer; and a second insulating cover pattern being vertically spaced apart from the metal layer and the first insulating cover pattern being located between the second insulating cover pattern and the metal layer, the second insulating cover pattern having a second density greater than the first density.

[0007] According to another embodiment, an integrated circuit device is provided, which includes: a pair of bit lines extending parallel to each other on a substrate along a first horizontal direction relative to an upper surface of the substrate, the pair of bit lines being adjacent to each other in a second horizontal direction relative to the upper surface of the substrate; a pair of insulating cover structures respectively covering the pair of bit lines; and a contact structure extending in a vertical direction from between the pair of bit lines to between the pair of insulating cover structures, wherein the pair of bit lines each include a metal layer, and each of the pair of insulating cover structures includes: a first insulating cover pattern located on the metal layer, the first insulating cover pattern having a first density; and a second insulating cover pattern spaced apart from the metal layer and the first insulating cover pattern located between the second insulating cover pattern and the metal layer, the second insulating cover pattern having a second density greater than the first density.

[0008] According to another embodiment, an integrated circuit device is provided, which includes: a substrate, including a cell array region and a peripheral circuit region; a bit line, located on the substrate in the cell array region, the bit line including a first metal layer; a first insulating cover structure, covering the bit line in the cell array region; a gate electrode, located on the substrate in the peripheral circuit region, the gate electrode including a second metal layer; and a second insulating cover structure, covering the gate electrode in the peripheral circuit region, wherein each of the first insulating cover structure and the second insulating cover structure includes: a first insulating cover pattern having a first density; and a second insulating cover pattern, which is spaced apart from the substrate and the first insulating cover pattern is located between the second insulating cover pattern and the substrate, the second insulating cover pattern having a second density greater than the first density, the first metal layer is in contact with the first insulating cover pattern included in the first insulating cover structure, the first metal layer includes a first region doped with nitrogen (N) atoms, the first region extends from an interface between the first metal layer and the first insulating cover pattern in the first insulating cover structure toward the substrate and has a partial thickness of the first metal layer.

[0009] According to another embodiment, a method for manufacturing an integrated circuit device is provided, the method comprising: forming a conductive line on a substrate, the conductive line comprising a metal layer; forming an insulating cap structure on the conductive line, the insulating cap structure comprising a plurality of insulating cap patterns. The step of forming the insulating cap structure comprises forming a first insulating cap layer directly on the metal layer, the first insulating cap layer having a first density. Forming a second insulating cap layer on the first insulating cap layer, the second insulating cap layer having a second density greater than the first density.

[0010] According to another embodiment, a method for manufacturing an integrated circuit device is provided, the method comprising: forming a plurality of conductive layers stacked on a substrate, the plurality of conductive layers having a metal layer as an uppermost layer of the plurality of conductive layers. Forming an insulating cap structure on the metal layer, the insulating cap structure comprising a first insulating cap pattern having a first density and a second insulating cap pattern having a second density greater than the first density. Forming a bit line by etching the plurality of conductive layers using the insulating cap structure as an etching mask.

[0011] According to another embodiment, a method for manufacturing an integrated circuit device is provided, the method comprising: forming a plurality of conductive layers on a substrate in a cell array region and a peripheral circuit region, the plurality of conductive layers including a metal layer as the uppermost layer of the plurality of conductive layers. Forming a first insulating cap structure on the plurality of conductive layers in the cell array region, the first insulating cap structure including a first insulating cap pattern and a second insulating cap pattern, the first insulating cap pattern having a first density, and the second insulating cap pattern having a second density greater than the first density. Forming a second insulating cap structure on the plurality of conductive layers in the peripheral circuit region, the second insulating cap structure including a third insulating cap pattern and a fourth insulating cap pattern, the third insulating cap pattern having a first density, and the fourth insulating cap pattern having a second density. Forming a bit line by etching the plurality of conductive layers in the cell array region using the first insulating cap structure as a mask. Forming a gate electrode by etching the plurality of conductive layers in the peripheral circuit region using the second insulating cap structure as an etching mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the inventive concept will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram of an integrated circuit device according to an embodiment of the inventive concept; Figure 2 is a plan view showing an example of arrangement in an integrated circuit device according to an embodiment of the inventive concept; Figure 3 is a diagram showing an embodiment according to the inventive concept Figure 2 A layout diagram of components in a cell array region of an integrated circuit device; Figure 4A and Figure 4B An integrated circuit device according to an embodiment of the inventive concept is provided along Figure 3 A cross-sectional view taken along lines AA' and BB'; Figure 4C According to the embodiment of the invention Figure 2 A cross-sectional view of a peripheral circuit region CORE / PERI of an integrated circuit device; Figure 5 yes Figure 4A An enlarged cross-sectional view of the dotted area “Q1” in FIG. FIG. 6A to FIG. 6C is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept; Figure 7 yes Fig. 6A An enlarged cross-sectional view of the dotted area “Q2” in FIG. FIG. 8A to FIG. 8Q is a cross-sectional view for describing a method of manufacturing an integrated circuit device according to one or more embodiments in a process order; and 9A to 9C are cross-sectional views for describing a method of manufacturing an integrated circuit device according to one or more embodiments in a process order. DETAILED DESCRIPTION

[0013] Hereinafter, one or more embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings represent the same elements, and detailed description thereof will be omitted.

[0014] Figure 1 is a block diagram of an integrated circuit device 100 according to one or more embodiments. Figure 1 An example of an integrated circuit device 100 including a dynamic random access memory (DRAM) device is shown.

[0015] Reference Figure 1 , the integrated circuit device 100 includes a first region 22 and a second region 24. The first region 22 may be a memory cell region of a DRAM device, and the second region 24 may be a peripheral circuit region of the DRAM device. The first region 22 may include a memory cell array 22A. In the memory cell array 22A, a plurality of memory cells for storing data may be arranged in a row direction and a column direction. The second region 24 may include a row decoder 52, a sense amplifier 54, a column decoder 56, a self-refresh control circuit 58, a command decoder 60 receiving a command CMD, a mode register set / extended mode register set (MRS / EMRS) circuit 62, an address buffer 64 receiving an address ADD, and a data input / output circuit 66 for inputting / outputting data DQ.

[0016] Figure 2 It is shown Figure 1 FIG. 1 is a plan view of an exemplary arrangement structure of an integrated circuit device 100 .

[0017] Reference Figure 2, the integrated circuit device 100 includes a plurality of first regions 22. Each of the plurality of first regions 22 may be surrounded by a second region 24. Each of the plurality of first regions 22 may include a cell array region MCA of a DRAM device, and the second region 24 may include a core region and a region for forming a peripheral circuit of the DRAM device and the core region (hereinafter referred to as "peripheral circuit region"). Among the plurality of first regions 22, the cell array region MCA may include the memory cell array 22A described above with reference to Figure 1 described.

[0018] The second region 24 may include a sub-word line driver block SWD, a sense amplifier block S / A, and a clump CJT. In the sense amplifier block S / A, a plurality of bit line sense amplifiers may be arranged. The clump CJT may be at a point where the sub-word line driver block SWD and the sense amplifier block S / A intersect. In the clump CJT, a ground driver and a power driver for driving the bit line sense amplifiers may be alternately arranged. In the second region 24, peripheral circuits such as an inverter chain, an input / output circuit, etc. may be further formed.

[0019] Figure 3 is a layout diagram for showing the components of the cell array region MCA shown in Figure 2 .

[0020] Referring to Figure 3 , the cell array region MCA may include a plurality of cell active regions A1. Each of the plurality of cell active regions A1 may be arranged to have a major axis in an inclined direction with respect to a first horizontal direction (X direction) and a second horizontal direction (Y direction). A plurality of word lines WL may extend parallel to each other in the X direction intersecting the plurality of cell active regions A1. A plurality of bit lines (or conductive lines) BL may extend parallel to each other in the second horizontal direction (Y direction) on the plurality of word lines WL. The plurality of bit lines BL may be connected to the plurality of cell active regions A1 via direct contacts DC. A plurality of buried contacts BC may be formed between two adjacent bit lines among the plurality of bit lines BL. The plurality of buried contacts BC may be arranged in rows along the first horizontal direction (X direction) and the second horizontal direction (Y direction). A plurality of conductive bonding pads LP may be respectively formed on the plurality of buried contacts BC. The plurality of buried contacts BC and the plurality of conductive bonding pads LP may connect a lower electrode (not shown) of a capacitor formed on the plurality of bit lines BL to the cell active region A1. Each of the plurality of conductive bonding pads LP may be partially overlapped with a corresponding one of the buried contacts BC.

[0021] FIG. 4A to FIG. 4C is a cross-sectional view showing an integrated circuit device 200 according to one or more embodiments. Figure 4A and Figure 4BA cross-sectional view showing an exemplary structure of a part of the cell array region MCA in the integrated circuit device 200, Figure 4C is a cross-sectional view showing an exemplary structure of a part of the peripheral circuit region CORE / PERI in the integrated circuit device 200. The cell array region MCA of the integrated circuit device 200 may have a layout as shown in Figure 3 . Figure 4A Shows a cross-section taken along line A-A' of Figure 3 , Figure 4B Shows a cross-section taken along line B-B' of Figure 3 .

[0022] Figure 5 Is Figure 4A An enlarged cross-sectional view of the dashed area "Q1" in

[0023] Referring to FIG. 4A to FIG. 4C and Figure 5 , the integrated circuit device 200 may be a part of the integrated circuit device 100 shown in Figures 1 to 3 . The integrated circuit device 200 includes a substrate 210 having a cell array region MCA and a peripheral circuit region CORE / PERI. Isolation trenches T1 are formed in the substrate 210, and an isolation layer 212 is formed in the isolation trenches T1. Each of the plurality of cell active regions A1 is defined in the substrate 210 in the cell array region MCA of the substrate 210 by the isolation layer 212. The peripheral active region A2 may be defined in the substrate 210 in the peripheral circuit region CORE / PERI by the isolation layer 212.

[0024] The substrate 210 may include silicon, such as single-crystalline silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, the substrate 210 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate 210 may include a conductive region doped with impurities (e.g., a well region) or a structure doped with impurities. The isolation layer 212 may include an oxide layer, a nitride layer, or a combination thereof.

[0025] In the cell array region MCA, a plurality of word line trenches T2 extending in the first horizontal direction (X direction) are formed in the substrate 210, and in the plurality of word line trenches T2, a plurality of gate dielectric layers 216, a plurality of gate lines 218, and a plurality of buried insulating layers 220 are formed. The plurality of gate lines 218 may be connected to Figure 3correspond to multiple word lines WL shown in the figure. A plurality of recessed spaces 220R may be formed in the upper surface of the buried insulating layer 220. Each of the plurality of gate dielectric layers 216 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, or a high-k dielectric layer having a dielectric constant greater than that of the silicon oxide layer. For example, each of the plurality of gate dielectric layers 216 may include HfO 2 、Al 2 O 3 、HfAlO 3 、Ta 2 O 3 or TiO 2 。Each of the plurality of gate lines 218 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. Each of the plurality of buried insulating layers 220 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.

[0026] In the cell array region MCA, a buffer layer 222 may be formed on the substrate 210. The buffer layer 222 may include a first insulating layer 222A and a second insulating layer 222B. Each of the first insulating layer 222A and the second insulating layer 222B may include an oxide layer, a nitride layer, or a combination thereof. A plurality of direct contacts DC may be disposed on the plurality of cell active regions A1. Each direct contact DC may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof.

[0027] A plurality of bit lines BL may extend along a second horizontal direction (Y direction) on the substrate 210 and the plurality of direct contacts DC. Each of the plurality of bit lines BL may be connected to a corresponding one of the cell active regions A1 via a corresponding one of the direct contacts DC. Each of the plurality of bit lines BL may include a lower conductive pattern 230B, an intermediate conductive pattern 232B, and an upper conductive pattern 234B sequentially stacked on the substrate 210. The upper conductive pattern 234B (i.e., the uppermost layer of the bit line BL) may include a metal. The lower conductive pattern 230B may include doped polysilicon. The intermediate conductive pattern 232B may include TiN, TiSiN, W, tungsten silicide, or a combination thereof. In one or more embodiments, the intermediate conductive pattern 232B may include TiN, TiSiN, or a combination thereof, and the upper conductive pattern 234B may include W.

[0028] In an exemplary embodiment, a plurality of insulating cover structures CSC may be respectively stacked vertically on a plurality of bit lines BL. The plurality of bit lines BL may be respectively covered by the plurality of insulating cover structures CSC. For example, each of the plurality of insulating cover structures CSC may cover the upper surface of a corresponding one of the plurality of bit lines BL. The plurality of bit lines BL and the plurality of insulating cover structures CSC may extend parallel to each other in a second horizontal direction (Y direction).

[0029] Each insulating cover structure CSC may include a first insulating cover pattern 236C, a second insulating cover pattern 238C, an insulating thin film pattern 244C, and a third insulating cover pattern 250C that are sequentially stacked on the upper conductive pattern 234B of the bit line BL. Among the plurality of insulating cover structures CSC, the bottom surface of the first insulating cover pattern 236C may be in contact with the upper surface of the upper conductive pattern 234B. The bottom surface of the second insulating cover pattern 238C may be in contact with the upper surface of the first insulating cover pattern 236C. Unless otherwise indicated by the context, the term "contact" or the phrase "in contact with" as used herein refers to direct connection (i.e., touching).

[0030] In each of the plurality of insulating cover structures CSC, the first insulating cover pattern 236C and the second insulating cover pattern 238C may have different densities from each other. In one or more embodiments, among the first insulating cover pattern 236C and the second insulating cover pattern 238C, the first insulating cover pattern 236C closer to the upper conductive pattern 234B of the bit line BL may have a first density, and the second insulating cover pattern 238C separated from the upper conductive pattern 234B of the bit line BL and having the first insulating cover pattern 236C therebetween may have a second density greater than the first density. The insulating thin film pattern 244C and the third insulating cover pattern 250C may have a second density similar to the density of the second insulating cover pattern 238C. In a first horizontal direction (X direction), the first insulating cover pattern 236C, the second insulating cover pattern 238C, the insulating thin film pattern 244C, and the third insulating cover pattern 250C may have substantially the same width. Unless otherwise indicated by the context or other statements, the term "substantially" may be used herein to emphasize this meaning. For example, items described as "substantially the same" or "substantially equal" may be exactly the same or equal, or may be the same or equal within acceptable variations that may occur, for example, due to manufacturing processes.

[0031] In one or more embodiments, the first insulating cap pattern 236C and the second insulating cap pattern 238C may include the same material as each other. In other embodiments, the first insulating cap pattern 236C and the second insulating cap pattern 238C may include different materials from each other. The first insulating cap pattern 236C may include a silicon nitride layer, a silicon carbonitride layer, or a combination thereof. The second insulating cap pattern 238C, the insulating thin film pattern 244C, and the third insulating cap pattern 250C may each include a silicon nitride layer. The thickness of the first insulating cap pattern 236C in the vertical direction (Z direction) may be smaller than the thickness of the second insulating cap pattern 238C in the vertical direction (Z direction). For example, the first insulating cap pattern 236C may have a thickness of about 20 Å to about 400 Å, and the thickness of the second insulating cap pattern 238C may be greater than the thickness of the first insulating cap pattern 236C. Terms such as "about" or "approximate" may reflect quantities, dimensions, orientations, or layouts that vary only in a minute relative manner and / or in a manner that does not significantly alter the operation, function, or structure of certain elements. For example, a range of "about 0.1 to about 1" may cover ranges of deviations of, for example, 0% - 5% near 0.1 and 0% to 5% near 1, especially if such deviations maintain the same effect as the listed range.

[0032] In one or more embodiments, the upper conductive pattern 234B may include a nitrogen atom diffusion region (i.e., a region doped with nitrogen atoms) in its upper region. The nitrogen atom diffusion region may be within a range from the interface between the upper conductive pattern 234B and the first insulating cap pattern 236C towards the substrate 210 to a partial thickness of the upper conductive pattern 234B. The thickness (length in the Z direction) of the nitrogen atom diffusion region may be about 0.01% to about 10% of the total thickness (length in the Z direction) of the upper conductive pattern 234B. For example, the nitrogen atom diffusion region may extend from the interface between the upper conductive pattern 234B and the first insulating cap pattern 236C to a thickness of about 5 Å to about 40 Å, or have a thickness of about 5 Å to about 40 Å in the upper conductive pattern 234B, but the thickness of the nitrogen atom diffusion region is not limited thereto.

[0033] In the nitrogen atom diffusion region, nitrogen (N) atoms can be in a diffused state without chemically bonding to other atoms included in the upper conductive pattern 234B. In one or more embodiments, when the upper conductive pattern 234B includes a tungsten (W) layer and the first insulating capping pattern 236C includes a silicon nitride layer, the nitrogen atom diffusion region in the upper conductive pattern 234B can include a tungsten (W) layer formed of tungsten (W) atoms, nitrogen (N) atoms distributed among the tungsten crystal structures included in the W layer (i.e., between the tungsten (W) atoms) without chemically bonding to the tungsten (W) atoms of the tungsten crystal structure of the W layer, and tungsten nitride particles diffused in the W layer. The tungsten nitride particles can include chemical bonds between W and N. In an exemplary embodiment, the nitrogen atom diffusion region can be the upper portion of the W layer, the upper portion of the W layer being doped with nitrogen (N) atoms and including tungsten nitride particles distributed within the upper portion of the W layer. The thickness of the first region (i.e., the nitrogen atom diffusion region) can be from about 0.01% to about 10% of the total thickness of the W layer.

[0034] The sidewalls of the plurality of bit lines BL and the sidewalls of the insulating capping structure CSC can be covered by a plurality of insulating spacers 252. The plurality of insulating spacers 252 can extend parallel to the plurality of bit lines BL in a second horizontal direction (Y direction). Each of the plurality of insulating spacers 252 can include an oxide layer, a nitride layer, an air spacer, or a combination thereof. In the specification, the term "air" can represent the atmosphere or a space including other gases that may be present during the manufacturing process.

[0035] A plurality of insulating barriers 254 and a plurality of conductive plugs 256 can be arranged in rows between the plurality of bit lines BL and between the plurality of insulating capping structures CSC in a second horizontal direction (Y direction). The plurality of insulating barriers 254 fill a plurality of recessed spaces 220R formed in the upper surface of the buried insulating layer 220, and each insulating barrier 254 can be arranged between two conductive plugs 256 spaced apart from each other in a second horizontal direction (Y direction). Opposite sidewalls of each of the plurality of conductive plugs 256 in a second horizontal direction (Y direction) can be covered by the plurality of insulating barriers 254. The plurality of conductive plugs 256 arranged in rows in a second horizontal direction (Y direction) can be insulated from each other by the plurality of insulating barriers 254. Each of the plurality of insulating barriers 254 can include a silicon nitride layer. The plurality of conductive plugs 256 can constitute Figure 3 the plurality of buried contacts BC shown in. One direct contact DC and a pair of conductive plugs 256 facing each other with the direct contact DC therebetween can be connected to different unit active regions A1 among the plurality of unit active regions A1.

[0036] Multiple metal silicide layers 258A and multiple conductive bonding pads LP may be formed on the multiple conductive plugs 256. The metal silicide layers 258A and the conductive bonding pads LP may be arranged to be stacked with the conductive plugs 256 in a vertical direction. Each of the multiple conductive bonding pads LP may be connected to the conductive plug 256 via the metal silicide layer 258A. The multiple conductive bonding pads LP may at least partially cover the upper surface of the third insulating cover pattern 250C to be vertically stacked with some of the multiple bit lines BL. The conductive plug 256, the metal silicide layer 258A, and the conductive bonding pad LP may constitute a contact structure CST, and the contact structure CST connects a capacitor lower electrode (not shown) formed on the conductive bonding pad LP to the cell active region A1.

[0037] The metal silicide layer 258A may include cobalt silicide, nickel silicide, or manganese silicide. Each of the multiple conductive bonding pads LP may include a conduction barrier layer 262 and a main conduction layer 264. The conduction barrier layer 262 may include Ti, TiN, or a combination thereof. The main conduction layer 264 may include a metal, a metal nitride, conductive polysilicon, or a combination thereof. For example, the main conduction layer 264 may include W. The multiple conductive bonding pads LP may have an island pattern shape in a plane. The multiple conductive bonding pads LP may be electrically insulated from each other by an insulating layer 270 that fills the insulating space 270S around each of the multiple conductive bonding pads LP. The insulating layer 270 may include a silicon nitride layer, a silicon oxide layer, or a combination thereof.

[0038] In the peripheral circuit region CORE / PERI, a gate structure PG may be formed on the substrate 210. The gate structure PG may include a gate dielectric layer 224, a gate electrode 240, and an insulating cover structure CSP that are sequentially stacked on the peripheral active region A2.

[0039] The gate dielectric layer 224 may include at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO), and a high-k dielectric layer having a dielectric constant greater than that of the silicon oxide layer. The gate electrode 240 may include a lower conductive pattern 230P, an intermediate conductive pattern 232P, and an upper conductive pattern 234P. The lower conductive pattern 230P, the intermediate conductive pattern 232P, and the upper conductive pattern 234P may respectively include the same materials as the lower conductive pattern 230B, the intermediate conductive pattern 232B, and the upper conductive pattern 234B included in the bit lines BL included in the cell array region MCA.

[0040] The insulating cap structure CSP may include a first insulating cap pattern 236P and a second insulating cap pattern 238P. In the insulating cap structure CSP, the bottom surface of the first insulating cap pattern 236P may contact the upper surface of the upper conductive pattern 234P of the gate electrode 240. The bottom surface of the second insulating cap pattern 238P may contact the upper surface of the first insulating cap pattern 236P. In the insulating cap structure CSP, the first insulating cap pattern 236P and the second insulating cap pattern 238P may have different densities from each other. In one or more embodiments, among the first insulating cap pattern 236P and the second insulating cap pattern 238P, similar to the first insulating cap pattern 236C in the cell array region MCA, the first insulating cap pattern 236P closer to the upper conductive pattern 234P of the gate electrode 240 may have a first density. Similar to the second insulating cap pattern 238C in the cell array region MCA, the second insulating cap pattern 238P separated from the upper conductive pattern 234P of the gate electrode 240 and having the first insulating cap pattern 236P therebetween may have a second density greater than the first density. In the horizontal direction parallel to the main surface 210M of the substrate 210, the width of the first insulating cap pattern 236P is substantially the same as the width of the second insulating cap pattern 238P.

[0041] In one or more embodiments, the first insulating cap pattern 236P and the second insulating cap pattern 238P may include the same material as each other. In another embodiment, the first insulating cap pattern 236P and the second insulating cap pattern 238P may have different materials from each other. The first insulating cap pattern 236P may include a silicon nitride layer, a silicon carbonitride layer, or a combination thereof. The second insulating cap pattern 238P may include a silicon nitride layer.

[0042] In one or more embodiments, the upper conductive pattern 234P of the gate electrode 240 may include a nitrogen atom diffusion region in a part of its upper region. The nitrogen atom diffusion region may extend in the upper conductive pattern 234P from the interface between the upper conductive pattern 234P of the gate electrode 240 and the first insulating cap pattern 236P toward the substrate 210 to a point in the thickness of the upper conductive pattern 234P. The thickness (length in the Z direction) of the nitrogen atom diffusion region may be about 0.01% to about 10% of the total thickness (length in the Z direction) of the upper conductive pattern 234P. For example, the nitrogen atom diffusion region may extend from the interface between the upper conductive pattern 234P and the first insulating cap pattern 236P to a thickness of about 5 Å to about 40 Å, or have a thickness of about 5 Å to about 40 Å in the upper conductive pattern 234P, but the thickness of the nitrogen atom diffusion region is not limited thereto.

[0043] In the nitrogen atom diffusion region, N atoms can be in a diffused state without chemically bonding to other atoms included in the upper conductive pattern 234P. In one or more embodiments, when the upper conductive pattern 234P includes a W layer and the first insulating capping pattern 236P includes a silicon nitride layer, the nitrogen atom diffusion region in the upper conductive pattern 234P can include a W layer formed of W atoms, N atoms distributed among the tungsten crystal structures included in the W layer (i.e., between W atoms) without chemically bonding to the W atoms of the tungsten crystal structure of the W layer, and tungsten nitride particles diffused in the W layer. The tungsten nitride particles can include chemical bonds between W and N.

[0044] The opposing sidewalls of the gate structure PG can be covered by the insulating spacer 242. The insulating spacer 242 can include an oxide layer, a nitride layer, or a combination thereof. The gate structure PG and the insulating spacer 242 can be covered by the insulating thin film 244. The insulating thin film 244 can include a silicon nitride layer. The interlayer insulating layer 246 filling the space around the gate structure PG can be formed on the insulating thin film 244. The interlayer insulating layer 246 can include Toray silicon nitride (TOSZ), but is not limited thereto. The gate structure PG, the insulating thin film 244, and the interlayer insulating layer 246 can be covered by the third insulating capping layer 250. The third insulating capping layer 250 can include a silicon nitride layer.

[0045] In the peripheral circuit region CORE / PERI, the contact space CS2 vertically penetrates the third insulating capping layer 250, the interlayer insulating layer 246, and the insulating thin film 244, and then extends into the peripheral active region A2 of the substrate 210. A plurality of conductive patterns CNP can be formed on the third insulating capping layer 250. The plurality of conductive patterns CNP can extend in various planar shapes on the third insulating capping layer 250. Each of the plurality of conductive patterns CNP can serve as a contact plug that extends vertically by passing through the third insulating capping layer 250, the interlayer insulating layer 246, and the insulating thin film 244 via the contact space CS2. Similar to the plurality of conductive bonding pads LP formed in the cell array region MCA, each of the plurality of conductive patterns CNP can include a diffusion barrier layer 262 and a main conductive layer 264. A metal silicide layer 258B can be between the peripheral active region A2 and each of the plurality of conductive patterns CNP. The metal silicide layer 258B can include cobalt silicide, nickel silicide, or manganese silicide.

[0046] FIG. 6A to FIG. 6C is a cross-sectional view showing an integrated circuit device 300 according to one or more embodiments. Fig. 6A and Figure 6B is a cross-sectional view showing an exemplary structure of a part of the cell array region MCA in the integrated circuit device 300, Figure 6Cis a cross-sectional view showing an exemplary structure of a part of a peripheral circuit region CORE / PERI in an integrated circuit device 300. A cell array region MCA of the integrated circuit device 300 may have a layout as shown in Figure 3 as follows. Fig. 6A shows a cross-section taken along line Figure 3 A-A'. Figure 6B shows a cross-section taken along line Figure 3 B-B'.

[0047] Figure 7 is a magnified cross-sectional view showing some elements in a dashed-line region “Q2” included in Fig. 6A .

[0048] Referring to FIG. 6A to FIG. 6C and Figure 7 , the integrated circuit device 300 has a structure similar to that of the integrated circuit device 200 shown above with reference to FIG. 4A to FIG. 4C and Figure 5 . The integrated circuit device 300 may include a plurality of insulating cover structures CSC3 covering a plurality of bit lines BL. The insulating cover structure CSC3 may have a structure similar to that of the insulating cover structure CSC shown with reference to Figure 4A and Figure 5 . However, the insulating cover structure CSC3 includes a first insulating cover pattern 336C instead of Figure 4A the first insulating cover pattern 236C of the insulating cover structure CSC.

[0049] The bottom surface of the first insulating cover pattern 336C may be in contact with the upper surface of the upper conductive pattern 234B. The bottom surface of the second insulating cover pattern 238C may be in contact with the upper surface of the first insulating cover pattern 336C.

[0050] In each of the plurality of insulating cover structures CSC3, the first insulating cover pattern 336C and the second insulating cover pattern 238C may have different densities from each other. In one or more embodiments, the first insulating cover pattern 336C may have a first density, and the second insulating cover pattern 238C may have a second density greater than the first density.

[0051] In a first horizontal direction (X direction), the first insulating cap pattern 336C and the second insulating cap pattern 238C may have different minimum widths from each other. That is, in the first horizontal direction (X direction), the minimum width of the first insulating cap pattern 336C is smaller than the minimum width of the second insulating cap pattern 238C. Due to the width difference between the first insulating cap pattern 336C and the second insulating cap pattern 238C in the first horizontal direction (X direction), an undercut region may be formed under the second insulating cap pattern 238C near the point where the sidewall of the first insulating cap pattern 336C and the bottom surface of the second insulating cap pattern 238C meet each other. The detailed structure of the first insulating cap pattern 336C is similar to that of the first insulating cap pattern 236C described with reference to Figure 4A , Figure 4B and Figure 5 .

[0052] The sidewalls of the plurality of bit lines BL and the sidewalls of the insulating cap structure CSC3 may be covered by a plurality of insulating spacers 352. Each of the plurality of insulating spacers 352 may include a protruding sidewall 352S protruding toward the first insulating cap pattern 336C. The detailed structure of the plurality of insulating spacers 352 is similar to the detailed structure of the plurality of insulating spacers 252 described above with reference to Figure 4A , Figure 4B and Figure 5 .

[0053] A plurality of conductive plugs 256 and a plurality of insulating fences 354 may be arranged in rows between the plurality of bit lines BL and between the plurality of insulating cap structures CSC3 in a second horizontal direction (Y direction). Each of the plurality of insulating fences 354 may include a protruding sidewall 354S protruding toward the first insulating cap pattern 336C. The detailed structure of the plurality of insulating fences 354 is similar to the detailed structure of the plurality of insulating fences 254 described above with reference to Figure 4A , Figure 4B and Figure 5 .

[0054] A plurality of metal silicide layers 258A and a plurality of conductive bonding pads LP3 may be formed on the plurality of conductive plugs 256. The conductive bonding pads LP3 may be stacked with the conductive plugs 256 and the metal silicide layers 258A in a vertical direction. The conductive plugs 256, the metal silicide layers 258A, and the conductive bonding pads LP3 may constitute a contact structure CST3 that connects a capacitor lower electrode (not shown) formed on the conductive bonding pads LP3 to the unit active region A1. A part of the contact structure CST3 may include a protruding sidewall protruding toward the first insulating cap pattern 336C. For example, as Fig. 6AAs shown, each of the plurality of conductive bonding pads LP3 may include a protruding sidewall LP3S protruding toward the first insulating cover pattern 336C. Each of the plurality of conductive bonding pads LP3 may include a conductive barrier layer 362 and a main conductive layer 364. Both the conductive barrier layer 362 and the main conductive layer 364 may include protruding sidewalls protruding toward the first insulating cover pattern 336C at portions corresponding to the protruding sidewall LP3S. The conductive bonding pad LP3 includes protruding sidewalls LP3S at opposite sides in the first horizontal direction (X direction), and thus, the conductive bonding pad LP3 may have a non-uniform width. For example, the conductive bonding pad LP3 may have a first portion having a first width and a second portion having a second width. The first portion is located between two adjacent first insulating cover patterns 336C, and the second portion is located between two adjacent second insulating cover patterns 238C. The first width and the second width are measured in the first horizontal direction (X direction). The first width may be larger than the second width. Accordingly, the volume of the conductive bonding pad LP3 located between two adjacent first insulating cover patterns 336C may be larger than the volume of the conductive bonding pad LP3 that does not include the protruding sidewall LP3S. As described above, since the conductive bonding pad LP3 includes an enlarged volume portion caused by the protruding sidewall LP3S, the resistance of the conductive bonding pad LP3 may be reduced.

[0055] In Fig. 6A the sidewall of the conductive bonding pad LP3 in the contact structure CST3 faces the first insulating cover pattern 336C, and accordingly, the protruding sidewall LP3S is formed on the conductive bonding pad LP3, but one or more embodiments are not limited thereto. For example, when the upper surface of the conductive plug 256 included in the contact structure CST3 has a level higher than the level shown in Fig. 6A and the sidewall of the conductive plug 256 faces the first insulating cover pattern 336C, the conductive plug 256 may have a protruding sidewall protruding toward the first insulating cover pattern 336C.

[0056] The detailed structure of the plurality of conductive bonding pads LP3 is similar to the detailed structure of the plurality of conductive bonding pads LP described above with reference to Figure 4A 、 Figure 4B and Figure 5 The detailed structure of the conductive barrier layer 362 and the main conductive layer 364 is similar to the detailed structure of the conductive barrier layer 262 and the main conductive layer 264 described above with reference to Figure 4A 、 Figure 4B and Figure 5 described.

[0057] In the peripheral circuit region CORE / PER1, a gate structure PG3 may be formed on the peripheral active region A2. The gate structure PG3 includes an insulating cover structure CSP3. The insulating cover structure CSP3 may have the same as Figure 4CThe structure of the insulating cover structure CSP shown is similar to the structure. However, the insulating cover structure CSP3 includes a first insulating cover pattern 336P instead of Figure 4C the first insulating cover pattern 236P of

[0058] In the horizontal direction, the minimum width of the first insulating cover pattern 336P is smaller than the minimum width of the second insulating cover pattern 238P. Due to the width difference between the first insulating cover pattern 336P and the second insulating cover pattern 238P in the horizontal direction, an undercut region can be formed under the second insulating cover pattern 238P near the point where the sidewall of the first insulating cover pattern 336P and the bottom surface of the second insulating cover pattern 238P meet each other. The detailed structure of the first insulating cover pattern 336P is similar to that of the first insulating cover pattern 236P described with reference to Figure 4C the structure of the first insulating cover pattern 236P described with reference to

[0059] The opposite sidewalls of the gate structure PG3 can be covered by insulating spacers 342. The insulating spacers 342 can include protruding sidewalls 342S protruding toward the first insulating cover pattern 336P. The detailed structure of the insulating spacers 342 is similar to the detailed structure of the insulating spacers 242 described above with reference to Figure 4C the structure of the insulating spacers 242 described above with reference to

[0060] FIG. 8A to FIG. 8Q is a cross-sectional view for describing a method of manufacturing an integrated circuit device according to one or more embodiments in a processing order. The method of manufacturing the integrated circuit device 200 shown with reference to FIG. 8A to FIG. 8Q will be described below with reference to FIG. 4A to FIG. 4C In FIG. 8A to FIG. 8Q (a) represents a cross-sectional view taken along line A-A' of Figure 3 according to the manufacturing order, and (b) represents a cross-sectional view of a part of the peripheral circuit region CORE / PERI according to the processing order.

[0061] With reference to Fig. 8A In a substrate 210 having a cell array region MCA and a peripheral circuit region CORE / PERI, a plurality of isolation trenches T1 are formed and a plurality of isolation layers 212 filling the plurality of isolation trenches T1 are formed. The plurality of isolation layers 212 can define a plurality of cell active regions A1 in the cell array region MCA of the substrate 210, and define peripheral active regions A2 in the peripheral circuit region CORE / PERI.

[0062] A plurality of word line trenches T2 extending parallel to each other can be formed in the substrate 210 in the cell array region MCA (see Figure 4B). To form a plurality of word line trenches T2 having steps on their bottom surfaces, the isolation layer 212 and the substrate 210 are etched through a separate etching process to distinguish the etching depth of the isolation layer 212 from the etching depth of the substrate 210. After cleaning the resulting structure having the plurality of word line trenches T2, a plurality of gate dielectric layers 216, a plurality of gate lines 218, and a plurality of buried insulating layers 220 can be sequentially formed in the plurality of word line trenches T2. Impurity ions are implanted into opposite sides of the plurality of gate lines 218 in the plurality of unit active regions A1 to form a plurality of source / drain regions on the plurality of unit active regions A1. In one or more embodiments, the plurality of source / drain regions can be formed before the plurality of gate lines 218 are formed.

[0063] After that, a buffer layer 222 is formed on the substrate 210 in the cell array region MCA, and a gate dielectric layer 224 is formed on the substrate 210 in the peripheral circuit region CORE / PERI.

[0064] Referring to Figure 8B , a lower conductive layer 230 is formed on the buffer layer 222 in the cell array region MCA and on the gate dielectric layer 224 in the peripheral circuit region CORE / PERI. The lower conductive layer 230 can include doped polysilicon.

[0065] Referring to Figure 8C , a mask pattern M21 is formed on the lower conductive layer 230. After that, the lower conductive layer 230 exposed through the opening M21O of the mask pattern M21 is etched in the cell array region MCA. Then, the exposed portion of the substrate 210 and a part of the isolation layer 212 as an etching result are etched to form a direct contact hole DCH exposing the unit active region A1 of the substrate 210. The mask pattern M21 can include an oxide layer, a nitride layer, or a combination thereof. A lithography process can be performed to form the mask pattern M21.

[0066] Referring to Fig.8D , the mask pattern M21 is removed (see Figure 8C ), and a direct contact DC is formed in each of the direct contact holes DCH.

[0067] In an exemplary process for forming the direct contact DC, a conductive layer is formed in the direct contact hole DCH and on the upper portion of the lower conductive layer 230 to a thickness sufficient to fill the direct contact hole DCH, and the conductive layer can be etched back only to remain in the direct contact hole DCH. The conductive layer can include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof.

[0068] Referring to Fig. 8E, an intermediate conductive layer 232 and an upper conductive layer 234 are sequentially formed on the lower conductive layer 230 and the direct contact DC in the cell array region MCA and the peripheral circuit region CORE / PERI. Each of the intermediate conductive layer 232 and the upper conductive layer 234 may include TiN, TiSiN, W, tungsten silicide, or a combination thereof. In one or more embodiments, the intermediate conductive layer 232 includes TiN, TiSiN, or a combination thereof, and the upper conductive layer 234 may include W.

[0069] Referring to Figure 8F , a first insulating capping layer 236 is formed on the upper conductive layer 234 in the cell array region MCA and the peripheral circuit region CORE / PERI.

[0070] To form the first insulating capping layer 236, a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process may be performed at a relatively low first temperature. The first temperature may be selected in the range of about 500 °C to about 700 °C. For example, the first temperature may be selected in the range of about 600 °C to about 650 °C. The first insulating capping layer 236 may include a silicon nitride layer. In this case, in the CVD or ALD process for forming the first insulating capping layer 236, a gas including SiH 4 , Si 2 Cl 2 H 2 , SiH 6 , Si 2 H 6 , Si 3 H 8 or a combination thereof is used as a Si-containing precursor, and a gas including NH 3 , N 2 , NO, N 2 O or a combination thereof is used as an N-containing precursor. However, one or more embodiments are not limited to the above examples.

[0071] Since the deposition process is performed at a relatively low first temperature when forming the first insulating capping layer 236, the formation of WN due to the reaction between the N-containing (N) precursor and the metal (e.g., W) included in the upper conductive layer 234 or the undesired diffusion of N atoms from the first insulating capping layer 236 to the upper conductive layer 234 during the formation of the first insulating capping layer 236 can be suppressed. Therefore, the formation of an insulating metal nitride (e.g., WN) between the upper conductive layer 234 and the first insulating capping layer 236 can be suppressed or reduced.

[0072] In one or more embodiments, during the formation of the first insulating capping layer 236, N atoms included in the first insulating capping layer 236 may diffuse into the upper conductive layer 234. As a result, after the first insulating capping layer 236 is formed, a nitrogen atom diffusion region is formed above a part of the thickness in the upper conductive layer 234 from the interface between the first insulating capping layer 236 and the upper conductive layer 234. The detailed structure of the nitrogen atom diffusion region is described above with reference to FIG. 4A to FIG. 4C The detailed structure of the nitrogen atom diffusion region is described.

[0073] Referring to Figure 8G , a second insulating capping layer 238 is formed on the first insulating capping layer 236 in the cell array region MCA and the peripheral circuit region CORE / PERI.

[0074] To form the second insulating capping layer 238, a CVD or ALD process may be performed at a second temperature that is relatively high. The second temperature is higher than the first temperature. For example, the second temperature may be selected in the range of about 700 °C to about 800 °C. The second insulating capping layer 238 may include a silicon nitride layer. In this case, the method of forming the second insulating capping layer 238 is the same as the method of forming the first insulating capping layer 236 described above with reference to Figure 8F The method of forming the first insulating capping layer 236 is described.

[0075] The process of forming the first insulating capping layer 236 described above with reference to Figure 8F And the process of forming the second insulating capping layer 238 described above with reference to Figure 8G The process of forming the second insulating capping layer 238 described above may be performed in-situ or non-in-situ. In an embodiment, in order to continuously form the first insulating capping layer 236 and the second insulating capping layer 238 in-situ in the same chamber, the first insulating capping layer 236 and the second insulating capping layer 238 may be formed by a CVD process respectively, and the deposition temperature of the first insulating capping layer 236 may be lower than the deposition temperature of the second insulating capping layer 238. In another embodiment, in order to form the first insulating capping layer 236 and the second insulating capping layer 238 non-in-situ, the first insulating capping layer 236 may be formed by an ALD process at a relatively low first temperature, and the second insulating capping layer 238 may be formed by a CVD process at a relatively high second temperature.

[0076] Since the deposition temperature of the second insulating capping layer 238 is higher than the deposition temperature when forming the first insulating capping layer 236, the density of the second insulating capping layer 238 may be greater than the density of the first insulating capping layer 236.

[0077] Referring to Figure 8H, in the peripheral circuit region CORE / PERI, the gate dielectric layer 224, the lower conductive layer 230, the intermediate conductive layer 232, the upper conductive layer 234, the first insulating capping layer 236, and the second insulating capping layer 238 are patterned by using a mask pattern (not shown) as an etching mask, and then a gate structure PG including the gate dielectric layer 224, the gate electrode 240, the first insulating capping pattern 236P, and the second insulating capping pattern 238P is formed in the peripheral circuit region CORE / PERI. The gate electrode 240 may include a lower conductive pattern 230P, an intermediate conductive pattern 232P, and an upper conductive pattern 234P.

[0078] Referring to Figure 8I , insulating spacers 242 are formed on opposite sidewalls of the gate structure PG in the peripheral circuit region CORE / PERI, and an ion implantation process is performed to form source / drain regions in the peripheral active region A2 at opposite sides of the gate structure PG.

[0079] After that, an insulating thin film 244 is formed to completely cover the exposed surfaces of the cell array region MCA and the peripheral circuit region CORE / PERI. The insulating thin film 244 may contact the upper surface of the second insulating capping layer 238 in the cell array region MCA and may contact the upper surface of the second insulating capping pattern 238P in the peripheral circuit region CORE / PER. The insulating thin film 244 may be formed by a process the same as or similar to the process of forming the second insulating capping layer 238 referred to above Figure 8G described.

[0080] In the peripheral circuit region CORE / PERI, an interlayer insulating layer 246 is formed to fill the space around the gate structure PG and the insulating thin film 244. The interlayer insulating layer 246 may have a planarized upper surface.

[0081] Referring to Figure 8J , a third insulating capping layer 250 is formed on the insulating thin film 244 and the planarized interlayer insulating layer 246 in the cell array region MCA and the peripheral circuit region CORE / PERI. The third insulating capping layer 250 may be formed by a process the same as or similar to the process of forming the second insulating capping layer 238 referred to above Figure 8G described.

[0082] Referring to Figure 8K, in a state where the third insulating capping layer 250 is covered with a mask pattern M22 in the peripheral circuit region CORE / PERI, the third insulating capping layer 250, the insulating thin film 244, the second insulating capping layer 238, and the first insulating capping layer 236 are patterned by a photolithography process in the cell array region MCA, and then a plurality of insulating capping structures CSC are formed, each of which includes a first insulating capping pattern 236C, a second insulating capping pattern 238C, an insulating thin film pattern 244C, and a third insulating capping pattern 250C that are sequentially stacked on the upper conductive layer 234.

[0083] Refer to Figure 8L , in a state where the third insulating capping layer 250 is covered with a mask pattern M22 in the peripheral circuit region CORE / PERI, the upper conductive layer 234, the intermediate conductive layer 232, and the lower conductive layer 230 are etched in the cell array region MCA by using the plurality of insulating capping structures CSC as an etching mask, and then a plurality of bit lines BL are formed, each of which includes a lower conductive pattern 230B, an intermediate conductive pattern 232B, and an upper conductive pattern 234B. The resulting structure having the plurality of bit lines BL can be cleaned and dried. In one or more embodiments, the cleaning process of the resulting structure having the plurality of bit lines BL can be performed by using diluted HF (DHF). The drying process can be performed by using isopropyl alcohol (IPA). After forming the plurality of bit lines BL, a line space LS can be reserved between the bit lines BL. Due to the etching process for forming the plurality of bit lines BL, the height of the third insulating capping pattern 250C in the insulating capping structure CSC can be reduced.

[0084] Refer to Figure 8M , a plurality of insulating spacers 252 are formed to cover the sidewalls of the plurality of bit lines BL and the sidewalls of the plurality of insulating capping structures CSC. The plurality of insulating spacers 252 can fill the direct contact holes DCH around the direct contacts DC.

[0085] Refer to Figure 8N , in a state where the third insulating capping layer 250 is covered with a mask pattern M22 in the peripheral circuit region CORE / PERI, a plurality of insulating fences 254 are respectively formed between the plurality of bit lines BL in the cell array region MCA (see Figure 4B), to divide the line space LS into a plurality of contact spaces CS1. A plurality of insulating fences 254 can all be stacked with the gate lines 218 in the vertical direction. One line space LS can be divided by a plurality of insulating fences 254 such that the plurality of contact spaces CS1 can all have a cylindrical shape. Thereafter, the structures exposed through the plurality of contact spaces CS1 can be partially removed to form a plurality of recessed spaces RS, and each recessed space RS exposes the unit active region A1 of the substrate 210 located between the bit lines BL. While forming the plurality of insulating fences 254 and the plurality of recessed spaces RS, the third insulating cover pattern 250C and the insulating spacers 252 are exposed to various etching process atmospheres, and the heights of the third insulating cover pattern 250C and the insulating spacers 252 can be further reduced.

[0086] Referring to Fig.8O , in a state where the third insulating cover layer 250 is covered with a mask pattern M22 in the peripheral circuit region CORE / PERI (see Figure 8M ), a plurality of conductive plugs 256 are formed in the cell array region MCA, wherein the plurality of conductive plugs 256 respectively fill the plurality of recessed spaces RS between the bit lines BL and partially fill the contact spaces CS1 between the bit lines BL.

[0087] The mask pattern M22 (see Figure 8N ) is removed to expose the third insulating cover layer 250 in the peripheral circuit region CORE / PERI. Thereafter, in a state where a mask pattern (not shown) covers the cell array region MCA, the third insulating cover layer 250, the interlayer insulating layer 246, and the insulating thin film 244 are etched in the peripheral circuit region CORE / PERI to form a plurality of contact spaces CS2 exposing the peripheral active region A2 on the substrate 210. Thereafter, the mask pattern (not shown) covering the cell array region MCA is removed, and then, a metal silicide layer 258A is formed on the conductive plugs 256 exposed through the plurality of contact spaces CS1 in the cell array region MCA, and a metal silicide layer 258B is formed on the surface of the peripheral active region A2 exposed through the plurality of contact spaces CS2 in the peripheral circuit region CORE / PERI. In one or more embodiments, the metal silicide layers 258A and 258B can be formed simultaneously. In another embodiment, the metal silicide layers 258A and 258B can be formed by separate processes.

[0088] Referring to Figure 8P , a conductive layer 260 covers the exposed surfaces on the substrate 210 in the cell array region MCA and the peripheral circuit region CORE / PERI. The conductive layer 260 can include a conduction barrier layer 262 and a main conductive layer 264.

[0089] Referring to Figure 8Q, the conductive layer 260 is patterned in the cell array region MCA and the peripheral circuit region CORE / PERI, and then a plurality of conductive bonding pads LP are formed from the conductive layer 260 in the cell array region MCA and a plurality of conductive patterns CNP are formed from the conductive layer 260 in the peripheral circuit region CORE / PERI. The plurality of conductive bonding pads LP may be disposed on the metal silicide layer and may be partially superimposed on the plurality of bit lines BL in the vertical direction.

[0090] According to the method of manufacturing the integrated circuit device 200 described above with reference to FIG. 8A to FIG. 8Q When forming the plurality of insulating cover structures CSC covering the plurality of bit lines BL, the first insulating cover layer 236 directly on the bit lines BL in the insulating cover structure CSC is formed at a relatively low temperature to suppress or reduce the formation of an undesired insulating metal nitride layer at the interface between the plurality of bit lines BL and the insulating cover structure CSC. Accordingly, an increase in the resistance of the plurality of bit lines BL can be reduced.

[0091] 9A to 9C is a cross-sectional view for describing a method of manufacturing an integrated circuit device 300 according to one or more embodiments in a processing order. Hereinafter, reference will be made to 9A to 9C Describe the manufacturing with reference to FIG. 6A to FIG. 6C The method of manufacturing the integrated circuit device 300 shown. In 9A to 9C , (a) represents a cross-sectional view taken along line A-A' of Figure 3 in accordance with the manufacturing order, and (b) represents a cross-sectional view of a part of the peripheral circuit region CORE / PERI in accordance with the processing order.

[0092] With reference to Fig. 9A , in the peripheral circuit region CORE / PERI, a gate structure PG3 including a gate dielectric layer 224, a gate electrode 240, a first insulating cover pattern 236P, and a second insulating cover pattern 238P is formed in the same manner as described above with reference to FIG. 8A to FIG. 8H . Thereafter, the exposed sidewalls of the first insulating cover pattern 236P are partially removed by a selective etching process using the difference in density between the first insulating cover pattern 236P and the second insulating cover pattern 238P, and then a first insulating cover pattern 336P having a minimum width smaller than the minimum width of the second insulating cover pattern 238P is formed. An etching agent such as DHF may be used to perform the selective etching process for forming the first insulating cover pattern 336P.

[0093] With reference to Fig. 9B , according to the manufacturing process described above with reference to FIG. 8I to FIG. 8L The resulting structure of Fig. 9A is subjected to a process for forming a plurality of insulating cover structures CSC and a plurality of bit lines BL in the cell array region MCA. However, in an embodiment, as described above with reference to Figure 8I In the described process, an insulating spacer 342 is formed having a protruding sidewall 342S protruding toward the first insulating cover pattern 336P.

[0094] Thereafter, in the cell array region MCA, the exposed sidewall of the first insulating cover pattern 236C is partially removed Figure 8K by a selective etching process to form a first insulating cover pattern 336C, the selective etching process utilizing Figure 8K the difference between the density of the first insulating cover pattern 236C and the densities of the second insulating cover pattern 238C, the insulating thin film pattern 244C, and the third insulating cover pattern 250C in the insulating cover structure CSC. The first insulating cover pattern 336C has a minimum width smaller than the minimum width of the second insulating cover pattern 238C. An etchant such as DHF can be used to perform the selective etching process for forming the first insulating cover pattern 336C.

[0095] Referring to Fig. 9C , the process described above can be performed on the Fig. 9B resulting structure. However, instead of the Figure 8M multiple insulating spacers 252, in an embodiment, multiple insulating spacers 352 can be formed having a protruding sidewall 352S protruding toward the first insulating cover pattern 336C. Figure 8M

[0096] Thereafter, the process shown in Fig. 9C is performed on the resulting structure to fabricate the Figures 8N to 8Q integrated circuit device 300 shown in FIG. 6A to FIG. 6C .

[0097] According to the method of manufacturing the integrated circuit device 300 described above with reference to 9A to 9C , when forming multiple insulating cover structures CSC3 covering multiple bit lines BL, the first insulating cover pattern 336C in the insulating cover structure CSC3 (where the first insulating cover pattern 336C is in contact with the bit line BL) is obtained from a film formed at a relatively low temperature. Thus, formation of an undesired insulating metal nitride layer at the interface between the multiple bit lines BL and the insulating cover structure CSC3 can be suppressed or reduced, and an increase in the resistance of the multiple bit lines BL can be prevented. Further, in the insulating cover structure CSC3, the sidewall profile of the insulating cover structure CSC3 can be optimized by utilizing the difference between the density of the first insulating cover pattern 336C and the density of the second insulating cover pattern 238C. Thus, the volume of multiple conductive structures (e.g., multiple conductive bonding pads LP3) between the bit lines BL can be increased to suppress an increase in the resistance of the multiple conductive structures and improve the reliability of the integrated circuit device.

[0098] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A semiconductor device, comprising: a substrate; bit lines on the substrate, the bit lines extending in a first direction parallel to the top surface of the substrate and including a metal layer; an insulating cap structure on the bit lines, the insulating cap structure including a first insulating cap pattern, a second covering insulating pattern on the first insulating cap pattern, a third insulating cap pattern on the second insulating cap pattern, and a fourth insulating cap pattern on the third insulating cap pattern; contact plugs arranged adjacent to the bit lines; bonding pads arranged on the contact plugs and extending on the insulating cap structure, the bonding pads including a first portion and a second portion on the first portion; and bit line spacers arranged between the bit lines and the contact plugs and extending on one side of the insulating cap structure, wherein, the bottom surface of the first insulating cap pattern of the insulating cap structure contacts the metal layer of the bit line, the top surface of the fourth insulating cap pattern of the insulating cap structure contacts the bottom surface of the second portion of the bonding pad.

2. The semiconductor device according to claim 1, wherein, the bonding pad includes a barrier layer and a conductive layer.

3. The semiconductor device according to claim 1, wherein, the top surface of the bit line spacer contacts the bottom surface of the second portion of the bonding pad.

4. The semiconductor device according to claim 1, wherein, the bit line spacer includes an oxide and / or a nitride.

5. The semiconductor device according to claim 1, wherein, the lower width of the first portion of the bonding pad in a second direction is greater than the upper width of the contact plug in the second direction, the second direction being parallel to the top surface of the substrate and perpendicular to the first direction.

6. The semiconductor device according to claim 1, wherein, the top surface of the first portion of the bonding pad is substantially coplanar with the top surface of the fourth insulating cap pattern of the insulating cap structure and / or the top surface of the bit line spacer.

7. The semiconductor device according to claim 1, wherein, each of the first insulating cap pattern to the fourth insulating cap pattern of the insulating cap structure includes silicon nitride.

8. The semiconductor device according to claim 1, wherein, the metal layer of the bit line includes tungsten (W).

9. The semiconductor device according to claim 1, wherein, the metal layer of the bit line includes nitrogen.

10. The semiconductor device according to claim 1, wherein, the bit line spacer contacts the side surfaces of each of the first insulating cap pattern to the fourth insulating cap pattern of the insulating cap structure.

11. A semiconductor device, comprising: a substrate including a cell region and a peripheral region; cell conductive lines arranged in the cell region of the substrate and including a first metal layer; a cell insulating cap structure on the cell conductive lines; peripheral conductive lines arranged in the peripheral region of the substrate and including a second metal layer; a peripheral insulating cap structure on the peripheral conductive lines; a first wiring arranged on one side of the cell insulating cap structure and extending on the top surface of the cell insulating cap structure; and a second wiring on the peripheral insulating cap structure, wherein, the cell insulating cap structure includes: a first cell insulating cap pattern; a second cell insulating cap pattern on the first cell insulating cap pattern; a third cell insulating cap pattern on the second cell insulating cap pattern; and a fourth cell insulating cap pattern on the third cell insulating cap pattern, Among them, the first unit insulating cover pattern of the unit insulating cover structure contacts the first metal layer of the unit conductive wire, and the fourth unit insulating cover pattern of the unit insulating cover structure contacts the first wiring, and Among them, the peripheral insulating cover structure includes: a first peripheral insulating cover pattern; a second peripheral insulating cover pattern on the first peripheral insulating cover pattern; a third peripheral insulating cover pattern on the second peripheral insulating cover pattern; and a fourth peripheral insulating cover pattern on the third peripheral insulating cover pattern, Among them, the first peripheral insulating cover pattern of the peripheral insulating cover structure contacts the second metal layer of the peripheral conductive wire, and the fourth peripheral insulating cover pattern of the peripheral insulating cover structure contacts the second wiring.

12. The semiconductor device according to claim 11, Among them, Each of the first to fourth unit insulating cover patterns of the unit insulating cover structure includes silicon nitride, Each of the first to fourth peripheral insulating cover patterns of the peripheral insulating cover structure includes silicon nitride.

13. The semiconductor device according to claim 11, Among them, The first wiring includes the same material as that of the second wiring.

14. The semiconductor device according to claim 11, further including: A unit conductive wire spacer between the unit insulating cover structure and the first wiring, Among them, the unit conductive wire spacer contacts the first to fourth unit insulating cover patterns of the unit insulating cover structure.

15. A semiconductor device, including: A substrate including a device isolation layer defining a first active region and a second active region; A bit line structure on the first active region of the substrate, the bit line structure including a conductive wire pattern and an insulating cover pattern on the conductive wire pattern, and the conductive wire pattern includes a metal layer; A contact plug arranged adjacent to the bit line structure and arranged on the second active region and the device isolation layer; A bonding pad arranged on the contact plug and extending on the insulating cover pattern of the bit line structure; And A bit line spacer arranged between the contact plug and the conductive wire pattern of the bit line structure and extending on one side of the insulating cover pattern of the bit line structure, Among them, the insulating cover pattern of the bit line structure includes: a first insulating cover pattern; a second insulating cover pattern on the first insulating cover pattern; a third insulating cover pattern on the second insulating cover pattern; and a fourth insulating cover pattern on the third insulating cover pattern, Among them, the first insulating cover pattern of the insulating cover pattern of the bit line structure contacts the metal layer of the conductive wire pattern of the bit line structure, The fourth insulating cover pattern of the insulating cover pattern of the bit line structure contacts the bonding pad, The width of the lower part of the bonding pad is greater than the width of the upper part of the contact plug, and The bit line spacer contacts the side surfaces of each of the first to fourth insulating cover patterns of the insulating cover pattern of the bit line structure.

16. The semiconductor device according to claim 15, Among them, The bit line spacer includes oxide and / or nitride.

17. The semiconductor device according to claim 15, Among them, The bonding pad includes a barrier layer and a conductive layer.

18. The semiconductor device according to claim 15, Among them, Each of the first to fourth insulating cover patterns of the insulating cover pattern of the bit line structure includes silicon nitride.

19. The semiconductor device according to claim 15, wherein, the top surface of the bit line spacer contacts the bonding pad.

20. The semiconductor device according to claim 15, wherein, the metal layer of the conductive wire pattern of the bit line structure includes tungsten (W) and / or nitrogen (N).

Images