Semiconductor structure and forming method thereof

Abstract

According to the semiconductor structure and the forming method thereof, in the semiconductor structure, the inclined side wall of a transition part and the top of a doped region in a third region form a convex corner, a floating gate surrounds the doped region in the convex corner, and when the semiconductor structure is subjected to write-in operation, according to the principle of point discharge, the doped region in the convex corner is formed by the floating gate. The electric field intensity between the doped region of the tip region in the convex corner and the floating gate is large, electrons in the doped region are easy to enter the floating gate, and the write-in performance of the semiconductor structure is improved. The inclined side wall of the transition part and the top of the doped region in the first region form a concave corner, the doped region surrounds the floating gate in the concave corner, and when the semiconductor structure is erased, according to the point discharge principle, the electric field intensity between the floating gate in the tip region in the concave corner and the doped region is relatively high, so that the erasure effect of the semiconductor structure is improved. And electrons in the floating gate easily enter the doped region, so that the erasing performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] Non-volatile memory is a storage technology that can retain data even after power is turned off. Non-volatile memory plays an important role in modern technology and life. Its importance is reflected in the following aspects: Data persistence: Non-volatile memory ensures that data is retained even after power is turned off, preventing data loss and ensuring the reliability of the system. High-speed reading and writing: Non-volatile memory such as flash memory provides fast data reading and writing speeds, improving the performance and response capabilities of devices. Large-capacity storage: Modern non-volatile memory can provide huge storage capacities to meet the growing data storage needs. Low power consumption: Compared with volatile memory, non-volatile memory generally has lower power consumption, which helps to extend battery life and reduce energy consumption.

[0003] EEPROM is a type of non-volatile memory. An EEPROM device has multiple cell storages inside. Each cell can be programmed and erased separately. Usually, each EEPROM cell includes a stacked gate (including a floating gate) and a select transistor. During operation, the select transistor will select a single EEPROM cell to be erased or programmed. The stacked gate is the transistor in each cell that actually performs the erase and programming operations. Programming and erasing the stacked gate utilize the well-known Fowler-Nordheim tunneling phenomenon to store positive or negative charges in the floating gate of the stacked gate respectively. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, and to optimize the electrical performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; doping a partial region of the substrate to form a doped region, the doped region including a first region, a second region, and a third region arranged in sequence; thinning the doped regions of the first region and the second region so that the overall thinned doped region is in a stepped shape, wherein the top of the doped region in the thinned first region is lower than the top of the doped region in the third region, the doped region in the second region is etched into a transition portion with inclined sidewalls, and the bottom end of the inclined sidewall of the transition portion is connected to the top of the doped region in the first region, and the top end of the inclined sidewall of the transition portion is connected to the top of the doped region in the third region; after performing the thinning process, a stacked gate is formed to conformally cover the doped region, and the stacked gate includes: a floating gate, a gate dielectric layer located on the floating gate, and a control gate located on the gate dielectric layer.

[0006] Optionally, a dry etching process is used to thin the doped regions of the first region and the second region.

[0007] Optionally, the process parameters of the dry etching include: the etching gas includes CF 4 , HBr, and O 2 or one or more of them, the bias power is 200 W to 1000 W, and the chamber pressure is 10 mTorr to 50 mTorr.

[0008] Optionally, in the step of thinning the doped regions of the first region and the second region, the distance from the top of the doped region in the first region to the top of the doped region in the third region is 200 angstroms to 500 angstroms.

[0009] Optionally, in the step of performing the thinning process, the included angle between the top of the doped region in the first region and the inclined sidewall in the transition portion is 90° to 120°, and the included angle between the top of the doped region in the third region and the inclined sidewall in the transition portion is 90° to 120°.

[0010] Optionally, in the step of thinning the doped regions of the first region and the second region, the included angle formed by the inclined sidewall in the transition portion and the top of the doped region in the first region is equal to the included angle formed by the inclined sidewall in the transition portion and the top of the doped region in the third region.

[0011] Optionally, the method for forming the semiconductor structure further includes: after thinning the doped regions of the first region and the second region and before forming the stacked gate, removing a partial thickness of the doped regions in the first region and the second region.

[0012] Optionally, the step of removing a partial thickness of the doped regions in the first region and the second region includes: performing a high-temperature oxidation treatment on the surfaces of the doped regions in the first region and the second region to form an oxide layer; after performing the high-temperature oxidation treatment, removing the oxide layer.

[0013] Optionally, during the process of removing a partial thickness of the doped regions in the first region and the second region, a partial thickness of the doped region in the third region is also removed.

[0014] Optionally, in the step of removing a partial thickness of the doped regions in the first region and the second region, the thickness of the doped regions removed from the first region and the second region is 80 angstroms to 110 angstroms.

[0015] Optionally, in the step of forming a stacked gate on the doped region, the stacked gate is also formed on the substrate in partial regions on both sides of the doped region.

[0016] Optionally, during the process of thinning the doped regions in the first region and the second region, the substrate on the side of the first region facing away from the second region is also thinned; in the step of forming the stacked gate, a select gate is also formed on the substrate of the first region facing away from the second region, and the select gate is spaced apart from the stacked gate.

[0017] Optionally, the method for forming the semiconductor structure further includes: after forming the stacked gate and the select gate, forming source / drain doped regions in the substrate between the select gate and the stacked gate, and the source / drain doped regions are adjacent to the doped region.

[0018] An embodiment of the present invention provides a semiconductor structure, including: a substrate; a doped region located in a partial region of the substrate, the doped region being in a stepped shape, and the doped region including a first region, a second region, and a third region arranged in sequence; the top of the doped region in the first region is lower than the top of the doped region in the third region, the doped region in the second region includes a transition portion having an inclined sidewall, and the bottom end of the inclined sidewall of the transition portion is connected to the top of the doped region in the first region, and the top end of the inclined sidewall of the transition portion is connected to the top of the doped region in the third region; a stacked gate conformally covering the doped region, and the stacked gate includes: a floating gate, a gate dielectric layer located on the floating gate, and a control gate located on the gate dielectric layer.

[0019] Optionally, the included angle between the top of the doped region in the first region and the inclined sidewall in the transition portion is 90° to 120°, and the included angle between the top of the doped region in the third region and the inclined sidewall in the transition portion is 90° to 120°.

[0020] Optionally, an angle formed by the inclined sidewall in the transition portion and the top of the doped region in the first region is equal to an angle formed by the inclined sidewall in the transition portion and the top of the doped region in the third region.

[0021] Optionally, a distance from a top of the doped region in the first region to a top of the doped region in the third region is 200 angstroms to 500 angstroms.

[0022] Optionally, the stacked gate is also located on the substrate in partial areas on both sides of the doped region.

[0023] Optionally, the top of the substrate on the side of the first region facing away from the second region is flush with the top of the doped region in the first region; the method for forming the semiconductor structure also includes: a selection gate, located on the substrate in the first region facing away from the second region, and the selection gate is spaced apart from the stacked gate.

[0024] Optionally, the semiconductor structure further includes: a source-drain doped region located in the substrate between the selection gate and the stacked gate, and the source-drain doped region is adjacent to the doped region.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0026] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a part of a region of the substrate is doped to form a doped region, and the doped region includes a first region, a second region, and a third region arranged in sequence; the doped regions of the first region and the second region are thinned, so that the overall thinned doped region is in a stepped shape, and the top of the doped region in the etched first region is lower than the top of the doped region in the third region. The doped region in the second region is etched into a transition portion with an inclined sidewall, and the bottom end of the inclined sidewall of the transition portion is connected to the top of the doped region in the first region, and the top end of the inclined sidewall of the transition portion is connected to the top of the doped region in the third region. Therefore, the inclined sidewall of the transition portion and the top of the doped region in the third region form an outwardly convex corner, and the floating gate surrounds the doped region in the outwardly convex corner, which is equivalent to the doped region in the outwardly convex corner being inserted into the floating gate. When a write operation is performed on the semiconductor structure, according to the principle of point discharge, the electric field strength between the doped region in the tip region of the outwardly convex corner and the floating gate is relatively large, and the electrons in the doped region are easy to enter the floating gate, which is beneficial to improving the write performance of the semiconductor structure. The inclined sidewall of the transition portion and the top of the doped region in the first region form an inwardly concave corner, and the doped region surrounds the floating gate in the inwardly concave corner, which is equivalent to the floating gate being inserted into the doped region. When an erase operation is performed on the semiconductor structure, according to the principle of point discharge, the electric field strength between the floating gate in the tip region of the inwardly concave corner and the doped region is relatively large, and the electrons in the floating gate are easy to enter the doped region, which is beneficial to improving the erase performance of the semiconductor structure.

[0027] In the semiconductor structure provided by the embodiment of the present invention, a doped region is located in a partial region of the substrate. The doped region is in a stepped shape and includes a first region, a second region, and a third region arranged in sequence. The top of the doped region in the first region is lower than the top of the doped region in the third region. The doped region in the second region includes a transition portion with an inclined sidewall. The bottom end of the inclined sidewall of the transition portion is connected to the top of the doped region in the first region, and the top end of the inclined sidewall of the transition portion is connected to the top of the doped region in the third region. A stacked gate conformally covers the doped region. The stacked gate is in a stepped shape and includes a floating gate, a gate dielectric layer located on the floating gate, and a control gate located on the gate dielectric layer. Therefore, the inclined sidewall of the transition portion and the top of the doped region in the third region form an outwardly convex corner. The floating gate surrounds the doped region in the outwardly convex corner, which is equivalent to the doped region in the outwardly convex corner being inserted into the floating gate. When a write operation is performed on the semiconductor structure, according to the principle of point discharge, the electric field strength between the doped region in the tip region of the outwardly convex corner and the floating gate is relatively large, and the electrons in the doped region are easily introduced into the floating gate, which is beneficial to improving the write performance of the semiconductor structure. The inclined sidewall of the transition portion and the top of the doped region in the first region form an inwardly concave corner. The doped region surrounds the floating gate in the inwardly concave corner, which is equivalent to the floating gate being inserted into the doped region. When an erase operation is performed on the semiconductor structure, according to the principle of point discharge, the electric field strength between the floating gate in the tip region of the inwardly concave corner and the doped region is relatively large, and the electrons in the floating gate are easily introduced into the doped region, which is beneficial to improving the erase performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic structural diagram of a semiconductor structure;

[0029] Figures 2 to 11 Schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the invention. DETAILED DESCRIPTION

[0030] As can be seen from the background art, the currently formed devices still have problems with poor performance. The reasons for the poor performance of the devices are analyzed in combination with a method for forming a semiconductor structure.

[0031] Refer to Figure 1 , which shows a schematic structural diagram of a semiconductor structure.

[0032] As shown in Figure 1As shown, the semiconductor structure includes: a substrate 1, the substrate 1 includes a device region for forming a memory cell and a peripheral region (not shown in the figure) for providing an operating voltage for the memory cell, and the substrate 1 of the device region includes a doped region 2; a stacked gate 3, located on the substrate 1 of the device region, and the stacked gate 3 covers the doped region 2, the stacked gate 3 includes: a floating gate 31, a gate dielectric layer 32 located on the floating gate 31, and a control gate 33 located on the gate dielectric layer 32; a select gate 5, located on the substrate 1 of the device region, and arranged at intervals with the stacked gate 3; source / drain doped regions 4, located in the substrate 1 between the select gate 5 and the stacked gate 3, in the substrate 1 on the side of the select gate 5 away from the stacked gate 3, and in the substrate on the side of the stacked gate 3 away from the select gate 5.

[0033] In order to improve the integration degree of the semiconductor structure, it is now necessary to reduce the area of the peripheral region. However, while the area of the peripheral region is reduced, the operating voltage provided by the peripheral region to the memory cells in the working region also decreases accordingly. When a write operation is performed on the semiconductor structure, if the peripheral region cannot provide a high voltage to the memory cells, the electric field intensity between the doped region 2 and the floating gate 31 is small, and it is difficult for electrons in the doped region 2 to enter the floating gate 31, resulting in poor electrical performance of the semiconductor structure. Similarly, when an erase operation is performed on the semiconductor structure, if the peripheral region cannot provide a high voltage to the memory cells, the electric field intensity between the doped region 2 and the floating gate 31 is small, and it is difficult for electrons in the floating gate 31 to enter the doped region 2, resulting in poor electrical performance of the semiconductor structure.

[0034] To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure. Doping is performed on a partial region of the substrate to form a doped region, and the doped region includes a first region, a second region, and a third region arranged in sequence. The doped regions in the first region and the second region are thinned, so that the overall thinned doped region is in a stepped shape. After etching, the top of the doped region in the first region is lower than the top of the doped region in the third region. The doped region in the second region is etched into a transition portion with an inclined sidewall, and the bottom end of the inclined sidewall of the transition portion is connected to the top of the doped region in the first region, and the top end of the inclined sidewall of the transition portion is connected to the top of the doped region in the third region. Therefore, the inclined sidewall of the transition portion and the top of the doped region in the third region form an outwardly convex corner, and the floating gate surrounds the doped region in the outwardly convex corner, which is equivalent to the doped region in the outwardly convex corner being inserted into the floating gate. When a write operation is performed on the semiconductor structure, according to the principle of point discharge, the electric field strength between the doped region in the tip region of the outwardly convex corner and the floating gate is relatively large, and the electrons in the doped region are easy to enter the floating gate, which is beneficial to improving the write performance of the semiconductor structure. The inclined sidewall of the transition portion and the top of the doped region in the first region form an inwardly concave corner, and the doped region surrounds the floating gate in the inwardly concave corner, which is equivalent to the floating gate being inserted into the doped region. When an erase operation is performed on the semiconductor structure, according to the principle of point discharge, the electric field strength between the floating gate in the tip region of the inwardly concave corner and the doped region is relatively large, and the electrons in the floating gate are easy to enter the doped region, which is beneficial to improving the erase performance of the semiconductor structure.

[0035] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the embodiments of the present invention will be given with reference to the accompanying drawings.

[0036] Figures 2 to 11 Schematic diagrams of the structures corresponding to the steps in an embodiment of the method for forming a semiconductor structure according to an embodiment of the invention.

[0037] Refer to Figure 2 , and provide a substrate 100.

[0038] The substrate 100 provides an operating basis for the formation process of the semiconductor structure, and the semiconductor structure belongs to an Electrically Erasable Programmable Read-Only Memory.

[0039] In this embodiment, the substrate 100 includes a device region for forming a storage unit and a peripheral region (not shown in the figure) for providing the operating voltage of the storage unit. Generally, the larger the area of the peripheral region, the larger the operating voltage that the peripheral region can provide for the device region.

[0040] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium. The substrate can also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.

[0041] Reference Figure 3 , doping is performed on a partial area of the substrate 100 to form a doped area 101, and the doped area 101 includes a first area I, a second area II, and a third area III arranged in sequence.

[0042] The method for forming the semiconductor structure further includes subsequently forming a stacked gate on the doped area 101. The stacked gate includes a floating gate, and source / drain doped areas are formed on the side portions of the doped area 101. When the semiconductor is operating, the doped area 101 can block the direct current flow between the floating gate and the source / drain doped areas. In addition, the F-N tunneling (Fowler-Nordheim Tunneling) that occurs between the doped area 101 and the floating gate enables the stacked gate to achieve data reading and writing.

[0043] In this embodiment, the doped area 101 is prepared for subsequent thinning treatment of the doped areas 101 of the first area I and the second area II.

[0044] In this embodiment, the doped area 101 is a doped area of heavy N-type doping ions (Buried N Plus, BNP). The more N-type ions are doped, the more beneficial it is to reduce the write and erase voltages of the storage unit when the semiconductor structure is operating. Specifically, the N-type doping ions include one or more of P, As, and Sb.

[0045] In this embodiment, the step of doping a partial area of the substrate 100 to form the doped area 101 includes: forming a doping mask layer (not shown in the figure) on the substrate 100, and the doping mask layer has an opening exposing the area 101 to be doped; performing ion doping using the doping mask layer as a mask to form the doped area 101 in the substrate 100.

[0046] In this embodiment, ion implantation is used to dope a partial area of the substrate 100 to form the doped area 101. Ion implantation has the characteristics of simple operation and low process cost.

[0047] It should be noted that while the doped region 101 is formed in a partial region of the substrate 100, it is also located on top of the substrate 100. The doped region 101 is formed on top of a partial region of the substrate 100 such that after subsequent thinning of the doped regions 101 in the first region I and the second region II, the tops of the first region I, the second region II, and the third region III belong to regions doped with N-type ions.

[0048] Reference Figure 4 , the doped regions 101 in the first region I and the second region II are thinned such that the overall thinned doped region 101 is stepped. Among them, the top of the doped region 101 in the thinned first region I is lower than the top of the doped region 101 in the third region III. The doped region 101 in the second region II is etched into a transition portion 101a having an inclined sidewall, and the bottom end of the inclined sidewall of the transition portion 101a is connected to the top of the doped region 101 in the first region I, and the top end of the inclined sidewall of the transition portion 101a is connected to the top of the doped region 101 in the third region III.

[0049] The doped regions 101 in the first region I and the second region II are thinned, while the doped region 101 in the third region III is not thinned. Therefore, the inclined sidewall of the transition portion 101a and the top of the doped region 101 in the third region III form a convex corner. The doped region 101 in the subsequent formed floating gate surrounds the convex corner, which is equivalent to the doped region 101 in the convex corner being inserted into the floating gate. When a write operation is performed on the semiconductor structure, according to the principle of tip discharge, the electric field strength between the doped region 101 in the tip region of the convex corner and the floating gate is relatively large, and the electrons in the doped region 101 are easily introduced into the floating gate, which is beneficial to improving the write performance of the semiconductor structure. The inclined sidewall of the transition portion 101a and the top of the doped region 101 in the first region I form a concave corner, and the doped region 101 surrounds the floating gate in the concave corner, which is equivalent to the floating gate being inserted into the doped region 101. When an erase operation is performed on the semiconductor structure, according to the principle of tip discharge, the electric field strength between the floating gate in the tip region of the concave corner and the doped region 101 is relatively large, and the electrons in the floating gate are easily introduced into the doped region 101, which is beneficial to improving the erase performance of the semiconductor structure.

[0050] Specifically, the steps for thinning the doped regions 101 in the first region I and the second region II include: forming a first mask layer 102 on the third region III, and the first mask layer 102 exposes the first region I and the second region II; using the first mask layer 102 as a thinning mask to thin the first region I and the second region II.

[0051] In this embodiment, a dry etching process is used to thin the doped regions 101 in the first region I and the second region II. The dry etching process is an anisotropic etching process, which has good etching profile controllability. This is conducive to etching the doped region 101 in the second region II into a transition portion 101a with an inclined sidewall, while keeping the surface of the first region I relatively flat, so that the doped region 101 after etching is in a stepped shape. In addition, the dry etching process is also conducive to precisely controlling the removal thickness of the doped region 101 in the first region I.

[0052] In this embodiment, the material of the substrate 100 is silicon, and correspondingly, the etching gas in the dry etching includes CF 4 , HBr and O 2 or one or more of them.

[0053] During the process of thinning the doped regions 101 in the first region I and the second region II by using the dry etching process, if the bias power is too large, the material removal rate of the doped regions 101 in the first region I and the second region II will be too fast, and the controllability of the etching process will be poor, which easily leads to poor flatness of the surface of the top of the doped region 101 in the first region I and the transition portion 101a. Subsequently, when a stacked gate is formed on the doped region 101 and the semiconductor structure is working, the electron tunneling rates at different positions on the surface of the top of the doped region 101 in the first region I and the transition portion 101a of the stacked gate vary greatly, reducing the reliability of the semiconductor structure. If the bias power is too small, it will take too much process time to form the stepped doped region 101. In this embodiment, the bias power in the dry etching is 200 W to 1000 W.

[0054] During the process of thinning the doped regions 101 in the first region I and the second region II by using the dry etching process, if the chamber pressure is too high, the reaction by-products in the chamber will redeposit on the doped regions 101 in the first region I and the second region II, resulting in poor flatness of the surface of the top of the doped region 101 in the first region I and the transition portion 101a. Subsequently, when a stacked gate is formed on the doped region 101 and the semiconductor structure is working, the electron tunneling rates at different positions on the surface of the top of the doped region 101 in the first region I and the transition portion 101a of the stacked gate vary greatly, reducing the reliability of the semiconductor structure. If the chamber pressure is too low, it will take too much process time to form the stepped doped region 101. In this embodiment, the chamber pressure in the dry etching is 10 mTorr to 50 mTorr.

[0055] It should be noted that the first mask layer 102 also covers the substrate 100 of the third region III facing away from the second region II, and exposes the substrate 100 of the first region I facing away from the second region II. Correspondingly, during the process of thinning the doped regions 101 of the first region I and the second region II, the substrate 100 on the side of the first region I facing away from the second region II is also thinned.

[0056] It should also be noted that in the step of thinning the doped regions 101 of the first region I and the second region II, the angle formed by the inclined sidewall in the transition portion 101a and the top of the doped region 101 in the first region I is equal to the angle formed by the inclined sidewall in the transition portion 101a and the top of the doped region 101 in the third region III. When a write operation is performed on the semiconductor structure, the electric field strength between the tip region formed by the doped regions 101 of the second region II and the third region II and the floating gate is the same as the electric field strength between the tip region of the doped region 101 of the second region II and the doped region 101 of the first region I when an erase operation is performed on the semiconductor structure, which is beneficial to making the write operation rate and the erase operation rate consistent.

[0057] It should be noted that in the step of performing the thinning treatment, if the angle α between the top of the doped region 101 in the third region III and the inclined sidewall in the transition portion 101a (as Figure 4 shown) is too large, according to the principle of tip discharge, when a write operation is performed on the semiconductor structure, the electric field strength between the tip region formed by the doped regions 101 of the second region II and the third region III and the floating gate is increased less, and the electrons in the doped region 101 are not easily introduced into the floating gate, resulting in insignificant improvement in the write performance of the semiconductor structure. If the angle α between the top of the doped region 101 in the third region III and the inclined sidewall in the transition portion 101a (as Figure 4 shown) is too small, in other words, the angle between the top of the doped region 101 in the third region III and the inclined sidewall in the transition portion 101a is less than 90°. The thinning treatment in the embodiment of the present invention is performed by etching, but it is difficult to form an angle less than 90° through the etching process. In this embodiment, in the step of performing the thinning treatment, the angle between the top of the doped region 101 in the third region III and the inclined sidewall in the transition portion 101a is 90° to 120°.

[0058] For similar reasons, if the angle α between the top of the doped region 101 in the first region I and the inclined sidewall in the transition portion 101a (as Figure 4If it is too large (as shown), based on the principle of tip discharge, when an erasing operation is performed on the semiconductor structure, the electric field strength between the tip region formed by the doped region in the second region and the doped region in the first region and the floating gate increases slightly, and it is not easy for the electrons in the floating gate to enter the doped region 101, resulting in insignificant improvement in the erasing performance of the semiconductor structure. If the angle α (as shown in Figure 4 ), that is, the angle between the top of the doped region 101 in the first region I and the inclined sidewall in the transition portion 101a is too small. In other words, the angle between the top of the doped region 101 in the first region I and the inclined sidewall in the transition portion 101a is less than 90°. In the embodiment of the present invention, the thinning process is performed by etching, but it is difficult to form an angle less than 90° through the etching process. In this embodiment, in the step of performing the thinning process, the angle between the top of the doped region 101 in the first region I and the inclined sidewall in the transition portion 101a is 90° to 120°.

[0059] It should be noted that in the step of thinning the doped regions 101 in the first region I and the second region II, if the distance L (as shown in Figure 4 ) from the top of the doped region 101 in the first region I to the top of the doped region 101 in the third region III is too large, the corresponding time for thinning the doped regions 101 in the first region I and the second region II is too long, which is not conducive to improving the formation efficiency of the semiconductor structure. In addition, it is also easy to cause the mechanical strength of the stacked gate formed subsequently on the second region II to be low and easy to break, resulting in the stacked gate being unable to write and erase data normally. If the distance L from the top of the doped region 101 in the first region I to the top of the doped region 101 in the third region III is too small, it will cause the overall stepped morphology of the doped region 101 to be poor. That is to say, the convex corner formed by the inclined sidewall of the transition portion 101a and the top of the doped region 101 in the third region III, and the concave corner formed by the inclined sidewall of the transition portion 101a and the top of the doped region 101 in the first region I have poor morphology. When the semiconductor structure is working, the tip effect is not significant, resulting in a small electric field strength at the convex corner and the concave corner, resulting in the stacked gate formed subsequently being unable to perform normal erasing and writing operations. In this embodiment, the distance L from the top of the doped region 101 in the first region I to the top of the doped region 101 in the third region III is 200 angstroms to 500 angstroms.

[0060] Referring to Figure 5 and Figure 6 , the method for forming the semiconductor structure further includes: after thinning the doped regions 101 in the first region I and the second region II, before forming the stacked gate, removing a part of the thickness of the doped regions 101 in the first region I and the second region II.

[0061] During the process of thinning the doped regions 101 in the first region I and the second region II by using a dry etching process, some etching ions will remain on the tops of the doped regions 101 in the first region I and the second region II. Subsequently, a stacked gate conformally covering the doped regions 101 is formed. During the process of writing and reading data in the semiconductor structure, the remaining etching ions will hinder the entry of electrons from the doped regions in the first region I and the second region II into the floating gate, and the entry of electrons from the floating gate into the doped regions 101 in the first region I and the second region II. Therefore, it is necessary to remove the etching ions remaining on the tops of the doped regions 101 in the first region I and the second region II.

[0062] In this embodiment, the step of removing a partial thickness of the doped regions 101 in the first region I and the second region II includes: performing a high-temperature oxidation treatment on the surfaces of the doped regions 101 in the first region I and the second region II to form an oxide layer 103; after performing the high-temperature oxidation treatment, removing the oxide layer 103.

[0063] In this embodiment, the material of the oxide layer 103 includes silicon oxide. Silicon oxide has the characteristics of high process compatibility, low formation difficulty, and is easy to be removed.

[0064] In this embodiment, the oxide layer 103 is formed by using a high-temperature oxidation process. The operation difficulty of using the high-temperature oxidation process is low, and the thickness uniformity and density of the formed oxide layer 103 are good.

[0065] In this embodiment, the wet etching process is isotropic etching, with simple operation and low process cost. The process parameters of the wet etching include: the etching solution includes hydrofluoric acid and ammonium fluoride.

[0066] It should be noted that in the step of removing a partial thickness of the doped regions 101 in the first region I and the second region II, the thickness of the doped regions 101 in the first region I and the second region II removed should not be too large or too small. If the thickness of the doped regions 101 in the first region I and the second region II removed is too large, it will take too much process time and is not easy to improve the formation efficiency of the semiconductor structure. If the thickness of the doped regions 101 in the first region I and the second region II removed is too small, it will cause that during the process of thinning the doped regions 101 in the first region I and the second region II, the etching ions remaining on the tops of the doped regions 101 in the first region I and the second region II are not completely removed. During the process of writing and reading data in the semiconductor structure, the remaining etching ions will hinder the entry of electrons into the floating gate and into the doped regions 101 in the first region I and the second region II, which is not conducive to the writing and erasing operations of the semiconductor structure. In this embodiment, the thickness of the doped regions 101 in the first region I and the second region II removed is 80 angstroms to 110 angstroms.

[0067] In this embodiment, during the process of removing a partial thickness of the doped region 101 in the first region I and the second region II, a partial thickness of the doped region 101 in the third region III is also removed. The doped regions 101 in the first region I, the second region II, and the third region III of the embodiment of the present invention are simultaneously removed of a partial thickness, which is beneficial to making the stepped morphology of the doped region after removal consistent with the stepped morphology before removal.

[0068] It should also be noted that during the process of removing a partial thickness of the doped region 101 in the first region I and the second region II in a maskless manner, a partial thickness of the substrate 100 on both sides of the doped region 101 is also removed. That is to say, a partial thickness of the entire substrate is removed without forming a removal mask. In other words, a maskless method is adopted, which is beneficial to simplifying the removal process.

[0069] It should also be noted that during the high-temperature oxidation process, the thickness of the oxide layer 103 formed on the doped region 101 and the substrate on both sides is equal. Before and after removing the oxide layer 103, the distance from the top of the doped region 101 in the first region I to the top of the doped region 101 in the third region III does not change.

[0070] Reference Figures 7 to 9 , after performing the thinning process, a stacked gate 105 that conformally covers the doped region 101 is formed. The stacked gate 105 is stepped. The stacked gate 105 includes: a floating gate 1051, an inter-gate dielectric layer 1052 located on the floating gate 1051, and a control gate 1053 located on the inter-gate dielectric layer 1052.

[0071] In the method for forming a semiconductor structure provided by an embodiment of the present invention, the inclined sidewall of the transition portion 101a and the top of the doped region 101 in the third region III form a convex corner. The floating gate 1051 surrounds the doped region 101 in the convex corner, which is equivalent to the doped region 101 in the convex corner being inserted into the floating gate 1051. When a write operation is performed on the semiconductor structure, according to the principle of point discharge, the electric field strength between the doped region 101 in the tip region of the convex corner and the floating gate 1051 is relatively large, and the electrons in the doped region 101 are likely to enter the floating gate 1051, which is beneficial to improving the write performance of the semiconductor structure. The inclined sidewall of the transition portion 101a and the top of the doped region 101 in the first region I form a concave corner, and the doped region 101 surrounds the floating gate 1051 in the concave corner, which is equivalent to the floating gate 1051 being inserted into the doped region 101. When an erase operation is performed on the semiconductor structure, according to the principle of point discharge, the electric field strength between the floating gate 1051 in the tip region of the concave corner and the doped region 101 is relatively large, and the electrons in the floating gate 1051 are likely to enter the doped region 101, which is beneficial to improving the erase performance of the semiconductor structure.

[0072] It should also be noted that when the area of the peripheral region in the substrate 100 is small and the peripheral region can only provide a low voltage to the control gate 1053 of the memory cell, according to the principle of point discharge, there can also be a sufficiently large electric field strength between the doped region 101 in the tip region of the convex corner and the floating gate 1051. When the semiconductor structure is working, the peripheral region only needs to provide a low operating voltage to the memory cell to enable the semiconductor structure to perform the erase operation and the write operation smoothly. When the area of the peripheral region is small, it is beneficial to reduce the overall area of the semiconductor structure and improve the integration degree of the semiconductor structure.

[0073] In this embodiment, the stacked gate is used as a memory cell for storing data and maintaining the data state. By storing or not storing electrons in the floating gate 1051, the memory cell is in the state after storing information or erasing information.

[0074] In this embodiment, in the step of forming the stacked gate 105 on the doped region 101, the stacked gate 105 is also formed on the substrate 100 in partial regions on both sides of the doped region 101. That is to say, the doped region 101 is completely covered by the stacked gate 105, so that when the semiconductor structure performs data write and erase operations, the stacked gate 105 can more effectively control the electrons in the doped region 101. When a write operation is performed, electrons are likely to enter the floating gate 1051 from the doped region 101, and when an erase operation is performed, electrons are likely to enter the doped region 101 from the floating gate 1051.

[0075] In this embodiment, the material of the floating gate 1051 is polysilicon. The floating gate 1051 is doped with N-type ions. The N-type ions include one or more of phosphorus, arsenic, and antimony.

[0076] The control gate 1053 is used for external electrical connection to control the longitudinal electric field of the floating gate 1051. During the write operation, it controls the injection or movement of the electron flow in the floating gate 1051 to change the charge state of the floating gate 1051; during the erase operation, the control gate 1053 creates an erase electric field.

[0077] The control gate 1053 is used to inject electrons into the floating gate 1051 or pull electrons out of the floating gate 1051 during the data writing or erasing process of the storage cell.

[0078] In this embodiment, the material of the control gate 1053 is polysilicon.

[0079] It should be noted that the control gate 1053 is doped with P-type ions, so that the control gate 1053 is not easily in the depletion state, and thus the control gate 1053 is in the conductive state.

[0080] The inter-gate dielectric layer 1052 is used to electrically isolate the floating gate 1051 and the control gate 1053.

[0081] In this embodiment, the material of the inter-gate dielectric layer 1052 is a dielectric material. Specifically, the material of the inter-gate dielectric layer 1052 includes one or both of silicon oxide and silicon nitride. In this embodiment, the material of the inter-gate dielectric layer 1052 is a sandwich structure composed of silicon oxide, silicon nitride, and silicon oxide (ONO).

[0082] It should also be noted that in the step of forming the stacked gate 105, a select gate 110 (Select Gate, EG) is further formed on the substrate 100 of the first region I facing away from the second region II, and the select gate 110 is spaced apart from the stacked gate 105.

[0083] The select gate 110 is used for access control of the storage cell, data transmission, and selection and erase operations of the storage cell.

[0084] The semiconductor structure further includes: a floating gate dielectric layer 104 (Floating Gate oxide), located between the substrate 100 and the stacked gate 105, and between the substrate 100 and the select gate 110.

[0085] The floating gate dielectric layer 104 is used to isolate the stacked gate 105 and the substrate 100, and the select gate 110 and the substrate 100.

[0086] In this embodiment, the material of the floating gate dielectric layer 104 is a dielectric material, such as silicon oxide. In other embodiments, the floating gate dielectric layer 104 may also be a stack layer composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0087] In this embodiment, the selection gate 110 and the stacked gate 105 are formed in the same step. Specifically, the steps of forming the selection gate 110 and the stacked gate 105 include: forming a floating gate material layer 1091 on the doped region 101 and the substrate 100 on both sides of the doped region 101, an inter-gate dielectric material layer 1092 located on the floating gate material layer 1091, and a control gate material layer 1093 located on the inter-gate dielectric material layer 1092; forming a second mask layer 106 on the control gate material layer 1093, and the second mask layer 106 is formed at a position where the selection gate and the stacked gate are preset to be formed; using the second mask layer 106 as a mask to etch the floating gate material layer 1091, the inter-gate dielectric material layer 1092, and the control gate material layer 1093 to form the stacked gate 105 and the selection gate 110.

[0088] It should be noted that the method for forming the semiconductor structure further includes: before forming the floating gate material layer 1091, a floating gate dielectric material layer 111 is also formed on the doped region 101 and the substrate 100 on both sides of the doped region 101, and during the process of forming the stacked gate 105 and the selection gate 110, the floating gate dielectric material layer 111 is etched to form the floating gate dielectric layer 104.

[0089] In this embodiment, the method for forming the semiconductor structure further includes: after forming the stacked gate and the selection gate, a sidewall layer 107 is formed on the sidewalls of the selection gate and the stacked gate (as Figure 9 shown).

[0090] The sidewall layer 107 is used to protect the sidewalls of the selection gate and the stacked gate, and is also used as a mask for subsequent source-drain doping.

[0091] Referring to Figure 10 and Figure 11 , the method for forming the semiconductor structure further includes: after forming the stacked gate 105 and the selection gate 110, a source-drain doping region 108 is formed in the substrate 100 between the selection gate 110 and the stacked gate 105, and the source-drain doping region 108 is adjacent to the doped region 101.

[0092] The source-drain doping region 108 and the doped region 101 are closely adjacent to each other, so that when a write or erase operation is performed, the distance of charge transfer is shorter, thereby reducing the time required for write and erase operations, reducing the diffusion and leakage of charges in the flow channel, and improving the efficiency of programming and erase operations.

[0093] In this embodiment, the source-drain doping region 108 is doped with P-type ions, and the P-type ions include one or more of B, Ga, and In.

[0094] In this embodiment, the source-drain doping region 108 is formed in the substrate 100 between the select gate 110 and the stacked gate 105 by ion implantation. Ion implantation has the characteristics of simple operation and low process cost.

[0095] Specifically, the source-drain doping region 108 includes a lightly doped region 1081 (Lightly Doped Drain, LDD) and a heavily doped region 1082 located on top of the lightly doped region 1081. The lightly doped region 1081 is used to change the electric field distribution, and the heavily doped region 1082 is used to reduce the resistance and provide better current transmission ability.

[0096] It should be noted that the source-drain doping region 108 is formed not only in the substrate 100 between the select gate 110 and the stacked gate 105, but also in the substrate on the side of the select gate 110 away from the stacked gate 105, and in the substrate on the side of the stacked gate 105 away from the select gate 110.

[0097] Reference Figure 11 , the embodiment of the present invention also provides a semiconductor structure.

[0098] The semiconductor structure includes: a substrate 100; a doping region 101 located in a partial region of the substrate 100, the doping region 101 being stepped, and the doping region 101 including a first region I, a second region II, and a third region III arranged in sequence; the top of the doping region 101 in the first region I is lower than the top of the doping region 101 in the third region III, the doping region 101 in the second region II includes a transition portion 101a having an inclined sidewall, and the bottom end of the inclined sidewall of the transition portion 101a is connected to the top of the doping region 101 in the first region I, and the top end of the inclined sidewall of the transition portion 101a is connected to the top of the doping region 101 in the third region III; a stacked gate 105 conformally covering the doping region 101, and the stacked gate 105 includes: a floating gate 1051, a gate dielectric layer 1052 located on the floating gate 1051, and a control gate 1053 located on the gate dielectric layer 1052.

[0099] In an embodiment of the present invention, an inclined sidewall of the transition portion 101a and a top of the doped region 101 in the third region III form a convex corner. The floating gate 1051 surrounds the doped region 101 in the convex corner, which is equivalent to the doped region 101 in the convex corner being inserted into the floating gate 1051. When a write operation is performed on the semiconductor structure, according to the principle of tip discharge, the electric field strength between the doped region 101 in the tip region of the convex corner and the floating gate 1051 is relatively large, and electrons in the doped region 101 easily enter the floating gate 1051, which is beneficial to improving the write performance of the semiconductor structure. The inclined sidewall of the transition portion 101a and the top of the doped region 101 in the first region I form a concave corner, and the doped region 101 surrounds the floating gate 1051 in the concave corner, which is equivalent to the floating gate 1051 being inserted into the doped region 101. When an erase operation is performed on the semiconductor structure, according to the principle of tip discharge, the electric field strength between the floating gate 1051 in the tip region of the concave corner and the doped region 101 is relatively large, and electrons in the floating gate 1051 easily enter the doped region 101, which is beneficial to improving the erase performance of the semiconductor structure.

[0100] In this embodiment, the substrate 100 includes a device region for accommodating a storage unit and a peripheral region (not shown in the figure) for providing an operating voltage for the storage unit. Generally, the larger the area of the peripheral region, the larger the operating voltage that the peripheral region can provide for the device region.

[0101] It should be noted that when the area of the peripheral region in the substrate 100 is small and the peripheral region can only provide a low voltage for the control gate 1053 of the storage unit, according to the principle of tip discharge, there can also be a sufficiently large electric field strength between the doped region 101 in the tip region of the convex corner and the floating gate 1051. When the semiconductor structure is operating, the peripheral region only needs to provide a low operating voltage for the storage unit to enable the semiconductor structure to perform the erase operation and the write operation smoothly. When the area of the peripheral region is small, it is beneficial to reduce the overall area of the semiconductor structure and improve the integration degree of the semiconductor structure.

[0102] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium. The substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.

[0103] When the semiconductor is operating, the doped region 101 can block the direct current flow between the floating gate and the source / drain doped regions. In addition, Fowler-Nordheim Tunneling occurring between the doped region 101 and the floating gate 1051 enables the stacked gate 105 to achieve data reading and writing.

[0104] In this embodiment, the doped region 101 is a buried N plus (BNP) doped region. The more N-type ions are doped, the more beneficial it is to reduce the write and erase voltages of the memory cell during the operation of the semiconductor structure. Specifically, the N-type doped ions include one or more of P, As, and Sb.

[0105] It should also be noted that the angle α formed by the inclined sidewall in the transition portion 101a and the top of the doped region 101 in the first region I is equal to the angle α formed by the inclined sidewall in the transition portion 101a and the top of the doped region 101 in the third region III. When the semiconductor structure performs a write operation, the electric field strength between the tip region formed by the doped region 101 in the second region II and the doped region 101 in the third region III and the floating gate 1051 is the same as the electric field strength between the tip region of the doped region 101 in the second region II and the doped region 101 in the first region I and the doped region 101 when the semiconductor structure performs an erase operation, which is beneficial to making the rates of the write operation and the erase operation consistent.

[0106] It should be noted that if the angle α (as shown in Figure 4 ) between the top of the doped region 101 in the third region III and the inclined sidewall in the transition portion 101a is too large, according to the principle of tip discharge, when the semiconductor structure performs a write operation, the increase in the electric field strength between the tip region formed by the doped region 101 in the second region II and the doped region 101 in the third region III and the floating gate is small, and the electrons in the doped region 101 are not easily introduced into the floating gate, resulting in insignificant improvement in the write performance of the semiconductor structure. If the angle α (as shown in Figure 4 ) between the top of the doped region 101 in the third region III and the inclined sidewall in the transition portion 101a is too small, in other words, the angle between the top of the doped region 101 in the third region III and the inclined sidewall in the transition portion 101a is less than 90°. In this embodiment of the present invention, the stepped doped region is formed by etching, but when the angle is less than 90°, it is difficult to form by the etching process. In this embodiment, the angle between the top of the doped region 101 in the third region III and the inclined sidewall in the transition portion 101a is 90° to 120°.

[0107] For similar reasons, if the angle α (as shown in Figure 4101a) is too large. According to the principle of tip discharge, when the semiconductor structure performs an erase operation, the electric field strength between the tip region formed by the doped region of the second region and the doped region of the first region and the floating gate is increased slightly, and the electrons in the floating gate are not easy to enter the doped region 101, resulting in insignificant improvement in the erase performance of the semiconductor structure. If the angle α (as shown in FIG. 101 ) between the top of the doped region 101 in the first region I and the inclined sidewall in the transition portion 101a is Figure 4 In other words, the angle between the top of the doped region 101 in the first region I and the inclined sidewall in the transition portion 101a is less than 90°. In the embodiment of the present invention, the stepped doped region is formed by etching, but when the angle is less than 90°, it is difficult to form by etching. In this embodiment, the angle between the top of the doped region 101 in the first region I and the inclined sidewall in the transition portion 101a is 90° to 120°.

[0108] It should be noted that if the distance L from the top of the doped region 101 in the first region I to the top of the doped region 101 in the third region III is too large, the overall step morphology of the doped region 101 needs to spend too much process time to form. In addition, it is easy to cause the mechanical strength of the stacked gate formed on the second region II to be low and easy to break, resulting in the stacked gate being unable to write and erase data normally. If the distance L from the top of the doped region 101 in the first region I to the top of the doped region 101 in the third region III is too small, the overall step morphology of the doped region 101 is poor, that is, the convex corner formed by the inclined sidewall of the transition portion 101a and the top of the doped region 101 in the third region III, and the concave corner formed by the inclined sidewall of the transition portion 101a and the top of the doped region 101 in the first region I are poor. When the semiconductor structure is working, the tip effect is not significant, resulting in a small electric field strength at the convex corner and the concave corner, resulting in the stacked gate 105 formed being unable to perform normal erase and write operations. In this embodiment, a distance L from the top of the doped region 101 in the first region I to the top of the doped region 101 in the third region III is 200 angstroms to 500 angstroms.

[0109] It should be noted that the top of the substrate 100 on the side of the first region I away from the second region II is flush with the top of the doped region of the first region I.

[0110] The stacked gate 105 is in a step-like shape and includes a floating gate 1051 , an inter-gate dielectric layer 1052 located on the floating gate 1051 , and a control gate 1053 located on the inter-gate dielectric layer 1052 .

[0111] In this embodiment, the stacked gate 105 is used as a storage unit for storing data and maintaining the data state. By storing or not storing electrons in the floating gate 1051, the storage unit is in the state after storing information or erasing information.

[0112] In this embodiment, the stacked gate 105 is also located on the substrate 100 in partial areas on both sides of the doped region 101. That is to say, the doped region 101 is completely covered by the stacked gate 105, so that when the semiconductor structure performs data writing and erasing operations, the stacked gate 105 can more effectively control the electrons in the doped region 101. During the writing operation, electrons easily enter the floating gate 1051 from the doped region 101, and during the erasing operation, electrons easily enter the doped region 101 from the floating gate 1051.

[0113] In this embodiment, the material of the floating gate 1051 is polysilicon. The floating gate 1051 is doped with N-type ions. The N-type ions include one or more of phosphorus, arsenic, and antimony.

[0114] The control gate 1053 is used for external electrical connection to control the longitudinal electric field of the floating gate 1051. During the writing operation, it controls the injection or movement of the electron flow in the floating gate 1051 to change the charge state of the floating gate 1051; during the erasing operation, the control gate 1053 creates an erasing electric field.

[0115] The control gate 1053 is used to inject electrons into the floating gate 1051 or pull electrons out of the floating gate 1051 during the data writing or erasing process of the storage unit.

[0116] In this embodiment, the material of the control gate 1053 is polysilicon.

[0117] It should be noted that the control gate 1053 is doped with P-type ions, so that the control gate 1053 is not easily in the depletion state, and further the control gate 1053 is in the conductive state.

[0118] The inter-gate dielectric layer 1052 is used to electrically isolate the floating gate 1051 and the control gate 1053.

[0119] In this embodiment, the material of the inter-gate dielectric layer 1052 is a dielectric material. Specifically, the material of the inter-gate dielectric layer 1052 includes one or both of silicon oxide and silicon nitride. In this embodiment, the material of the inter-gate dielectric layer 1052 is a sandwich structure composed of silicon oxide, silicon nitride, and silicon oxide (ONO).

[0120] The semiconductor structure further includes: a select gate 110 (Select Gate, EG), located on the substrate 100 of the first region I facing away from the second region II, and the select gate 110 is spaced apart from the stacked gate 105.

[0121] The select gate 110 is used for access control of the memory cell, data transmission, and selection and erasure operations of the memory cell.

[0122] The semiconductor structure further includes: a floating gate dielectric layer 104 (Floating Gate oxide), located between the substrate 100 and the stacked gate 105, and between the substrate 100 and the select gate 110.

[0123] The floating gate dielectric layer 104 is used to isolate the stacked gate 105 and the substrate 100, and the select gate 110 and the substrate 100.

[0124] In this embodiment, the material of the floating gate dielectric layer 104 is a dielectric material, such as silicon oxide. In other embodiments, the floating gate dielectric layer 104 can also be a stack composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0125] In this embodiment, the semiconductor structure further includes: a sidewall layer 107, located on the sidewalls of the select gate and the stacked gate.

[0126] The sidewall layer 107 is used to protect the sidewalls of the select gate and the stacked gate.

[0127] The semiconductor structure further includes: source / drain doping regions 108, located in the substrate 100 between the select gate 110 and the stacked gate 105, and the source / drain doping regions 108 are adjacent to the doping region 101.

[0128] The source / drain doping regions 108 and the doping region 101 are adjacent to each other, so that when performing write or erase operations, the distance of charge transfer is shorter, thereby reducing the time required for write and erase operations, reducing the diffusion and leakage of charges in the flow channel, and improving the efficiency of programming and erase operations.

[0129] In this embodiment, the source / drain doping regions 108 are doped with P-type ions, and the P-type ions include one or more of B, Ga, and In.

[0130] Specifically, the source / drain doping regions 108 include lightly doped drain regions 1081 (Lightly Doped Drain, LDD) and heavily doped regions 1082 located on top of the lightly doped drain regions 1081. The lightly doped drain regions 1081 are used to change the electric field distribution, and the heavily doped regions 1082 are used to reduce the resistance and provide better current transmission ability.

[0131] It should be noted that the source-drain doping regions 108 are also located in the substrate on the side of the selection gate 110 away from the stacked gate 105, and in the substrate on the side of the stacked gate 105 away from the selection gate 110.

[0132] The semiconductor structure can be formed by the formation method described in the foregoing embodiments, or can be formed by other formation methods. For the specific description of the semiconductor structure in this embodiment, reference can be made to the corresponding description in the foregoing embodiments, and details are not repeated herein.

[0133] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, comprising: providing a substrate; doping a partial region of the substrate to form a doped region, the doped region including a first region, a second region, and a third region arranged in sequence; thinning the doped regions of the first region and the second region to make the overall thinned doped region in a stepped shape, wherein the top of the doped region in the thinned first region is lower than the top of the doped region in the third region, the doped region in the second region is etched into a transition portion with inclined sidewalls, and the bottom end of the inclined sidewall of the transition portion is connected to the top of the doped region in the first region, and the top end of the inclined sidewall of the transition portion is connected to the top of the doped region in the third region; after performing the thinning process, a stacked gate is conformally formed to cover the doped region, and the stacked gate includes: a floating gate, a gate dielectric layer located on the floating gate, and a control gate located on the gate dielectric layer.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, a dry etching process is used to thin the doped regions of the first region and the second region.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The process parameters of the dry etching include: the etching gas includes one or more of CF 4 , HBr and O 2 , the bias power is 200 W to 1000 W, and the chamber pressure is 10 mTorr to 50 mTorr.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, in the step of thinning the doped regions of the first region and the second region, the distance from the top of the doped region in the first region to the top of the doped region in the third region is 200 angstroms to 500 angstroms.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, in the step of performing the thinning process, the angle between the top of the doped region in the first region and the inclined sidewall in the transition portion is 90° to 120°, and the angle between the top of the doped region in the third region and the inclined sidewall in the transition portion is 90° to 120°.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, in the step of thinning the doped regions of the first region and the second region, the angle formed by the inclined sidewall in the transition portion and the top of the doped region in the first region is equal to the angle formed by the inclined sidewall in the transition portion and the top of the doped region in the third region.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, the method for forming the semiconductor structure further includes: after thinning the doped regions of the first region and the second region, before forming the stacked gate, removing a partial thickness of the doped regions in the first region and the second region.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, the step of removing a partial thickness of the doped regions in the first region and the second region includes: performing a high-temperature oxidation treatment on the surface of the doped regions in the first region and the second region to form an oxide layer; after performing the high-temperature oxidation treatment, removing the oxide layer.

9. The method for forming a semiconductor structure according to claim 7, characterized in that, During the process of removing a partial thickness of the doped regions in the first region and the second region, a partial thickness of the doped region in the third region is also removed.

10. The method for forming a semiconductor structure according to claim 7, characterized in that, In the step of removing a partial thickness of the doped regions in the first region and the second region, the thickness of the doped regions removed from the first region and the second region is 80 angstroms to 110 angstroms.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, In the step of forming a stacked gate on the doped region, the stacked gate is also formed on the substrate in partial regions on both sides of the doped region.

12. The method for forming a semiconductor structure according to claim 1, characterized in that, During the process of thinning the doped regions in the first region and the second region, the substrate on the side of the first region facing away from the second region is also thinned; In the step of forming the stacked gate, a select gate is also formed on the substrate of the first region facing away from the second region, and the select gate is spaced apart from the stacked gate.

13. The method for forming a semiconductor structure according to claim 12, characterized in that, The method for forming the semiconductor structure further includes: after forming the stacked gate and the select gate, forming source / drain doped regions in the substrate between the select gate and the stacked gate, and the source / drain doped regions are adjacent to the doped regions.

14. A semiconductor structure, characterized in that, including: a substrate; a doped region, located in a partial region of the substrate, the doped region is in a stepped shape, and the doped region includes a first region, a second region, and a third region arranged in sequence; the top of the doped region in the first region is lower than the top of the doped region in the third region, the doped region in the second region includes a transition portion having an inclined sidewall, and the bottom end of the inclined sidewall of the transition portion is connected to the top of the doped region in the first region, and the top end of the inclined sidewall of the transition portion is connected to the top of the doped region in the third region; a stacked gate, conformally covering the doped region, and the stacked gate includes: a floating gate, a gate dielectric layer located on the floating gate, and a control gate located on the gate dielectric layer.

15. The semiconductor structure according to claim 14, characterized in that, The included angle between the top of the doped region in the first region and the inclined sidewall in the transition portion is 90° to 120°, and the included angle between the top of the doped region in the third region and the inclined sidewall in the transition portion is 90° to 120°.

16. The semiconductor structure according to claim 14, characterized in that, The included angle formed by the inclined sidewall in the transition portion and the top of the doped region in the first region is equal to the included angle formed by the inclined sidewall in the transition portion and the top of the doped region in the third region.

17. The semiconductor structure according to claim 14, characterized in that, The distance from the top of the doped region in the first region to the top of the doped region in the third region is 200 angstroms to 500 angstroms.

18. The semiconductor structure according to claim 14, characterized in that, The stacked gate is also located on the substrate in partial regions on both sides of the doped region.

19. The semiconductor structure according to claim 14, wherein, the top of the substrate on the side of the first region facing away from the second region is flush with the top of the doped region in the first region; the method for forming the semiconductor structure further includes: selecting a gate located on the substrate of the first region facing away from the second region, and the selected gate is spaced apart from the stacked gate.

20. The semiconductor structure according to claim 19, wherein, the semiconductor structure further includes: source / drain doping regions located in the substrate between the selected gate and the stacked gate, and the source / drain doping regions are adjacent to the doped region.

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