Device with sidewalls fabricated at predetermined locations in the vertical direction and process for fabricating the same

Abstract

A device and its manufacturing process for fabricating sidewalls at predetermined positions in a vertical direction are disclosed. According to an embodiment, the semiconductor device may include a first constituent device on a substrate and a second constituent device stacked on the first constituent device. Each of the first and second constituent devices includes: a first source / drain layer; a second source / drain layer above the first source / drain layer; a channel layer extending vertically from the sidewall of the first source / drain layer to the sidewall of the second source / drain layer; and a gate stack on the side of the channel layer opposite to the sidewalls of the first and second source / drain layers. Between the gate stack of the first constituent device and the gate stack of the second channel device, a dielectric layer extends vertically from the sidewall of the second source / drain layer of the first constituent device to the sidewall of the first source / drain layer of the second constituent device.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically, to a device and a manufacturing process thereof for fabricating sidewalls at predetermined positions in a vertical direction. Background Technology

[0002] Vertical channel transistor (VCT) technology is considered one of the key technologies for increasing integration density and extending Moore's Law. Vertical structure devices place many new demands on thin-film deposition and etching processes, making the fabrication and structural improvement of vertical devices more difficult. Current methods aim to reduce manufacturing difficulty by adding self-aligned structures to the structural design.

[0003] In addition, VCT currently lacks the corresponding spacer technology in the vertical direction, making it technically challenging to achieve a vertical device structure. Summary of the Invention

[0004] In view of this, the purpose of this disclosure is at least in part to provide a device for manufacturing a sidewall at a predetermined position in the vertical direction and a manufacturing process thereof.

[0005] According to one aspect of this disclosure, a semiconductor device is provided, including a first constituent device on a substrate and a second constituent device stacked on the first constituent device. Each of the first and second constituent devices includes: a first source / drain layer; a second source / drain layer above the first source / drain layer; a channel layer extending vertically from a sidewall of the first source / drain layer to a sidewall of the second source / drain layer; and a gate stack on a side of the channel layer opposite to the sidewalls of the first and second source / drain layers. Between the gate stack of the first constituent device and the gate stack of the second channel device, a dielectric layer extends vertically from a sidewall of the second source / drain layer of the first constituent device to a sidewall of the first source / drain layer of the second constituent device.

[0006] According to another aspect of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming on a substrate a vertically stacked layer comprising, in sequence: a first source / drain defining layer, a channel defining layer, and a second source / drain defining layer of a first device, a first source / drain defining layer, a channel defining layer, and a second source / drain defining layer of a second device, and a second dopant source layer; forming a sidewall defining layer on the sidewalls of the vertically stacked layer; driving dopants from the first dopant source layer and the second dopant source layer into the sidewall defining layer, thereby forming doped regions in the sidewall defining layer corresponding to the first dopant source layer and the second dopant source layer, respectively; selectively etching the sidewall defining layer to retain the doped regions therein while removing the remainder; forming a channel layer extending between the sidewalls on the sidewalls of the vertically stacked layer; and forming a gate stack on the side of the channel layer opposite to the sidewalls, wherein the doped regions define sidewalls between adjacent gate stacks in the vertical direction.

[0007] According to another aspect of this disclosure, an electronic device is provided, including the aforementioned semiconductor device.

[0008] According to embodiments of this disclosure, vertical sidewalls are implemented, making it easier to manufacture vertical devices, especially stacked vertical devices. Attached Figure Description

[0009] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0010] Figures 1(a) to 21 The illustrations schematically depict some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure;

[0011] Figures 22(a) to 26 The illustration schematically depicts a process using a support structure according to an embodiment of the present disclosure.

[0012] Throughout the accompanying drawings, the same or similar reference numerals denote the same or similar parts. Detailed Implementation

[0013] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0014] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0015] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0016] This disclosure may be presented in various forms, some of which are described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation) but also etch selectivity. In the following description, the desired etch selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etch selectivity relative to other layers exposed to the same etch formulation.

[0017] Figures 1(a) to 21 The illustrations schematically depict some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure.

[0018] like Figure 1(a) and 1(b) As shown in the top view and the cross-sectional view along line AA′, a substrate 1001 is provided. This substrate 1001 can be of various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SO1) substrates, and compound semiconductor substrates such as SiGe substrates. For ease of explanation, a bulk Si substrate will be used as an example in the following description. Here, a silicon wafer is provided as the substrate 1001.

[0019] On the substrate 1001, the following layers may be formed sequentially: a first source / drain defining layer 1003, a channel defining layer 1005, and a second source / drain defining layer 1007 for a first constituting device; a first dopant source layer 1009; a first source / drain defining layer 1011, a channel defining layer 1013, and a second source / drain defining layer 1015 for a second constituting device; and a second dopant source layer 1017.

[0020] The source / drain defining layers 1003, 1007, 1011, and 1015 can be used to form or define the source / drain layers of the first and second constituent devices, and may include materials that are etch-selective relative to the channel defining layers 1005 and 1013 and the doped source layers 1009 and 1017.

[0021] The channel defining layers 1005 and 1013 can define the positions of the channels of the first constituent device and the second constituent device, respectively, and can include materials that have etch selectivity relative to the source / drain defining layers 1003, 1007, 1011, 1015 and the dopant source layers 1009, 1017.

[0022] The first dopant source layer 1009 and the second dopant source layer 1017 contain dopants such as boron (B) so as to be used as a diffusion source for dopants in subsequent processes.

[0023] According to embodiments of this disclosure, non-single-crystal devices or single-crystal devices can be formed.

[0024] In one example, an indium gallium zinc oxide (IGZO) transistor can be formed. In this case, the source / drain defining layers 1003, 1007, 1011, and 1015 can comprise a metal such as tungsten (W), and each has a thickness of, for example, about 20 nm to 200 nm. Considering etching selectivity, the channel defining layers 1005 and 1013 can comprise oxides (e.g., silicon oxide), and have a thickness of, for example, about 20 nm to 50 nm. The first doped source layer 1009 and the second doped source layer 1017 can be formed as an amorphous structure, such as a polycrystalline film or an amorphous film. For example, the first doped source layer 1009 and the second doped source layer 1017 can comprise a silicon (Si) film with a thickness of, for example, about 20 nm to 200 nm, containing, for example, about 0.1% to 5% dopant. These layers can be formed by, for example, deposition such as chemical vapor deposition (CVD).

[0025] Here, using a silicon film can facilitate processing it together with the sidewall defining layer in subsequent processes. However, this disclosure is not limited thereto. For example, the first dopant source layer 1009 or the second dopant source layer 1017 may also comprise a dielectric material containing dopant, such as an oxide.

[0026] In another example, the aforementioned layers may be, for example, single-crystal layers formed by epitaxial growth, and each layer may include a material selected according to the etch selectivity described above. For example, non-Si-based transistors such as GaAs transistors may be formed, and each layer may have the desired etch selectivity by varying the elemental ratios and / or including different elements. Alternatively, Si-based transistors may be formed, and each layer may include, for example, Si or SiGe, to have the desired etch selectivity.

[0027] A hard mask for patterning can be formed on top of the aforementioned material layers. In this example, an etch stop layer 1019, a core mold layer 1021, and a hard mask layer 1023 can be formed by deposition. For example, the etch stop layer 1019 may include an oxide with a thickness of about 1 nm to 10 nm; the core mold layer 1021 may include polysilicon with a thickness of about 50 nm to 150 nm; and the hard mask layer 1023 may include a nitride (e.g., silicon nitride) with a thickness of about 30 nm to 100 nm. Note that, depending on the patterning process, the hard mask can have different numbers of layers and can be made of different materials.

[0028] The active region can be defined from the aforementioned layers. According to embodiments of this disclosure, the definition of the active region can be based on sidewall image transfer (SIT) technology to improve pattern size control.

[0029] For example, such as Figure 2(a) and 2(b) As shown in the top view and the cross-sectional view along line AA′, respectively, photoresist (not shown) can be formed on the hard mask layer 1023 and patterned into stripes extending along a first direction (e.g., the vertical direction within the plane of the paper in the top view of FIG. 2(a)). Using this patterned photoresist as an etching mask, the hard mask layer 1023 and the mandrel layer 1021 are sequentially anisotropically etched by, for example, reactive ion etching (RIE) in the vertical direction, transferring the photoresist pattern into the hard mask layer 1023 and the mandrel layer 1021. Etching can stop at the etch stop layer 1019. Here, the etch stop layer 1019 can also be further anisotropically etched. Afterwards, the photoresist can be removed.

[0030] Sidewalls can be formed on the sidewalls of the core mold layer 1021 on opposite sides in a second direction (e.g., the horizontal direction within the plane of the paper in the top view of FIG. 2(a)) that intersects (e.g., is perpendicular to) the first direction. For example, as Figure 3 As shown, a preliminary sidewall layer 1025p can be formed on the obtained structure by deposition. The preliminary sidewall layer 1025p can be formed in a substantially conformal manner (in... Figure 3In the illustration, for ease of illustration, such as to more clearly show the subsequently formed sidewalls and the active region defined therein, the film thickness of the vertically extending portion of the pre-sidewall layer 1025p has been enlarged, so that in the illustration, the film thickness of the vertically extending portion of the sidewall layer 1025p appears to be greater than the film thickness of the laterally extending portion (although they may be substantially equal to each other). Considering etching selectivity, the pre-sidewall layer 1025p may include nitrides. For example... Figure 4 As shown, the prepared sidewall layer 1025p can be anisotropically etched, for example, by a vertical RIE. The etching depth can be substantially equal to (or slightly greater than) the film thickness of its lateral extension. Thus, the vertical extension of the prepared sidewall layer 1025p can be left to form the sidewall 1025. Note that due to the control of the etching depth, the nitride hard mask layer 1023 can be retained in this example.

[0031] Isolation processes can be performed, such as forming trenches in the aforementioned layers to divide them into several vertically stacked sections, thereby defining the active region of the device. For example, as... Figure 5 As shown, the hard mask layer 1023 and the sidewall 1025 can be used as etching masks, and anisotropic etching can be performed on each layer on the substrate 1001 sequentially through, for example, a RIE in the vertical direction. Figure 5 The diagram shows vertically stacked structures isolated in a second direction (e.g., horizontal direction within the paper).

[0032] It should be noted that isolation can also be performed in the first direction (e.g., the direction perpendicular to the paper). For example, in the above combination Figure 2(a) and 2(b) In the described process, the hard mask layer 1023 and the core mold layer 1021 can be patterned as a shape defined in both a first direction and a second direction, such as a rectangle or square, rather than a strip extending along the first direction. In this case, the sidewall 1025 can be formed as a closed shape around the periphery of the pattern, such as a rectangular ring or a square ring. In combination Figure 5 In the described isolation process, using the hard mask layer 1023 and sidewall 1025 thus formed as etching masks, a vertical stack with dimensions defined in both the first and second directions can be obtained. Alternatively, isolation can be performed later. Different isolation process sequences do not affect device fabrication, but may result in different channel configurations.

[0033] Sidewall defining layers can be formed on vertically stacked sidewalls to subsequently define sidewalls on the vertically stacked sidewalls. For example, as Figure 6As shown, the sidewall defining layer 1027 can be formed in a substantially conformal manner. As described above, in this embodiment, the sidewall defining layer 1027 may include a silicon film for processing together with the dopant source layer in subsequent processes. The silicon film may be a non-monocrystalline silicon film, such as a polycrystalline silicon film or an amorphous silicon film (e.g., in the case of forming a non-monocrystalline transistor), and may be formed by deposition. Alternatively, the silicon film may be a monocrystalline silicon film (e.g., in the case of forming a monocrystalline transistor), and may be formed by (selective) epitaxial growth. In the selective epitaxial growth process, the silicon film may not be formed on the hard mask layer 1023 and the sidewall 1025. The formed silicon film may not be intentionally doped, and its thickness may be, for example, about 40 nm to 80 nm. The main reason for using a silicon film here is that the silicon film can have etching selectivity due to different doping concentrations. Alternatively, other materials that can have etching selectivity due to different doping concentrations may be selected, even dielectric materials.

[0034] The sidewall defining layer 1027 thus formed extends on the vertically stacked vertical sidewalls (and top surface). The sidewalls, self-aligned to the dopant source layer, can be defined by diffusion doping. For example, as... Figure 7 As shown, annealing can be performed to drive or diffuse the dopants in the first dopant source layer 1009 and the second dopant source layer 1017 into the sidewall defining layer 1027. Specifically, the dopants can diffuse laterally from the first dopant source layer 1009 and the second dopant source layer 1017 into the sidewall defining layer 1027, and the dopants entering the sidewall defining layer 1027 can diffuse upward and downward, thereby defining a doped region 1029 in the sidewall defining layer 1027 in the vertical direction.

[0035] Here, the upward and downward diffusion conditions can be substantially the same, and therefore the upward and downward diffusion ranges can be substantially the same. Therefore, the doped regions 1029 at the ends of the first dopant source layer 1009 and the second dopant source layer 1017 can be vertically symmetrical with respect to the respective dopant source layers; that is, the upward height from the end of the respective dopant source layer can be substantially equal to the downward height from the end of the respective dopant source layer.

[0036] When the materials and thicknesses of the first dopant source layer 1009 and the second dopant source layer 1017 are substantially the same, as are the types and concentrations of dopants therein, the diffusion from the first dopant source layer 1009 and the second dopant source layer 1017 into the sidewall defining layer 1027 can also be substantially the same. Therefore, the doped region at the end of the first dopant source layer 1009 and the doped region at the end of the second dopant source layer 1017 can have substantially the same height.

[0037] Since the doped region 1029 is defined by diffusion from the first dopant source layer 1009 and the second dopant source layer 1017, it can be self-aligned with the first dopant source layer 1009 and the second dopant source layer 1017. Furthermore, the degree of diffusion can be controlled by controlling the annealing process parameters. Therefore, the position and height of the doped region 1029 (and the sidewalls defined theretherein) can be well controlled.

[0038] Here, although each source / drain defining layer may also include dopants, the type and / or concentration of dopants in the dopant source layer can be appropriately selected so that even if diffusion originating from the source / drain defining layer exists in the sidewall defining layer, the doped region 1029 caused by diffusion originating from the dopant source layer can still be etch-selective relative to the rest of the sidewall defining layer due to the doping type and / or concentration. Therefore, although the doped region 1029 may extend on a portion of the sidewall of each source / drain defining layer, it may not extend to the entire sidewall of each source / drain defining layer.

[0039] like Figure 8 As shown, the sidewall defining layer 1027 in which the doped regions 1029 are formed can be selectively etched. An etching formulation can be chosen such that the doped regions 1029 are substantially preserved while other portions of the sidewall defining layer 1027 are removed. This can be due to different etching rates resulting from varying doping concentrations in the sidewall defining layer 1027.

[0040] Therefore, the doped region 1029 can be left on the vertically stacked sidewalls (self-aligned to the dopant source layers 1009, 1017). When the sidewall defining layer 1027 is a dielectric material, this doped region 1029 can directly constitute the sidewall. Alternatively, when the sidewall defining layer 1027 is, for example, a silicon film, the sidewall can be defined by the doped region 1029 through oxidation or replacement processes as described below. Hereinafter, for convenience, the doped region 1029 left on the vertically stacked sidewalls will be referred to as a sidewall.

[0041] Sidewall 1029 defines a channel layer forming region on vertically stacked sidewalls. More specifically, the channel layer can be formed on vertically stacked sidewalls between adjacent sidewalls 1029 in the vertical direction.

[0042] For example, such as Figure 9As shown, the pre-channel layer 1031p can be formed in a substantially conformal manner. The pre-channel layer 1031p may include a suitable semiconductor material. In this embodiment, the pre-channel layer 1031p may include a silicon film. Similarly, the pre-channel layer 1031p may include a single-crystal material (e.g., in the case of forming a single-crystal transistor) and can be formed, for example, by epitaxial growth; or, it may include a non-single-crystal material (e.g., in the case of forming a non-single-crystal transistor) and can be formed, for example, by deposition. The formed silicon film may be undoped or lightly doped to adjust the device threshold voltage (Vth). t ).

[0043] On the pre-trench layer 1031p, a sacrificial gate can be formed to facilitate the subsequent formation of a self-aligned gate stack. For example, the pre-sacrificial gate layer 1033p can be formed by deposition such as CVD. The pre-sacrificial gate layer 1033p may include oxide and may be formed in a substantially conformal manner, and its portion extending between the sidewalls 1029 may cover the pre-trench layer 1031p and at least partially fill or even substantially completely fill the voids between adjacent sidewalls 1029 in the vertical direction (after the formation of the pre-trench layer 1031p).

[0044] The continuously extending pre-channel layer 1031p can be separated into portions extending between the first source / drain defining layers and the second source / drain defining layers of each device. For example, as... Figure 10 As shown, the pre-sacrificial gate layer 1033p and pre-channel layer 1031p formed as described above can be anisotropically etched, for example, using a vertical RIE. Thus, the pre-sacrificial gate layer 1033p and pre-channel layer 1031p can remain below each sidewall 1029 and can (substantially completely) overlap with the sidewall 1029 in a top view. The remaining pre-channel layer 1031p can form the channel layer 1031, and the remaining pre-sacrificial gate layer 1033p can form the sacrificial gate 1033, extending between adjacent sidewalls 1029.

[0045] If the sidewall 1029 is not a dielectric as described above (e.g., a silicon film in this embodiment), the sidewall 1029 can be further processed to give it electrical insulation properties.

[0046] For example, at least a surface portion of the sidewall 1029 can be oxidized to an oxide using an oxidation process. When the dopant source layers 1009 and 1017 are also silicon films, they may not be sufficiently oxidized during the oxidation process because they are located within the stack. If electrical isolation is required between the first and second constituent devices, then in the above-described combination... Figure 1(a) and 1(b)In the aforementioned process, an additional dielectric layer can be formed between the doped source layers 1009 and 1017 and the source / drain defining layers. For example, as shown in FIG11(a), dielectric layer 1035 can be formed between the source / drain defining layer 1007 and the first doped source layer 1009, dielectric layer 1037 can be formed between the first doped source layer 1009 and the source / drain defining layer 1011, and dielectric layer 1039 can be formed between the source / drain defining layer 1015 and the second doped source layer 1017. However, electrical isolation between the first and second constituent devices is not necessary. Depending on the device design, the first and second constituent devices can be electrically connected to each other. In this case, the doped silicon films 1009 and 1017 can even remain between the first and second constituent devices. As shown in FIG11(b), the oxidation process can convert at least a surface portion or even completely of the sidewall 1029 into oxide 1041 to achieve electrical isolation with the adjacent channel layer. Additionally, the ends of the channel layer may also be oxidized due to the oxidation process. The process parameters in the oxidation process can be controlled so that the vertical portions of the channel layer 1031 extending on the sidewalls of the vertical stack remain unoxidized.

[0047] According to another embodiment, the sidewalls 1029 (and the dopant source layers 1009, 1017) can be replaced with a dielectric material. For example, as shown in FIG12(a), photoresist 1043 can be formed on the resulting structure and patterned as part of the masking structure. Using the patterned photoresist 1043 as an etching mask, the sidewalls 1029 and the dopant source layers 1009, 1017 (both silicon films in this embodiment) are selectively etched, for example, by wet etching. Thus, a portion of the sidewalls 1029 (e.g., the sidewalls on the right sidewall of the vertically stacked structure in FIG12(a)) and a portion of the dopant source layers 1009, 1017 can be removed. Here, the reason for not removing all of the dopant source layers 1009, 1017 is at least in part to avoid the collapse of the vertical stack. Afterward, the photoresist 1043 can be removed. As shown in Figure 12(b), the voids left by the partial removal of dopant source layers 1009 and 1017 can be filled with a dielectric material such as oxide by deposition such as CVD followed by etching back such as vertical RIE. The dielectric material can fill the spaces between adjacent vertical channel layers (and the sacrificial gates formed thereon) to form sidewalls 1045. Note that the sidewalls above the uppermost channel layer may not be re-formed, but this does not affect subsequent processes. The remaining sidewalls 1029 and dopant source layers 1009 and 1017 can then be processed in a similar manner. For example, as shown in Figure 12(c), they can be removed by selective etching, and then, as shown in Figure 12(d), sidewalls 1047 can be formed by filling with a dielectric material such as oxide. In Figure 12(d), the two-filled dielectric materials are shown as a single unit.

[0048] Since the sidewalls may take different forms, for convenience, the following illustration will still use the sidewall 1029 obtained from the previous sidewall-defined layer as an example.

[0049] Return to reference Figure 10 Device fabrication can be achieved by replacing the sacrificial gate 1033 with a gate stack using an alternative gate process. The resulting gate stack can be self-aligned to the channel layer. If the above is combined... Figure 5 In the described isolation process, the vertical stack is isolated in two directions (e.g., horizontally within the paper and perpendicular to the paper). The channel layer can then be formed as a sidewall surrounding the vertical stack, and the gate stack can surround the channel layer on the outside of the channel layer. If the above is combined... Figure 5In the described isolation process, the vertical stack is isolated only in one direction (e.g., the horizontal direction within the paper plane). Then, isolation in another direction (e.g., the direction perpendicular to the paper plane) can be performed (before or after the alternative gate process). In this case, a channel layer can be formed on one sidewall of the vertical stack, and the gate stack can extend over the channel layer so that the channel layer is opposite to that sidewall of the vertical stack.

[0050] According to other embodiments, a multi-gate structure can be formed.

[0051] To avoid masking layers in subsequent etching processes (see...) Figure 14 The 1051 in the middle loses too much thickness, for example, Figure 13 As shown, a protective layer 1049 having the same material as the sidewall 1025 (nitride in this example) can first be formed, for example by deposition such as CVD. The protective layer 1049 can be formed in a substantially conformal manner.

[0052] like Figure 14 As shown, a masking layer 1051 can be formed on substrate 1001 by, for example, deposition such as CVD, to mask and protect the channel layer and sacrificial gate already formed on the sidewalls of the vertically stacked structure in subsequent processes. In this embodiment, the masking layer 1051 may comprise an oxide. The masking layer 1051 may be planarized, such as by chemical mechanical polishing (CMP), and the planarization process may stop at the mandrel layer 1021 (and thus the hard mask layer 1023 is removed during the planarization process). Subsequently, an opening may be made in the inner side of the vertically stacked structure based on the mandrel layer 1021 to allow another gate stack to be formed inside the channel layer.

[0053] If the above combination Figure 5 In the described isolation process, vertical stacking is isolated in only one direction (e.g., the horizontal direction within the paper plane), so isolation in another direction (e.g., the direction perpendicular to the paper plane) can be performed before the filling layer 1051 is formed.

[0054] like Figure 15(a) and 15(b) As shown in the top view and the cross-sectional view along line AA′, the core mold layer 1021 can be removed by selective etching, such as wet etching using a TMAH solution. This leaves sidewalls 1025 on the vertical stack. Here, the sidewalls 1025 take the form of two strips that are opposite each other and extend along the first direction. As mentioned above, the sidewalls 1025 may also be annular.

[0055] Using the sidewall 1025 as an etching mask, anisotropic etching can be performed sequentially on each layer of the substrate 1001 via, for example, a vertically oriented RIE. Etching can stop at the substrate 1001. Thus, the vertical stack can be separated into two sub-stacks corresponding to the two opposing strips of the sidewall 1025. Alternatively, the vertical stack can be formed into a ring structure corresponding to the sidewall 1025. Thus, each channel-defining layer is exposed on the inside. In the example where the channel-defining layers 1005 and 1013 include oxides, the oxide-based masking layer 1051 can also be etched away to a certain thickness.

[0056] Here, each source / drain defining layer is separated into portions corresponding to each device. Hereafter, the portion of the source / drain defining layer in the final device will be collectively referred to as the source / drain layer.

[0057] Next, an alternative gate process can be implemented.

[0058] For example, such as Figure 16 As shown, the masking layer 1051 (in this example, the channel defining layers 1005 and 1013, which are also oxides, can also be removed) can be removed by selective etching, such as wet etching, to remove the sidewalls 1025 and the protective layer 1049, and the sacrificial gate 1033, which is an oxide, can also be removed. In this example, when removing the masking layer 1051, the sidewalls 1045 and 1047 (and the sidewall defining layers 1009 and 1017) can be retained, for example, by selecting materials with appropriate etching selectivity for them (although they are all described as including oxides in the above embodiments, this is merely an example), or by retaining the sidewalls 1045 and 1047 (and the sidewall defining layers 1009 and 1017) as silicon films for later replacement, which will be described in further detail below.

[0059] A gate stack 1053 can be formed on the obtained structure. For example, a gate dielectric layer, a work function adjustment layer, and a gate conductor layer can be formed sequentially in a substantially conformal manner by deposition, such as CVD. For example, the gate dielectric layer may include a high-k gate dielectric such as HfO2, with a thickness of, for example, about 3 nm-5 nm; the work function adjustment layer may include (in combination with the gate dielectric layer) a material with an appropriate work function, such as a conductive metal nitride such as TiN, with a thickness of, for example, about 3 nm-5 nm; the gate conductor layer may include a conductive material, such as a metal such as W. The gate stack 1053, including the gate dielectric layer, the work function adjustment layer, and the gate conductor layer, can extend along the surface of the structure, such as... Figure 17 As shown.

[0060] like Figure 18As shown, the gate stack 1053 can be anisotropically etched, for example, by a vertical RIE. Thus, the gate stack 1053 can remain self-aligned with the channel layer within the region defined by the original sidewalls 1025. In particular, the gate stack 1053 can include two portions sandwiching the channel layer from opposite sides.

[0061] At this point, the basic fabrication of the component is complete. Next, the contact parts can be fabricated.

[0062] If the sidewalls 1045, 1047 and the sidewall limiting layers 1009, 1017 have not yet undergone oxidation or replacement treatment as described above (see above combination) Figure 11(a) and 11(b) Description or combination Figures 12(a) to 12(d) (as described), such alternative processing can be performed here.

[0063] For example, such as Figure 19 As shown, when a support structure is formed on the vertically stacked sides, the sidewalls 1045 and 1047, as well as the sidewall defining layers 1009 and 1017, can be removed by selective etching. The support structure will be described in further detail below.

[0064] like Figure 20 As shown, the interlayer dielectric layer 1055 can be formed on the substrate 1001, for example, by deposition such as CVD followed by a planarization process such as CMP. In this embodiment, the interlayer dielectric layer 1055 may include an oxide. The interlayer dielectric 1055 can fill the voids left by the removal of the sidewalls 1045, 1047 and the sidewall defining layers 1009, 1017.

[0065] Various contacts can be formed in the interlayer dielectric layer 1055. Figure 21 The diagram schematically illustrates the contact portion of one of the devices. (For example...) Figure 21 As shown, the contacts may include a contact 1057-1 electrically connected to a first source / drain layer, a contact 1057-2 electrically connected to a gate stack, a contact 1057-3 electrically connected to a second source / drain layer, and a contact 1057-4 electrically connected to another gate stack. Contacts for other devices can be formed similarly. Various methods exist in the art for forming contacts for vertical devices, which will not be described in detail here.

[0066] like Figure 21 As shown, the semiconductor device according to the embodiment may include a first constituent device and a second constituent device stacked on the first constituent device (see [link to embodiment]). Figure 21(The dotted coil in the image). The first constituent device may include a first source / drain layer 1003, a second source / drain layer 1007 above the first source / drain layer 1003, and a channel layer 1031 extending vertically from the sidewall of the first source / drain layer 1003 to the sidewall of the second source / drain layer 1007. Similarly, the second constituent device may include a first source / drain layer 1011, a second source / drain layer 1015 above the first source / drain layer 1011, and a channel layer 1031 extending vertically from the sidewall of the first source / drain layer 1011 to the sidewall of the second source / drain layer 1015. A gate stack 1053 is formed on the side of the channel layer 1031 opposite to the source / drain layer. As described above, the gate stack 1053 may be self-aligned with the channel layer 1031. In addition, a gate stack may also be formed on the other side of the channel layer 1031, which may also be self-aligned with the channel layer 1031.

[0067] A sidewall 1029' can be formed between the gate stacks 1053 of the first and second constituent devices (e.g., Figure 21 (As shown in the dashed box in the image). As described above, this sidewall can be formed separately or as part of the interlayer dielectric layer 1055. The position and size of the gate stack 1053 can be defined by the sidewall, so the gate stack 1053 and the sidewall can be self-aligned with each other. In the top view, the gate stack 1053 can overlap with the sidewall. The sidewalls of the gate stack 1053 can be substantially coplanar with the sidewalls of the sidewall.

[0068] As described above, the degree of upward and downward diffusion of the dopant in the sidewall defining layer can be substantially the same. Therefore, the extension height of the diffusion-defined sidewall on the sidewall of the second source / drain layer 1007 of the first device (the extent from which the first dopant source layer 1009 extends downward in the sidewall defining layer) can be substantially equal to the extension height on the sidewall of the first source / drain layer 1011 of the second device (the extent from which the first dopant source layer 1009 extends upward in the sidewall defining layer).

[0069] The portion of the doped source layer remaining between the second source / drain layer 1007 of the first constituent device and the first source / drain layer 1011 of the second constituent device (or replaced with a dielectric material as described above) can constitute an isolation layer between the first constituent device and the second constituent device. The sidewalls can be symmetrical about the top and bottom of the isolation layer.

[0070] Figures 22(a) to 26 The illustration schematically depicts a process using a support structure according to an embodiment of the present disclosure.

[0071] For example, in the above combination Figure 14 After the shielding layer 1051 is formed in the described process, as Figure 22(a) , 22(b)As shown in 22(c) (top view, cross-sectional view along line BB′, and cross-sectional view along line CC′, respectively), photoresist 1059 can be formed on the obtained structure and patterned by photolithography into a stripe occupying a certain range in a first direction (e.g., the vertical direction within the plane of the paper in FIG. 22(a)) extending, for example, along a second direction (e.g., the horizontal direction within the plane of the paper in FIG. 22(a)). Figure 23(a) , 23(b) As shown in 23(c) (top view, cross-sectional view along line BB′, and cross-sectional view along line CC′, respectively), the photoresist 1059 can be configured as an etching mask to anisotropically etch the layers on the substrate using, for example, a vertical RIE. The photoresist 1059 can then be removed. A support layer 1061 can be filled into the trenches (between the vertical stacks) formed on the substrate due to etching. For example, the support layer 1061 can be formed by depositing a dielectric material and planarizing the deposited dielectric material using CMP, which can stop at the sidewalls 1025. Considering etching selectivity in subsequent processes, the support layer 1061 can include, for example, oxide nitride (e.g., silicon oxynitride).

[0072] Subsequently, the process can be carried out similarly. For example, as described above in conjunction with 15(a) and 15(b), an opening can be made on the inner side of the vertical stack to obtain, as shown in the diagram. Figure 24(a) , 24(b) The structure shown in 24(c). Then, as described above, combined... Figures 16 to 18 As described above, gate stacks can be formed to obtain, as shown in the figure. Figure 25(a) and 25(b) The structure is shown. Then, as described above, sidewalls 1045 and 1047, as well as sidewall defining layers 1009 and 1017, can be removed. Figure 26 As shown, the vertical stacking can be maintained due to the presence of the support layer 1061.

[0073] The semiconductor devices according to embodiments of this disclosure can be applied to various electronic devices. For example, by integrating multiple such semiconductor devices and possibly other devices (e.g., other forms of transistors, etc.), an integrated circuit (IC) can be formed, thereby constructing an electronic device. Therefore, this disclosure also provides an electronic device including the aforementioned semiconductor devices. The electronic device may further include components such as a display screen that mates with the integrated circuit and a wireless transceiver that mates with the integrated circuit. Examples of such electronic devices include smartphones, personal computers (PCs), tablet computers, artificial intelligence devices, wearable devices, power banks, etc.

[0074] According to embodiments of this disclosure, a method for manufacturing a system-on-a-chip (SoC) is also provided. This method may include the methods described above. Specifically, multiple devices may be integrated on the chip, at least some of which are manufactured according to the methods of this disclosure.

[0075] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0076] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, comprising: a first constituent device on a substrate and a second constituent device stacked on the first constituent device, wherein each of the first constituent device and the second constituent device comprises: a first source / drain layer, a second source / drain layer above the first source / drain layer, a channel layer vertically extending from a sidewall of the first source / drain layer onto a sidewall of the second source / drain layer, and a gate stack on a side of the channel layer opposite the sidewalls of the first source / drain layer and the second source / drain layer, wherein, between the gate stack of the first constituent device and the gate stack of the second constituent device, a dielectric layer vertically extends from a sidewall of the second source / drain layer of the first constituent device onto a sidewall of the first source / drain layer of the second constituent device, wherein the dielectric layer comprises a material having etch selectivity with respect to surrounding interlayer dielectric layers, and further comprises a portion between the second source / drain layer of the first constituent device and the first source / drain layer of the second constituent device.

2. The semiconductor device of claim 1, wherein, a portion of the dielectric layer between the gate stack of the first constituent device and the gate stack of the second constituent device overlaps the gate stacks in a top view.

3. The semiconductor device of claim 1, wherein, sidewalls of a portion of the dielectric layer between the gate stack of the first constituent device and the gate stack of the second constituent device are substantially coplanar with sidewalls of the gate stacks.

4. The semiconductor device of claim 1, wherein, an extension height of the dielectric layer on a sidewall of the second source / drain layer of the first constituent device is substantially equal to an extension height of the dielectric layer on a sidewall of the first source / drain layer of the second constituent device.

5. The semiconductor device of claim 1, further comprising: an isolation layer between the second source / drain layer of the first constituent device and the first source / drain layer of the second constituent device, wherein the dielectric layer is substantially vertically symmetric with respect to the isolation layer.

6. The semiconductor device of claim 5, wherein, the isolation layer comprises a dopant for doping the dielectric layer.

7. The semiconductor device of claim 1, further comprising: another gate stack on a side of the channel layer opposite the sidewalls of the first source / drain layer and the second source / drain layer.

8. The semiconductor device of claim 1, wherein, sidewalls of the first source / drain layer of the first constituent device and the second source / drain layer are substantially coplanar with sidewalls of the first source / drain layer of the second constituent device and the second source / drain layer.

9. The semiconductor device of claim 8, wherein, the channel layer has substantially planar sidewalls.

10. The semiconductor device of claim 1, wherein, the first source / drain layer and the second source / drain layer comprise a metal, and the channel layer comprises an amorphous or polycrystalline semiconductor material.

11. The semiconductor device of claim 1, wherein, the first source / drain layer, the second source / drain layer, and the channel layer comprise a single crystalline semiconductor material.

12. The semiconductor device of claim 1, wherein, the gate stack is self-aligned to the channel layer.

13. A method of fabricating a semiconductor device, comprising: forming a vertical stack comprising, in order, a first source / drain defining layer, a channel defining layer, and a second source / drain defining layer of a first constituent device, a first dopant source layer, a first source / drain defining layer, a channel defining layer, and a second source / drain defining layer of a second constituent device, and a second dopant source layer on a substrate; forming a sidewall defining layer on sidewalls of the vertical stack; driving dopants from the first and second dopant source layers into the sidewall-defining layer, thereby forming in the sidewall-defining layer dopant regions corresponding to the first and second dopant source layers, respectively; selectively etching the sidewall-defining layer to leave the dopant regions therein and remove the rest of the sidewall-defining layer; forming a channel layer on the sidewalls of the vertical stack, the channel layer extending between the sidewalls; and forming a gate stack on a side of the channel layer opposite the sidewalls, wherein the dopant regions define sidewalls between vertically adjacent gate stacks.

14. The method of claim 13, wherein, The dopants diffuse from the first dopant source layer in the sidewall-defining layer to substantially the same extent upward and downward, and the dopants diffuse from the second dopant source layer in the sidewall-defining layer to substantially the same extent upward and downward.

15. The method of claim 13, wherein, The vertical stack is formed by deposition, the first and second source / drain-defining layers comprise metal, the first and second dopant source layers comprise amorphous or polycrystalline films containing dopants or dielectric layers, and the channel layer comprises amorphous or polycrystalline semiconductor material.

16. The method of claim 15, wherein, Forming the sidewall-defining layer comprises depositing an amorphous or polycrystalline silicon film in a substantially conformal manner.

17. The method of claim 13, wherein, The vertical stack is formed by epitaxial growth, the first and second source / drain-defining layers, the channel-defining layer, the second source / drain-defining layer, and the channel layer comprise single-crystalline semiconductor material, and the first and second dopant source layers comprise single-crystalline films containing dopants.

18. The method of claim 17, wherein, Forming the sidewall-defining layer comprises epitaxially growing a single-crystalline film.

19. The method of claim 13, further comprising: Oxidizing at least surface portions of the dopant regions remaining to oxides, or replacing the dopant regions with dielectric material, to define the sidewalls.

20. The method of claim 13, wherein, Forming the channel layer comprises: forming a preliminary channel layer in a substantially conformal manner; forming a sacrificial gate material layer on the preliminary channel layer; anisotropically etching the preliminary channel layer and the sacrificial gate material layer in a vertical direction with the sidewalls as a mask, the etched preliminary channel layer forming the channel layer, and the etched sacrificial gate material layer constituting a sacrificial gate.

21. The method of claim 20, wherein, Replacing the sacrificial gate with a gate stack self-aligned to the channel layer by a replacement gate process.

22. The method of claim 13, further comprising: forming an opening in the vertical stack to expose an interior of the vertical stack; removing the channel-defining layer via the opening; and forming another gate stack opposite the channel layer in a void left by the removal of the channel-defining layer.

23. The method of claim 13, further comprising: forming an opening in the vertical stack to expose an interior of the vertical stack; removing the first and second dopant source layers and the dopant regions remaining via the opening; filling a space left by the removal with a dielectric layer. ​

Images