Top gate IGZO (Indium Gallium Zinc Oxide) transistor with laminated gate dielectric and preparation method thereof

Abstract

The invention provides a top gate IGZO transistor with a laminated gate dielectric and a preparation method of the top gate IGZO transistor. The top gate IGZO transistor with the laminated gate dielectric comprises a silicon-based substrate; a SiO2 dielectric layer; an IGZO semiconductor thin film channel layer; a source electrode layer and a drain electrode layer; an yttrium oxide gate dielectric; a hafnium oxide gate medium and a gate metal layer. The hafnium oxide gate dielectric and the hafnium oxide gate dielectric form a high-k laminated gate dielectric layer; the yttrium oxide gate dielectric is firstly prepared through an electron beam coating process, then the hafnium oxide laminated gate dielectric grows on the surface of the yttrium oxide gate dielectric through an ALD process, and the yttrium oxide gate dielectric isolates contact between an ALD precursor source and an IGZO film. According to the invention, the quality of the gate dielectric is improved, the high-k-value yttrium oxide and hafnium oxide laminated gate dielectric layer structure is obtained, the interface state formed on the surface of an IGZO channel material is optimized and reduced, the lattice defects on the surface of an IGZO channel are reduced, the on-state current and carrier mobility are improved, the gate leakage current is reduced, and the device performance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS transistors (MOSFETs), especially the fourth-generation IGZO devices. Specifically, it relates to a top-gate IGZO transistor with a stacked gate dielectric and a method for manufacturing the same. Background Art

[0002] A MOS transistor (MOSFET) is a voltage-controlled field-effect transistor based on a metal-oxide-semiconductor structure, which regulates the drain-source current through the gate voltage. Its core structure includes a gate (isolated by an insulating layer), a source, a drain, and a substrate, and is divided into enhancement type (requiring an external voltage to form a conductive channel) and depletion type (with a channel existing by default). During operation, it relies on the gate voltage to control the formation of an inversion layer (such as the accumulation of electrons in an N-channel) to achieve conduction and cutoff. MOS transistors have high input impedance, low static power consumption, and high-frequency characteristics, and are widely used in digital circuits (such as CMOS logic), analog amplification, and power switching.

[0003] Currently, the transistors used in integrated circuit systems are mainly based on silicon-based CMOS (Complementary Metal-Oxide-Semiconductor) technology. As an indium-based oxide semiconductor, IGZO (indium gallium zinc oxide) plays a complementary technology role in current CMOS devices, especially showing unique advantages in the fields of low power consumption, high-density integration, and new computing architectures.

[0004] In 8K OLEDs, the mobility of the top-gate IGZO TFT (usually 10 - 30 cm 2 / Vs) supports reducing the pixel charging time to less than 1 μs and increasing the aperture ratio to 85%. For example, the sixth-generation IGZO panel mass-produced by Sharp adopts a top-gate etch-stop structure, reducing power consumption by 40%. Although the double-gate design can further reduce the leakage current (<10-22 A / μm), the gate signal delay increases in large-size panels, resulting in a decrease in the dynamic response speed. In the field of in-memory computing, the 2T0C DRAM cell developed by the Institute of Microelectronics uses the low leakage characteristics of the top-gate IGZO (the off-state current can be <10 -21 A / μm) to achieve a non-volatile storage cycle exceeding 10 14 times. Although the double-gate all-around structure can increase the cell density, it is necessary to solve the threshold voltage drift problem caused by hydrogen doping, and it is currently only in the laboratory verification stage.

[0005] The IGZO top-gate structure is significantly superior to the back-gate and double-gate designs in the display and storage fields due to its high process compatibility, controllable interface defects, and 3D integration potential. For example, the top-gate structure can directly grow a gate dielectric layer on top of the channel through the ALD (Atomic Layer Deposition) process, precisely controlling the oxygen vacancies and hydrogen doping issues at the interface. Although the double-gate structure has superior theoretical electrical properties, its complex manufacturing process and high cost limit large-scale commercial applications. In contrast, the top-gate device has lower process complexity and cost, as well as better stability in electrical performance and 3D integration compared to the double-gate device.

[0006] In the process of traditional IGZO top-gate devices, such as in the design of single-layer gate dielectric devices or multi-layer ALD gate dielectric devices, when using the ALD process to directly grow a single-layer hafnium oxide gate dielectric layer, interface states will be formed at the hafnium oxide and IGZO channel interface, improving Ohmic contact. At the same time, the precursor sources used in ALD will cause irreversible damage to the active layer IGZO. These damages come from the erosion of the active layer IGZO by the precursors (hafnium precursor source (dimethylamino hafnium) and oxygen precursor source (water)) during the ALD growth of hafnium oxide, generating defects related to oxygen and metal, as well as hydroxyl groups, increasing the leakage current. This defect-filled channel / GI interface will affect the transistor characteristics. Summary of the Invention

[0007] The object of the present invention is to provide a top-gate IGZO transistor with a stacked gate dielectric and its manufacturing method, which can not only improve the quality of the gate dielectric, obtain a high-k yttrium hafnium oxide stacked gate dielectric layer structure, but also reduce the interface states formed on the surface of the IGZO channel material through process optimization, reduce the lattice defects on the surface of the IGZO channel material, improve the on-state current and carrier mobility, reduce the effect of gate leakage current, and improve the device performance.

[0008] According to the first aspect of the object of the present invention, a top-gate IGZO transistor with a stacked gate dielectric is proposed, including:

[0009] Deposit SiO 2 dielectric layer on a silicon-based substrate to form a Si / SiO 2 structure;

[0010] An IGZO semiconductor thin film channel layer covering the upper surface of the SiO 2 dielectric layer;

[0011] Source electrode layers and drain electrode layers respectively disposed on the upper surface of the IGZO semiconductor thin film channel layer and at both sides;

[0012] Yttrium oxide gate dielectric on the upper surface of the source electrode layer and the drain electrode layer, and on the upper surface of the IGZO semiconductor thin film channel layer and at the middle position between the source electrode layer and the drain electrode layer;

[0013] A hafnium oxide gate dielectric grown on the upper surface of a yttrium oxide gate dielectric, the hafnium oxide gate dielectric extending from the yttrium oxide gate dielectric at the middle position between the source electrode layer and the drain electrode layer to cover the yttrium oxide gate dielectric on the upper surfaces of the source electrode layer and the drain electrode layer; and

[0014] A gate metal layer deposited on the upper surface of the hafnium oxide gate dielectric;

[0015] Wherein, the hafnium oxide gate dielectric on the upper surface of the IGZO semiconductor thin film channel layer and the hafnium oxide gate dielectric 106 form a high-k stacked gate dielectric layer;

[0016] The yttrium oxide gate dielectric is provided to be prepared by an electron beam coating process, attached to the upper surface of the IGZO semiconductor thin film channel layer, and constitutes a repair / insulation structure;

[0017] The hafnium oxide gate dielectric is provided to be grown on the surface of the yttrium oxide gate dielectric by ALD process, and during the growth process, the yttrium oxide gate dielectric isolates the contact between the precursor source used in the ALD process and the IGZO semiconductor thin film channel layer.

[0018] As an optional embodiment, the yttrium oxide gate dielectric is provided to be fabricated in the following manner:

[0019] A layer of metallic yttrium is deposited on the upper surface of the IGZO semiconductor thin film channel layer by electron beam coating, and then a high-k oxide layer is formed on the IGZO semiconductor thin film channel layer by annealing oxidation.

[0020] As an optional embodiment, the lattice damage of the IGZO semiconductor thin film channel layer is repaired during the annealing oxidation process of the metallic yttrium attached to the upper surface of the IGZO semiconductor thin film channel layer.

[0021] As an optional embodiment, both the source electrode layer and the drain electrode layer adopt a Ti / Au electrode layer, with the same thickness and both controlled within 60 - 80 nm.

[0022] As an optional embodiment, the thickness of the IGZO semiconductor thin film channel layer is controlled within 10 - 20 nm.

[0023] As an optional embodiment, the thickness of the yttrium oxide gate dielectric is less than that of the hafnium oxide gate dielectric.

[0024] As an optional embodiment, the thickness of the yttrium oxide gate dielectric is within 1 - 2 nm; the thickness of the hafnium oxide gate dielectric is within 8 - 10 nm.

[0025] As an optional embodiment, the gate metal layer is an Au metal layer, with the thickness controlled within 50 - 70 nm.

[0026] According to the second aspect of the object of the present invention, a method for manufacturing a top-gate IGZO transistor with a stacked gate dielectric is further provided, including the following steps:

[0027] Step 1: Deposit a SiO 2 dielectric layer on a silicon-based substrate to form a Si / SiO 2 structure;

[0028] Step 2: Sputter an IGZO thin film on the upper surface of the SiO 2 dielectric layer by magnetron sputtering, and control the thickness to be 10 - 20 nm;

[0029] Step 3: Spin-coat the surface of the Si / SiO 2 structure sputtered with the IGZO thin film by a spin coater, expose the corresponding pattern by photolithography technology, and etch the IGZO thin film to obtain an IGZO channel layer;

[0030] Step 4: Spin-coat again, use a lithography machine to expose the source electrode and the drain electrode, and deposit a certain thickness of metal by electron beam evaporation technology to form the source electrode and the drain electrode;

[0031] Step 5: After spin-coating again, expose the gate dielectric layer of the device. First, prepare a yttrium oxide gate dielectric by an electron beam evaporation instrument, and then grow a hafnium oxide gate dielectric layer on the basis of the yttrium oxide gate dielectric by ALD technology;

[0032] Step 6: Spin-coat again, expose the gate metal layer of the device, and then deposit to form the gate metal layer by electron beam evaporation technology.

[0033] With the top-gate IGZO transistor having a stacked gate dielectric and its manufacturing method according to the embodiments of the present invention above, while improving the quality of the gate dielectric, enhancing the material quality, and reducing the interface states between the material and the gate dielectric, the manufacturing yield can be improved. Since the single-layer yttrium oxide is prepared by an electron beam coater, it does not have step coverage, which increases the requirements for exposure accuracy and dose during the manufacturing process. Moreover, the low K value of the single-layer yttrium oxide cannot well meet the requirements for a high-K gate dielectric in two-dimensional devices. If ALD is used to grow a single layer of hafnium oxide, interface states will be formed at the interface between the hafnium oxide and the IGZO channel, improving the ohmic contact. Additionally, the precursor source used in ALD growth will also damage the IGZO, increasing the surface defects of the IGZO and the leakage current. Through the device design proposed by the present invention, a stacked gate dielectric is prepared. First, yttrium is deposited on the IGZO channel by electron beam coating to form a yttrium oxide gate dielectric, which plays an isolation and protection role, reducing the contact of the precursor in the subsequent ALD process with the active channel layer. Then, a hafnium oxide thin film gate dielectric is grown by the ALD method. Due to the excellent step coverage of ALD growth, this can not only reduce the ohmic contact, reduce the interface states, but also improve the manufacturing yield and reduce the requirements for the process.

[0034] Compared with the prior art, the manufacturing method of the top-gate IGZO transistor with a stacked gate dielectric according to the present invention proposes to first prepare a yttrium oxide gate dielectric by an electron beam coater and then form a stacked gate dielectric layer with the hafnium oxide gate dielectric grown by ALD under the manufacturing process of traditional IGZO devices (single-layer gate dielectric devices or multi-layer ALD gate dielectric devices), successfully preparing a top-gate IGZO transistor with a yttrium oxide / hafnium oxide stacked gate dielectric. Compared with the prior art, the significant advantages of the present invention are as follows:

[0035] 1) First, a layer of yttrium is deposited on the active layer by electron beam coating, and then a dense high-K oxide layer is formed on the active layer by annealing oxidation. This can not only act as a "passivation layer" to play an isolation role, blocking the erosion of the precursor source during the ALD growth of hafnium oxide and protecting the active layer channel (yttrium oxide can adhere to the surface of the IGZO active layer, reducing the contact between the precursor source and the active layer during the ALD growth of hafnium oxide and reducing the damage to the active layer), but also repair the lattice defects of the active layer and increase the on-state current. This is because when the coater sputters Y onto the active layer, due to the active characteristics of metallic Y, during the process of annealing and oxidizing Y into yttrium oxide, the lattice damage of the active layer will be repaired. At the same time, yttrium oxide can also act as an oxygen source, taking oxygen atoms from the surface of the active layer, resulting in an increase in oxygen vacancies on the surface of the IGZO channel. This is beneficial to the electron enrichment ability on the channel surface, thereby increasing the on-state current and improving the carrier mobility;

[0036] 2) On the basis of yttrium oxide gate dielectric, hafnium oxide gate dielectric is continuously grown by ALD process. Since single-layer yttrium oxide is produced by electron beam evaporation, it does not have step coverage. At the same time, as an oxide, IGZO does not have the ability to be thinned into a two-dimensional material due to the limitations of current instruments. Therefore, a thicker yttrium oxide film needs to be deposited to reduce the effect of gate leakage current. However, this does not conform to the original intention of improving device performance and thinning the gate dielectric. At the same time, due to the relatively low K value of yttrium oxide, the gate control ability of single-layer yttrium oxide will also be weak. Considering that electron beam deposited yttrium oxide does not have step coverage and a relatively low k value, ALD is used to grow high-k gate dielectric hafnium oxide on the basis of yttrium oxide gate dielectric. By utilizing the step coverage and high-k properties of ALD-grown hafnium oxide, not only the risk of gate leakage can be reduced but also the gate control ability can be improved. Yttrium oxide can adhere to the surface of the IGZO active layer, reducing the contact between the precursor source and the active layer during the ALD growth of hafnium oxide and minimizing the damage to the active layer.

[0037] 3) In the post-process annealing, under the same conditions (annealing at 200 °C for 30 min in air), the IGZO transistor with a yttrium oxide / hafnium oxide stacked gate dielectric has an on-state current that is one order of magnitude higher and a positive threshold voltage closer to 0 compared to the top-gate IGZO transistor with a single-layer hafnium oxide gate dielectric.

[0038] It should be understood that all combinations of the foregoing concepts and additional concepts described in greater detail below are considered to be part of the inventive subject matter of the present disclosure as long as such concepts are not mutually inconsistent. In addition, all combinations of the claimed subject matter are considered to be part of the inventive subject matter of the present disclosure.

[0039] The foregoing and other aspects, embodiments, and features of the teachings of the present invention can be more fully understood from the following description in conjunction with the accompanying drawings. Other additional aspects of the present invention, such as the features and / or beneficial effects of exemplary embodiments, will be apparent from the following description or will be learned through practice of the specific embodiments according to the teachings of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component shown in various figures can be represented by the same reference numeral. For clarity, not every component is labeled in each figure. Now, embodiments of various aspects of the present invention will be described by way of example and with reference to the drawings.

[0041] Figure 1 is a schematic structural diagram of a top-gate IGZO transistor with a stacked gate dielectric according to an embodiment of the present invention.

[0042] Figure 2 is a front view of the structure of a top-gate IGZO transistor with a stacked gate dielectric according to an embodiment of the present invention.

[0043] Figure 3 It is a schematic flow chart of a method for fabricating a top-gate IGZO transistor with a stacked gate dielectric according to an embodiment of the present invention.

[0044] Figure 4 It is an example of test comparison results between a top-gate IGZO transistor with a stacked gate dielectric and a single-layer hafnium oxide top-gate IGZO device according to an embodiment of the present invention.

[0045] Figure 5 It is according to Figure 4 in the test comparison diagram, the comparison result of the transfer characteristic curves of a yttrium oxide hafnium oxide stacked gate dielectric top-gate IGZO device and a single-layer hafnium oxide top-gate IGZO device when V ds = 1V is extracted. Detailed implementation manners

[0046] To better understand the technical content of the present invention, specific embodiments are hereby given and described in conjunction with the accompanying drawings as follows.

[0047] In the present disclosure, aspects of the present invention are described with reference to the accompanying drawings, in which many illustrative embodiments are shown. The embodiments of the present disclosure are not necessarily intended to cover all aspects of the present invention. It should be understood that the various concepts and embodiments introduced above, as well as those described in more detail below, can be implemented in any of many ways, because the concepts and embodiments disclosed in the present invention are not limited to any implementation manner. In addition, some aspects of the present invention can be used alone, or in any suitable combination with other aspects of the present invention.

[0048] {Embodiment 1}

[0049] Combined with Figure 1 、 Figure 2 the illustrated example of a top-gate IGZO transistor with a stacked gate dielectric, which includes a silicon-based substrate 100, a SiO 2 dielectric layer 101, an IGZO semiconductor thin film channel layer 102, a source electrode layer 103, a source electrode layer 104, a yttrium oxide gate dielectric 105, a hafnium oxide gate dielectric 106, and a gate metal layer 107.

[0050] As shown in Figure 1 、 Figure 2 , a SiO 2 dielectric layer 101 is deposited on the silicon-based substrate 100 to form a Si / SiO 2 structure. The SiO 2 dielectric layer 101 serves as a deposition substrate for the IGZO thin film on the one hand, and realizes electrical insulation between the IGZO thin film and the silicon-based substrate 100 on the other hand.

[0051] The IGZO semiconductor thin film channel layer 102 covers the upper surface of the SiO 2 dielectric layer.

[0052] On the upper surface of the IGZO semiconductor thin film channel layer 102 and at both side positions, a source electrode layer 103 and a source electrode layer 104 are respectively arranged, and the two are symmetrically distributed at both side positions.

[0053] On the upper surfaces of the source electrode layer 103 and the drain electrode layer 104, and on the upper surface of the IGZO semiconductor thin film channel layer 102 and at the middle position between the source electrode layer 103 and the drain electrode layer 104, a yttrium oxide gate dielectric 105 is provided.

[0054] On the upper surface of the yttrium oxide gate dielectric 105, a hafnium oxide gate dielectric 106 is continuously grown, as Figure 1 , 2 shown. The hafnium oxide gate dielectric 106 is particularly preferably grown by an ALD process, and extends from the yttrium oxide gate dielectric 105 at the middle position between the source electrode layer 103 and the drain electrode layer 104 to cover the yttrium oxide gate dielectric 105 on the upper surfaces of the source electrode layer 103 and the drain electrode layer 104.

[0055] As Figure 1 , 2 shown, a gate metal layer 107 is deposited on the upper surface of the hafnium oxide gate dielectric 106.

[0056] In an embodiment of the present invention, the hafnium oxide gate dielectric 106 on the upper surface of the IGZO semiconductor thin film channel layer 102 and the hafnium oxide gate dielectric 106 form a high-k stacked gate dielectric layer.

[0057] The aforementioned yttrium oxide gate dielectric 105 is provided to be prepared by an electron beam coating process, adhered to the upper surface of the IGZO semiconductor thin film channel layer 102, and forms a repair / insulation structure.

[0058] The aforementioned hafnium oxide gate dielectric 106 is provided to be grown on the surface of the yttrium oxide gate dielectric 105 by an ALD process, and during the growth process, the contact between the precursor source used in the ALD process and the IGZO semiconductor thin film channel layer 102 is isolated by the yttrium oxide gate dielectric 105.

[0059] It should be understood that the aforementioned source electrode layer 103, drain electrode layer 104, and gate metal layer 107 can all be led to the corresponding output electrodes through their respective metal leads to realize the output of signals. In particular, the metal leads are subjected to an insulation packaging process and are insulated from the conductive parts during detection. The output electrodes can be electrically connected to external devices, such as a computer system, a server, etc., to output the signals to the outside for signal analysis.

[0060] In a preferred embodiment, the yttrium oxide gate dielectric 105 is provided to be fabricated in the following manner:

[0061] A metal yttrium layer is deposited on the upper surface of the IGZO semiconductor thin film channel layer 102 by electron beam coating, and then a high-k oxide layer is formed on the IGZO semiconductor thin film channel layer 102 by annealing oxidation. The lattice damage of the IGZO semiconductor thin film channel layer 102 is repaired during the annealing oxidation process of the metal yttrium attached to the upper surface of the IGZO semiconductor thin film channel layer 102.

[0062] As an alternative embodiment, both the source electrode layer 103 and the drain electrode layer 104 adopt a Ti / Au electrode layer, with the same thickness and both controlled within 60 - 80 nm.

[0063] As an alternative embodiment, the thickness of the IGZO semiconductor thin film channel layer 102 is controlled within 10 - 20 nm.

[0064] As an alternative embodiment, the thickness of the yttrium oxide gate dielectric 105 is less than the thickness of the hafnium oxide gate dielectric 106.

[0065] As an alternative embodiment, the thickness of the yttrium oxide gate dielectric 105 is within 1 - 2 nm; the thickness of the hafnium oxide gate dielectric 106 is within 8 - 10 nm.

[0066] As an alternative embodiment, the gate metal layer 107 is an Au metal layer, with the thickness controlled within 50 - 70 nm.

[0067] {Example 2}

[0068] Combined with Figure 1 , Figure 2 , as Figure 3 shown in the process of preparing a top-gate IGZO transistor with a stacked gate dielectric, which includes the following steps:

[0069] Step 1, deposit a SiO 2 dielectric layer on a silicon-based substrate to form a Si / SiO 2 structure;

[0070] Step 2, sputter an IGZO thin film on the upper surface of the SiO 2 dielectric layer by magnetron sputtering, with the thickness controlled within 10 - 20 nm;

[0071] Step 3, spin-coat the surface of the Si / SiO 2 structure sputtered with the IGZO thin film by a spin coater, expose the corresponding pattern by photolithography, and etch the IGZO thin film to obtain an IGZO channel layer;

[0072] Step 4, spin-coat again, use a lithography machine to expose the source electrode and the drain electrode, and deposit a certain thickness of metal by electron beam coating technology to form the source electrode and the drain electrode;

[0073] Step 5: After secondary spin coating, expose the gate dielectric layer of the device. First, use an electron beam coater to prepare a yttrium oxide gate dielectric, and then grow a hafnium oxide gate dielectric layer on the basis of the yttrium oxide gate dielectric through the ALD process;

[0074] Step 6: Spin coat again and expose the gate metal layer of the device, and then use the electron beam coating process to deposit and form the gate metal layer.

[0075] The preparation process of a top-gate IGZO transistor with a stacked gate dielectric as an optional specific embodiment includes the following steps:

[0076] Step 1: Deposit a certain thickness of SiO 2 , as a dielectric layer, to form a Si / SiO 2 structure, with a total thickness of 300 - 400 nm;

[0077] Step 2: Sputter an IGZO thin film on the upper surface of the SiO 2 dielectric layer through magnetron sputtering, with the thickness controlled at 10 - 20 nm;

[0078] Step 3: Spin coat the surface of the Si / SiO 2 structure sputtered with the IGZO thin film through a spin coater, use the photolithography process to expose the corresponding pattern, and etch the IGZO thin film to obtain an IGZO channel layer;

[0079] Specifically: On the substrate of the Si / SiO 2 two-layer structure sputtered with the IGZO thin film, spin coat two layers of photoresist, namely LOR and S1813, through a spin coater, and then etch the IGZO thin film through laser direct writing exposure and dilute hydrochloric acid etching to form an IGZO channel layer, so that the IGZO becomes the channel region, and heat anneal on a heating table at 300 °C for 30 minutes;

[0080] Step 4: Spin coat again, use a lithography machine to expose the source electrode and the drain electrode, and use the electron beam coating process to deposit a certain thickness of metal to form the source electrode and the drain electrode;

[0081] Specifically: Spin coat two layers of photoresist, namely LOR and S1813, on the etched substrate through a spin coater, expose the source electrode and the drain electrode with a laser direct writer, and deposit 20 nm thick Ti and 50 nm thick Au through an electron beam coater to form the source and the drain;

[0082] Step 5: Spin coat again and expose the gate dielectric layer of the device. First, coat a yttrium oxide gate dielectric under the electron beam coater, and then grow a hafnium oxide gate dielectric based on the ALD process;

[0083] Specifically: On the substrate where the source and drain are formed, two layers of photoresist, LOR and S1813, are spin-coated by a spin coater, and then the gate insulating layer is exposed by a laser direct writer. First, a 2-nm-thick yttrium oxide gate dielectric is deposited by an electron beam coater, and then an 8-nm-thick hafnium oxide gate dielectric is grown by ALD.

[0084] Step 6: Spin-coat and expose the gate metal layer of the device again, and then use electron beam deposition to form the gate metal layer.

[0085] Specifically: On the substrate with the gate dielectric grown, two layers of photoresist, LOR and S1813, are spin-coated by a spin coater, and then the gate metal layer is exposed by a laser direct writer. 60 nm of Au is deposited by an electron beam coater to form the gate metal layer.

[0086] As an optional embodiment, the deposition of the SiO 2 dielectric layer can be prepared by existing semiconductor micro-nano processes, and the Si / SiO 2 two-layer structure is controlled within 300 - 400 nm.

[0087] The sputtering length of the IGZO is 10 μm to 80 μm, the width is 5 to 20 μm, and the thickness is 10 to 20 nm.

[0088] As an example, the length of the source and drain electrode layers is controlled to be at least 10 μm, the width is controlled to be at least 2 μm, and the thickness is above 60 nm.

[0089] As an example, the source and drain electrodes are Ti / Au metal electrodes with a thickness of 60 - 80 nm.

[0090] As an example, the gate dielectric layer is a stack composed of a yttrium oxide gate dielectric layer and a hafnium oxide gate dielectric layer, with a length of 30 - 90 μm, a width of 15 - 35 μm, a yttrium oxide thickness of 2 nm, and a hafnium oxide thickness of 10 nm.

[0091] As an example, the gate electrode is an Au metal electrode with a length of 20 - 80 μm, a width of 5 - 20 μm, and a thickness of 50 - 60 nm.

[0092] As Figure 1 、 2 shown, the parameters of the IGZO transistor prepared by the present invention are as follows:

[0093] Active layer: length 60 μm, width 30 μm, thickness 17 nm;

[0094] Source and drain electrodes: length 70 μm, width 10 μm, thickness 60 nm;

[0095] Gate dielectric: Yttrium oxide dielectric layer thickness 2nm, hafnium oxide dielectric layer thickness 8nm, length and width dimensions are both 90μm*30μm;

[0096] Gate metal: 80μm long, 20μm wide, 60nm thick;

[0097] Output electrode (pad): size is 150μm*150μm, thickness is 80nm.

[0098] {Example 3}

[0099] In this embodiment, we prepared a prototype of a top-gate IGZO transistor with a stacked gate dielectric according to the aforementioned process method, and also prepared a top-gate IGZO transistor with a hafnium oxide single-layer gate dielectric. The electrical parameters of the two devices were measured using a semiconductor analyzer, and performance indicators were obtained through data collation for comparison.

[0100] The test method is: use a semiconductor analyzer to measure, set a positive voltage between the source and drain, and then set the voltage at the gate to control the current between the source and drain through the gate voltage.

[0101] Analyze the results through the transfer characteristic curve and output curve: The transfer characteristic curve can be used to obtain I on ,I on / I off 、V th ,SS,μ n , g m , analyzed and extracted by origin data analysis software on ,I on / I off , SS, g is obtained by partial differentiation m and D it (The subthreshold swing method is suitable for rapid evaluation at the device level), and then the maximum transconductance method is used to extract μ n , the contact resistance can be obtained through the output curve.

[0102] Combination Figure 4 As shown in the figure a on the left, the test results of the top-gate IGZO device with a 10nm single-layer hafnium oxide gate dielectric with a width-to-length ratio of W / L=60 / 20μm are shown. V ds =0.5v~3V, V gs Transfer characteristic curve from -3 to 3V.

[0103] The right side of the graph b shows the test results of the top-gate IGZO device with 2nm yttrium oxide and 8nm hafnium oxide stacked gate dielectrics with a width-to-length ratio of W / L=60 / 20μm. The V gs From -3 to 3V, V ds Transfer characteristic curve from 0.5v to 3V.

[0104] Comparison Figure 4 From the test results of two different devices, it can be seen that for the test results in Figure b compared to those in Figure a, the △V th (threshold voltage drift) has a certain increase. The reason is that there are trace defects between the stacked gate dielectrics. However, the △V th is within an acceptable range and can be improved by subsequent annealing. At the same time, when the threshold voltages of the two are similar, the on-state current in the test results of Figure b has increased by 1 - 2 orders of magnitude. This is because during the process of coating yttrium oxide, yttrium oxide, as an oxygen source, will extract oxygen atoms from the surface of the active layer, resulting in an increase in oxygen vacancies on the surface of the IGZO channel, which is beneficial to the electron enrichment ability on the channel surface, thus improving the on-state current.

[0105] Based on Figure 4 the comparison of the test results, the comparison results of the transfer characteristics curves of the top-gate IGZO device with a stacked yttrium oxide hafnium oxide gate dielectric and the top-gate IGZO device with a single-layer hafnium oxide when V ds = 1V extracted from the figure are as follows:

[0106] Test results of the device with a stacked gate dielectric:

[0107] Ion = 292 μA, SS = 98 mV / dec, Vth = -0.7V, Ion / Ioff = 0.87E+6,

[0108] Gm is 141 μS, and the mobility μn = 29.5 cm 2 / (V*s).

[0109] Test results of the device with a single-layer gate dielectric:

[0110] Ion = 2.78 μA, SS = 199 mV / dec, Vth = -1.1V, Ion / Ioff = 0.68E+4

[0111] Gm is 1.51 μS, and the mobility μn = 4.9 cm 2 / (V*s).

[0112] Combining the above comparison of test results, as Figure 5 shown, the SS of the single-layer hafnium oxide device is 199 mV / dec, while the SS of the stacked gate dielectric device designed in the present invention is 98 mV / dec. This is because during the ALD growth of hafnium oxide, the damage to IGZO by the precursor source (single-layer hafnium oxide device), which includes oxygen and metal-related defects as well as some hydroxyl groups, increases the roughness, resulting in a decrease in the gate control ability.

[0113] Meanwhile, the positive shift of the threshold voltage of the stacked gate dielectric relative to that of the single-layer hafnium oxide and the increase of the on-state current by 1-2 orders of magnitude jointly confirm the enhancement and advantages of yttrium oxide in the stacked gate dielectric for the active layer material. Since the coating instrument sputters Y onto the active layer, due to the high chemical activity of Y, during the annealing process of Y to form yttrium oxide, the lattice damage of the active layer can be repaired. At the same time, yttrium oxide can also act as an oxygen source, absorbing oxygen atoms from the surface of the active layer, resulting in an increase in oxygen vacancies on the surface of the IGZO channel. This is beneficial to the electron enrichment ability on the channel surface, thereby increasing the on-state current and significantly improving the device performance.

[0114] Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those of ordinary skill in the technical field to which the present invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A top-gate IGZO transistor with a stacked gate dielectric, characterized in that: include: Depositing a SiO2 dielectric layer (101) on a silicon-based substrate (100) to form a Si / SiO2 structure; An IGZO semiconductor thin film channel layer (102) covers the upper surface of the SiO2 dielectric layer; A source electrode layer (103) and a drain electrode layer (104) are respectively arranged on the upper surface of the IGZO semiconductor thin film channel layer (102) and at both sides thereof; An yttrium oxide gate dielectric (105) is provided on the upper surfaces of the source electrode layer (103) and the drain electrode layer (104), and on the upper surface of the IGZO semiconductor thin film channel layer (102) and located between the source electrode layer (103) and the drain electrode layer (104); A hafnium oxide gate dielectric (106) grown on the upper surface of the yttrium oxide gate dielectric (105), wherein the hafnium oxide gate dielectric (106) extends from the yttrium oxide gate dielectric (105) in the middle of the source electrode layer (103) and the drain electrode layer (104) to cover the yttrium oxide gate dielectric (105) on the upper surface of the source electrode layer (103) and the drain electrode layer (104); and A gate metal layer (107) deposited on the upper surface of the hafnium oxide gate dielectric (106); Wherein, the hafnium oxide gate dielectric (106) on the upper surface of the IGZO semiconductor thin film channel layer (102) and the hafnium oxide gate dielectric (106) form a high-k stacked gate dielectric layer; The yttrium oxide gate dielectric (105) is prepared by an electron beam coating process and is attached to the upper surface of the IGZO semiconductor thin film channel layer (102) to form a repair / isolation structure; The hafnium oxide gate dielectric (106) is arranged to be grown on the surface of the yttrium oxide gate dielectric (105) through an ALD process, and during the growth process, the yttrium oxide gate dielectric (105) isolates the contact between the precursor source used in the ALD process and the IGZO semiconductor thin film channel layer (102).

2. The top-gate IGZO transistor with a stacked gate dielectric according to claim 1, characterized in that: The yttrium oxide gate dielectric (105) is configured to be manufactured in the following manner: A layer of metal yttrium is plated on the upper surface of an IGZO semiconductor thin film channel layer (102) by electron beam plating, and then a high-k oxide layer is formed on the IGZO semiconductor thin film channel layer (102) by annealing and oxidation.

3. The top-gate IGZO transistor with a stacked gate dielectric according to claim 2, characterized in that: The metal yttrium attached to the upper surface of the IGZO semiconductor thin film channel layer (102) repairs the lattice damage of the IGZO semiconductor thin film channel layer (102) during the annealing and oxidation process.

4. The top-gate IGZO transistor with a stacked gate dielectric according to claim 1, characterized in that: The source electrode layer (103) and the drain electrode layer (104) are both Ti / Au electrode layers with the same thickness controlled within the range of 60 to 80 nm.

5. The top-gate IGZO transistor with a stacked gate dielectric according to claim 1, characterized in that: The thickness of the IGZO semiconductor thin film channel layer (102) is controlled to be 10-20 nm.

6. The top-gate IGZO transistor with a stacked gate dielectric according to claim 1, characterized in that: The thickness of the yttrium oxide gate dielectric (105) is smaller than the thickness of the hafnium oxide gate dielectric (106).

7. The top-gate IGZO transistor with a stacked gate dielectric according to claim 1, characterized in that: The thickness of the yttrium oxide gate dielectric (105) is 1-2 nm; the thickness of the hafnium oxide gate dielectric (106) is 8-10 nm.

8. The top-gate IGZO transistor with a stacked gate dielectric according to claim 1, characterized in that: The gate metal layer (107) is an Au metal layer, and the thickness is controlled to be 50-70 nm.

9. The method for preparing a top-gate IGZO transistor with a stacked gate dielectric according to any one of claims 1 to 8, characterized in that: The preparation method comprises the following steps: Step 1, depositing a SiO2 dielectric layer on a silicon-based substrate to form a Si / SiO2 structure; Step 2, sputtering an IGZO film on the upper surface of the SiO2 dielectric layer by magnetron sputtering, with the thickness controlled at 10 to 20 nm; Step 3, using a coating machine to coat the surface of the Si / SiO2 structure sputtered with the IGZO film, exposing the corresponding pattern using a photolithography process, etching the IGZO film, and obtaining an IGZO channel layer; Step 4: Spread the film again, use a photolithography machine to expose the source electrode and the drain electrode, and use an electron beam coating process to deposit a certain thickness of metal to form the source electrode and the drain electrode; Step 5: After the second coating, the gate dielectric layer of the device is exposed, and the yttrium oxide gate dielectric is first prepared by an electron beam coating apparatus, and then the hafnium oxide gate dielectric layer is grown on the basis of the yttrium oxide gate dielectric by an ALD process; Step 6: coat and expose the gate metal layer of the device again, and then use an electron beam coating process to deposit and form the gate metal layer.

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