MOS tube chip with electrostatic protection structure

Abstract

The application discloses a MOS tube core chip with an electrostatic protection structure, a first diffusion region and a second diffusion region form a PN super junction to improve a reverse breakdown voltage, a third implantation region, a third epitaxial layer and a second epitaxial layer form a parasitic NPN, the first implantation region increases a hole conduction path of the third epitaxial layer, reduces the number of holes flowing into the MOS tube core chip, the first implantation region reduces the on-resistance of the parasitic NPN and increases the difficulty of being turned on, reduces the possibility of large current in the device, and enhances the anti-single particle burnout and electrostatic protection capability of the MOS tube core chip. The trench extending through the third implantation region to part of the first diffusion region and the second diffusion region, the fourth implantation region as a shielding layer, the first diffusion region, the second diffusion region and the fourth implantation region jointly deplete to make the electric field distribution more uniform, the charge compensation of the super junction in the on state makes the on-resistance drop, and the capacitance characteristics of the super junction and the shielding effect of the shielding layer on the gate-drain capacitance make the switching characteristics significantly improve.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor manufacturing process, and particularly relates to a MOS chip with an electrostatic protection structure. BACKGROUND

[0002] With the progress of silicon carbide material technology, high-voltage silicon carbide devices have been developed. Compared with traditional silicon power devices, a silicon carbide metal oxide semiconductor field effect transistor (MOSFET) chip has ideal gate insulation characteristics, high-speed switching performance, low on-circuit and high stability. In addition, the silicon carbide MOSFET chip has high breakdown field strength, good thermal stability, high carrier saturation drift velocity, high thermal conductivity and other characteristics, and can be used to manufacture various high-temperature, high-frequency, high-efficiency and high-power devices. There is a parasitic bipolar junction transistor in the body of the MOS chip. When the MOS chip works in an environment with radiation, the MOS chip is very easy to cause permanent and irreversible damage to the device due to single particle burnout and leakage problems, thereby reducing the working performance of the MOS chip. SUMMARY

[0003] The application provides a MOS chip with an electrostatic protection structure, which improves the voltage resistance, reduces the device off time and increases the current path, to solve the above technical problems. The following technical solutions are used to realize the application.

[0004] The application provides a MOS chip with an electrostatic protection structure, which includes:

[0005] A substrate of a first conduction type, a first epitaxial layer of the first conduction type formed on the upper surface of the substrate, and a first diffusion region of a second conduction type, a second diffusion region of the first conduction type formed on the first epitaxial layer in a staggered manner;

[0006] A second epitaxial layer of the first conduction type formed on the first diffusion region, a third epitaxial layer of the second conduction type located on the second epitaxial layer, a first implantation region of the second conduction type formed in the third epitaxial layer, a second implantation region of the second conduction type located on the third epitaxial layer, and a third implantation region of the first conduction type connected with the second implantation region;

[0007] A trench extending through the third implantation region to the upper surface of part of the first diffusion region and the second diffusion region, and a fourth implantation region of the second conduction type formed at the bottom of the trench;

[0008] a first oxide layer formed on the fourth implant region and on the trench sidewall, a polysilicon layer formed in the trench, a third oxide layer formed on the first oxide layer, part of the third implant region and the polysilicon layer;

[0009] a first metal layer formed on the second implant region, the third implant region and the second oxide layer and a second metal layer formed on the lower surface of the substrate.

[0010] Further, the first conductivity type is N type, the second conductivity type is P type, and the junction depth of the fourth implant region is less than the junction depth of the second epitaxial layer.

[0011] Further, the doping concentration of the substrate is greater than the doping concentration of the first epitaxial layer, and the doping concentration of the third epitaxial layer is less than the doping concentration of the first implant region.

[0012] Further, the preparation process of the MOS die includes the following specific steps:

[0013] a first conductivity type substrate is provided, a first epitaxial layer is formed on the upper surface of the substrate, and first diffusion regions and second diffusion regions are formed on the first epitaxial layer in an interlaced arrangement;

[0014] a second epitaxial layer is formed on the first diffusion regions and the second diffusion regions in sequence, a third sub-epitaxial layer is formed on the second epitaxial layer, a first implant sub-region is formed by implanting ions of a second conductivity type into the third sub-epitaxial layer, a third epitaxial layer is formed by growing the third sub-epitaxial layer and the first implant sub-region, and a first implant region is formed in the third epitaxial layer;

[0015] second implant regions and third implant regions between the second implant regions are formed on the third epitaxial layer in intervals;

[0016] a trench extending through the third implant regions to part of the first diffusion regions and the second diffusion regions, and a fourth implant region formed by implanting ions of the second conductivity type into the bottom of the trench;

[0017] a first oxide layer is deposited on the trench sidewall and the upper surface of the fourth implant region, the trench is filled with polysilicon to form a polysilicon layer, a second oxide layer is formed on part of the third implant region, the first oxide layer and the polysilicon layer, a first metal layer is formed on the second implant region, the third implant region and the second oxide layer, and a second metal layer is formed on the lower surface of the substrate.

[0018] Further, the first conductivity type is N type, the second conductivity type is P type, and the doping concentration of the substrate is 1.2×10 19 cm -3The substrate is made of silicon carbide, and the thickness of the substrate is 1.2 microns.

[0019] Further, the diffusion concentration of the first diffusion region and the second diffusion region is 6.5*10 16 cm -3 The width of the first diffusion region and the second diffusion region is 0.8-1.2 microns.

[0020] Further, the first epitaxial layer is a buffer layer of the MOS tube chip, the second epitaxial layer is a current expansion layer of the MOS tube chip, the diffusion concentration of the first epitaxial layer is 1.2*10 -17 cm -3 The thickness of the second epitaxial layer is 0.2 microns.

[0021] Further, the depth of the trench is 1-1.65 microns, the thickness of the first oxide layer at the bottom of the trench and the oxide layer on the sidewall of the trench is 0.08 microns, and the junction depth of the fourth implantation region is 0.3 microns.

[0022] Further, the doping concentration of the third epitaxial layer is 2.4*10 17 cm -3 The ion implantation concentration of the second implantation region is 1.2*10 19 cm -3 The ion implantation concentration of the third implantation region is 1.2*10 19 cm -3 .

[0023] Further, the first metal layer and the second metal layer are prepared by a magnetron sputtering method, and the trench is prepared by a dry etching method.

[0024] The application provides a MOS tube chip with an electrostatic protection structure, which has the following beneficial effects:

[0025] (1) The first epitaxial layer is formed on the substrate, the first epitaxial layer can increase the blocking voltage of the device as a buffer layer of the device, the first diffusion region and the second diffusion region with different conductive types are formed on the first epitaxial layer, the PN super junction formed by the first diffusion region and the second diffusion region can improve the reverse breakdown voltage of the device;

[0026] (2) The third epitaxial layer with a different conductive type from the second epitaxial layer is formed on the second epitaxial layer as a body region, the first implantation region with high diffusion is formed in the body region, the second implantation region and the third implantation region with different conductive types are sequentially formed on the third epitaxial layer, the third implantation region, the third epitaxial layer and the second epitaxial layer form a parasitic NPN, the first implantation region can increase the hole conduction path of the third epitaxial layer, and the number of holes flowing into the MOS tube chip is reduced;

[0027] (3) The first implantation region reduces the base region on-resistance of the parasitic NPN, increases the difficulty of turning on the parasitic NPN, reduces the possibility of large current in the device, and enhances the single event burnout resistance of the MOS tube chip, thereby enhancing the working performance of the device;

[0028] (4) The trench extending through the third implantation region to the upper surface of the partial first diffusion region and the second diffusion region, the trench bottom forms the fourth implantation region, the fourth implantation region as a shielding layer, in the blocking state, the first diffusion region, the second diffusion region and the fourth implantation region are collectively depleted to make the electric field distribution more uniform, the breakdown voltage rises, and in the on state, the charge compensation effect of the super junction makes the on-resistance drop significantly; In the switching process, the capacitance characteristics of the super junction and the shielding effect of the shielding layer on the gate-drain capacitance make the switching characteristics significantly improved, without additional increase in the size of the device, and also reduce the preparation cost. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0030] Figure 1 The structure diagram of the MOS tube chip with electrostatic protection structure provided by the present application is shown in the figure.

[0031] Figure 2 The preparation flow chart of the MOS tube chip with electrostatic protection structure provided by the present application is shown in the figure.

[0032] Figures 3 to 10 The preparation process diagram of the MOS tube chip with electrostatic protection structure provided by the present application is shown in the figure.

[0033] The main element symbols are explained as follows:

[0034] 10-MOS tube chip; 100-substrate; 110-first epitaxial layer; 120-first diffusion region; 130-second diffusion region; 140-second epitaxial layer; 150-third epitaxial layer; 160-third sub-epitaxial layer; 170-first implantation region; 180-first sub-implantation region; 190-second implantation region; 200-third implantation region; 210-trench; 220-fourth implantation region; 230-first oxide layer; 240-polysilicon layer; 250-second oxide layer; 260-first metal layer; 270-second metal layer. DETAILED DESCRIPTION

[0035] Embodiments of the present application are described in detail below with reference to several drawings. The embodiments of this application described below are exemplary and are not intended to be limiting of the scope of the application, as defined by the appended claims and their equivalents.

[0036] It is to be understood that the terms "on" and "under" are used interchangeably in this disclosure. It is to be understood that when an element as a layer, region or plate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. It will be understood that, although the terms "on" and "under" can be used herein to describe the relationship between elements, other relationships between elements are also possible.

[0037] Referring to Figure 1 The present application provides a MOS chip with an electrostatic protection structure, the MOS chip 10 comprising:

[0038] a substrate 100 of a first conductivity type, a first epitaxial layer 110 of the first conductivity type formed on an upper surface of the substrate 100, and a first diffusion region 120 of a second conductivity type, a second diffusion region 130 of the first conductivity type formed alternately on the first epitaxial layer 110;

[0039] a second epitaxial layer 140 of the first conductivity type formed on the first diffusion region 120, a third epitaxial layer 150 of the second conductivity type formed on the second epitaxial layer 140, a first implant region 190 of the second conductivity type formed in the third epitaxial layer 150, a second implant region 190 of the second conductivity type formed on the third epitaxial layer 150, and a third implant region 200 of the first conductivity type connected to the second implant region 190;

[0040] a trench 210 extending through the third implant region 200 to an upper surface of the first diffusion region 120 and the second diffusion region 130, and a fourth implant region 220 of the second conductivity type formed at a bottom of the trench 210;

[0041] a first oxide layer 230 formed on the fourth implant region 220 and on sidewalls of the trench 210, a polysilicon layer 240 formed in the trench 240, and a third oxide layer 250 formed on the first oxide layer 230, part of the third implant region 200, and the polysilicon layer 240;

[0042] A first metal layer 260 formed on the second implant region 190, the third implant region 200 and the second oxide layer 250, and a second metal layer 270 located on the lower surface of the substrate 100.

[0043] In this embodiment, the first conductivity type is N type, the second conductivity type is P type, the junction depth of the fourth implant region 220 is less than that of the second epitaxial layer 140, the doping concentration of the substrate 100 is greater than that of the first epitaxial layer 110, and the doping concentration of the third epitaxial layer 150 is less than that of the first implant region 170. The third epitaxial layer 150 is a P body region, the first implant region 170 is a P+ region, and the P body region with the ground P+ region can affect the on-resistance of the parasitic NPN transistor, effectively reduce the voltage drop of NPN conduction, so that the MOS tube chip 10 is not easy to appear large current and cause burnout. The first epitaxial layer 110 is a buffer layer of the device, and the super junction formed by the first diffusion region 120 and the second diffusion region 130 can improve the voltage resistance performance of the MOS tube chip 10, and the buffer layer can reduce the peak electric field after the MOS tube chip 10 is turned on.

[0044] It needs to be explained that by forming the first epitaxial layer 110 on the substrate 100, the first epitaxial layer 110 can increase the blocking voltage of the device as the buffer layer of the device, and the first diffusion region 120 and the second diffusion region 130 with different conductive types are formed on the first epitaxial layer 110, and the first diffusion region 120 and the second diffusion region 130 form a PN super junction as a junction type voltage resistant layer, which can improve the reverse breakdown voltage of the MOS tube chip 10. The third epitaxial layer 150 with a different conductive type from the second epitaxial layer 140 is formed as a body region, a highly doped first injection region 170 is formed in the body region, and the second injection region 190 and the third injection region 200 with different conductive types are sequentially formed on the third epitaxial layer 150, and the third injection region 200, the third epitaxial layer 150 and the second epitaxial layer 140 form a parasitic NPN, the first injection region 170 can increase the hole conduction path of the third epitaxial layer 150, reduce the number of holes flowing into the MOS tube chip 10, and the first injection region 170 reduces the base conduction resistance of the parasitic NPN and increases the difficulty of being turned on, also reduces the possibility of large current in the device, and enhances the single particle burnout and electrostatic protection capability of the MOS tube chip. The trench 210 extending through the third injection region 200 to the upper surface of part of the first diffusion region 120 and the second diffusion region 130, the fourth injection region 220 formed at the bottom of the trench 210 and the fourth injection region 220 as a shielding layer, in the blocking state, the first diffusion region 120, the second diffusion region 130 and the fourth injection region 220 are collectively depleted to make the electric field distribution more uniform, the breakdown voltage rises, in the conduction state, the charge compensation effect of the super junction makes the conduction resistance drop sharply, in the switching process, the capacitance characteristics of the super junction and the shielding effect of the shielding layer on the gate-drain capacitance make the switching characteristics significantly improve, without additional increase in the volume of the device, also reduces the preparation cost.

[0045] Referring to Figure 2 , Figures 3 to 10 , the application provides a MOS tube chip with an electrostatic protection structure, and the preparation process of the MOS tube chip 10 comprises the following specific steps:

[0046] S1: providing a substrate 100, forming a first epitaxial layer 110 on the upper surface of the substrate 100, and forming first diffusion regions 120 and second diffusion regions 130 arranged alternately on the first epitaxial layer 110;

[0047] Referring to Figure 2 , in the embodiment, the first conductive type is N type, the second conductive type is P type, the doping concentration of the substrate 100 is 1.2*10 19 cm -3 , the material of the substrate 100 is silicon carbide, and the thickness of the substrate 100 is 1.2μm. The doping concentration of the first diffusion region 120 and the second diffusion region 130 is 6.5*10 16 cm-3 The width of the first diffusion region 120 and the second diffusion region 130 is 0.8-1.2 μm. The N type is phosphorus and the P type is boron. The first epitaxial layer 110 is formed on the N+ substrate by epitaxial growth technology, and the first diffusion region 120 and the second diffusion region 130 with different conductive types are formed on the first epitaxial layer 110.

[0048] It should be noted that the first diffusion region 120 and the second diffusion region 130 have different conductive types, and the super-junction structure of the PN junction can be formed. The first diffusion region 120 and the second diffusion region 130 are staggered and arranged, and the doping concentration and the width of the first diffusion region 120 and the second diffusion region 130 are the same. The lateral PN junction type region in the depletion region can be used as a junction type voltage resistance layer. When the device is in an off state, the drift region is completely depleted. The lateral electric field in the drift region will make the current line generated by the ionized donors in the second diffusion region 130 (N type drift region) terminate in the ionized acceptors in the first diffusion region 120 (P type drift region). The electric flux generated by the N type drift region charge is almost absorbed by the P type drift region. The charge balance between the N region and the P region eliminates the influence of the ionized impurity charge on the longitudinal electric field, so that the longitudinal field strength is uniformly distributed.

[0049] S2: sequentially forming a second epitaxial layer 130 on the first diffusion region 120 and the second diffusion region 130, a third sub-epitaxial layer 160 on the second epitaxial layer 130, injecting second conductive type ions into the third sub-epitaxial layer 160 to form a first injection sub-region 180, and growing the third sub-epitaxial layer 160 and the first injection sub-region 180 to form a third epitaxial layer 150 and a first injection region 170 in the third epitaxial layer 150;

[0050] Referring to Figure 4 , Figure 5 and Figure 6 In this embodiment, the first epitaxial layer 110 is a buffer layer of the device, the second epitaxial layer 140 is a current expansion layer of the MOS tube chip 10, and the doping concentration of the first epitaxial layer 110 is 1.2×10 -17 cm -3The thickness of the second epitaxial layer 140 is 0.2 μm. The second epitaxial layer 140 is formed on the first diffusion region 120 and the second diffusion region 130 by epitaxial growth, and then the third sub-epitaxial layer 160 is formed on the second epitaxial layer 140 by epitaxial growth. The first implantation sub-region 180 is formed in the third sub-epitaxial layer 160 by ion implantation. The process of forming the first implantation sub-region 180 is as follows: first, an etching stop layer (not shown) is formed on the third sub-epitaxial layer 160, and then a photoresist layer (not shown) is formed on the etching stop layer. The photoresist layer is exposed using a mask having the pattern of the first implantation sub-region 180, and then developed to obtain the photoresist layer having the pattern of the first implantation sub-region 180. The photoresist layer having the pattern of the first implantation sub-region 180 is used as a mask to form the pattern opening of the first implantation sub-region 180 on the etching stop layer by reactive ion etching or other etching method. Then, the etching stop layer having the pattern opening of the first implantation sub-region 180 is used as a mask to remove the region of the third sub-epitaxial layer 160 not covered by the etching stop layer by wet etching or dry etching, thereby forming the first implantation sub-region 180 in the third sub-epitaxial layer 160. Thereafter, the photoresist layer and the etching stop layer can be removed by chemical cleaning or other method. In the above process, an antireflection layer can be formed between the photoresist layer and the etching stop layer to ensure the exposure accuracy.

[0051] It should be noted that after the third sub-epitaxial layer 160 and the first implantation sub-region 180 are formed, the other half of the third sub-epitaxial layer 160 and the first implantation sub-region 180 are formed by epitaxial growth to obtain the first implantation region 170 and the third epitaxial layer 150. The third epitaxial layer 150 is a P-body region, and the first implantation region 170 is a P+ region. The greater the length of the P+ region in the P-body region, the smaller the on-resistance of the subsequent parasitic NPN. When the voltage generated by the transient current caused by the incidence of high-energy particles flowing through the base region of the parasitic NPN transistor in the MOS tube chip 10 is reduced, the reduced voltage drop makes it more difficult for the NPN in the MOS tube chip 10 to turn on, thereby ensuring that the MOS tube chip 10 is not prone to large current and device burnout.

[0052] S3: forming the second implantation region 190 and the third implantation region 200 between the second implantation region 190 on the third epitaxial layer 150 in a spaced manner;

[0053] Referring to Figure 7 In this embodiment, the second implantation region 190 and the third implantation region 200 have different conductive types and can be prepared by ion implantation. The width of the second implantation region 190 is smaller than that of the third implantation region 200. The doping concentration of the third epitaxial layer 150 is 2.4 x 1019 cm-3. 17 cm-3 The ion implantation concentration in the second implantation region 190 is 1.15 × 10⁻⁶. 19 cm -3 The ion implantation concentration in the third implantation region 200 is 1.2 × 10⁻⁶. 19 cm -3 The second injection region 190 and the third injection region 200 can form a lateral PN junction, thereby improving the working stability of the MOS transistor chip 10.

[0054] S4: A trench 210 extending through the third injection region 200 to a portion of the first diffusion region 120 and the second diffusion region 130 is injected into the bottom of the trench 210 to form a fourth injection region 220;

[0055] See Figure 8 and Figure 9 In this embodiment, photoresist is first coated between the second implantation region 190 and a portion of the third implantation region 200. Photolithography is then performed on the third implantation region 200 that is not covered by photoresist. A trench 210 extends through the second implantation region 190 to a portion of the first diffusion region 120 and the second diffusion region 130. A fourth implantation region 220 is prepared at the bottom of the trench 210 using ion implantation technology or a self-aligned method. The fourth implantation region 220 is located between the second epitaxial layers 140. The fourth implantation region 220 and the second epitaxial layer 140 have different conductivity types, which can form a parasitic NPN transistor. The second epitaxial layer 140 reduces the depletion effect of the fourth implantation region 220 and the subsequent gate protection zone, i.e., the first oxide layer, near the second diffusion region 130, thereby reducing the parasitic NPN effect of the MOS transistor chip 10.

[0056] S5: A first oxide layer 230 is deposited on the sidewall of the trench 210 and the upper surface of the fourth implantation region 220. The trench 210 is filled with polysilicon to form a polysilicon layer 240. A second oxide layer 250 is formed on a portion of the third implantation region 200, the first oxide layer 230 and the polysilicon layer 240. A first metal layer 260 is formed on the second implantation region 190, the third implantation region 200 and the second oxide layer 250. A second metal layer 270 is formed on the lower surface of the substrate 100.

[0057] See Figure 10In the embodiment, the depth of the trench 210 is 1-1.65 μm, the thickness of the first oxide layer 230 at the bottom of the trench 210 and the oxide layer at the sidewall of the trench 210 is 0.08 μm, the junction depth of the fourth implantation region 220 is 0.3 μm, the first metal layer 260 and the second metal layer 270 are prepared by magnetron sputtering, and the trench 210 is prepared by dry etching. The first metal layer 260 is the source electrode of the MOS transistor chip 10, the polysilicon layer 240 is the gate electrode of the MOS transistor chip 10, the second metal layer 270 is the drain electrode of the MOS transistor chip 10, the first oxide layer 230 and the second oxide layer 250 are both silicon dioxide, and the thickness of the first oxide layer 230 at the sidewall of the trench 210 and the first oxide layer 230 on the fourth implantation region 220 is the same, which can be used as the gate oxide of the MOS transistor chip 10, so as to ensure the uniform distribution of the electric field in the MOS transistor chip 10. The second oxide layer 250 can isolate the source electrode and the gate electrode, prevent the electric leakage, and achieve the electrostatic protection, thereby improving the working reliability of the MOS transistor chip 10.

[0058] In all examples shown and described herein, any specific values should be interpreted as merely exemplary and not as a limitation, and thus, other examples of the exemplary embodiments can have different values.

[0059] It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

[0060] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the present application. It should be pointed out that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A MOS transistor chip with an electrostatic protection structure, characterized in that, The MOS transistor chip includes: A substrate of a first conductivity type, a first epitaxial layer of the first conductivity type formed on the upper surface of the substrate, and a first diffusion region of the second conductivity type and a second diffusion region of the first conductivity type interleaved on the first epitaxial layer; A second epitaxial layer of a first conductivity type formed on the first diffusion region and a third epitaxial layer of a second conductivity type located on the second epitaxial layer, a first implantation region of a second conductivity type formed in the third epitaxial layer, a second implantation region of a second conductivity type located on the third epitaxial layer, and a third implantation region of a first conductivity type connected to the second implantation region; A trench extending through the third injection region to a portion of the first and second diffusion regions, and a fourth injection region of the second conductivity type formed at the bottom of the trench; A first oxide layer formed on the fourth implantation region and located on the trench sidewall, a polysilicon layer formed in the trench, and a third oxide layer located on the first oxide layer, a portion of the third implantation region, and the polysilicon layer; A second oxide layer is formed on a portion of the third implantation region, the first oxide layer, and the polysilicon layer; A first metal layer formed on the second implantation region, the third implantation region, and the second oxide layer, and a second metal layer located on the lower surface of the substrate.

2. The MOS transistor chip with electrostatic protection structure according to claim 1, characterized in that, The first conductivity type is N-type, the second conductivity type is P-type, and the junction depth of the fourth injection region is less than the junction depth of the second epitaxial layer.

3. The MOS transistor chip with electrostatic protection structure according to claim 1, characterized in that, The doping concentration of the substrate is greater than that of the first epitaxial layer, and the doping concentration of the third epitaxial layer is less than that of the first implantation region.

4. The MOS transistor chip with electrostatic protection structure according to any one of claims 1-3, characterized in that, The fabrication process of the MOS transistor chip includes the following specific steps: A substrate is provided, on the upper surface of the substrate a first epitaxial layer is formed, and a first diffusion region and a second diffusion region are formed in an alternating manner on the first epitaxial layer; A second epitaxial layer is formed sequentially on the first diffusion region and the second diffusion region, and a third sub-epitaxial layer is formed on the second epitaxial layer. A first implanted sub-region is formed by implanting ions of a second conductivity type into the third sub-epitaxial layer. The third epitaxial layer and the first implanted sub-region are grown to form a third epitaxial layer and a first implanted region within the third epitaxial layer. A second injection region and a third injection region located between the second injection regions are formed on the third epitaxial layer at intervals; A trench extending through the third implantation region to a portion of the first and second diffusion regions is formed by injecting ions of a second conductivity type into the bottom of the trench to create a fourth implantation region. A first oxide layer is deposited on the sidewalls of the trench and the upper surface of the fourth implantation region. The trench is filled with polysilicon to form a polysilicon layer. A second oxide layer is formed on a portion of the third implantation region, the first oxide layer, and the polysilicon layer. A first metal layer is formed on the second implantation region, the third implantation region, and the second oxide layer. A second metal layer is formed on the lower surface of the substrate.

5. The MOS transistor chip with electrostatic protection structure according to claim 4, characterized in that, The substrate has a doping concentration of 1.2 × 10⁻⁶. 19 cm -3 The substrate is made of silicon carbide.

6. The MOS transistor chip with electrostatic protection structure according to claim 4, characterized in that, The doping concentration of the first diffusion region and the second diffusion region is 6.5 × 10⁻⁶. 16 cm -3 The widths of the first diffusion region and the second diffusion region are 0.8~1.2μm.

7. The MOS transistor chip with electrostatic protection structure according to claim 4, characterized in that, The first epitaxial layer is the buffer layer of the MOS transistor chip, and the second epitaxial layer is the current spreading layer of the MOS transistor chip. The doping concentration of the first epitaxial layer is 1.2 × 10⁻⁶. 17 cm -3 The thickness of the second epitaxial layer is 0.2 μm.

8. The MOS transistor chip with electrostatic protection structure according to claim 4, characterized in that, The trench has a depth of 1~1.65μm, the thickness of the first oxide layer at the bottom of the trench and the oxide layer on the sidewall of the trench are both 0.08μm, and the junction depth of the fourth injection zone is 0.3μm.

9. The MOS transistor chip with electrostatic protection structure according to claim 4, characterized in that, The doping concentration of the third epitaxial layer is 2.4 × 10⁻⁶. 17 cm -3 The ion implantation concentration in the second implantation region is 1.2 × 10⁻⁶. 19 cm -3 The ion implantation concentration in the third implantation region is 1.2 × 10⁻⁶. 19 cm -3 .

10. The MOS transistor chip with electrostatic protection structure according to claim 4, characterized in that, The first metal layer and the second metal layer are prepared by magnetron sputtering, and the trench is prepared by dry etching.

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