Semiconductor package and semiconductor device

Abstract

The purpose of the present invention is to provide a technique capable of reducing the cost or size of a semiconductor package. The wiring element includes: a second substrate; a plurality of first relay pads disposed on a surface of the second substrate on the opposite side from the conductor substrate and connected to the control pads of the plurality of semiconductor elements via wires; a plurality of second relay pads disposed on a surface of the second substrate opposite to the conductor substrate, the number of the second relay pads being smaller than or equal to the number of the first relay pads; and a plurality of wirings that are disposed on the surface of the second substrate on the opposite side from the conductor substrate and selectively connect the plurality of first relay pads and the plurality of second relay pads.

Description

[0001] This application is a divisional application of the Chinese national application No. 201880099699.8 (PCT / JP2018 / 043391) (Semiconductor package, method for manufacturing the same, and semiconductor device) filed on November 26, 2018, and the content thereof is incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor package, a method for manufacturing the same, and a semiconductor device. Background Art

[0004] Various techniques have been proposed for power semiconductor devices. For example, Patent Document 1 proposes a semiconductor device in which a semiconductor element and a column electrode connected to the semiconductor element are encapsulated with resin, and power controlled by the semiconductor element is obtained from the column electrode.

[0005] On the other hand, in a power semiconductor device such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) module using silicon carbide (SiC), it is difficult to increase the area of the MOSFET or even increase the current capacity, and the technique of Patent Document 1 cannot be directly used. Therefore, a structure in which a plurality of semiconductor chips are connected in parallel to cope with an increase in current capacity has been proposed. For example, Patent Document 2 proposes a structure in which signals are input from a plurality of semiconductor chips to a signal wiring pattern on an insulating substrate via wires.

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2014-199955

[0007] Patent Document 2: International Publication No. 2014 / 046058 Summary of the Invention

[0008] However, in the technique of Patent Document 2, a signal wiring pattern corresponding to a gate electrode and a main current circuit pattern corresponding to a source electrode are disposed on the same component. Therefore, when a relatively large current flows through the main current circuit pattern, for example, in order to ensure insulation between the signal wiring pattern and the main current circuit pattern, it is necessary to sufficiently separate these patterns. As a result, there are problems such as an increase in the size of the semiconductor device and an increase in cost due to a complicated assembly method.

[0009] Therefore, the present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of reducing the cost or miniaturizing a semiconductor package.

[0010] The semiconductor package according to the present invention includes: a conductor substrate; a plurality of semiconductor elements that are bonded to the first main surface of the conductor substrate and have a switching function; and a wiring component that is bonded to the first main surface of the conductor substrate. Each of the plurality of semiconductor elements includes: a first substrate; a first main electrode portion disposed on a surface of the first substrate opposite to the conductor substrate; a second main electrode portion disposed on the surface of the first substrate on the side of the conductor substrate and bonded to the conductor substrate; and a control pad for controlling the current flowing between the first main electrode portion and the second main electrode portion. The wiring component includes: a second substrate; a plurality of first relay pads disposed on a surface of the second substrate opposite to the conductor substrate and connected to the control pads of the plurality of semiconductor elements through wires; a plurality of second relay pads disposed on the surface of the second substrate opposite to the conductor substrate, the number of which is less than or equal to the number of the plurality of first relay pads; and a plurality of wirings disposed on the surface of the second substrate opposite to the conductor substrate for selectively connecting the plurality of first relay pads and the plurality of second relay pads. The semiconductor package further includes: a plurality of first conductor components bonded to the first main electrode portions of the plurality of semiconductor elements; a plurality of second conductor components bonded to the plurality of second relay pads of the wiring component; and a packaging material that covers at least a part of the plurality of semiconductor elements, the wiring component, at least a part of the plurality of first conductor components, at least a part of the plurality of second conductor components, and the first main surface of the conductor substrate in a state where the exposed surfaces on the side opposite to the conductor substrate of the plurality of first conductor components, the exposed surfaces on the side opposite to the conductor substrate of the plurality of second conductor components, and the second main surface on the side opposite to the first main surface of the conductor substrate are exposed.

[0011] Effects of the Invention

[0012] According to the present invention, the wiring component includes: a second substrate; a plurality of first relay pads connected to the control pads of the plurality of semiconductor elements through wires; a plurality of second relay pads, the number of which is less than or equal to the number of the plurality of first relay pads; and a plurality of wirings for selectively connecting the plurality of first relay pads and the plurality of second relay pads. Thereby, cost reduction or miniaturization of the semiconductor package can be achieved.

[0013] The object, features, aspects and advantages of the present invention will become clearer through the following detailed description and drawings. Description of the Drawings

[0014] Figure 1 It is a plan schematic view showing the structure of the semiconductor package according to Embodiment 1.

[0015] Figure 2 It is a schematic cross-sectional view showing the structure of the semiconductor package related to Embodiment 1.

[0016] Figure 3 It is a schematic perspective view showing the structure of the semiconductor device related to Embodiment 1.

[0017] Figure 4 It is a schematic cross-sectional view showing the structure of the semiconductor device related to Embodiment 1.

[0018] Figure 5 It is a schematic perspective view showing the structure of the semiconductor device related to Embodiment 1.

[0019] Figure 6 It is a schematic cross-sectional view showing the structure of the semiconductor package related to Embodiment 2.

[0020] Figure 7 It is a schematic cross-sectional view showing the structure of the semiconductor package related to Embodiment 3.

[0021] Figure 8 It is a schematic perspective view showing the structure of the semiconductor device related to Embodiment 4.

[0022] Figure 9 It is a schematic cross-sectional view showing the structure of the semiconductor device related to Embodiment 5. Detailed Embodiments

[0023] <Embodiment 1>

[0024] Figure 1 It is a schematic plan view showing the structure of the semiconductor package 1 related to Embodiment 1 of the present invention. Figure 2 It shows the structure of the semiconductor package 1 and is a schematic cross-sectional view along the Figure 1 A-A' line.

[0025] As Figure 1 and Figure 2 shown, the semiconductor package 1 has a conductor substrate 2, a plurality of semiconductor elements 3, and wiring elements 4. Hereinafter, the number of the plurality of semiconductor elements 3 is described as 5, but it may be 2 or more. In addition, hereinafter, the number of the wiring elements 4 is described as 1, but it may be any number less than the number of the plurality of semiconductor elements 3.

[0026] The plurality of semiconductor elements 3 are bonded to the first main surface 2S1 of the conductor substrate 2 ( Figure 2 ), and each of the plurality of semiconductor elements 3 has a switching function. The wiring element 4 is bonded to the first main surface 2S1 of the conductor substrate 2. In Figure 1In the example, when viewed from above, the wiring component 4 approaches the plurality of semiconductor components 3 in a state of being surrounded by the plurality of semiconductor components 3 in three directions (above, left, and right) except for one direction (downward).

[0027] Each of the plurality of semiconductor components 3 includes a first substrate, i.e., a semiconductor substrate 31, a first main electrode portion, i.e., a surface electrode 32f, a second main electrode portion, i.e., a back electrode 33b, and at least one control pad 34c. In addition, at least one of the plurality of semiconductor components 3 may further include at least one of a current sensing element and a temperature sensing element (not shown).

[0028] The surface electrode 32f is disposed on the surface of the semiconductor substrate 31 opposite to the conductor substrate 2. The surface electrode 32f includes nickel as a main material, for example, and includes gold or silver on the outermost surface of the material. In addition, the surface electrode 32f corresponds to the source electrode.

[0029] The back electrode 33b is disposed on the back surface of the semiconductor substrate 31 on the side of the conductor substrate 2 and is bonded to the conductor substrate 2. Thus, the potentials of the back electrodes 33b of the plurality of semiconductor components 3 are equal to each other. The back electrode 33b includes nickel as a main material, for example, and includes gold or silver on the outermost surface of the material. In addition, the back electrode 33b corresponds to the drain electrode.

[0030] The control pad 34c is a pad for controlling the current flowing between the surface electrode 32f and the back electrode 33b. In addition, the control pad 34c corresponds to the gate electrode.

[0031] The wiring component 4 includes a second substrate, i.e., a wiring substrate 41, a plurality of first relay pads 42r, a plurality of second relay pads 43r, and a plurality of wirings, i.e., a plurality of internal wirings 44i.

[0032] The plurality of first relay pads 42r, the plurality of second relay pads 43r, and the internal wirings 44i are disposed on the surface of the wiring substrate 41 opposite to the conductor substrate 2 and are insulated from the conductor substrate 2 through the wiring substrate 41 and the like.

[0033] The plurality of first relay pads 42r are connected to the control pads 34c of the plurality of semiconductor components 3 through wires 5. The wire 5 has a wire diameter of less than or equal to 100 μmΦ, for example, and includes gold as a main material.

[0034] The number of the plurality of second relay pads 43r is less than or equal to the number of the plurality of first relay pads 42r. In addition, in Figure 1 the example, the plurality of second relay pads 43r are arranged along the edge portion of the wiring substrate 41 close to the outside of the semiconductor package 1, but the positions of the plurality of second relay pads 43r are not limited thereto.

[0035] A plurality of internal wirings 44i selectively connect a plurality of first relay pads 42r and a plurality of second relay pads 43r inside the wiring component 4. In addition, in Figure 1 this example, the width of the first relay pad 42r is larger than the width of the internal wiring 44i, and the width of the second relay pad 43r is larger than the width of the first relay pad 42r.

[0036] As Figure 1 and Figure 2 shown, the semiconductor package 1 further includes a plurality of first conductor components, namely a plurality of conductor plates 38, a plurality of second conductor components, namely a plurality of conductor sheets 48, and a packaging material 6.

[0037] A plurality of conductor plates 38 are joined to the surface electrodes 32f of a plurality of semiconductor elements 3, and a plurality of conductor sheets 48 are joined to a plurality of second relay pads 43r of the wiring component 4. In addition, each of the surface electrode 32f and the second relay pad 43r contains a solderable metal such as nickel as a main material.

[0038] The packaging material 6 covers at least a part of the plurality of semiconductor elements 3, the wiring component 4, at least a part of the plurality of conductor plates 38, at least a part of the plurality of conductor sheets 48, and the first main surface 2S1 of the conductor substrate 2, and substantially encapsulates them. The packaging material 6 contains epoxy resin, and is formed by, for example, a transfer molding method, a compression molding method, or a casting method.

[0039] In addition, the exposed surfaces of the plurality of conductor plates 38 on the side opposite to the conductor substrate 2, the exposed surfaces of the plurality of conductor sheets 48 on the side opposite to the conductor substrate 2, and the second main surface 2S2 of the conductor substrate 2 on the side opposite to the first main surface 2S1 are exposed from the packaging material 6. As Figure 2 shown, the semiconductor package 1 has a first surface 1S1 and a second surface 1S2 facing in opposite directions. The second main surface 2S2 of the conductor substrate 2 corresponds to the first surface 1S1 of the semiconductor package, and the exposed surfaces of the plurality of conductor plates 38 and the exposed surfaces of the plurality of conductor sheets 48 correspond to the second surface 1S2 of the semiconductor package 1.

[0040] The structure in which a part of the plurality of conductor plates 38 and the plurality of conductor sheets 48 are exposed from the packaging material 6 is formed, for example, by a grinding process. In this grinding process, after covering the metal components that become the plurality of conductor plates 38 and the plurality of conductor sheets 48 with a packaging component that becomes the packaging material 6, a part of them is ground to expose the metal components. At this time, when the height of the ground packaging material 6 is sufficiently higher than the loop height h of the wire 5 and the wire 5 is not exposed from the packaging material 6, the grinding is terminated.

[0041] In the present Embodiment 1, the melting point of the bonding material 21 that bonds the plurality of semiconductor elements 3 and the conductor substrate 2 is higher than the melting point of solder. Further, since the solder bonding process in the manufacturing process of a general semiconductor device is less than or equal to 450°C, it is preferable that the melting point of the bonding material 21 is higher than 450°C.

[0042] Here, the plurality of semiconductor elements 3 and the conductor substrate 2 are sintered and bonded (fired and bonded) by, for example, a silver-based material or a copper-based material.

[0043] In a structure in which a silver-based material is used for the bonding material 21, for example, after a paste that will be the bonding material 21 is formed at a predetermined position on the conductor substrate 2 by printing or a dispenser, the semiconductor element 3 is placed on the paste, and the semiconductor element 3 and the conductor substrate 2 are brought into close contact with as few bubbles as possible in the paste. After that, the paste is sintered in a nitrogen atmosphere at a temperature of 200°C to 300°C for several tens of minutes without applying pressure. As described above, in the structure in which a silver-based material is used for the bonding material 21, the sintering and bonding for bonding the plurality of semiconductor elements 3 and the conductor substrate 2 is performed without accompanying pressure.

[0044] In a structure in which a copper-based material is used for the bonding material 21, for example, after a paste that will be the bonding material 21 is formed at a predetermined position on the conductor substrate 2 by printing or a dispenser, the semiconductor element 3 is placed on the paste, and pressure is applied by applying a load of 10 to 40 MPa. At the same time, the paste is sintered in a nitrogen atmosphere at a temperature of 200°C to 300°C for several tens of minutes. At the time of this sintering, in order to prevent damage to the surface of the semiconductor element 3 caused by the applied load, for example, a Teflon sheet is used. In addition, in the case where a sheet molded product is used for supplying the sintering material, after the sintering material is temporarily attached to the back surface of the semiconductor element 3 in advance, the semiconductor element 3 is temporarily pressed against a predetermined position on the conductor substrate 2, and then pressure sintering is performed under the same conditions. As described above, in the structure in which a copper-based material is used for the bonding material 21, the sintering and bonding for bonding the conductor substrate 2 and the plurality of semiconductor elements 3 is performed with accompanying pressure.

[0045] Further, the conductor substrate 2 and the plurality of semiconductor elements 3 may be diffusion-bonded instead of sintering and bonding. In addition, above, the bonding material 21 for bonding the conductor substrate 2 and the plurality of semiconductor elements 3 has been described, but the bonding material 22 for bonding the wiring element 4 and the conductor substrate 2 may be the same as the bonding material 21.

[0046] The semiconductor package 1 according to the first embodiment further includes a protective film 36. The protective film 36 is a film that covers the end portions, i.e., the edge portions, of the plurality of semiconductor elements 3 and has a Young's modulus lower than that of the encapsulation material 6. The protective film 36 contains, for example, polyimide. Further, for example, after the wiring elements 4 and the plurality of semiconductor elements 3 are bonded to the conductor substrate 2, a precursor solution of the protective film 36 is drawn using a dispenser, and the protective film 36 is formed by firing the precursor solution.

[0047] The conductor substrate 2 contains copper as a main material, for example. A recess, i.e., a groove 2d, is provided in a region of the first main surface 2S1 of the conductor substrate 2 other than the region bonded to the wiring elements 4 and the plurality of semiconductor elements 3. Further, the recess may be a depression hole or the like instead of the groove 2d.

[0048] The plurality of conductor plates 38 and the plurality of conductor sheets 48 contain copper as a main material, for example. Additionally, as Figure 2 shown, the plurality of conductor plates 38 and the surface electrodes 32f of the plurality of semiconductor elements 3 are bonded by solder 37, for example, and the plurality of conductor sheets 48 and the plurality of second relay pads 43r of the wiring elements 4 are bonded by solder 47, for example. The thicknesses of the plurality of conductor plates 38 and the plurality of conductor sheets 48, i.e., the thickness d of the plurality of conductor plates 38 and the thickness of the plurality of conductor sheets 48 after the above polishing process, are sufficiently greater than the loop height h of the wire 5.

[0049] In the first embodiment, the plurality of semiconductor elements 3 include compound semiconductors. For example, the plurality of semiconductor elements 3 contain silicon carbide (SiC) as a main material of the compound semiconductor. Each of the plurality of semiconductor elements 3 includes, for example, a MOSFET (not shown) that performs an on / off operation and a body diode (not shown) that performs a freewheeling operation. Moreover, bidirectional power conduction between the MOSFET and the body diode can be performed.

[0050] In the first embodiment, after the plurality of conductor plates 38 are formed, the semiconductor package 1 is further formed, and then a screening test for detecting defects in the plurality of semiconductor elements 3 is performed. Thereby, deterioration of the characteristics of elements such as electrodes caused by energizing the body diode in the screening test can be suppressed. Further, in a structure in which the body diode is not used for the main freewheeling path, the semiconductor element 3 may include, for example, a freewheeling SBD (Schottky barrier diode) instead of the body diode.

[0051] The wiring substrate 41 of the wiring component 4 may also be, for example, a silicon substrate containing silicon (Si) as a main material. In this case, for example, an oxide film is formed on the silicon substrate, and a plurality of first relay pads 42r, a plurality of second relay pads 43r, and a plurality of internal wirings 44i are formed on the oxide film. The patterns of these pads and wirings can be formed, for example, by using a normal wafer process method such as patterning achieved by photolithography after sputtering. These pads and wirings are covered with a cover film 46, and the cover film 46 contains polyimide, for example, in the same manner as the protective film 36.

[0052] The wiring substrate 41 of the wiring component 4 is not limited to the above substrate. For example, it may also be a resin substrate containing resin. In this case, for example, before bonding the wiring substrate 41 to the conductor substrate 2, the first relay pad 42r and the second relay pad 43r are formed in advance on the surface of the resin substrate with a copper material. Then, the conductor sheet 48 is bonded to the second relay pad 43r that is electrically connected to the outside by sintering bonding. After that, the wiring substrate 41 is bonded to the conductor substrate 2. In addition, on the back surface of the resin substrate, at least one of a bonding film such as a thin film of copper, a connection film such as a thin film of nickel, silver, copper, etc., and an anti-oxidation film such as a thin film of gold is selectively formed. In addition, when a thin film of nickel is used for the connection film, in order to ensure the bonding property of the sintering bonding using silver, it is preferable to provide a thin film of gold on the outermost surface of the connection film.

[0053] The semiconductor substrate 31 of the semiconductor component 3 is ground to a thickness of about 100 μm, for example. On the other hand, the wiring component 4 is ground to about 400 μm, about 250 μm in thickness, and ground to about 150 μm as needed. When a silicon substrate is used for the wiring substrate 41 and the wiring component 4 is thinned to about 150 μm, it is also difficult to cause problems in the wafer process. In this way, if there is a height difference between the semiconductor component 3 and the wiring substrate, there is an effect that wire bonding of the wire 5 is easily performed. In addition, the outer peripheral portion of the semiconductor component 3 has a withstand voltage holding structure such as a guard ring. Since it becomes a high electric field, it is preferable to make the loop portion of the wire 5 above the outer peripheral portion of the semiconductor component 3 in the cross section as far away from the surface of the semiconductor component 3 as possible. When the semiconductor component 3 is thinner than the wiring substrate 4, since the loop portion of the wire 5 can be made far away from the surface of the semiconductor component 3, it is preferable that the semiconductor component 3 is thinner than the wiring component 4.

[0054] Figure 3 It is a perspective view showing the structure of the semiconductor device 7 using the semiconductor package 1 according to the first embodiment. Figure 4 It is a cross-sectional view showing a part thereof.

[0055] As Figure 3 and Figure 4As shown, the semiconductor device 7 has one or more semiconductor packages 1. Additionally, as Figure 3 and Figure 4 shown, the semiconductor device 7 also has a resin housing 71, an insulating substrate 72, a first circuit pattern, i.e., a first main current circuit pattern 73, external electrodes 74, a circuit pattern 75, leads 76, main terminals, i.e., external electrodes 77, leads 78, control terminals, i.e., signal terminals 79. Additionally, as Figure 4 shown, the semiconductor device 7 also has a packaging material 80, a lid 81, and a metal layer 82. Furthermore, one or more semiconductor packages 1 may also be six semiconductor packages that constitute a full-bridge circuit as a unit.

[0056] The resin housing 71 and the insulating substrate 72 form a container body having a space that is open at the top. The first main current circuit pattern 73 is disposed in a portion of the insulating substrate 72 that forms the space of the container body. Additionally, the first main current circuit pattern 73 is joined, for example, by solder to the second main surface 2S2 of the conductor substrate 2 that is exposed from the packaging material 6 in the first surface 1S1 of the semiconductor package 1 ( Figure 2 ). In the semiconductor device 7 thus configured, the first main current circuit pattern 73 is used as a drain electrode. This first main current circuit pattern 73 is connected to the external electrode 74.

[0057] The circuit pattern 75 is connected by a lead 76 to the exposed surface of the conductor plate 38 in the second surface 1S2 of the semiconductor package 1 ( Figure 2 ). Additionally, this circuit pattern 75 is connected to the external electrode 77. In this way, the external electrode 77 is electrically connected to the exposed surface of the conductor plate 38 through the lead 76. The lead 76 that electrically connects the exposed surface of the conductor plate 38 and the external electrode 77 may, for example, be a lead having a wire diameter of 400 μmΦ or more and containing aluminum as a main material, or may be a lead containing copper or the like as a main material. Furthermore, when the lead 76 is a lead containing copper as a main material, the conductivity can be improved.

[0058] The signal terminal 79 is connected by a lead 78 to the exposed surface of the conductor sheet 48 in the second surface 1S2 of the semiconductor package 1 ( Figure 2 ). The lead 78 that electrically connects the exposed surface of the conductor sheet 48 and the signal terminal 79 may, for example, also be a lead having a wire diameter of 200 μmΦ or more and containing aluminum as a main material.

[0059] As described above, the semiconductor package 1 is electrically connected to the external electrode 74, the external electrode 77, and the signal terminal 79. Furthermore, in the first embodiment 1, the resin housing 71, the external electrodes 74, 77, and the signal terminal 79 are integrally formed, but it is not limited to this. After connecting the semiconductor package 1 to the external electrode 74, etc., as Figure 4As shown, by enclosing the encapsulation material 80 in the space of the above-described container body, the periphery of the semiconductor package 1 is encapsulated by the encapsulation material 80. The encapsulation material 80 contains, for example, silicone gel. After gel encapsulation, as Figure 4 and Figure 5 shown, by mounting the lid 81 on the resin housing 71, the outside of the semiconductor device 7 is isolated from the inside of the semiconductor device 7 including the semiconductor package 1 and the bonding structure around the semiconductor package 1.

[0060] In Figure 4 the example, a metal layer 82 such as a conductor plate is disposed on the surface of the insulating substrate 72 opposite to the semiconductor package 1 and is connected to a cooling fin (not shown). The connection of the metal layer 82 to the cooling fin uses, for example, ordinary bonding materials and methods such as solder, welding material, and thermal grease. By cooling the cooling fin, the heat generated from the semiconductor element 3 is dissipated. In addition, instead of connecting the metal layer 82 to the cooling fin, the metal layer 82 and even the semiconductor element 3 can be cooled by directly bringing cooling water into contact with the metal layer 82.

[0061] <Summary of Embodiment 1>

[0062] According to the semiconductor package 1 according to the present Embodiment 1, by using, for example, the wiring element 4 containing Si to perform signal wiring for a plurality of semiconductor elements 3 such as a MOSFET containing SiC, etc., the conductor sheet 48 can be used as a control pad (for example, gate electrode, source Kelvin electrode, current sensing source electrode, temperature sensing element electrode, etc.), the conductor plate 38 can be used as a source electrode, and the conductor substrate 2 can be used as a drain electrode. Thereby, a plurality of semiconductor elements 3 can be used like a single semiconductor element or even a single semiconductor chip. Therefore, for example, cost reduction and miniaturization of the semiconductor device 7 due to improved assembly of the semiconductor device 7 in wire bonding, chip soldering processes, etc. can be achieved. In addition, since no main current circuit pattern corresponding to the source electrode is provided in the wiring element 4, cost reduction and miniaturization of the semiconductor package 1 due to improved assembly of the semiconductor package 1 can be achieved.

[0063] In addition, by having the wiring element 4, the length of the wire 78 can be minimized as much as possible, and the diameter of the wire 78 can be reduced. Therefore, the size of the control pad 34c of the semiconductor element 3 can be minimized as much as possible. Thereby, the effective area of the semiconductor element 3 can be enlarged. Particularly, in the case where an expensive material such as SiC is used for the base material of the semiconductor element 3, it is effective to reduce the product cost by enlarging the effective area of the semiconductor element 3.

[0064] In addition, in the present Embodiment 1, each of the plurality of semiconductor elements 3 includes, for example, a MOSFET (not shown) that performs an on / off operation and a body diode (not shown) that performs a freewheeling operation. With such a structure, since semiconductor elements such as SBDs can be omitted, miniaturization and cost reduction of the semiconductor package 1 can be achieved.

[0065] Furthermore, when crystal defects exist in a MOSFET containing SiC, if the body diode is energized, sometimes these defects grow and the characteristics deteriorate. However, by performing a screening test, it is possible to prevent the semiconductor package 1 containing defects from being mounted on the semiconductor device 7. In this screening test, since a relatively large current needs to flow, there are concerns that if a large current flows through the thin surface electrode 32f, the surface electrode 32f may be damaged, and also concerns that since the heat generated by energization is not efficiently dissipated and accumulates in the semiconductor element 3, the semiconductor element 3 becomes high temperature. For example, there are also concerns that current and heat concentrate at the positions where test tools such as probes come into contact. However, as shown in the present Embodiment 1, by forming the plurality of conductor plates 38 and then further forming the semiconductor package 1 and then performing the screening test, such electrode damage can be suppressed. In addition, since a material with a large heat capacity such as copper is directly bonded for electrical and thermal connection, compared with the case where the heat generation during the screening test is tested with the semiconductor element 3 alone, heat can be effectively dissipated from the semiconductor element 3. In addition, since test tools such as probes come into contact with the conductor plate 38 once, the current can be distributed and the screening test current can be uniformly applied to the semiconductor element 3. That is, it is preferable to apply a material such as copper with a large heat capacity and high electrical conductivity to the conductor plate 38. In addition, as shown in the present Embodiment 1, in the structure where the semiconductor package 1 is the smallest unit (1-in-1) in the circuit structure, the defect rate can be reduced compared with the case where a screening test is performed on a semiconductor device with a larger circuit scale such as 2-in-1 or 6-in-1.

[0066] In a structure where the wiring substrate 41 of the wiring element 4 contains Si as the main material, the wiring element 4 can be easily formed by existing wafer processes. Therefore, if a back electrode the same as or similar to that of the semiconductor element 3 is also formed on the wiring element 4, the wiring element 4 can be formed by the same method as the semiconductor element 3, and thus the manufacturing cost can be reduced.

[0067] In the structure in which the wiring substrate 41 of the wiring component 4 contains resin, since the resin substrate pre-bonded with the conductor sheet 48 can be bonded to the conductor substrate 2, the assemblability of the semiconductor package 1 can be improved. Further, for example, when the plurality of first relay pads 42r and the plurality of second relay pads 43r disposed on the surface of the resin substrate contain a copper material, after the conductor sheet 48 is bonded to the second relay pad 43r by sintering bonding, the wiring substrate 41 can be bonded to the conductor substrate 2. Further, by selectively forming at least one of a thin film such as copper as a bonding film, a thin film such as nickel, silver, or copper as a connection film, and a thin film such as gold as an antioxidant film on the back surface of the resin substrate, the solder bondability and the sintering bondability using silver or copper can be improved, and thus the manufacturability can be improved. Further, according to the wiring substrate 41 made of a resin substrate, compared with the wiring substrate 41 made of a silicon substrate, the processing time for bonding the conductor sheet 48 to the second relay pad 43r can be shortened, and thus the manufacturing cost can be suppressed.

[0068] Further, in the first embodiment, the bonding material 21 for bonding the conductor substrate 2 and the plurality of semiconductor elements 3 uses a bonding material having a melting point higher than that of the solder. Thereby, when the semiconductor package 1 is solder-bonded to the first main current circuit pattern 73 on the insulating substrate 72, for example, remelting of the bonding material 21 under the semiconductor element 3 can be suppressed. As a result, deterioration of the yield and heat dissipation performance can be suppressed. Further, since deterioration of the bonding material 21 when the semiconductor element 3 operates at a high junction temperature can also be suppressed, the reliability of the semiconductor package 1 can be improved.

[0069] Further, in the first embodiment, the sintering bonding for bonding the conductor substrate 2 and the plurality of semiconductor elements 3 is performed using a silver-based material without applying pressure. Thereby, since positional deviation during pressurization can be avoided and dimensional tolerance can be reduced, the semiconductor package 1 can be miniaturized. In addition, since consumable parts such as Teflon sheets used for the pressing process can be reduced, the manufacturing cost can be reduced. Further, when sintering bonding for bonding the conductor substrate 2 and the plurality of semiconductor elements 3 is performed using a copper-based material, compared with the case where this sintering bonding is performed using a gold-based material, since this bonding is of high strength, improvement in the reliability of the semiconductor package 1 can be expected.

[0070] In addition, in the present Embodiment 1, the end portion of the semiconductor element 3 is covered with the protective film 36. Thereby, not only the adhesion between the semiconductor element 3 and the encapsulating material 6 can be improved, but also the reliability of the semiconductor package 1 can be improved due to stress buffering. In the structure in which the protective film 36 contains polyimide, since the compatibility between the structural material on the surface of the semiconductor element 3 and the encapsulating material 6 is good, the reliability of the semiconductor package 1 can be improved.

[0071] In addition, in the present Embodiment 1, after the wiring element 4 and the plurality of semiconductor elements 3 are bonded to the conductor substrate 2, the precursor solution of the protective film 36 is drawn using a dispenser, and the precursor solution is fired to form the protective film 36. Thereby, melting of the bonding material 21 under the semiconductor element 3 in the process of firing the protective film 36 can be suppressed.

[0072] In addition, in the present Embodiment 1, the conductor substrate 2 contains copper as a main material. Thereby, the semiconductor package 1 can be easily solder-bonded to a circuit pattern (for example, the first main current circuit pattern 73) outside the semiconductor package 1. In addition, according to such a structure, heat of the semiconductor element 3 can be efficiently diffused, so that the thermal resistance can be reduced. Generally, since the loss deteriorates if the temperature of the SiC MOSFET rises, it is preferable to cool the MOSFET efficiently, but there are problems such as difficulty in increasing the area due to the influence of the yield and high thermal resistance. In contrast, in the present Embodiment 1, the conductor substrate 2 that is sintered and bonded using silver directly under the semiconductor element 3 contains a copper material having high thermal conductivity. Therefore, heat diffusion can be promoted. Specifically, efficient heat diffusion can be substantially performed through an area equal to or larger than the area of the semiconductor element 3, so that the thermal resistance can be reduced.

[0073] In addition, in the present Embodiment 1, a recess, i.e., a groove 2d, is provided in a region of the first main surface 2S1 of the conductor substrate 2 other than the region bonded to the wiring element 4 and the plurality of semiconductor elements 3. Thereby, the adhesion between the encapsulating material 6 and the conductor substrate 2 is improved, so that the reliability of the semiconductor package 1 can be improved. In addition, since the tensile stress on the surface of the conductor substrate 2 can be dispersed, warping of the semiconductor package 1 can be suppressed.

[0074] In addition, in the present Embodiment 1, the main materials of the conductor plate 38 and the conductor sheet 48 contain copper. Thereby, the conductor plate 38 and the conductor sheet 48 can be formed inexpensively, and they can be easily bonded by solder.

[0075] In addition, in the present Embodiment 1, various bonding methods such as wire bonding and solder bonding are used for the external electrodes 74, 77, and the signal terminal 79. Thereby, the semiconductor package 1 can be easily mounted and bonded to the semiconductor device 7, and the conventional semiconductor devices and manufacturing equipment can be made common, so that the manufacturing cost of the semiconductor device 7 and the investment in the manufacturing equipment can be suppressed.

[0076] <Embodiment 2>

[0077] Figure 6 is a cross-sectional schematic view corresponding to the structure of the semiconductor package 1 according to Embodiment 2 of the present invention. Hereinafter, the same or similar structural elements as those of the above structural elements among the structural elements according to the present Embodiment 2 are denoted by the same reference numerals, and mainly the different structural elements will be described. Figure 2 As shown in, the conductor substrate 2 of the semiconductor package 1 according to the present Embodiment 2 includes a laminate 2e containing carbon fibers 2cf. The carbon fibers 2cf are arranged in the planar direction of the semiconductor substrates 31 of the plurality of semiconductor elements 3. By adjusting parameters such as the content, diameter, and length of the carbon fibers 2cf, the thermal conductivity and the coefficient of linear expansion in the lateral direction of the semiconductor elements 3 can be arbitrarily adjusted. The laminate 2e contains aluminum as a main material.

[0078] In addition Figure 6 as shown, the conductor substrate 2 of the semiconductor package 1 according to the present Embodiment 2 includes: a laminate sheet 2f disposed on the first main surface 2S1 side and not containing carbon fibers 2cf; and a laminate sheet 2g disposed on the second main surface 2S2 side and not containing carbon fibers 2cf. Each of the laminate sheets 2f, 2g may also include a connection film disposed on the outermost surface of the laminate 2e and containing, for example, nickel or copper as a main material. In addition, each of the laminate sheets 2f, 2g may also include an anti-oxidation film disposed on the outermost surface of the connection film and containing, for example, gold as a main material. The connection film and the anti-oxidation film can be formed by, for example, plating treatment. In addition, even if the connection film is oxidized, the oxide film can be relatively easily removed by performing a treatment such as solder bonding in a reducing environment, so the anti-oxidation film is not essential.

[0079]

[0080] <Summary of Embodiment 2>

[0081] In the present Embodiment 2, the conductor substrate 2 includes a laminate 2e containing carbon fibers 2cf. According to such a structure, by adjusting the coefficient of linear expansion of the conductor substrate 2, warpage of the semiconductor package 1 can be suppressed, so that the assemblability and reliability of the semiconductor package 1 can be improved.

[0082] ​In addition, in the second embodiment, the carbon fibers 2cf are arranged in the planar direction of the semiconductor substrate 31 of the plurality of semiconductor elements 3. Thereby, the heat emitted from the semiconductor element 3 can be efficiently diffused, and thus cooling can be efficiently performed in a range greater than or equal to the effective area of the semiconductor element 3.

[0083] In addition, as shown in the second embodiment, in the structure in which the laminated plate 2e contains aluminum as the main material, the Young's modulus can be reduced as compared with the structure in which the laminated plate 2e contains copper as the main material. By taking advantage of this and the adjustment of the linear expansion coefficient of the conductor substrate 2 achieved by including the carbon fibers 2cf, the stress generated in the semiconductor element 3 and the encapsulation material 6 can be reduced. As a result, warping of the semiconductor package 1 can be suppressed, and peeling of the encapsulation material 6 from the conductor substrate 2 can be suppressed, and thus the assemblability and reliability of the semiconductor package 1 can be improved.

[0084] In addition, in the case where the laminated plates 2f and 2g are each composed of a connection film containing nickel or copper as the main material disposed on the outermost surface of the laminated plate 2e containing aluminum, an antioxidant film containing gold as the main material disposed on the outermost surface of the connection film, etc., since solder bondability and silver-based sintering bondability can be improved, manufacturability can be improved. In addition, when nickel is used for the connection film, in order to ensure silver-based sintering bondability, it is preferable to provide gold on the outermost surface.

[0085] <Embodiment 3>

[0086] Figure 7 is a cross-sectional schematic view corresponding to the structure of the semiconductor package 1 according to the third embodiment of the present invention. Hereinafter, the same or similar structural elements as those of the above structural elements among the structural elements according to the third embodiment are denoted by the same reference numerals, and mainly different structural elements will be described. Figure 2 As shown in, the conductor substrate 2 of the semiconductor package 1 according to the third embodiment includes a laminated metal film having three or more metal films. In

[0087] As Figure 7 shown, Figure 7In the example, three or more metal films are the first metal film located on the inner side in the stacking direction, i.e., the inner-layer metal film 2j, and the second metal film and the third metal film located on the outer side in the stacking direction, i.e., the surface-layer metal films 2k and 2l. The surface-layer metal film 2k is disposed on one surface of the inner-layer metal film 2j, and the surface-layer metal film 2l is disposed on the other surface of the inner-layer metal film 2j. The linear expansion coefficient of the inner-layer metal film 2j is lower than that of the surface-layer metal films 2k and 2l. The surface-layer metal films 2k and 2l contain copper as the main material, and the inner-layer metal film 2j contains nickel and iron as the main material. In addition, the three or more metal films are not limited to the inner-layer metal film 2j and the surface-layer metal films 2k and 2l.

[0088] <Summary of Embodiment 3>

[0089] In this Embodiment 3, since the linear expansion coefficient of the conductor substrate 2 can be adjusted by the inner-layer metal film 2j and the surface-layer metal films 2k and 2l, warpage of the semiconductor package 1 can be suppressed, and as a result, the assemblability and reliability of the semiconductor package 1 can be improved.

[0090] In addition, in this Embodiment 3, since the surface-layer metal film 2k contains copper as the main material, heat generated by the semiconductor element 3 can be easily diffused. In addition, since the surface-layer metal film 2l contains copper as the main material, solder bonding can be easily performed. Moreover, by sandwiching the inner-layer metal film 2j containing nickel with a lower linear expansion coefficient than copper between the surface-layer metal films 2k and 2l containing copper, warpage of the semiconductor package 1 can be suppressed. In addition, since the bondability between copper and nickel is relatively good, bondability between the inner-layer metal film 2j and the surface-layer metal films 2k and 2l can be ensured. As a result, the above-mentioned warpage can be suppressed, and manufacturability and reliability of the semiconductor package 1 can be ensured.

[0091] <Embodiment 4>

[0092] Figure 8 It is a perspective view showing the structure of the semiconductor device 7 according to this Embodiment 4. Hereinafter, the same or similar structural elements as those in the above structural elements among the structural elements according to this Embodiment 4 are denoted by the same reference numerals, and mainly different structural elements will be described.

[0093] As Figure 8 shown, for the semiconductor device 7 according to this Embodiment 4, instead of Figure 3A conductor frame 83 is used for the wire 76. Specifically, the circuit pattern 75 is connected to the exposed surface of the conductor plate 38 in the second surface 1S2 of the semiconductor package 1 through the conductor frame 83, and the circuit pattern 75 is connected to the external electrode 77. That is, the external electrode 77 is electrically connected to the exposed surface of the conductor plate 38 through the conductor frame 83. In addition, the conductor frame 83 and the external electrode 77 may be integrally formed. The exposed surface of the conductor plate 38 and the conductor frame 83 can be joined by, for example, solder, or can be joined by, for example, ultrasonic bonding.

[0094] <Summary of Embodiment 4>

[0095] In this Embodiment 4, the external electrode 77 is electrically connected to the exposed surface of the conductor plate 38 through the conductor frame 83. Thus, compared with the semiconductor device 7 Figure 3 using the wire 76, the resistance can be reduced, and the bonding can be easily performed. In addition, compared with wire bonding, the processing time can be shortened, and the manufacturing cost can be suppressed.

[0096] <Embodiment 5>

[0097] Figure 9 FIG. is a cross-sectional schematic view showing the structure of the semiconductor device 7 according to this Embodiment 5. Hereinafter, the same or similar structural elements as those in the above structural elements among the structural elements related to this Embodiment 5 are denoted by the same reference numerals, and mainly the different structural elements will be described.

[0098] As Figure 9 shown, the semiconductor device 7 according to this Embodiment 5, similar to the semiconductor device 7 Figure 4 has a semiconductor package 1, an insulating substrate 72, a first main current circuit pattern 73, and a metal layer 82. The first main current circuit pattern 73, similar to that in Embodiment 1, is joined to the second main surface 2S2 of the conductor substrate 2 in the first surface 1S1 of the semiconductor package 1 by, for example, solder. The first main current circuit pattern 73 is connected to the first main electrode 87 corresponding to the external electrode 74 Figure 3 corresponding to.

[0099] In addition, the semiconductor device 7 according to this Embodiment 5 further has an insulating substrate 84, a second circuit pattern, i.e., a second main current circuit pattern 85, and a third circuit pattern, i.e., a control terminal pattern 86. The insulating substrate 84 is disposed opposite to the exposed surface of the conductor plate 38 and the exposed surface of the conductor sheet 48.

[0100] The second main current circuit pattern 85 is disposed on the insulating substrate 84 and joined to the exposed surface of the conductor plate 38 in the second surface 1S2 of the semiconductor package 1. The exposed surface of the conductor plate 38 and the second main current circuit pattern 85 are joined by, for example, solder. The second main current circuit pattern 85 is connected to the correspondingFigure 3 is connected to the second main electrode 88 of the external electrode 77.

[0101] The control terminal pattern 86 is disposed on the insulating substrate 84 and joined to the exposed surface of the conductor sheet 48 in the second surface 1S2 of the semiconductor package 1. The exposed surface of the conductor sheet 48 and the control terminal pattern 86 are joined by, for example, solder. The control terminal pattern 86 is connected to the control terminal 89 corresponding to Figure 3 the signal terminal 79. Thus, a control signal from outside the semiconductor device 7 is input into the semiconductor element 3 in the semiconductor package 1 via the signal terminal 79 and the like.

[0102] A cooling metal layer 82 is disposed on the surface of the insulating substrate 72 opposite to the surface on which the first main current circuit pattern 73 is disposed, and a cooling metal layer 90 is disposed on the surface of the insulating substrate 84 opposite to the surface on which the second main current circuit pattern 85 is disposed. Moreover, by directly or indirectly cooling the cooling metal layers 82 and 90, the semiconductor package 1 is cooled from both sides. In a structure for direct cooling, by making a part of the cooling metal layers 82 and 90 a watertight region, the cooling water is directly brought into contact with the cooling portions of the metal layers 82 and 90 for cooling. In a structure for indirect cooling, for example, ordinary bonding materials and methods such as solder, brazing material, and thermal grease are used to connect the cooling metal layers 82 and 90 to cooling fins. By cooling the cooling fins, the heat generated from the semiconductor element 3 is dissipated.

[0103] <Summary of Embodiment 5>

[0104] In this Embodiment 5, by the double-sided cooling structure that cools both sides of the semiconductor device 7, the semiconductor package 1 can be efficiently cooled. In addition, according to the structure of this Embodiment 5 in which the semiconductor package 1 is sandwiched between two insulating substrates 72 and 84, compared with the case where a plurality of chips of relatively small size, each including a SiC MOSFET, are assembled side by side separately, the semiconductor device can be easily assembled.

[0105] In addition, since the area of the semiconductor package 1 is larger than that of the single semiconductor element 3, compared with the case where the semiconductor element 3 is directly mounted on the double-sided cooling structure, the tilt accuracy can be easily improved. As a result, the thermal resistance of the double-sided cooling structure can be stabilized. Moreover, since the tilt accuracy and the position accuracy are improved, damage to the semiconductor element generated in the case of pressurization or fixation by a tool can be suppressed.

[0106] In addition, the present invention can freely combine the respective embodiments within the scope of the invention, and appropriately deform and omit the respective embodiments.

[0107] Although the present invention has been described in detail, the above description is illustrative in all respects, and the present invention is not limited thereto. It should be understood that countless variations that are not illustrated can be conceived without departing from the scope of the present invention.

[0108] Description of Reference Numerals

[0109] 1 semiconductor package, 2 conductor substrate, 2cf carbon fiber, 2d groove, 2e laminate, 2j inner layer metal film, 2k, 2l surface layer metal film, 2S1 first main surface, 2S2 second main surface, 3 semiconductor element, 4 wiring element, 5, 76, 78 wire, 6 encapsulating material, 7 semiconductor device, 31 semiconductor substrate, 32f surface electrode, 33b back electrode, 34c control pad, 36 protective film, 37 solder, 38 conductor plate, 41 wiring substrate, 42r first relay pad, 43r second relay pad, 44i internal wiring, 47 solder, 48 conductor sheet, 73 first main current circuit pattern, 77 external electrode, 79 signal terminal, 83 conductor frame, 84 insulating substrate, 85 second main current circuit pattern, 86 control terminal pattern.

Claims

1. A semiconductor package having: A conductor substrate; A plurality of semiconductor elements bonded to a first main surface of the conductor substrate and having a switching function; and A wiring component bonded to the first main surface of the conductor substrate, Each of the plurality of semiconductor elements includes: A first substrate; A first main electrode portion disposed on a surface of the first substrate opposite to the conductor substrate; A second main electrode portion disposed on the surface of the first substrate on the side of the conductor substrate and bonded to the conductor substrate; and A control pad for controlling a current flowing between the first main electrode portion and the second main electrode portion, The wiring component includes: A second substrate; A plurality of first connection portions disposed on a surface of the second substrate opposite to the conductor substrate and electrically connected to the control pads of the plurality of semiconductor elements; and A plurality of second connection portions disposed on the surface of the second substrate opposite to the conductor substrate and electrically connected to the first connection portions.

2. The semiconductor package according to claim 1, further having: A plurality of first conductor members bonded to the first main electrode portions of the plurality of semiconductor elements; A plurality of second conductor members bonded to the plurality of second connection portions of the wiring component; and A packaging material covering at least a part of the plurality of semiconductor elements, the wiring component, at least a part of the plurality of first conductor members, at least a part of the plurality of second conductor members, and at least a part of the first main surface of the conductor substrate in a state where an exposed surface on a side opposite to the conductor substrate of the plurality of first conductor members, an exposed surface on a side opposite to the conductor substrate of the plurality of second conductor members, and a second main surface on a side opposite to the first main surface of the conductor substrate are exposed.

3. The semiconductor package according to claim 1, Wherein, The number of the plurality of second connection portions is less than or equal to the number of the plurality of first connection portions.

4. The semiconductor package according to claim 1, Wherein, The melting point of the bonding material for bonding the plurality of semiconductor elements and the conductor substrate is higher than the melting point of solder.

5. The semiconductor package according to claim 1, Wherein, The plurality of semiconductor elements and the conductor substrate are sintered and bonded through a silver-based material or a copper-based material.

6. The semiconductor package according to claim 1, Wherein, The plurality of semiconductor elements and the conductor substrate are diffusion-bonded.

7. The semiconductor package according to claim 2, Wherein, It further has a protective film that covers the ends of the plurality of semiconductor elements and has a lower Young's modulus than the packaging material.

8. The semiconductor package according to claim 7, Wherein, The protective film includes polyimide.

9. The semiconductor package according to claim 1, Wherein, A recess is provided in a region of the first main surface of the conductor substrate other than a region bonded to the plurality of semiconductor elements and the wiring component.

10. The semiconductor package according to claim 2, Wherein, The first main electrode portions of the plurality of first conductor components and the plurality of semiconductor elements are joined by solder.

11. The semiconductor package according to claim 1, wherein, the plurality of semiconductor elements include compound semiconductors.

12. The semiconductor package according to claim 11, wherein, the plurality of semiconductor elements include silicon carbide as a main material of the compound semiconductor.

13. The semiconductor package according to claim 1, wherein, the second substrate of the wiring component includes silicon as a main material.

14. The semiconductor package according to claim 1, wherein, the second substrate of the wiring component includes resin.

15. The semiconductor package according to claim 1, wherein, the semiconductor elements are thinner than the wiring components.

16. The semiconductor package according to claim 1, wherein, each of the plurality of semiconductor elements includes a MOSFET that performs an on / off operation and a body diode that performs a freewheeling operation, and bidirectional energization of the MOSFET and the body diode can be performed.

17. A semiconductor device having at least one semiconductor package according to claim 1.

18. The semiconductor device according to claim 17, wherein, at least one of the semiconductor packages is configured to include six semiconductor packages that constitute a full-bridge circuit as a unit.

19. A semiconductor device having at least one semiconductor package according to claim 2, the semiconductor device further having a first circuit pattern that is joined to the second main surface of the conductor substrate exposed from the encapsulating material by solder.

20. The semiconductor device according to claim 19, wherein, the first circuit pattern is used as a drain electrode.

21. A semiconductor device having at least one semiconductor package according to claim 2, the semiconductor device further having a control terminal that is connected to the exposed surface of the second conductor component by a wire.

22. A semiconductor device having at least one semiconductor package according to claim 2, the semiconductor device further having a main terminal that is electrically connected to the exposed surface of the first conductor component by a wire.

23. The semiconductor device according to claim 22, wherein, the wire that electrically connects the exposed surface of the first conductor component and the main terminal includes copper as a main material.

24. A semiconductor device having at least one semiconductor package according to claim 2, the semiconductor device further having a main terminal that is electrically connected to the exposed surface of the first conductor component by a conductor frame.

25. The semiconductor device according to claim 24, wherein, the exposed surface of the first conductor component and the conductor frame are joined by solder.

26. The semiconductor device according to claim 24, wherein, the exposed surface of the first conductor component and the conductor frame are ultrasonically joined.

27. A semiconductor device having at least one semiconductor package according to claim 2, The semiconductor device further includes: an insulating substrate disposed opposite to the exposed surfaces of the first conductor member and the second conductor member; a second circuit pattern disposed on the insulating substrate and joined to the exposed surface of the first conductor member; and a third circuit pattern disposed on the insulating substrate and joined to the exposed surface of the second conductor member.

28. The semiconductor device according to claim 27, wherein the exposed surface of the first conductor member and the second circuit pattern are joined by solder, the exposed surface of the second conductor member and the third circuit pattern are joined by solder.

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