Solar cell, preparation method thereof and power utilization device

Abstract

The invention provides a solar cell, a preparation method thereof and a power utilization device, and the preparation method comprises the following steps: providing a substrate of a first conductive type, the substrate having a first surface and a second surface opposite to the first surface; preparing a tunneling oxide material layer and an intrinsic polycrystalline silicon material layer which are laminated on the first surface, diffusing a doped material to the intrinsic polycrystalline silicon material, and preparing a doped polycrystalline silicon material layer with a second conduction type; forming a mask layer on the second surface, and performing laser processing on the partially doped polycrystalline silicon material layer to prepare a first prefabricated structure; and the first prefabricated structure is sequentially placed in a first corrosive liquid and a second corrosive liquid to be subjected to first corrosion treatment and second corrosion treatment correspondingly. According to the invention, the doped polycrystalline silicon material and the amorphous glass layer on the preset first conductive type doped region are loosened by utilizing laser treatment, and two times of corrosion treatment are matched, so that an engraving effect with depth and flatness is realized on the doped region, and the electrical property of the solar cell is improved.

Description

Technical Field

[0001] This application relates to the technical field of batteries, and particularly to a solar cell, a preparation method thereof, and an electrical device. Background Art

[0002] With the rapid development of society, the consumption and demand for energy have been increasing year by year, and the global warming trend caused by the increasing carbon emissions has become more and more serious. Among renewable clean energies, solar photovoltaics (SPV) is one of the most potential and sustainable energies in the world. Solar photovoltaics, such as solar cells, can convert light energy into electrical energy, and do not cause pollution to the environment during energy conversion, which is a new energy source. Solar cells are mainly divided into crystalline silicon solar cells, compound solar cells (such as gallium arsenide, copper indium gallium selenide), organic solar cells (such as perovskite, etc.), and dye-sensitized solar cells. Among them, crystalline silicon solar cells occupy an absolute dominant position in the commercial market because of their mature technology and rich raw materials. Currently, the market share exceeds 85%, and will maintain the leading position in the next decade or even longer. Improving the conversion efficiency of the battery and reducing the production cost of the battery have always been the goals pursued by the photovoltaic industry. Among them, the improvement of the conversion efficiency often also brings a certain degree of cost reduction. The early products of silicon solar cells were aluminum back surface field (Al-BSF) with an efficiency of less than 20%; later, they were upgraded to passivated emitter and rear cell (PERC), with a conversion efficiency exceeding 22.5%. Although polysilicon occupies a considerable scale due to its low-cost advantage, in 2019, n-type and p-type monocrystalline silicon cells accounted for 60% of the market share. Among them, n-type cell technology will continue to grow, mainly including n-type heterojunction (SHJ), tunnel oxide passivated contact (TOPCon), and interdigitated back contact (IBC) structures. The structural feature of the IBC cell is that there are no grid lines on the front side, and the positive and negative electrodes are both formed in a cross-arrangement structure on the back side. This front-side unobstructed structure completely eliminates the shielding loss caused by the grid line electrodes, realizes the maximum utilization of incident photons, and thus effectively improves the battery efficiency and power generation.

[0003] The biggest difficulty and also the biggest loss point of the good efficiency in the preparation process of traditional IBC cells is how to prepare a good PN junction structure. There are mainly two methods for preparing the PN junction structure, namely the one-step method and the mask method. Among them, the one-step method has high requirements for additives and auxiliary materials such as lye, and the process control is difficult. The etching depth in the laser window area, that is, the P region, is relatively shallow, which has a great impact on the battery leakage. While the mask method has a complex process and a long process flow, which is not conducive to mass production. Summary of the Invention

[0004] Based on this, in order to improve the flatness of the doped region and improve the performance of the solar cell, the present application provides a solar cell, a preparation method thereof and an electrical device.

[0005] The present application provides a preparation method of a solar cell, comprising the following steps:

[0006] Providing a substrate of a first conductivity type, the substrate having a first surface and a second surface opposite to the first surface;

[0007] Preparing a stacked tunneling oxide material layer and an intrinsic polysilicon material layer on the first surface, diffusing a doping material into the intrinsic polysilicon material layer to prepare a doped polysilicon material layer, the doped polysilicon material layer having a second conductivity type, and the first conductivity type being opposite to the second conductivity type;

[0008] Forming a mask layer on the second surface, performing laser treatment on a part of the doped polysilicon material layer to prepare a first prefabricated structure, wherein the output power in the laser treatment is 20W - 40W, and the overlapping area of adjacent laser spots is 1 / 3 - 2 / 3 of the laser spot area;

[0009] Placing the first prefabricated structure in a first etching solution and a second etching solution respectively for a first etching treatment and a second etching treatment until a part of the substrate is exposed on the first surface, and removing the mask layer, wherein the first etching solution and the second etching solution each independently comprise a monobasic strong base, and the monobasic strong base comprises one or both of sodium hydroxide and potassium hydroxide.

[0010] In one embodiment, the first etching treatment satisfies one or more of the following conditions:

[0011] (1) The composition of the first etching solution comprises 0.5% - 2% of a polishing additive, 0.5% - 2% of the monobasic strong base and 96% - 99% of a first solvent by mass percentage;

[0012] (2) The time of the first etching treatment is 250s - 400s;

[0013] (3) The temperature of the first etching treatment is 65°C - 70°C.

[0014] In one embodiment, the second etching treatment satisfies one or more of the following conditions:

[0015] (1) The composition of the second etching solution includes 0.5% to 2% of a polishing additive, 0.5% to 5% of the monobasic strong base, and 93% to 99% of a second solvent by mass percentage;

[0016] (2) The time of the second etching treatment is 150 s to 300 s;

[0017] (3) The temperature of the second etching treatment is 70°C to 75°C.

[0018] In one embodiment, the mask layer satisfies one or two of the following conditions:

[0019] (1) The material of the mask layer includes one or both of silicon nitride and silicon dioxide;

[0020] (2) The thickness of the mask layer is 5 nm to 10 nm.

[0021] In one embodiment, the method for removing the mask layer includes: placing it in a cleaning solution for cleaning, and the cleaning solution includes one or both of hydrofluoric acid and hydrochloric acid.

[0022] In one embodiment, the composition of the cleaning solution includes 8% to 25% of hydrofluoric acid, 4.5% to 15% of hydrogen chloride, and 60% to 87.5% of a third solvent by mass percentage.

[0023] In one embodiment, after preparing the doped polysilicon material layer and before forming the mask layer, it further includes: performing a texturing treatment on the first surface.

[0024] In one embodiment, after removing the mask layer, it further includes: preparing a stacked first passivation layer and a first antireflection layer on the first surface, and preparing a stacked second passivation layer and a second antireflection layer on the second surface.

[0025] This application also provides a solar cell prepared by the above preparation method.

[0026] This application also provides an electrical device, including the above solar cell as a power source.

[0027] The preparation method of the solar cell provided by the present application performs local treatment on the tunneling oxide material layer and the doped polysilicon material layer prepared on a substrate of a first conductivity type by laser treatment to make their internal structures loose, and then cooperates with two etching treatments to obtain a doped region of the first conductivity type with an engraving effect that combines depth and flatness. During the process of preparing the above-mentioned doped region, the influences such as residues, leakage, and hot spots can be effectively reduced, and a good engraving effect of the doped region can be achieved, so as to facilitate the subsequent passivation process, thereby improving the overall electrical performance of the IBC solar cell. Description of the Drawings

[0028] Figure 1 It is a schematic structural diagram of a solar cell of a specific example provided by the present application.

[0029] Description of the reference numerals: 10: solar cell; 110: substrate; 120: tunneling oxide layer; 130: doped polysilicon layer; 140: first passivation layer; 141: second passivation layer; 150: first antireflection layer; 151: second antireflection layer; 160: first electrode; 170: second electrode. Detailed Embodiments

[0030] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0031] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined. In the description of the present application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise specifically defined.

[0032] The terms "preferably", "more preferably", etc. in the present application refer to the embodiments of the present application that can provide certain beneficial effects in certain cases. However, in the same or other cases, other embodiments may also be preferred. In addition, the description of one or more preferred embodiments does not imply that other embodiments are not available, nor is it intended to exclude other embodiments from the scope of the present application.

[0033] When a numerical range is disclosed herein, the above range is considered continuous and includes the minimum and maximum values of the range, as well as every value therebetween. Further, when the range refers to integers, every integer between the minimum and maximum values of the range is included. In addition, when multiple ranges are provided to describe features or characteristics, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all sub-ranges subsumed therein.

[0034] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another film layer, it can be directly on the other film layer or there can also be an intermediate film layer. Further, when a layer is referred to as being "under" another layer, it can be directly below or there can be one or more intermediate layers. It can also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there can also be one or more intermediate layers.

[0035] In cases where "comprising", "having", and "including" as described herein are used, the intention is to cover non-exclusive inclusion. Unless an explicit limiting term such as "only", "consisting of", etc. is used, another component can also be added.

[0036] Unless stated to the contrary, terms in the singular form may include the plural form and should not be construed as having a quantity of one.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0038] This application provides a method for preparing a solar cell, comprising the following steps:

[0039] Providing a substrate having a first conductivity type, the substrate having a first surface and a second surface opposite to the first surface;

[0040] Preparing a stacked tunneling oxide material layer and an intrinsic polysilicon material layer on the first surface, diffusing a doping material into the intrinsic polysilicon material to prepare a doped polysilicon material layer, the doped polysilicon material layer having a second conductivity type, and the first conductivity type being opposite to the second conductivity type;

[0041] A mask layer is formed on the second surface, and the partially doped polysilicon material layer is subjected to laser treatment to prepare a first prefabricated structure, where the output power of the laser treatment is 20 w to 40 w, and the overlapping area of adjacent laser spots is 1 / 3 to 2 / 3 of the laser spot area;

[0042] The first prefabricated structure is successively placed in a first etching solution and a second etching solution for the first etching treatment and the second etching treatment respectively until a part of the substrate is exposed on the first surface, and the mask layer is removed, where the first etching solution and the second etching solution each independently include a strong base, and the strong base includes one or both of sodium hydroxide and potassium hydroxide.

[0043] The method for preparing a solar cell provided in this application performs local treatment on a stacked tunneling oxide material layer and a doped polysilicon material layer on a substrate of a first conductivity type by using laser treatment to make the internal structure of the doped polysilicon material layer loose. Subsequently, with two etching treatments, a doped region of the first conductivity type with both depth and flatness engraving effects can be obtained. During the process of preparing the above-mentioned doped region, the influences of residues, leakage, hot spots, etc. can be effectively reduced, and a good engraving effect of the doped region can be achieved, so as to facilitate the subsequent passivation process, thereby improving the overall electrical performance of the IBC solar cell.

[0044] In a specific example, the conductivity type of the substrate is N-type, the conductivity type of the doped polysilicon material layer is P-type, the conductivity type of the substrate is P-type, and the conductivity type of the doped polysilicon material layer is N-type.

[0045] In a specific example, before preparing the tunneling oxide material layer, the substrate is further polished. Specifically, the substrate is placed in a polishing solution, the reaction temperature of the polishing is 68 °C to 75 °C, the reaction time of the polishing is 200 s to 300 s, and the composition of the polishing solution includes 0.9% to 1.4% of a polishing additive, 1.5% to 5% of sodium hydroxide, and 93.6% to 97.6% of water by mass percentage.

[0046] Furthermore, the reaction temperature of the polishing can be but is not limited to 68 °C, 69 °C, 70 °C, 71 °C, 72 °C, 73 °C, 74 °C or 75 °C, and the reaction time of the polishing can be but is not limited to 200 s, 220 s, 240 s, 260 s, 280 s or 300 s.

[0047] In a specific example, the thickness of the tunneling oxide material layer is 1.2 nm to 1.8 nm, and the thickness of the intrinsic polysilicon material layer is 80 nm to 180 nm. The method for preparing the tunneling oxide material layer and the intrinsic polysilicon material layer can be but is not limited to low-pressure chemical vapor deposition (LPCVD).

[0048] Understandably, the doping material is phosphorus oxychloride. Further, the doping concentration of phosphorus in the doped polysilicon material layer is 1e20 / cm 3 ~4e21 / cm 3 , and during the diffusion process, the doped polysilicon material layer further includes an amorphous glass layer formed on its outermost layer, specifically a phosphosilicate glass layer PSG. The thickness of the phosphosilicate glass layer PSG is 30 nm to 55 nm. Preferably, the thickness of the phosphosilicate glass layer PSG is 35 nm to 50 nm. Understandably, the limitation on the thickness of the amorphous glass layer, i.e., the phosphosilicate glass layer PSG, here is due to protecting the first surface during subsequent texturing to avoid corrosion of the first surface by the texturing solution.

[0049] Further, since the inner lining silicon wafers of the commonly used phosphorus diffusion machine are in a single-insert state, tunneling oxide material layers, doped polysilicon material layers, and amorphous glass layers on the surfaces of the doped polysilicon material layers will be generated on both sides of the substrate silicon wafer. It is necessary to etch the tunneling oxide material, doped polysilicon material, and amorphous glass material on the front side, i.e., the second surface, of the substrate silicon wafer. Specifically, the composition of the etching solution includes, by weight percentage, 8% to 20% hydrofluoric acid (HF), 8% to 20% sulfuric acid (H 2 SO 4 ), 8% to 20% nitric acid (HNO 3 ), and 40% to 76% water. Among them, the hydrofluoric acid (HF) is 48% to 50% EL-grade hydrofluoric acid (HF), and the sulfuric acid (H 2 SO 4 ) is 36% EL-grade sulfuric acid (H 2 SO 4 ). The etching reaction time is 50 s to 100 s, and the etching reaction temperature is 23 °C to 27 °C. Understandably, the mixed acid process is used to maintain good corrosion to ensure that the silicon substrate can be corroded. Secondly, a certain amount of acid mist will be generated by the high-concentration mixed acid in the tank, and the acid mist will also have a micro-corrosion effect on the back side of the substrate silicon wafer to facilitate subsequent cleaning to remove the silicon surface attachment layer.

[0050] Specifically, the etching reaction time can be but is not limited to 50 s, 60 s, 70 s, 75 s, 80 s, 90 s, or 100 s, and the etching reaction temperature can be but is not limited to 23 °C, 24 °C, 25 °C, 26 °C, or 27 °C.

[0051] In a specific example, after preparing the doped polysilicon material layer and before forming the mask layer, it further includes: texturing the first surface. Specifically, the texturing treatment is carried out after removing the tunneling oxide material, doped polysilicon material, and amorphous glass material on the first surface of the substrate and before forming the mask layer.

[0052] Further, during the texturing process, the temperature of the texturing reaction is 75°C to 85°C, the time of the texturing reaction is 400 s to 600 s, and the composition of the texturing solution by weight percentage includes: 1.5% to 5% of NaOH, 0.3% to 1.5% of Shichuang EP12v88 additive, and 93.5% to 97.2% of water.

[0053] Specifically, the temperature of the texturing reaction can be but is not limited to 75°C, 76°C, 77°C, 78°C, 79°C, 80°C, 81°C, 82°C, 83°C, 84°C or 85°C, and the time of the texturing reaction can be but is not limited to 400 s, 420 s, 440 s, 460 s, 480 s, 500 s, 520 s, 540 s, 560 s, 580 s or 600 s.

[0054] In a specific example, in the laser treatment, the main grid width is 800 μm to 1000 μm, the main grid interval is 12 mm to 20 mm, the sub-grid width is 180 μm to 250 μm, and the sub-grid interval is 1.1 mm to 1.5 mm. The laser output power is 20 W to 40 W, the frequency of the laser treatment is 400 KHz to 800 KHz, and the overlapping area of adjacent laser spots is 1 / 3 to 2 / 3 of the laser spot area.

[0055] Specifically, the overlapping area of adjacent laser spots as a proportion of the laser spot area can be but is not limited to 1 / 3, 1 / 2 or 2 / 3. The laser intensity focuses on loosening the amorphous glass material on the surface of the doped polysilicon material layer of the second conductivity type to be removed by laser, so as to be removed during the subsequent cleaning process. However, too high laser intensity will cause obvious morphological differences between the non-overlapping area and the overlapping area of the laser, affecting the overall flatness, and too low laser intensity cannot effectively act on the amorphous glass material on the preset doped area of the first conductivity type, resulting in the inability to remove the excess amorphous glass material and other material layers on the preset doped area of the first conductivity type during the subsequent cleaning. Therefore, it is necessary to limit the laser power and the overlapping area of adjacent laser spots as described above to achieve efficient etching of the tunneling oxide material, doped polysilicon material and amorphous glass material on the preset doped area of the first conductivity type. In a specific example, the composition of the first etching solution by mass percentage includes 0.5% to 2% of polishing additive, 0.5% to 2% of monobasic strong base, and 96% to 99% of the first solvent. The time of the first etching treatment is 250 s to 400 s, and the temperature of the first etching treatment is 65°C to 70°C.

[0056] Specifically, the composition of the first etching solution includes, by mass percentage, 0.8% to 1.5% of a polishing additive, 0.8% to 1.5% of a monobasic strong base, and 97% to 98.4% of a first solvent. The time of the first etching treatment can be, but is not limited to, 250 s, 280 s, 300 s, 350 s, 340 s, 360 s, 380 s, or 400 s. The temperature of the first etching treatment can be, but is not limited to, 65 °C, 66 °C, 67 °C, 68 °C, 69 °C, or 70 °C. It can be understood that the first etching treatment is directed at a part of the amorphous glass layer and a part of the doped polysilicon material corresponding to the preset doped region with the first conductivity type in the laser treatment.

[0057] In a specific example, the conditions of the second etching treatment include: the composition of the second etching solution includes, by mass percentage, 0.5% to 2% of a polishing additive, 0.5% to 5% of a monobasic strong base, and 93% to 99% of a second solvent. The time of the second etching treatment is 150 s to 300 s; the temperature of the second etching treatment is 70 °C to 75 °C.

[0058] Further, the composition of the second etching solution includes, by mass percentage, 0.5% to 1.5% of a polishing additive, 1.5% to 4% of a monobasic strong base, and 94.5% to 98% of a second solvent. The time of the second etching treatment can be, but is not limited to, 150 s, 180 s, 210 s, 240 s, 270 s, or 300 s. The temperature of the second etching treatment can be, but is not limited to, 70 °C, 71 °C, 72 °C, 73 °C, 74 °C, or 75 °C. The second etching is directed at a part of the tunneling oxide material layer and a part of the doped material diffused into the substrate corresponding to the preset doped region with the first conductivity type in the laser treatment, and finally a doped region with the first conductivity type and a doped region with the second conductivity type with a certain height difference are formed.

[0059] In a specific example, both the first solvent and the second solvent are pure water with a conductivity of 1000 μs / cm to 3000 μs / cm. Specifically, the conductivity of the pure water can be, but is not limited to, 1000 μs / cm, 1200 μs / cm, 1400 μs / cm, 1600 μs / cm, 1800 μs / cm, 2000 μs / cm, 2200 μs / cm, 2400 μs / cm, 2600 μs / cm, 2800 μs / cm, or 3000 μs / cm.

[0060] In a specific example, the material of the mask layer includes one or both of silicon nitride and silicon dioxide. Preferably, the material of the mask layer is silicon dioxide. Specifically, a silicon dioxide layer is formed on the second surface. It can be understood that the silicon dioxide layer is prepared on the substrate by LPCVD, and the reaction temperature of the process is 800 °C to 900 °C, and the thickness of the silicon dioxide layer is 5 nm to 10 nm.

[0061] Further, the thickness of the silicon dioxide layer can be, but is not limited to, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. This thickness can effectively protect the second surface of the substrate.

[0062] Furthermore, the method for removing the mask layer includes: cleaning in a cleaning solution, and the cleaning solution includes one or both of hydrofluoric acid and hydrochloric acid. Specifically, the composition of the cleaning solution includes 8% - 25% hydrofluoric acid, 4.5% - 15% hydrogen chloride, and 60% - 87.5% of a third solvent by mass percentage. It can be understood that the third solvent is water.

[0063] In a specific example, the cleaning time of the cleaning solution is 80 s - 120 s, and the cleaning temperature is 23°C - 27°C. Specifically, the cleaning time of the cleaning solution can be, but is not limited to, 80 s, 90 s, 100 s, 110 s, or 120 s, and the cleaning temperature can be, but is not limited to, 23°C, 24°C, 25°C, 26°C, or 27°C.

[0064] After the above treatment, a first conductivity type doping region and a second conductivity type doping region are formed on the first surface of the substrate. There is a certain height difference between the first conductivity type doping region and the second conductivity type doping region. The first conductivity type doping region is inside the substrate, and the second conductivity type doping region includes a tunneling oxide layer and a doped polysilicon layer.

[0065] In a specific example, after removing the mask layer, it further includes: preparing a stacked first passivation layer and a first antireflection layer on the first surface, and preparing a stacked second passivation layer and a second antireflection layer on the second surface.

[0066] It can be understood that the first passivation layer covers the doped polysilicon layer in the first conductivity type doping region and the second conductivity type doping region. Further, the material of the first passivation layer and the material of the second passivation layer each independently include one or more of aluminum oxide, molybdenum oxide, and silicon dioxide. The material of the first antireflection layer and the material of the second antireflection layer each independently include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0067] Furthermore, the thickness of the first passivation layer and the second passivation layer each independently is 2 nm - 10 nm, and the thickness of the first antireflection layer and the second antireflection layer each independently is 60 nm - 180 nm.

[0068] Preferably, the material of the first passivation layer and the material of the second passivation layer are aluminum oxide, and the material of the first antireflection layer and the material of the second antireflection layer are silicon nitride.

[0069] In a specific example, after preparing the first antireflection layer, the following steps are further included: preparing a first electrode that penetrates through the first passivation layer and the first antireflection layer and is connected to the substrate, and preparing a second electrode that penetrates through the first passivation layer and the first antireflection layer and is connected to the doped polysilicon layer.

[0070] Further, the preparation methods of the first electrode and the second electrode can be but are not limited to screen printing and metallization treatment.

[0071] This application also provides a solar cell prepared according to the above preparation method.

[0072] This application also provides an electrical device including the above solar cell as a power source.

[0073] Further, an electrical device including the above solar cell as a power source is provided. It can be understood that the above electrical device can include but is not limited to a transformer, a reactor, a capacitor, a combined electrical apparatus, a circuit breaker, an instrument transformer, a lightning arrester, a coupling capacitor, a transmission line, a power cable, a grounding device, a generator, a synchronous condenser, a motor, an enclosed busbar, and a thyristor.

[0074] The following provides specific embodiments to further illustrate in detail the solar cell and its preparation method of this application. The raw materials involved in the following specific embodiments, unless otherwise specified, can all be obtained commercially. The brand of the polishing additive is Tuobang BP21V24.

[0075] Example 1

[0076] The preparation method of the solar cell 10 provided in this example, as Figure 1 shown, includes the following steps:

[0077] Double-sided polishing is performed on the original P-type silicon wafer as the substrate 110. Specifically, a trough-type device is used, the polishing reaction temperature is 72 °C, the polishing reaction time is 240 s, and the polishing liquid is composed of 2% NaOH, 1% polishing additive, and 97% water by weight percentage;

[0078] The double-sided polished silicon wafer substrate 110 is put into a diffusion furnace tube, and a tunneling oxide material layer of silicon dioxide with a thickness of 1.7 nm and an intrinsic polysilicon material layer with a thickness of 150 nm are sequentially formed on both sides of the silicon wafer by using LPECVD equipment;

[0079] The above silicon wafer is placed on a phosphorus diffusion machine platform, and phosphorus oxychloride as a doping material is diffused on the back surface of the silicon wafer, that is, the first surface, to dope the intrinsic polysilicon material to prepare a doped polysilicon material layer, and the phosphorus concentration is 1e20 / cm 3 , and a non-crystalline glass PSG layer with a thickness of 40 nm is attached to the outermost layer of the doped polysilicon material layer;

[0080] The above silicon wafers are sent into an acid etching machine to remove the amorphous glass PSG, doped polysilicon material, and tunneling oxide material on the front side using an etching solution, reacting to the silicon wafer substrate 110; the composition of the etching solution includes, by weight percentage, 10% HF, 10% H 2 SO 4 、10% HNO 3 and 70% water, the etching reaction time is 75 s, the etching temperature is controlled at 25 °C, the above HF is 48 - 50% EL grade HF, H 2 SO 4 is 36% EL grade H 2 SO 4 When using a mixed solution of HF, H 2 SO 4 and HCl for etching, it should be noted that the etching depth controls the sum of the thicknesses of the amorphous glass material, doped polysilicon material, and silicon dioxide on the second surface of the silicon wafer substrate 110;

[0081] The etched silicon wafer substrate 110 enters a tank - type cleaning device to texture the front side, i.e., the second surface, of the silicon wafer; during the texturing process, the texturing reaction temperature is 82 °C, the texturing reaction time is 450 s, and the composition of the texturing solution includes, by weight percentage, 2% NaOH, 1% Shichuang EP12v88 additive, and 97% water;

[0082] After the front side, i.e., the second surface, is textured into a matte surface, a PSG amorphous glass layer above the preset P - type region on the back side, i.e., the first surface, is engraved with a laser to create a laser window. The output power of the laser is 30 w, the overlapping area of adjacent laser spots is 1 / 2 of the laser spot area, the frequency is 500 KHz, the main grid width is 900 μm, the main grid interval is 15 mm, the sub - grid width is 200 μm, and the sub - grid interval is 1.2 mm;

[0083] Then the silicon wafer substrate 110 is sent into a diffusion machine. At a reaction temperature of 900 °C, a SiO 2 with a thickness of 8 nm is deposited on the textured surface of the front side, i.e., the second surface, as a mask layer to protect the textured structure on the front side of the silicon wafer;

[0084] First etching: The PSG amorphous glass layer and the doped polysilicon material layer on the preset P region on the back side, i.e., the first surface, are laser - treated, and the first etching treatment is carried out using a first etching solution. The first etching solution includes, by weight percentage, 1% polishing additive, 1% NaOH, and 98% pure water with a conductivity of 2200 μs / cm. The reaction temperature of the first etching is 67 °C, and the reaction time of the first etching is 300 s. Since there is a tunneling oxide material layer, i.e., SiO 2 above the silicon substrate 110 on the back side, i.e., the first surface, the silicon substrate will not be damaged. At the same time, there is also a relatively thick SiO on the front side, i.e., the second surface.2 Mask layer protection will not cause loss to the matte surface of the front side, i.e., the second surface;

[0085] Second etching: After the back side of the battery, i.e., the first surface, is laser-treated, there is still SiO on the preset P region 2 layer and the excessive phosphorus inner diffusion layer formed by phosphorus diffusion in the substrate 110. At this time, due to the dense PSG layer on the doped polysilicon material layer on the first surface of the substrate 110 that is not laser-treated, and the dense and relatively thick SiO on the second surface of the substrate 110 2 layer protection, it will not be damaged by NaOH. Preferably, after the first etching treatment, there is still tunneling oxide material SiO above the preset P region 2 layer and the excessive phosphorus diffused into the substrate. The reaction temperature is 72 °C and the reaction time is 220 s. The composition of the second etching solution includes 3% NaOH, 1% polishing additive, and 97% pure water with a conductivity of 2200 μs / cm by mass percentage for the second etching to remove part of the tunneling oxide material SiO existing on the preset P region 2 layer and the excessive phosphorus inner diffusion layer formed by phosphorus diffusion in the substrate 110. The height difference between the regions after laser treatment and two etchings and the N-type region should be within 200 nm to 2 μm to ensure complete removal of the phosphorus source diffused into the substrate, otherwise it will cause high battery leakage;

[0086] Then, use an acid solution to clean and remove the PSG amorphous glass layer on the first surface that is not laser-treated and the SiO on the second surface 2 mask layer to achieve PN region engraving and form a P-type doped region and an N-type doped region with a height difference; specifically, clean the silicon dioxide mask layer on the front side, i.e., the second surface, and the amorphous glass layer on the back side, i.e., the first surface. The composition of the cleaning solution includes 20% HF, 10% HCl, and 70% water by mass percentage. The cleaning time is 100 s and the cleaning temperature is 25 °C. After cleaning, a first N-type doped region including a tunneling oxide layer 120 and a doped polysilicon layer 130, and a P-type doped region with a height difference from the N-type doped region are formed;

[0087] Deposit a stacked 2.0 nm thick alumina as the first passivation layer 140 and an 85 nm thick silicon nitride as the first antireflection layer 150 on the first surface, and deposit a stacked 2.0 nm thick alumina as the second passivation layer 141 and a 75 nm thick silicon nitride as the second antireflection layer 151 on the second surface;

[0088] Screen-printed electrode paste, with a laser virtual-to-real ratio of 0.5:0.3 - 0.8:0.3, a silver grid line aspect ratio of 1:3 - 1:6, an aluminum grid line aspect ratio of 1:5 - 1:7, a total wet weight of silver paste of 120 g - 170 g, a total wet weight of aluminum paste of 120 g - 150 g, sintered to form a first electrode 160 in contact with the substrate 110 and a second electrode 170 in contact with the doped polysilicon layer 130, and finally forming a finished cell

[0089] Example 2

[0090] The difference between this example and Example 1 is that: when preparing the front SiO 2 mask layer, the temperature of LPCVD is inconsistent. The temperature in Experimental Example 1 is 820 °C, and that in Experimental Example 2 is 800 °C. The temperature in Experimental Example 1 is higher, and the prepared SiO 2 is thicker and denser, and the protection of the textured surface is more complete. Therefore, the front reflectivity is 0.14% lower than that in Experimental Example 1.

[0091] Comparative Example 1

[0092] The difference between this comparative example and Example 1 is that: Example 1 uses a SiO 2 mask layer to protect the front textured surface area, while Comparative Example 1 does not use a SiO 2 mask to protect the textured surface area. The front textured surface is laser-treated and the processes of etching the material layers on the preset P region on the first surface of the back twice without protection will damage the front textured surface and affect the short-circuit current of the cell.

[0093] Comparative Example 2

[0094] The difference between this comparative example and Example 1 is that: in this comparative example, the laser power is 20 W and the laser is 1 / 2 overlapping laser, resulting in poor loosening of the amorphous glass material PSG on the preset P region. Therefore, from the analysis of the electrical performance results, due to the increased difficulty of preparing the back structure, without mask protection and with a greater degree of damage to the front textured surface, more current loss is caused.

[0095] Performance testing method and result analysis

[0096] The control of the etching depth of each of the above steps can be observed and tested using ZETA, SEM, etc. The reflectivity of the front textured surface is monitored using a D8 reflectometer, and the monitoring range of the front reflectivity is 8% - 9.5%. The battery performance parameters obtained from the above examples and comparative examples are shown in the following table.

[0097] Eta Uoc (V) Isc (A) FF Front reflectance Experimental Example 1 23.69 0.7049 13.639 81.35 9.11％ Experimental Example 2 23.71 0.7052 13.642 81.34 9.25％ Comparative Example 1 23.53 0.7053 13.544 81.31 10.33％ Comparative Example 2 23.42 0.7031 13.528 81.35 11.28％

[0098] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0099] The above-described embodiments merely represent several implementation manners of the present application, which are convenient for understanding the technical solutions of the present application specifically and in detail. However, it should not be construed as a limitation on the scope of patent protection of the application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. It should be understood that the technical solutions obtained by those skilled in the art through logical analysis, reasoning or limited experiments based on the technical solutions provided in the present application are all within the protection scope of the appended claims of the present application. Therefore, the protection scope of the patent of the present application should be subject to the content of the appended claims, and the specification can be used to explain the content of the claims.

Claims

1. A method for preparing a solar cell, characterized in that, it includes the following steps: providing a substrate with a first conductivity type, the substrate having a first surface and a second surface opposite to the first surface; preparing a stacked tunneling oxide material layer and an intrinsic polysilicon material layer on the first surface, diffusing a doping material into the intrinsic polysilicon material layer to prepare a doped polysilicon material layer, the doped polysilicon material layer having a second conductivity type, and the first conductivity type being opposite to the second conductivity type; forming a mask layer on the second surface, and performing laser treatment on a part of the doped polysilicon material layer to prepare a first prefabricated structure, wherein the output power in the laser treatment is 20W - 40W, and the overlapping area of adjacent laser spots is 1 / 3 - 2 / 3 of the laser spot area; placing the first prefabricated structure in a first etching solution and a second etching solution respectively for a first etching treatment and a second etching treatment until a part of the substrate is exposed on the first surface, and removing the mask layer, wherein the first etching solution and the second etching solution each independently include a monobasic strong base, and the monobasic strong base includes one or both of sodium hydroxide and potassium hydroxide.

2. The preparation method according to claim 1, characterized in that, the first etching treatment satisfies one or more of the following conditions: (1) The composition of the first etching solution includes 0.5% - 2% of a polishing additive, 0.5% - 2% of the monobasic strong base, and 96% - 99% of a first solvent by mass percentage; (2) The time of the first etching treatment is 250s - 400s; (3) The temperature of the first etching treatment is 65°C - 70°C.

3. The preparation method according to claim 1, characterized in that, the second etching treatment satisfies one or more of the following conditions: (1) The composition of the second etching solution includes 0.5% - 2% of a polishing additive, 0.5% - 5% of the monobasic strong base, and 93% - 99% of a second solvent by mass percentage; (2) The time of the second etching treatment is 150s - 300s; (3) The temperature of the second etching treatment is 70°C - 75°C.

4. The preparation method according to claim 1, characterized in that, the mask layer satisfies one or two of the following conditions: (1) The material of the mask layer includes one or both of silicon nitride and silicon dioxide; (2) The thickness of the mask layer is 5nm - 10nm.

5. The preparation method according to claim 1, characterized in that, the method for removing the mask layer includes: placing it in a cleaning solution for cleaning, and the cleaning solution includes one or both of hydrofluoric acid and hydrochloric acid.

6. The preparation method according to claim 5, characterized in that, the composition of the cleaning solution includes 8% - 25% of hydrofluoric acid, 4.5% - 15% of hydrogen chloride, and 60% - 87.5% of a third solvent by mass percentage.

7. The preparation method according to any one of claims 1 - 6, characterized in that, before forming the mask layer after preparing the doped polysilicon material layer, it further includes: performing texturing treatment on the first surface.

8. The preparation method according to any one of claims 1 to 6, characterized in that, after removing the mask layer, it further includes: preparing a stacked first passivation layer and a first antireflection layer on the first surface, and preparing a stacked second passivation layer and a second antireflection layer on the second surface.

9. A solar cell, characterized in that, it is prepared by the preparation method according to any one of claims 1 to 8.

10. An electrical device, characterized in that, it includes the solar cell according to claim 9 as a power source.

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