Preparation method of solar cell

Abstract

A preparation method of a solar cell comprises the following steps: providing a semiconductor substrate comprising a front surface and a back surface opposite to the front surface; forming an oxide layer on the front surface of the semiconductor substrate; forming a doped silicon layer on the oxide layer; forming a passivation layer on the doped silicon layer; performing a laser annealing / patterning process to obtain a passivation pattern and a doped silicon pattern; and performing a battery post-processing process, the laser annealing / patterning process including irradiating the front surface of the semiconductor substrate with a pulsed laser having a pulse width greater than 0 ps and less than or equal to 10 ps.

Description

Technical Field

[0001] The present invention relates to the technical field of the preparation method of semiconductor devices, and particularly relates to a preparation method of a solar cell. Background Art

[0002] Solar light is an environment-friendly energy source. A solar cell is a photoelectric element that can directly convert solar light from light energy into electrical energy.

[0003] A tunnel oxide passivated contact (TOPCon) solar cell is a solar cell based on the principle of selective carriers and is one of the most competitive commercial high-efficiency solar cells at present. The tunnel oxide passivated contact solar cell can effectively reduce the recombination rate of carriers on the back surface of the cell, further improve the conversion efficiency of the solar cell, and has the advantage of good stability in a high-temperature environment. Summary of the Invention

[0004] The present invention provides some embodiments regarding a preparation method of a solar cell, including: providing a semiconductor substrate including a front surface and a back surface opposite to the front surface; forming an oxide layer on the front surface of the semiconductor substrate; forming a doped silicon layer on the oxide layer; forming a passivation layer on the doped silicon layer; performing a laser annealing / patterning process to obtain a passivation pattern and a doped silicon pattern; and performing a post-treatment process for the cell. The laser annealing / patterning process includes irradiating the front surface of the semiconductor substrate with pulsed laser having a pulse width greater than 0 ps and less than or equal to 10 ps. Brief Description of the Drawings

[0005] To make the features and advantages of the embodiments of the present invention more obvious and understandable, the present invention will be described in detail below in conjunction with the drawings.

[0006] The exemplary embodiments of the present invention are described in detail with reference to the following drawings, where:

[0007] Figure 1 A flowchart of the preparation method of the solar cell in an embodiment of the present invention is shown;

[0008] Figures 2A to 2F A partial schematic diagram of a solar cell semi-finished product during the preparation of the solar cell in an embodiment of the present invention is shown;

[0009] Figure 2G A schematic diagram of the solar cell in an embodiment of the present invention is shown;

[0010] Figure 3 A schematic diagram of the average implicit open-circuit voltage of the solar cell semi-finished products of the embodiments and comparative examples of the present invention is shown; and

[0011] Figure 4 Shows the relationship diagram of current density and voltage of the solar cells of the embodiments and comparative examples of the present invention.

[0012]

Description of the reference numerals

[0013] S101, S103, S105, S107, S109, S111: Step 10: Semiconductor substrate

[0014] 101: Textured structure

[0015] 10S1: Front surface

[0016] 10S2: Back surface

[0017] 20: Emitter layer

[0018] 30: Oxide layer

[0019] 40: Doped silicon layer

[0020] 40': Annealed doped silicon layer

[0021] 41: Doped silicon pattern

[0022] 50: Passivation layer

[0023] 50': Modified passivation layer

[0024] 51: Passivation pattern

[0025] 60: Positive electrode

[0026] 70: Back electrode

[0027] 80: Back surface tunneling oxidation passivation structure

[0028] 81: Back surface oxide layer

[0029] 83: Back surface passivation layer

[0030] 85: Protective layer

[0031] L: Laser

[0032] W: Width Detailed implementation manners

[0033] The following provides a detailed description of some embodiments of the present invention. It should be understood that the following description provides many different embodiments or examples for implementing different embodiments of some embodiments of the present invention. The specific elements and arrangements described below are only for simply and clearly describing some embodiments of the present invention. Of course, these are only for illustration and not for limiting the present invention. In addition, repeated reference numerals or signs may be used in different embodiments. These repetitions are only for simply and clearly describing some embodiments of the present invention and do not represent any association between the different embodiments and / or structures discussed.

[0034] In addition, the terms "about", "approximately", and "substantially" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3%, or 2%, or 1%, or 0.5%. The quantity given herein is an approximate quantity, that is, the meaning of "about", "approximately", or "substantially" may still be implied even without specifically stating "about", "approximately", or "substantially".

[0035] In addition, the term "less than or equal to" means including a given value and values below the given value, and the term "greater than or equal to" means including a given value and values above the given value. Conversely, the term "less than" means including values less than a given value but not including the given value, and the term "greater than" means including values exceeding a given value but not including the given value. For example, "greater than or equal to a" means including a and values above it, and "greater than a" means including values exceeding a but not including a.

[0036] In addition, the term "any combination of the above" means including combinations of two or more of the listed features. For example, in "including A, B, C or any combination of the above", the "any combination of the above" means including at least one combination of AB, AC, BC, and ABC.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention belongs. It can be understood that these terms, such as those defined in a commonly used dictionary, should be interpreted to have a meaning consistent with the related art and the background or context of the present invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of the present invention.

[0038] Figure 1 It is a flowchart of a method for manufacturing a solar cell according to an embodiment of the present invention. Figures 2A to 2F It is a partial schematic view of a semi-finished solar cell during the manufacture of a solar cell according to an embodiment of the present invention. Figure 2G It is a schematic view of a solar cell according to an embodiment of the present invention. The following combines Figure 1 andFigures 2A to 2G Further illustrate the preparation method of the solar cell in an embodiment of the present invention and the structure of the solar cell in an embodiment of the present invention.

[0039] As Figure 1 shown, the preparation method of the solar cell according to an embodiment of the present invention includes: step S101 of providing a semiconductor substrate, step S103 of forming an oxide layer, step S105 of forming a doped silicon layer, step S107 of forming a passivation layer, step S109 of performing a laser annealing / patterning process, and step S111 of performing a post-treatment process for the cell. The laser annealing / patterning process includes irradiating the front surface of the semiconductor substrate with pulsed laser having a pulse width greater than 0 ps and less than or equal to 10 ps. The semiconductor substrate may include a front surface and a back surface opposite to the front surface, and the oxide layer, the doped silicon layer, and the passivation layer are formed on the front surface of the semiconductor substrate. The doped silicon layer is formed on the oxide layer, and the passivation layer is formed on the doped silicon layer. In other words, the doped silicon layer is located between the oxide layer and the passivation layer.

[0040] The semiconductor substrate 10 provided in step S101 includes a front surface 10S1 and a back surface 10S2 opposite to the front surface 10S1. The semiconductor substrate 10 may include a silicon substrate. In some embodiments, the step S101 of providing the semiconductor substrate may include a substrate cleaning process and optionally a texturing structure forming process. The substrate cleaning process includes cleaning the semiconductor substrate 10 with a cleaning solution. The cleaning solution may include sulfuric acid, hydrochloric acid, ammonium hydroxide, hydrogen peroxide, hydrogen fluoride, deionized water, or any combination thereof. The texturing structure forming process includes potassium hydroxide, deionized water, a texturing additive, or any combination thereof. Apply to form a texturing structure 101 including a plurality of protrusions and recesses on the front surface 10S1 of the semiconductor substrate 10, but the present invention is not limited thereto. In some embodiments, the texturing structure forming process further includes forming a texturing structure 101 on the back surface 10S2 of the semiconductor substrate 10. In some embodiments, the texturing structure forming process may be omitted.

[0041] In some embodiments, the preparation method of the solar cell according to an embodiment of the present invention may further include an emitter layer forming step between step S101 and step S103. The emitter layer forming step may form an emitter layer 20 on the texturing structure 101 on the front surface 10S1 of the semiconductor substrate 10, as Figure 2AAs shown, but the present invention is not limited thereto. In some embodiments, the emitter layer formation step may include an ion diffusion process. Specifically, in some embodiments, the formation of the emitter layer 20 includes performing an ion diffusion process by diffusing ions on the front surface 10S1 of the semiconductor substrate 10 to form the emitter layer 20. In some embodiments, the ions used in the emitter layer formation step may be P-type ions, but the present invention is not limited thereto. Examples of P-type ions may include, but are not limited to, boron ions, aluminum ions, gallium ions, indium ions, or any combination thereof. In some embodiments, the ion diffusion process may include a thermal diffusion process, a laser diffusion process, any suitable diffusion process, or any combination thereof.

[0042] Step S103 may be performed after the emitter layer formation step. In step S103, an oxide layer 30 may be formed on the front surface 10S1 of the semiconductor substrate 10. In some embodiments, the oxide layer 30 may be formed on Figure 2A the structure shown. In other words, the oxide layer 30 may be formed on the emitter layer 20, and the emitter layer 20 may be disposed between the oxide layer 30 and the front surface 10S1 of the semiconductor substrate 10, as Figure 2B shown, but the present invention is not limited thereto. In some embodiments, the oxide layer 30 may be a tunneling oxide layer. In some embodiments, the oxide layer 30 may include silicon oxide, but the present invention is not limited thereto. The oxide layer 30 may be formed by a physical deposition process, a chemical deposition process, or a combination thereof. Examples of physical deposition processes may include vacuum evaporation, sputtering, ion plating, etc., but the present invention is not limited thereto. Examples of chemical deposition processes may include electroplating, chemical vapor deposition, low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), etc., but the present invention is not limited thereto.

[0043] Step S105 may be performed after step S103. In step S105, a doped silicon layer 40 may be formed on the oxide layer 30. For example, in some embodiments, the doped silicon layer 40 may be formed on Figure 2B the structure shown. In other words, the oxide layer 30 may be disposed between the emitter layer 20 and the doped silicon layer 40, as Figure 2CAs shown, but the present invention is not limited thereto. The oxide layer 30 may be disposed between the front surface 10S1 of the semiconductor substrate 10 and the doped silicon layer 40. In some embodiments, the doped silicon layer 40 may include amorphous silicon, microcrystalline silicon, polycrystalline silicon, single-crystalline silicon, silicon carbide, or any combination thereof, but the present invention is not limited thereto. In some embodiments, the ions doped in the doped silicon layer 40 may be P-type ions and / or N-type ions. Examples of P-type ions are as described above. Examples of N-type ions may include, but are not limited to, phosphorus ions, arsenic ions, antimony ions, bismuth ions, or any combination thereof. In some embodiments, the doped silicon layer 40 may be boron ion-doped microcrystalline silicon or boron ion-doped amorphous silicon, but the present invention is not limited thereto. The ions doped in the doped silicon layer 40 may be the same as or different from the ions used in the formation step of the emitter layer. In some embodiments, the ions doped in the doped silicon layer 40 and the ions used in the formation step of the emitter layer are both boron ions, but the present invention is not limited thereto. The doped silicon layer 40 may be formed by a physical deposition process, a chemical deposition process, or a combination thereof. Examples of the physical deposition process and the chemical deposition process are as described above.

[0044] Step S107 is performed after step S105. In step S107, the passivation layer 50 may be formed on the doped silicon layer 40. For example, in some embodiments, the passivation layer 50 may be formed on the Figure 2C structure shown. That is, the doped silicon layer 40 may be disposed between the oxide layer 30 and the passivation layer 50, as Figure 2D shown. In some embodiments, the passivation layer 50 may include silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, or any combination thereof, but the present invention is not limited thereto. The passivation layer 50 may be formed by a physical deposition process, a chemical deposition process, or a combination thereof. Examples of the physical deposition process and the chemical deposition process are as described above.

[0045] Step S109 is performed after step S107. The laser annealing / patterning process in step S109 may include a laser modification process and a patterning process. The laser modification process includes irradiating a specific area of the front surface 10S1 of the semiconductor substrate 10 with a pulsed laser L having a pulse width greater than 0 ps and less than or equal to 10 ps. The laser wavelength of the pulsed laser L may be greater than or equal to 235 nm and less than 533 nm. In some embodiments, the laser wavelength of the pulsed laser L may be 355 nm, but the present invention is not limited thereto.

[0046] In the laser modification process, the doped silicon layer 40 in the specific area is annealed by the pulsed laser L to form an annealed doped silicon layer 40', and the passivation layer 50 is modified by the pulsed laser L to form a modified passivation layer 50', as Figure 2EAs shown. In the annealed doped silicon layer 40', the doping ions originally in the doped silicon layer 40 can be activated and / or doped deeper by the pulsed laser L. In embodiments where the doped silicon layer 40 comprises microcrystalline silicon or amorphous silicon, the doped silicon layer 40 is annealed by the pulsed laser L to form an annealed doped silicon layer 40' comprising polycrystalline silicon. The modified passivation layer 50' formed after the passivation layer 50 is modified by the pulsed laser L can improve the acid and alkali resistance of the passivation layer. The modified passivation layer 50' also has the advantages of reducing the carrier recombination rate and increasing the minority carrier lifetime in the subsequently formed solar cell. In other words, through the laser modification process, the passivation layer 50 can be changed into a modified passivation layer 50' with better acid and alkali resistance, the doped silicon layer 40 can be changed into an annealed doped silicon layer 40' in which the doping ions are activated, the doped silicon layer 40 comprising microcrystalline silicon or amorphous silicon can be changed into an annealed doped silicon layer 40' comprising polycrystalline silicon, and the subsequently formed solar cell can have better photoelectric conversion efficiency.

[0047] The patterning process may include removing the doped silicon layer 40 and the passivation layer 50 by an etching solution and forming a passivation pattern 51 and a doped silicon pattern 41, as Figure 2F shown. In some embodiments, the etching solution used in the patterning process may include hydrofluoric acid, but the present invention is not limited thereto. In some embodiments, the width W of the passivation pattern 51 is greater than or equal to 150 μm and less than or equal to 300 μm. In some embodiments, the width W of the passivation pattern 51 is greater than or equal to 200 μm and less than or equal to 250 μm. In some embodiments, the width W of the passivation pattern 51 is approximately equal to 210 μm.

[0048] Step S111 is performed after step S109. The cell post-treatment process of step S111 includes an optional back surface treatment process and an electrode formation process. In other words, in some embodiments, the cell post-treatment process may only include the electrode formation process. In embodiments where the cell post-treatment process only includes the electrode formation process, the back surface treatment process may be performed before step S103, but the present invention is not limited thereto. In embodiments where the cell post-treatment process includes the back surface treatment process and the electrode formation process, the electrode formation process may be performed after the back surface treatment process. In some embodiments, the execution temperature of the back surface treatment process may be less than or equal to the execution temperature of the laser modification process in step S109 to avoid damaging the layers formed on the front surface 10S1 of the semiconductor substrate 10 or reducing the risk of damaging the layers formed on the front surface 10S1 of the semiconductor substrate 10.

[0049] The back surface treatment process may include forming a back tunneling oxidation passivation structure 80 including a back oxidation layer 81 and a back passivation layer 83 on the back surface 10S2 of the semiconductor substrate 10. The electrode formation process may include a positive electrode formation process of forming the positive electrode 60 on the passivation pattern 51 and the doped silicon pattern 41, and a back electrode formation process of forming the back electrode 70 on the back surface 10S2 of the semiconductor substrate 10.

[0050] In some embodiments, the positive electrode formation process and the back electrode formation process may include a screen printing process, a physical vapor deposition process, an inkjet printing process, etc. In some embodiments, the positive electrode 60 and the back electrode 70 may include copper, silver, aluminum, gold, or any combination thereof. In some embodiments, the back electrode 70 may be formed on the back tunneling oxidation passivation structure 80. The back passivation layer 83 may be located between the back oxidation layer 81 and the back electrode 70. In some embodiments, the back surface treatment process may further include forming a protective layer 85 on the back tunneling oxidation passivation structure 80. In some embodiments, the protective layer 85 may have an opening that exposes a portion of the back passivation layer 83. The back electrode 70 may be formed in the opening and in contact with the back passivation layer 83, as Figure 2G shown, but the present invention is not limited thereto. The back tunneling oxidation passivation structure 80 and the protective layer 85 may be formed by any existing methods and materials in the art, and thus will not be described in detail herein. The solar cell of the present invention may be completed after step S111, and the completed solar cell has a structure as Figure 2G shown, but the present invention is not limited thereto. In some embodiments, the back tunneling oxidation passivation structure 80 may also include a textured structure formed on the back surface 10S2 of the semiconductor substrate 10.

[0051] By using the above steps, especially the laser annealing / patterning process in step 109, the method for manufacturing a solar cell of the present invention can obtain a modified passivation layer 50' with better acid and alkali resistance while obtaining an annealed doped silicon layer 40' in which the doped ions are activated and doped to a deeper depth, or an annealed doped silicon layer 40' in which microcrystalline silicon or amorphous silicon becomes polycrystalline silicon. Therefore, the method for manufacturing a solar cell of the present invention can manufacture a solar cell through fewer process steps, thereby achieving the purpose of reducing production costs. In addition, the pulsed laser L with a pulse width greater than 0 ps and less than or equal to 10 ps does not damage the oxide layer 30 below the doped silicon layer 40. Therefore, the method for manufacturing a solar cell of the present invention can maintain the integrity of the oxide layer 30, thereby improving the electrical characteristics of the solar cell. Further, the pulsed laser L with a laser wavelength greater than or equal to 235 nm and less than 533 nm can be absorbed on the surface of the solar cell without affecting the underlying film layers, so as to avoid the influence of overall high temperature on other film layers.

[0052] One or more advantages of the present invention will now be further described with reference to the following embodiments. However, these embodiments are only used to illustrate the embodiments of the present invention and are not intended to limit the scope of the embodiments of the present invention.

[0053] Preparation of Solar Cells

[0054] Example 1

[0055] Provide a silicon substrate (manufacturer: AUO), clean the silicon substrate with a mixed solution of hydrochloric acid, hydrogen peroxide and deionized water, and then clean it with an aqueous hydrofluoric acid solution. Then, apply a mixed aqueous solution of potassium hydroxide, deionized water, and texturing additive (TS55, purchased from Changzhou Sino-Creat Energy Co., Ltd.) heated to 80 °C on the front side of the silicon substrate to form a textured structure. Then, boron diffusion is carried out by LPCVD, and boron ions are diffused on the front side of the silicon substrate with a textured structure to form a boron emitter layer.

[0056] By chemical vapor deposition, introduce oxygen to react oxygen with the silicon substrate to form a tunneling oxide layer with a thickness of 1 nm to 2 nm. Then, deposit a boron-doped microcrystalline silicon layer on the tunneling oxide layer by low-pressure chemical vapor deposition process. Finally, deposit a silicon nitride layer on the boron-doped microcrystalline silicon layer by plasma-enhanced chemical vapor deposition process.

[0057] Irradiate a specific area on the front side of the silicon substrate with a boron emitter layer, a tunneling oxide layer, a boron-doped microcrystalline silicon layer, and a silicon nitride layer with a laser having a wavelength of 355 nm and a pulse width of 7 ps. After the laser irradiation, the boron-doped microcrystalline silicon layer on this specific area becomes a boron-doped polycrystalline silicon layer, and the silicon nitride layer on this specific area becomes a modified silicon nitride layer.

[0058] Use a 7% hydrofluoric acid and 25% sodium hydroxide aqueous solution to remove the unmodified silicon nitride layer and boron-doped microcrystalline silicon layer outside this specific area to form a passivation pattern and a doped silicon pattern. Form a back tunneling oxide passivation structure on the back side of the silicon substrate by existing methods and materials to complete the preparation of the solar cell semi-finished product.

[0059] Finally, form a positive electrode and a back electrode on the passivation pattern, the doped silicon pattern, and the back tunneling oxide passivation structure to complete the preparation of the solar cell.

[0060] Comparative Example 1

[0061] Prepare a solar cell semi-finished product and a solar cell in the same manner as in Example 1, except that a specific area on the front side of the silicon substrate with a boron emitter layer, a tunneling oxide layer, a boron-doped microcrystalline silicon layer, and a silicon nitride layer is irradiated with a laser having a wavelength of 533 nm and a pulse width of 20 ns.

[0062] Comparative Example 2 (Traditional L-biPC Process)

[0063] A silicon substrate (manufacturer: AUO) is provided. After cleaning the silicon substrate with a mixed solution of hydrochloric acid, hydrogen peroxide, and deionized water, and then with an aqueous hydrofluoric acid solution, a textured structure is formed on the front surface of the silicon substrate by heating it in a mixed aqueous solution of potassium hydroxide, deionized water, and a texturing additive at 80 °C. Then, boron diffusion is carried out by LPCVD to diffuse boron ions on the front surface of the silicon substrate with the textured structure to form a boron emitter layer.

[0064] By chemical vapor deposition, oxygen is introduced to react oxygen with the silicon substrate to form a tunneling oxide layer with a thickness of 1 nm to 2 nm. Then, a boron-doped microcrystalline silicon layer is deposited on the tunneling oxide layer by LPCVD. After depositing the boron-doped microcrystalline silicon layer, a high-temperature annealing treatment at 880 °C to 910 °C is carried out to transform the boron-doped microcrystalline silicon layer into a boron-doped polycrystalline silicon layer. Finally, a silicon nitride layer is deposited on the boron-doped polycrystalline silicon layer by PECVD.

[0065] Using a resist in combination with screen printing technology, screen printing is carried out on specific regions of the boron emitter layer, tunneling oxide layer, boron-doped polycrystalline silicon layer, and silicon nitride layer on the front surface of the silicon substrate. Ensure that the specific regions maintain the required hierarchical structure in subsequent processes.

[0066] A mixed aqueous solution of 7% hydrofluoric acid and 25% sodium hydroxide is used to remove the unmodified silicon nitride layer and boron-doped polycrystalline silicon layer outside the specific regions to form a passivation pattern and a doped silicon pattern.

[0067] A 70% nitric acid solution is used to remove the resist on the silicon substrate. This step ensures that the resist is completely removed, restoring the cleanliness of the silicon substrate surface. A back surface tunneling oxide passivation structure is formed on the back surface of the silicon substrate by existing methods and materials to complete the preparation of the solar cell semi-finished product.

[0068] Finally, a positive electrode and a back electrode are formed on the passivation pattern, doped silicon pattern, and back surface tunneling oxide passivation structure to complete the preparation of the solar cell.

[0069] Comparative Example 3 (TOPCon Cell)

[0070] A silicon substrate (manufacturer: AUO) is provided. After cleaning the silicon substrate with a mixed solution of hydrochloric acid, hydrogen peroxide, and deionized water, and then with an aqueous hydrofluoric acid solution, a textured structure is formed on the front surface of the silicon substrate by applying a mixed aqueous solution of potassium hydroxide, deionized water, and a texturing additive heated to 80 °C. Then, boron diffusion is carried out by LPCVD to diffuse boron ions on the front surface of the silicon substrate with the textured structure to form a boron emitter layer.

[0071] By chemical vapor deposition, oxygen is introduced to react oxygen with the back of the silicon substrate to form a tunneling oxide layer with a thickness of 1 nm to 2 nm. Then, a boron-doped microcrystalline silicon layer is deposited on the tunneling oxide layer by LPCVD. After depositing the boron-doped microcrystalline silicon layer, a high-temperature annealing treatment at 880 °C to 910 °C is carried out to transform the boron-doped microcrystalline silicon layer into a boron-doped polycrystalline silicon layer. Finally, a silicon nitride layer is deposited on the boron-doped polycrystalline silicon layer by PECVD.

[0072] Finally, a positive electrode and a back electrode are formed on the front silicon nitride passivation layer, the doped silicon pattern, and the back tunneling oxide passivation structure, thereby completing the preparation of the solar cell.

[0073] Performance evaluation of the semi-finished solar cell

[0074] The implied open-circuit voltage (Imply Voc, iVoc) of 4 semi-finished solar cells of Example 1, 4 semi-finished solar cells of Comparative Example 1, 4 semi-finished solar cells of Comparative Example 2, and 4 semi-finished solar cells of Comparative Example 3 was measured by the quasi-steady-state photoconductance (QSSPC) method. The results are shown in Table 1 below and Figure 3 as shown.

[0075] The recombination current (J 0 ) and the minority carrier lifetime (Lifetime) of 4 semi-finished solar cells of Example 1, 4 semi-finished solar cells of Comparative Example 1, 4 semi-finished solar cells of Comparative Example 2, and 4 semi-finished solar cells of Comparative Example 3 were measured by the QSSPC method. The results are shown in Table 1 below.

[0076] Table 1

[0077]

[0078]

[0079] Figure 3 This is a schematic diagram of the iVoc of the semi-finished solar cells of the examples and comparative examples of the present invention. The higher the iVoc, the better the surface passivation effect of the semi-finished solar cell, and the better the photoelectric conversion effect of the subsequent formed solar cell. In addition, the higher the minority carrier lifetime, the better the photoelectric conversion effect of the subsequent formed solar cell. In addition, the J 0 parameter refers to the dark saturation current density, which is a key indicator for measuring the carrier recombination loss in semiconductor materials. A low J 0 value usually means small carrier recombination loss, a higher open-circuit voltage can be obtained, thereby improving the efficiency of the solar cell. From Figure 3As can be clearly seen from Table 1, the average iVoc of the semi-finished solar cells in Example 1 is at least 7 mV higher than that of the semi-finished solar cells in Comparative Examples 1 to 3. The average minority carrier lifetime of the semi-finished solar cells in Example 1 is at least 178.5 μs longer than that of the semi-finished solar cells in Comparative Examples 1 to 3. The average J 0 of the semi-finished solar cells in Example 1 is at least 1.425 fA / cm less than the average J 0 of the semi-finished solar cells in Comparative Examples 1 to 3. 2 Therefore, the solar cells prepared by the method for preparing a solar cell according to the present invention at least have a good photoelectric conversion effect, and can reduce more than two processes, thereby reducing the cost.

[0080] Solar Cell Performance Evaluation

[0081] The relationship diagram of current density and voltage of the solar cell in Example 1 and the solar cell in Comparative Example 2 was measured by a solar simulator IV measuring instrument, and the results are as Figure 4 shown.

[0082] The short-circuit current density (Short Circuit Current Density, Jsc), open-circuit voltage (Open Circuit Voltage, Voc), fill factor (Fill Factor, F.F.) of the solar cell, and cell efficiency (Eff) of the solar cell in Example 1 and the solar cell in Comparative Example 2 were measured by a solar simulator IV measuring instrument. The above measurement results are shown in Table 2.

[0083] Table 2

[0084] <![CDATA[Jsc (mA / cm 2 )]]> Voc (mV) F.F (%) Eff (%) Example 1 35.87 657 77.26 18.11 Comparative Example 2 35.84 664 75.10 17.88

[0085] Figure 4 is the relationship diagram of current density and voltage of the solar cells according to the examples and comparative examples of the present invention. From Figure 4 Table 2, it can be seen that the solar cell in Example 1 has an F.F. 2.16% higher and an Eff 0.23% higher than the solar cell in Comparative Example 2. It can be seen that the solar cells prepared by the method for preparing a solar cell according to the present invention at least have a good photoelectric conversion efficiency.

[0086] In summary, the method for preparing a solar cell according to the present invention can not only prepare solar cells through fewer process steps, thereby achieving the purpose of reducing production costs, but also the prepared solar cells at least have a good photoelectric conversion efficiency.

[0087] Although the embodiments of the present invention and their advantages have been disclosed as above, it should be understood that any person skilled in the art can make changes, substitutions, and modifications without departing from the spirit and scope of the present invention. In addition, the protection scope of the present invention is not limited to the processes, machines, manufactures, compositions of matter, devices, methods, and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the processes, machines, manufactures, compositions of matter, devices, methods, and steps developed currently or in the future from the disclosure of some embodiments of the present invention. As long as they can perform substantially the same functions or achieve substantially the same results in the embodiments described herein, they can be used according to some embodiments of the present invention. Therefore, the protection scope of the present invention includes the above-mentioned processes, machines, manufactures, compositions of matter, devices, methods, and steps. In addition, each claim constitutes an individual embodiment, and the protection scope of the present invention also includes the combination of each claim and embodiment.

Claims

1. A method for preparing a solar cell, characterized in that, comprising: providing a semiconductor substrate, wherein the semiconductor substrate includes a front surface and a back surface opposite to the front surface; forming an oxide layer on the front surface of the semiconductor substrate; forming a doped silicon layer on the oxide layer; forming a passivation layer on the doped silicon layer; performing a laser annealing / patterning process to obtain a passivation pattern and a doped silicon pattern; and performing a post-treatment process for the cell, wherein the laser annealing / patterning process includes irradiating the front surface of the semiconductor substrate with a pulsed laser having a pulse width greater than 0 ps and less than or equal to 10 ps.

2. The method for preparing a solar cell according to claim 1, characterized in that, the laser wavelength of the pulsed laser is greater than or equal to 235 nm and less than 533 nm.

3. The method for preparing a solar cell according to claim 2, characterized in that, the laser wavelength of the pulsed laser is 355 nm.

4. The method for preparing a solar cell according to claim 1, characterized in that, the step of providing the semiconductor substrate includes forming a textured structure on the front surface of the semiconductor substrate.

5. The method for preparing a solar cell according to claim 1, characterized in that, further comprising: forming an emitter layer on the front surface of the semiconductor substrate before forming the oxide layer.

6. The method for preparing a solar cell according to claim 5, characterized in that, the formation of the emitter layer includes: performing an ion diffusion process to form the emitter layer.

7. The method for preparing a solar cell according to claim 1, characterized in that, the width of the passivation pattern is greater than or equal to 150 μm and less than or equal to 300 μm.

8. The method for preparing a solar cell according to claim 1, characterized in that, the doped silicon layer includes: amorphous silicon, microcrystalline silicon, polycrystalline silicon, single crystal silicon, silicon carbide, or any combination thereof.

9. The method for preparing a solar cell according to claim 1, characterized in that, the passivation layer includes: silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, or any combination thereof.

10. The method for preparing a solar cell according to claim 1, characterized in that, the oxide layer includes: silicon oxide.

11. The method for preparing a solar cell according to claim 1, characterized in that, the post-treatment process for the cell includes: a back surface treatment process, a front electrode formation process, and / or a back electrode formation process.

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