Preparation method of back contact cell, back contact cell and photovoltaic module
During the preparation of the back contact battery, an annealing process is used to form a doped polysilicon layer containing oxygen elements, which solves the problems of complex processes and impurities introduction in the prior art, and achieves efficient preparation of polysilicon layer and improves battery performance.
Patent Information
- Application Number
- CN202510211419.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-06-10
AI Technical Summary
The prior art When preparing polysilicon layers containing oxygen doped, the process is complicated and an additional oxygen source is required, which may introduce other impurities interference.
During the preparation of the back contact battery, the oxygen atoms in the first ultra-thin oxide layer and the second ultra-thin oxide layer are combined with the silicon atoms in the doped polysilicon layer to form Si-O bonds to form a doped polysilicon layer, forming an oxygen-containing doped polysilicon layer, simplifying the preparation process and avoiding the introduction of impurities.
The preparation process of the polysilicon layer containing oxygen elements is simplified, the passivation effect and photoelectric conversion efficiency of the doped polysilicon layer are improved, and the performance of the battery is enhanced.
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Figure CN120129331A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of photovoltaics, and particularly relates to a preparation method of a back contact battery, a back contact battery, and a photovoltaic module. Background Art
[0002] A back contact battery (BC) refers to a solar cell in which both the positive and negative electrodes are disposed on the back surface, so as to reduce the light shielding when the electrodes are disposed on the front surface and improve the conversion efficiency of the battery. The back contact battery technology is considered to be the development direction of future crystalline silicon solar cell technology. TOPCon batteries, due to their unique structure, achieve selective carrier transport, thereby reducing recombination, increasing the open-circuit voltage and fill factor of the battery, and improving the battery conversion efficiency. Currently, the types of back contact batteries mainly include TBC, HPBC, HBC, etc. Among them, the TBC battery adopts the TOPCon structure for both polarities P-type / N-type in the back surface structure of the battery. On the basis of satisfying a high open-circuit voltage and fill factor, a high current is achieved, thereby greatly improving the battery efficiency.
[0003] A Chinese patent application with the application number 202410694691.3 discloses a solar cell, a photovoltaic module, and a photovoltaic system, which discloses a TBC battery structure, and at least one of the elements oxygen, carbon, and nitrogen is doped in the polysilicon layer. In the prior art solution, when preparing a polysilicon layer doped with oxygen element, an additional oxygen source needs to be introduced, and the preparation process is complex. Summary of the Invention
[0004] One of the purposes of the present invention is to provide a preparation method of a back contact battery, which solves the problems proposed in the above background art.
[0005] To achieve the above purpose, the technical solution adopted by the present invention is: a preparation method of a back contact battery, comprising the following steps:
[0006] S1. Provide a silicon substrate and texture the surface of the silicon substrate;
[0007] S2. Sequentially prepare a first tunneling layer and a first intrinsic amorphous silicon layer on the back surface of the silicon substrate;
[0008] S3. Alternately prepare multiple layers of a first ultra-thin oxide layer and a first intrinsic amorphous silicon layer on the surface of the first intrinsic amorphous silicon layer;
[0009] S4. Perform a first diffusion on the back surface, dope and anneal the first intrinsic amorphous silicon layer to form a first doped polysilicon layer having a first polarity; when annealing the back surface of the silicon substrate, simultaneously combine oxygen atoms with silicon atoms in the first doped polysilicon layer to form Si-O bonds, thereby forming a first doped polysilicon layer containing oxygen element;
[0010] S5. Remove part of the first doped polysilicon layer, the first ultra-thin oxide layer and the first tunneling layer to expose part of the back surface of the silicon substrate;
[0011] S6. Sequentially prepare a second tunneling layer and a second intrinsic amorphous silicon layer on the back surface of the silicon substrate;
[0012] S7. Sequentially and alternately prepare multiple layers of the second ultra-thin oxide layer and the second intrinsic amorphous silicon layer on the surface of the second intrinsic amorphous silicon layer;
[0013] S8. Perform a second diffusion on the back surface, dope and anneal the second intrinsic amorphous silicon layer to form a second doped polysilicon layer, and the second doped polysilicon layer has a second polarity opposite to the first polarity; when annealing the back surface of the silicon substrate, simultaneously combine oxygen atoms with silicon atoms in the second doped polysilicon layer to form Si-O bonds, so that oxygen elements enter the second doped polysilicon layer to form a second doped polysilicon layer containing oxygen elements;
[0014] S9. Remove the second doped polysilicon layer, the second ultra-thin oxide layer and the second tunneling layer covering the surface of the first doped polysilicon layer, and make an isolation groove between the first doped polysilicon layer and the second doped polysilicon layer;
[0015] S10. Prepare a front passivation layer and a front antireflection layer on the front surface of the battery, and prepare a back passivation layer on the back surface of the battery;
[0016] S11. Prepare electrodes to make the electrodes contact with the first doped polysilicon layer and the second doped polysilicon layer respectively.
[0017] Based on the above solution and as a preferred solution of the above solution, the thickness of each layer of the first ultra-thin oxide layer and each layer of the second ultra-thin oxide layer is 0.1 nm to 1 nm.
[0018] Based on the above solution and as a preferred solution of the above solution, the thickness of each layer of the first doped polysilicon layer and each layer of the second doped polysilicon layer is 5 nm to 80 nm.
[0019] Based on the above solution and as a preferred solution of the above solution, the total thickness of each layer of the first doped polysilicon layer is 40 nm to 250 nm, and the total thickness of each layer of the second doped polysilicon layer is 40 nm to 250 nm.
[0020] Based on the above solution and as a preferred solution of the above solution, the first tunneling layer, the first intrinsic amorphous silicon layer, the first ultra-thin oxide layer, the second tunneling layer, the second intrinsic amorphous silicon layer and the second ultra-thin oxide layer are all prepared by LPCVD process.
[0021] Based on the above - mentioned solution and as a preferred solution of the above - mentioned solution, the doping element in the first doped polysilicon layer is phosphorus, the doping element in the second doped polysilicon layer is boron, and the doping concentration of phosphorus or boron in each of the first doped polysilicon layer and the second doped polysilicon layer increases successively from the inside to the outside.
[0022] Based on the above - mentioned solution and as a preferred solution of the above - mentioned solution, the front and back surfaces of the silicon substrate are both provided with a textured structure.
[0023] Based on the above - mentioned solution and as a preferred solution of the above - mentioned solution, the first ultra - thin oxide layer and the second ultra - thin oxide layer are silicon oxide layers.
[0024] The second object of the present invention is to provide a back - contact battery prepared by the above - mentioned preparation method.
[0025] The third object of the present invention is to provide a photovoltaic module, and the photovoltaic module includes the back - contact battery as described above.
[0026] The beneficial effects of the present invention are as follows:
[0027] 1. When preparing the doped polysilicon layer containing oxygen element by this preparation method of the back - contact battery, through the annealing process, oxygen atoms in the first ultra - thin oxide layer and the second ultra - thin oxide layer respectively combine with silicon atoms in the first doped polysilicon layer and the second doped polysilicon layer to form Si - O bonds, forming a doped polysilicon layer containing oxygen element. There is no need to additionally introduce an oxygen source, no other impurities will be introduced for interference, and only one diffusion process is required subsequently, simplifying the preparation process of the doped polysilicon layer containing oxygen element.
[0028] 2. The first doped polysilicon layer and the second doped polysilicon layer contain oxygen element, which helps to improve the passivation effect of the doped polysilicon layer and can also reduce the parasitic absorption in the medium - and long - wavelength bands; at the same time, it makes the bandgap of the doped polysilicon layer increase, thereby reducing the absorption ability of the doped polysilicon layer to incident light, increasing the short - circuit current of the doped polysilicon layer, and thus improving the photoelectric conversion efficiency of the solar cell.
[0029] 3. Setting multiple layers of the first ultra - thin oxide layer and the second ultra - thin oxide layer can enhance the multiple reflections of incident light in the battery, enhance light absorption, reduce the external reflection loss and back - surface absorption loss at the back of the battery, and improve Jsc; multiple layers of the first ultra - thin oxide layer and the second ultra - thin oxide layer can also block the diffusion of P or B impurities to the silicon substrate, reduce the Auger recombination loss caused by impurity diffusion in the silicon substrate, improve the passivation effect, and improve Voc; and due to the blocking of multiple layers of the first ultra - thin oxide layer and the second ultra - thin oxide layer, a part of the impurities are blocked and then flow back to the surface layer, reducing the contact resistance between the electrode and the doped polysilicon layer. Description of the Drawings
[0030] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0031] Figure 1 It is a schematic structural diagram after step S1 of the present invention.
[0032] Figure 2 It is a schematic structural diagram after step S2 of the present invention.
[0033] Figure 3 It is a schematic structural diagram after step S3 of the present invention.
[0034] Figure 4 It is a schematic structural diagram after step S4 of the present invention.
[0035] Figure 5 It is a schematic structural diagram after step S5 of the present invention.
[0036] Figure 6 It is a schematic structural diagram after step S6 of the present invention.
[0037] Figure 7 It is a schematic structural diagram after step S7 of the present invention.
[0038] Figure 8 It is a schematic structural diagram after step S8 of the present invention.
[0039] Figure 9 It is a schematic structural diagram after step S9 of the present invention.
[0040] Figure 10 It is a schematic structural diagram after step S10 of the present invention.
[0041] Figure 11 It is a schematic structural diagram after step S11 of the present invention.
[0042] The reference numerals are as follows:
[0043] 1, silicon substrate; 2, first tunneling layer; 3, first intrinsic amorphous silicon layer; 4, first ultra-thin oxide layer; 5, first doped polysilicon layer; 6, second tunneling layer; 7, second intrinsic amorphous silicon layer; 8, second ultra-thin oxide layer; 9, second doped polysilicon layer; 10, front passivation layer; 11, front anti-reflection layer; 12, back passivation layer; 13, electrode. Detailed implementation manners
[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0045] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.
[0046] As shown in the attached Figure 1 to the attached Figure 11 figures, a method for preparing a back-contact battery includes the following steps:
[0047] S1. Provide a silicon substrate 1 and texture the surface of the silicon substrate 1.
[0048] S2. Sequentially prepare a first tunneling layer 2 and a first intrinsic amorphous silicon layer 3 on the back surface of the silicon substrate 1.
[0049] S3. Alternately prepare multiple layers of a first ultra-thin oxide layer 4 and a first intrinsic amorphous silicon layer 3 on the surface of the first intrinsic amorphous silicon layer 3 in sequence.
[0050] S4. Perform a first diffusion on the back surface, dope and anneal the first intrinsic amorphous silicon layer 3 to form a first doped polysilicon layer 5, and the first doped polysilicon layer 5 has a first polarity; when annealing the back surface of the silicon substrate 1, simultaneously combine oxygen atoms with silicon atoms in the first doped polysilicon layer 5 to form Si-O bonds, forming a first doped polysilicon layer 5 containing oxygen elements.
[0051] S5. Remove part of the first doped polysilicon layer 5, the first ultra-thin oxide layer 4, and the first tunneling layer 2 to expose a part of the back surface of the silicon substrate 1.
[0052] S6. Sequentially prepare a second tunneling layer 6 and a second intrinsic amorphous silicon layer 7 on the back surface of the silicon substrate 1.
[0053] S7. Alternately prepare multiple layers of a second ultra-thin oxide layer 8 and a second intrinsic amorphous silicon layer 7 on the surface of the second intrinsic amorphous silicon layer 7 in sequence.
[0054] S8. Perform a second diffusion on the back surface, dope and anneal the second intrinsic amorphous silicon layer 7 to form a second doped polysilicon layer 9, where the second doped polysilicon layer 9 has a second polarity opposite to the first polarity; when annealing the back surface of the silicon substrate 1, simultaneously combine oxygen atoms with silicon atoms in the second doped polysilicon layer 9 to form Si-O bonds, enabling oxygen elements to enter the second doped polysilicon layer 9, thus forming a second doped polysilicon layer 9 containing oxygen elements;
[0055] S9. Remove the second doped polysilicon layer 9, the second ultra-thin oxide layer 8, and the second tunneling layer 6 covering the surface of the first doped polysilicon layer 5, and create an isolation groove between the first doped polysilicon layer 5 and the second doped polysilicon layer 9;
[0056] S10. Prepare a front passivation layer 10 and a front antireflection layer 11 on the front side of the battery, and prepare a back passivation layer 12 on the back side of the battery;
[0057] S11. Prepare electrodes 13, making the electrodes 13 contact the first doped polysilicon layer 5 and the second doped polysilicon layer 9 respectively.
[0058] When preparing the back-contact battery with multiple layers of ultra-thin oxide layers and doped polysilicon layers containing oxygen elements stacked, through the annealing process, oxygen atoms in the first ultra-thin oxide layer and the second ultra-thin oxide layer respectively combine with silicon atoms in the first doped polysilicon layer and the second doped polysilicon layer to form Si-O bonds, forming the first doped polysilicon layer and the second doped polysilicon layer containing oxygen elements. There is no need to additionally introduce an oxygen source, no other impurities will be introduced for interference, and only one diffusion process is required subsequently to complete, simplifying the preparation process of the polysilicon layer containing oxygen elements.
[0059] Setting multiple layers of the first ultra-thin oxide layer and the second ultra-thin oxide layer can enhance the multiple reflections of incident light in the battery, enhance light absorption, reduce the external reflection loss and the back absorption loss on the back side of the battery, and improve Jsc; the multiple layers of the first ultra-thin oxide layer and the second ultra-thin oxide layer can also block the diffusion of P or B impurities into the silicon substrate, reduce the Auger recombination loss caused by impurity diffusion in the silicon substrate, improve the passivation effect, and increase Voc; and due to the blocking of the multiple layers of the first ultra-thin oxide layer and the second ultra-thin oxide layer, a part of the impurities are blocked and then flow back to the surface layer, reducing the contact resistance between the electrode and the doped polysilicon layer.
[0060] The thickness of each layer of the first ultra-thin oxide layer 4 and each layer of the second ultra-thin oxide layer 8 is 0.1 nm to 1 nm. In the case of stacking multiple layers of ultra-thin oxide layers and semiconductor layers, the diffusion blocking effect of each ultra-thin oxide layer is weak, which is beneficial for doping elements to enter the silicon substrate to form a field passivation effect.
[0061] The thickness of each layer of the first doped polysilicon layer 5 and each layer of the second doped polysilicon layer 9 is 5 nm to 80 nm.
[0062] The total thickness of each layer of the first doped polysilicon layer 5 is 40 nm to 250 nm, and the total thickness of each layer of the second doped polysilicon layer 9 is 40 nm to 250 nm.
[0063] The first tunneling layer 2, the first intrinsic amorphous silicon layer 3, the first ultra-thin oxide layer 4, the second tunneling layer 6, the second intrinsic amorphous silicon layer 7, and the second ultra-thin oxide layer 8 are all prepared by LPCVD process.
[0064] The doping element in the first doped polysilicon layer 5 is phosphorus, and the doping element in the second doped polysilicon layer 9 is boron. The doping concentration of phosphorus or boron in each layer of the first doped polysilicon layer 5 and the second doped polysilicon layer 9 increases sequentially from the inside to the outside. The first doped polysilicon layer and the second doped polysilicon layer located in the outer layer are in direct contact with the electrode, with a high doping concentration and better conductivity, which can reduce the contact resistance between the electrode and the semiconductor layer; the first doped polysilicon layer and the second doped polysilicon layer located in the inner layer are close to the silicon substrate, with a low doping concentration and better passivation performance, which can reduce the recombination with the silicon substrate.
[0065] The front and back surfaces of the silicon substrate 1 are both provided with a textured structure.
[0066] The first ultra-thin oxide layer 4 and the second ultra-thin oxide layer 8 are silicon oxide layers.
[0067] A back-contact battery is prepared by using the above-mentioned preparation method.
[0068] A photovoltaic module, the photovoltaic module includes the back-contact battery as described above.
[0069] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments described herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for preparing a back contact battery, characterized in that: The following steps are involved: S1, providing a silicon substrate (1), and texturing the surface of the silicon substrate (1); S2, sequentially preparing a first tunneling layer (2) and a first intrinsic amorphous silicon layer (3) on the back side of the silicon substrate (1); S3, alternately preparing multiple layers of the first ultra-thin oxide layer (4) and the first intrinsic amorphous silicon layer (3) on the surface of the first intrinsic amorphous silicon layer (3); S4, performing a first diffusion on the back side, doping and annealing the first intrinsic amorphous silicon layer (3), forming a first doped polysilicon layer (5), wherein the first doped polysilicon layer (5) has a first polarity; when annealing the back side of the silicon substrate (1), oxygen atoms and silicon atoms in the first doped polysilicon layer (5) are combined to form Si-O bonds, thereby forming a first doped polysilicon layer (5) containing oxygen elements; S5, removing part of the first doped polysilicon layer (5), the first ultra-thin oxide layer (4) and the first tunneling layer (2), so that the back side of the silicon substrate (1) is partially exposed; S6, sequentially preparing a second tunneling layer (6) and a second intrinsic amorphous silicon layer (7) on the back side of the silicon substrate (1); S7, alternately preparing multiple layers of second ultra-thin oxide layer (8) and second intrinsic amorphous silicon layer (7) on the surface of the second intrinsic amorphous silicon layer (7); S8, performing a second diffusion on the back side, doping and annealing the second intrinsic amorphous silicon layer (7) to form a second doped polysilicon layer (9), wherein the second doped polysilicon layer (9) has a second polarity opposite to the first polarity; when annealing the back side of the silicon substrate (1), oxygen atoms and silicon atoms in the second doped polysilicon layer (9) are combined to form Si-O bonds, so that oxygen elements enter the second doped polysilicon layer (9), thereby forming a second doped polysilicon layer (9) containing oxygen elements; S9, removing the second doped polysilicon layer (9), the second ultra-thin oxide layer (8) and the second tunneling layer (6) covering the surface of the first doped polysilicon layer (5), and providing an isolation groove between the first doped polysilicon layer (5) and the second doped polysilicon layer (9); S10, preparing a front passivation layer (10) and a front anti-reflection layer (11) on the front side of the battery, and preparing a back passivation layer (12) on the back side of the battery; S11, preparing an electrode (13), so that the electrode (13) is in contact with the first doped polysilicon layer (5) and the second doped polysilicon layer (9), respectively.
2. A method for preparing a back contact battery according to claim 1, characterized in that: The thickness of each layer of the first ultra-thin oxide layer (4) and each layer of the second ultra-thin oxide layer (8) is 0.1 nm to 1 nm.
3. The method for preparing a back contact battery according to claim 2, characterized in that: The thickness of each of the first doped polysilicon layers (5) and each of the second doped polysilicon layers (9) is 5 nm to 80 nm.
4. A method for preparing a back contact battery according to claim 3, characterized in that: The total thickness of each layer of the first doped polysilicon layer (5) is 40 nm to 250 nm, and the total thickness of each layer of the second doped polysilicon layer (9) is 40 nm to 250 nm.
5. The method for preparing a back contact battery according to claim 1, characterized in that: The first tunneling layer (2), the first intrinsic amorphous silicon layer (3), the first ultra-thin oxide layer (4), the second tunneling layer (6), the second intrinsic amorphous silicon layer (7) and the second ultra-thin oxide layer (8) are all prepared by adopting the LPCVD process.
6. The method for preparing a back contact battery according to claim 1, characterized in that: The doping element in the first doped polysilicon layer (5) is phosphorus, and the doping element in the second doped polysilicon layer (9) is boron. The doping concentration of phosphorus or boron in the first doped polysilicon layer (5) and the second doped polysilicon layer (9) increases from the inside to the outside.
7. The method for preparing a back contact battery according to claim 1, characterized in that: The front and back sides of the silicon substrate (1) are both provided with velvet structures.
8. The method for preparing a back contact battery according to claim 1, characterized in that: The first ultra-thin oxide layer (4) and the second ultra-thin oxide layer (8) are silicon oxide layers.
9. A back contact battery, characterized in that: The method is prepared by any one of claims 1 to 8.
10. A photovoltaic module, characterized in that: The photovoltaic module comprises the back-contact cell according to claim 9.
Citation Information
Patent Citations
Solar cell, photovoltaic module and photovoltaic system
CN118538792A