Passivation structure, solar cell and preparation method

Abstract

The invention discloses a passivation structure, a solar cell and a preparation method, the passivation structure comprises a tunneling oxide layer, a first silicide layer and a first polycrystalline silicon layer which are sequentially laminated on a backlight surface of a silicon substrate, the first silicide layer and the first polycrystalline silicon layer are both N-type doped, the thickness of the first silicide layer is 5-50nm, the thickness of the first polycrystalline silicon layer is 5-50nm, and the thickness of the second silicide layer is 5-50nm. The thickness of the first polycrystalline silicon layer ranges from 10 nm to 95 nm, and the total thickness of the first silicide layer and the first polycrystalline silicon layer ranges from 15 nm to 100 nm. According to the invention, the N-type doped silicide layer is added on the back surface of the silicon substrate, so that the thickness of the N-type doped polycrystalline silicon layer can be reduced on the premise of not changing slurry, the passivation performance is considered, parasitic absorption is reduced, and the photoelectric conversion efficiency of the cell is remarkably improved while a sintering process window is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of solar energy, and in particular relates to a passivation structure, a solar cell and a preparation method thereof. Background Art

[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in the domestic and foreign photovoltaic markets are also constantly increasing, and industry manufacturers have focused on the research and development of high-efficiency batteries. TOPCon (Tunnel Oxide Passivated Contact) batteries can improve the surface passivation performance of the battery, reduce the metal contact composite current, and effectively increase the open circuit voltage and short circuit current of the battery by sequentially preparing an ultra-thin tunnel oxide layer and a doped polysilicon layer on the back of the silicon substrate.

[0003] In the prior art, the thicker the doped polysilicon layer on the back of the TOPCon cell, the larger the window for metal slurry burn-through resistance, but the parasitic absorption is also higher. Therefore, one of the solutions to improve the efficiency of the TOPCon cell is to reduce the thickness of the doped polysilicon layer and reduce the parasitic absorption of the long-wave band on the back. However, this requires the slurry to be matched. Otherwise, the doped polysilicon layer is too thin and the slurry will penetrate the doped polysilicon layer during sintering, destroying the underlying tunneling oxide layer, resulting in poor passivation and low cell efficiency. Currently, mass-produced TOPCon cells are limited by the slurry sintering window, and the thickness of the doped polysilicon layer on the back is 100nm to 150nm, which cannot be thinned any further.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a passivation structure, a solar cell and a preparation method thereof. Summary of the invention

[0005] In view of this, an object of the present invention is to provide a passivation structure, a solar cell and a preparation method thereof, so as to reduce the thickness of the back polysilicon layer while avoiding the destruction of the tunnel oxide layer during the slurry sintering process.

[0006] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0007] A passivation structure is located on the backlight surface of a silicon substrate. The passivation structure includes a tunneling oxide layer, a first silicide layer and a first polysilicon layer stacked in sequence on the backlight surface of the silicon substrate. The first silicide layer and the first polysilicon layer are both N-type doped. The thickness of the first silicide layer is 5nm to 50nm, the thickness of the first polysilicon layer is 10nm to 95nm, and the total thickness of the first silicide layer and the first polysilicon layer is 15nm to 100nm.

[0008] In one embodiment, the first silicide layer is any one or more combinations of a silicon carbide layer, a silicon nitride layer, and a silicon oxide layer; and / or,

[0009] The first silicide layer is a layer of N-type doped silicide layer, or a combination of multiple silicide layers with the same or different N-type doping concentrations; and / or,

[0010] The first polysilicon layer is a layer of N-type doped polysilicon layer, or a combination of multiple polysilicon layers with the same or different N-type doping concentrations.

[0011] In one embodiment, the silicide layer is doped with phosphorus, and the first polysilicon layer is doped with phosphorus; and / or,

[0012] The doping concentration of the first silicide layer is 2E20cm -3 ~3E21cm -3 or 5E20cm -3 ~2E21cm -3 and / or,

[0013] The doping concentration of the first polysilicon layer is 2E20cm -3 ~3E21cm -3 or 5E20cm -3 ~2E21cm -3 .

[0014] In one embodiment, the passivation structure also includes a second silicide layer stacked between the tunneling oxide layer and the first silicide layer and / or stacked between the first silicide layer and the first polysilicon layer, the thickness of the second silicide layer is 0 to 50 nm, and the total thickness of the first silicide layer, the second silicide layer and the first polysilicon layer is 15 nm to 100 nm.

[0015] In one embodiment, the second silicide layer is any one or more combinations of a silicon carbide layer, a silicon nitride layer, and a silicon oxide layer; and / or,

[0016] The second silicide layer is an intrinsic silicide layer, or an N-type doped silicide layer, or a combination of multiple silicide layers with the same or different N-type doping concentrations.

[0017] In one embodiment, the passivation structure further includes a second polysilicon layer stacked between the tunnel oxide layer and the silicide layer, the thickness of the second polysilicon layer is 0 to 70 nm, and the total thickness of the silicide layer, the first polysilicon layer and the second polysilicon layer is 15 nm to 100 nm.

[0018] In one embodiment, the second polysilicon layer is an intrinsic polysilicon layer, or an N-type doped polysilicon layer, or a combination of multiple polysilicon layers with the same or different N-type doping concentrations.

[0019] In one embodiment, the tunneling oxide layer is any one or more combinations of a silicon dioxide layer and a silicon oxynitride layer; and / or,

[0020] The thickness of the tunnel oxide layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm; and / or,

[0021] The silicon substrate is an N-type silicon substrate.

[0022] Another embodiment of the present invention provides a technical solution as follows:

[0023] A solar cell comprises a silicon substrate, a P-type emitter is formed on the light-receiving surface of the silicon substrate, the above-mentioned passivation structure is formed on the backlight surface of the silicon substrate, the solar cell also comprises a first electrode and a second electrode, the first electrode is in electrical contact with the P-type emitter, and the second electrode is in electrical contact with a first polysilicon layer.

[0024] In one embodiment, a passivation layer and / or a first anti-reflection layer is further formed on the P-type emitter; and / or,

[0025] A second anti-reflection layer is also formed on the passivation structure.

[0026] Another embodiment of the present invention provides a technical solution as follows:

[0027] A method for preparing a solar cell, the method comprising the following steps:

[0028] Providing a silicon substrate;

[0029] A tunneling oxide layer, a first silicide layer and a first polysilicon layer are sequentially deposited on one surface of a silicon substrate by a PECVD process. Both the first silicide layer and the first polysilicon layer are N-type doped. The thickness of the first silicide layer is 5nm to 50nm, the thickness of the first polysilicon layer is 10nm to 95nm, and the total thickness of the first silicide layer and the first polysilicon layer is 15nm to 100nm.

[0030] In one embodiment, the tunnel oxide layer, the first silicide layer and the first polysilicon layer are deposited sequentially in the same PECVD equipment.

[0031] In one embodiment, before the PECVD process, the process further includes: forming a P-type emitter on the other side surface of the silicon substrate; and,

[0032] After the PECVD process, the method further includes: preparing a first electrode on the P-type emitter, and preparing a second electrode on the first polysilicon layer.

[0033] The present invention has the following beneficial effects:

[0034] The present invention adds an N-type doped silicide layer on the back of the silicon substrate, which can reduce the thickness of the N-type doped polysilicon layer without changing the slurry, while taking into account the passivation performance and reducing parasitic absorption, thereby significantly improving the photoelectric conversion efficiency of the battery while improving the sintering process window. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 is a schematic structural diagram of the passivation structure in Example 1 of the present invention;

[0037] Figure 2 is a schematic structural diagram of a passivation structure in Example 2 of the present invention;

[0038] Figure 3 is a schematic structural diagram of a passivation structure in Example 3 of the present invention;

[0039] Figure 4 is a schematic structural diagram of a solar cell in Example 4 of the present invention;

[0040] Figure 5 is a schematic structural diagram of a solar cell in Example 5 of the present invention;

[0041] Figure 6 is a schematic structural diagram of a solar cell in Example 6 of the present invention;

[0042] Figure 7 It is a schematic diagram of the structure of a solar cell in a comparative example of the present invention. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0044] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0045] The present invention discloses a passivation structure, which is located on the backlight surface of a silicon substrate. The passivation structure comprises a tunneling oxide layer, a first silicide layer and a first polysilicon layer which are sequentially stacked on the backlight surface of the silicon substrate. The first silicide layer and the first polysilicon layer are both N-type doped. The thickness of the first silicide layer is 5nm to 50nm, the thickness of the first polysilicon layer is 10nm to 95nm, and the total thickness of the first silicide layer and the first polysilicon layer is 15nm to 100nm.

[0046] The present invention also discloses a solar cell including a silicon substrate, a P-type emitter formed on the light-receiving surface of the silicon substrate, and the above-mentioned passivation structure formed on the backlight surface of the silicon substrate. The solar cell also includes a first electrode and a second electrode, the first electrode is electrically in contact with the P-type emitter, and the second electrode is electrically in contact with the first polysilicon layer.

[0047] In addition, the present invention also discloses a method for preparing a solar cell, comprising the following steps:

[0048] Providing a silicon substrate;

[0049] A tunneling oxide layer, a first silicide layer and a first polysilicon layer are sequentially deposited on one surface of a silicon substrate by a PECVD process. Both the first silicide layer and the first polysilicon layer are N-type doped. The thickness of the first silicide layer is 5nm to 50nm, the thickness of the first polysilicon layer is 10nm to 95nm, and the total thickness of the first silicide layer and the first polysilicon layer is 15nm to 100nm.

[0050] The present invention is further described below in conjunction with specific embodiments.

[0051] Embodiment 1:

[0052] Ginseng Figure 1 The figure shows a schematic diagram of the structure of the passivation structure in this embodiment. The passivation structure is located on the backlight surface of the silicon substrate 10. The passivation structure 10 includes a tunneling oxide layer 21, a first silicide layer 221 and a first polysilicon layer 231 stacked in sequence on the backlight surface of the silicon substrate. The first silicide layer 221 and the first polysilicon layer 231 are both N-type doped.

[0053] The silicon substrate 10 in the present invention is an N-type silicon wafer, which includes a light-receiving surface (ie, the front or upper surface of the silicon substrate) and a backlight surface (ie, the back or lower surface of the silicon substrate) that are arranged opposite to each other.

[0054] Illustratively, the silicon substrate 10 in this embodiment is an N-type silicon wafer with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0055] The tunneling oxide layer 21 in the present invention is silicon dioxide (SiO 2 ) layer, silicon oxynitride (SiO x N y ) layer, and any one or more combinations of oxide layers, with a thickness of 0.5nm to 3nm, preferably 1.5nm to 2.5nm. For example, the tunneling oxide layer in this embodiment is made of silicon dioxide (SiO 2 ) layer as an example.

[0056] The first silicide layer 221 in the present invention may be a silicon carbide (SiC) layer, a silicon nitride (SiN x ) layer, silicon dioxide (SiO 2 ) layers, etc., which can be a single N-type doped silicide layer, or a combination of multiple silicide layers with the same or different N-type doping concentrations.

[0057] Exemplarily, the first silicide layer 221 in this embodiment is a silicon carbide layer with a thickness of 1 nm to 100 nm, preferably 5 nm to 50 nm.

[0058] The first silicide layer 221 in the present invention is N-type doped, and the doping element is a pentavalent element (such as phosphorus, arsenic, etc.). For example, the present invention is described by taking phosphorus doping as an example, and the doping concentration is 2E20cm -3 ~3E21cm -3 , preferably 5E20cm -3 ~2E21cm -3 .

[0059] The first polysilicon layer 231 in the present invention may be a single N-type doped polysilicon layer, or a combination of multiple polysilicon layers with the same or different N-type doping concentrations.

[0060] For example, the first polysilicon layer 231 in this embodiment is an N-type doped polysilicon layer with a thickness of 5nm to 150nm, preferably 10nm to 95nm. N-type doping is described by taking phosphorus doping as an example, and the doping concentration is 2E20cm -3 ~3E21cm -3 , preferably 5E20cm -3 ~2E21cm-3 .

[0061] Furthermore, in this embodiment, the total thickness of the first silicide layer 221 and the first polysilicon layer 231 is 6 nm to 120 nm, preferably 15 nm to 100 nm.

[0062] Embodiment 2:

[0063] Ginseng Figure 2 The structure schematic diagram of the passivation structure in this embodiment is shown, and the passivation structure is located on the backlight surface of the silicon substrate 10. The passivation structure 10 includes a tunneling oxide layer 21, a second polysilicon layer 232, a first silicide layer 221, and a first polysilicon layer 231 sequentially stacked on the backlight surface of the silicon substrate. The silicon substrate 10, the tunneling oxide layer 21, the first silicide layer 221, and the first polysilicon layer 231 in this embodiment are exactly the same as those in Embodiment 1, and will not be described again here.

[0064] Different from Example 1, in this embodiment, a second polysilicon layer 232 is added between the tunneling oxide layer 21 and the first silicide layer 221, and the total thickness of the second polysilicon layer 232, the first silicide layer 221 and the first polysilicon layer 231 is 6nm to 120nm, preferably 15nm to 100nm.

[0065] The second polysilicon layer may be an intrinsic polysilicon layer, or may be an N-type doped polysilicon layer, or may be a combination of multiple polysilicon layers with the same or different N-type doping concentrations.

[0066] For example, the second polysilicon layer 232 in this embodiment is an N-type doped polysilicon layer with a thickness of 0 nm to 100 nm, preferably 0 nm to 70 nm. N-type doping is described by taking phosphorus doping as an example, and the doping concentration is 2E20 cm -3 ~3E21cm -3 , preferably 5E20cm -3 ~2E21cm -3 .

[0067] Embodiment 3:

[0068] Ginseng Figure 3 The structure schematic diagram of the passivation structure in this embodiment is shown, and the passivation structure is located on the backlight surface of the silicon substrate 10. The passivation structure 10 includes a tunneling oxide layer 21, a second silicide layer 222, a first silicide layer 221, and a first polysilicon layer 231 sequentially stacked on the backlight surface of the silicon substrate. The silicon substrate 10, the tunneling oxide layer 21, the first silicide layer 221, and the first polysilicon layer 231 in this embodiment are exactly the same as those in Embodiment 1, and will not be described again here.

[0069] Different from Example 1, in this embodiment, a second silicide layer 222 is added between the tunneling oxide layer 21 and the first silicide layer 221, and the total thickness of the second silicide layer 222, the first silicide layer 221 and the first polysilicon layer 231 is 6nm to 120nm, preferably 15nm to 100nm.

[0070] The second silicide layer 222 may be a silicon carbide (SiC) layer, a silicon nitride (SiN x ) layer, silicon dioxide (SiO 2 ) layers, etc.; the second silicide layer 222 can be a layer of intrinsic silicide layer, can also be a layer of N-type doped silicide layer, or can be a combination of multiple layers of silicide layers with the same or different N-type doping concentrations.

[0071] Exemplarily, the second silicide layer 222 in this embodiment is an intrinsic silicon carbide layer with a thickness of 0-50 nm.

[0072] In other embodiments, the second silicide layer 222 may also be formed between the first silicide layer 221 and the first polysilicon layer 231; in addition, the second silicide layer 222 may be an N-type doped silicon carbide layer, where phosphorus doping is used as an example for N-type doping, and the doping concentration is 2E20cm -3 ~3E21cm -3 , preferably 5E20cm -3 ~2E21cm -3 .

[0073] In the passivation structures of the above-mentioned embodiments 1-3, based on the difference in corrosion of the N-type doped silicide layer and the polysilicon layer by the slurry during sintering, the N-type doped first silicide layer can serve as a barrier layer to prevent the slurry from sintering further inside. Even when the thickness of the back polysilicon layer is relatively thin, the tunneling oxide layer can be protected from being damaged, thereby improving the sintering process window.

[0074] Embodiment 4:

[0075] Ginseng Figure 4 The figure shows the structure of the solar cell in this embodiment. The cell is a TOPCon cell, which includes:

[0076] The silicon substrate 10 is an N-type silicon wafer, and has a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm. By way of example, the front side of the silicon substrate in this embodiment is a pyramid velvet structure, and the back side is a polished surface;

[0077] The P-type emitter 24 is located on the light-receiving surface of the silicon substrate 10. By way of example, the P-type emitter 24 in this embodiment is a boron-doped emitter with a doping concentration of 3E18 cm -3 ~3E19cm-3 , the square resistance is 40Ω / sq~300Ω / sq, preferably 100Ω / sq~180Ω / sq;

[0078] The passivation layer 25 is located on the P-type emitter 24. For example, the passivation layer 25 in this embodiment is an aluminum oxide passivation layer, which is used to passivate the P-type emitter 24 and has a thickness of 2 nm to 7 nm, preferably 3 nm to 6 nm;

[0079] The first anti-reflection layer 261 is located on the passivation layer 25. The first anti-reflection layer 261 can be made of silicon nitride (SiN x ) layer, silicon oxynitride (SiO x N y ) layer, silicon dioxide (SiO 2 ) layer, etc., the thickness of the first anti-reflection layer 261 is 60nm to 130nm;

[0080] The tunnel oxide layer 21 is located on the backlight surface of the silicon substrate 10. The tunnel oxide layer 21 is completely the same as that in the first embodiment and will not be described in detail here.

[0081] A second polysilicon layer 232 is located on the tunnel oxide layer 21. The second polysilicon layer 232 is completely the same as that in Embodiment 2 and will not be described in detail herein.

[0082] A first silicide layer 221 is located on the second polysilicon layer 232. The first silicide layer 221 is completely the same as that in Embodiment 2 and will not be described again.

[0083] A first polysilicon layer 231 is located on the first silicide layer 221. The first polysilicon layer 231 is completely the same as that in Embodiment 2 and will not be described in detail herein.

[0084] The second anti-reflection layer 262 is located on the first polysilicon layer 231. The second anti-reflection layer 262 may be silicon nitride (SiN x ) layer, silicon oxynitride (SiO x N y ) layer, silicon dioxide (SiO 2 ) layer, etc., the thickness of the second anti-reflection layer 262 is 60nm to 130nm;

[0085] The first electrode 271 is located on the light-receiving surface of the battery, and the first electrode 271 is in electrical contact with the P-type emitter 24, but cannot penetrate the P-type emitter 24. Exemplarily, the first electrode is an Ag / Al gate line electrode;

[0086] The second electrode 272 is located on the backlight side of the battery, and the second electrode 272 is in electrical contact with the first polysilicon layer 231, but cannot penetrate the first silicide layer 221 to avoid damaging the tunnel oxide layer 21. Exemplarily, the second electrode is an Ag gate line electrode.

[0087] The preparation process of the solar cell in this embodiment is as follows:

[0088] 1. Double-sided velveting

[0089] The alkali texturing process is used to form a pyramid texture structure on the light-receiving side and the backlight side of the silicon substrate (N-type silicon wafer), and the pyramid size is 0.5μm to 3μm.

[0090] 2. Preparation of P-type emitter

[0091] A boron-doped amorphous silicon layer with a thickness of 10nm to 100nm is deposited on the front of the silicon substrate by PECVD process, and then high-temperature oxidation annealing is performed to form a P+ emitter with a doping concentration of 3E18cm -3 ~3E19cm -3 .

[0092] 3. Back polishing

[0093] First, the silicon oxide on the back of the silicon substrate is removed by using hydrofluoric acid through a single-sided chain device, and then the back of the silicon substrate is alkaline polished to remove the edge junction and the back side plating, and finally cleaned.

[0094] 4. Preparation of passivation structure

[0095] First, a 1nm to 3nm thick tunneling silicon dioxide layer is deposited on the back of the silicon substrate using the PECVD process;

[0096] Then, a phosphorus-doped amorphous silicon layer or multiple amorphous silicon layers with different phosphorus doping concentrations are deposited by PECVD process, with a total thickness of 0 to 100 nm, preferably 0 to 70 nm;

[0097] Then, a phosphorus-doped amorphous silicide layer or multiple amorphous silicide layers with different phosphorus doping concentrations are deposited by PECVD process, where the silicide may be silicon carbide, silicon nitride, silicon oxide, etc., with a thickness of 1nm to 100nm, preferably 5nm to 50nm;

[0098] Then, a phosphorus-doped amorphous silicon layer or multiple amorphous silicon layers with different phosphorus doping concentrations are deposited by PECVD process, with a thickness of 5nm to 150nm, preferably 10nm to 100nm;

[0099] Finally, a silicon oxide mask layer is deposited by using the PECVD process, and the mask thickness is 2nm to 50nm.

[0100] In this embodiment, each film layer of the back passivation structure is deposited by a PECVD process, and the deposition of each film layer is completed in the same PECVD equipment (i.e., one PECVD process). The preparation process is simple and no new steps or processes are added.

[0101] 5. Annealing activation

[0102] Annealing treatment is performed in a high-temperature annealing furnace, the annealing temperature is 880°C to 980°C, preferably 900°C to 950°C, after annealing, the phosphorus-doped amorphous silicon layer is transformed into a phosphorus-doped polysilicon layer, the phosphorus-doped amorphous silicide layer is transformed into a phosphorus-doped polysilicon layer, the phosphorus is activated, and a tunnel passivation contact structure is formed on the back side.

[0103] 6. De-plating and cleaning

[0104] First, the front side of the silicon substrate is passed through a chain hydrofluoric acid bath to remove the edge-plated silicon oxide mask on one side, then the front side and edge-plated are removed by alkaline etching, and finally hydrofluoric acid is used to remove the front and back side silicon oxide masks, and RCA cleaning is performed.

[0105] 7. Preparation of front passivation layer

[0106] An aluminum oxide passivation layer is deposited on the front side of the silicon substrate by using the ALD process, with a thickness of 2nm to 7nm, preferably 3nm to 6nm.

[0107] 8. Preparation of anti-reflection layer

[0108] The PECVD process is used to deposit the first anti-reflection layer and the second anti-reflection layer on the front and other sides of the silicon substrate respectively. The anti-reflection layer can be one or more of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the anti-reflection layer is 60nm to 130nm.

[0109] 9. Screen printing metal electrodes

[0110] Metal electrodes are printed on the front and back sides respectively by screen printing, and then sintered and light-injected / electrically-injected to form ohmic contacts.

[0111] 10. Test sorting

[0112] Test, sort and store solar cells.

[0113] It should be understood that the passivation structure in the solar cell of this embodiment is the passivation structure in Embodiment 2. In other embodiments, the passivation structure may also be Embodiment 1 or Embodiment 3 or other passivation structures, which will not be described one by one here.

[0114] In addition, in this embodiment, the front surface of the silicon substrate has a pyramid-shaped textured structure, and the back surface is a polished surface. In other embodiments, the front surface of the silicon substrate can also have other textured structures, and the back surface can also have a pyramid-shaped textured structure or other textured structures, which will not be elaborated here one by one.

[0115] Embodiment 5:

[0116] Refer Figure 5 The following is a schematic structural diagram of the solar cell in this embodiment. This cell is a TOPCon cell and includes:

[0117] A silicon substrate 10, which is an N-type silicon wafer with a resistivity of 1.5 Ω·cm. The surface of the silicon substrate has a pyramid-shaped textured structure with a pyramid size of 1 μm;

[0118] A P-type emitter 24, located on the light-receiving surface of the silicon substrate 10. The P-type emitter 24 is a boron-doped emitter with a doping concentration of 6E18 cm -3 , and a thickness of 50 nm;

[0119] A passivation layer 25, located on the P-type emitter 24. The passivation layer 25 is an aluminum oxide passivation layer with a thickness of 4.5 nm;

[0120] A first antireflection layer 261, located on the passivation layer 25. The first antireflection layer 261 is a silicon nitride + silicon oxynitride + silicon dioxide stack with a thickness of 100 nm;

[0121] A tunneling oxide layer 21, located on the backlight surface of the silicon substrate 10. The tunneling oxide layer 21 is a silicon dioxide layer with a thickness of 1.5 nm;

[0122] A second polysilicon layer 232, located on the tunneling oxide layer 21. The second polysilicon layer 232 successively includes an intrinsic polysilicon layer 2321 with a thickness of 5 nm and a phosphorus-doped polysilicon layer 2322 with a thickness of 15 nm, with a doping concentration of 3.5E20 cm -3 , and the intrinsic polysilicon layer and the phosphorus-doped polysilicon layer are formed by annealing an intrinsic amorphous silicon layer and a phosphorus-doped amorphous silicon layer at 930 °C;

[0123] A first silicide layer 221, located on the second polysilicon layer 232. The first silicide layer 221 is a phosphorus-doped silicon carbide layer with a thickness of 15 nm and a doping concentration of 5.5E20 cm -3 , and the silicon carbide layer is an amorphous silicon carbide layer formed by annealing an intrinsic silicon carbide layer at 930 °C;

[0124] A first polysilicon layer 231, located on the first silicide layer 221. The first polysilicon layer 231 is a phosphorus-doped polysilicon layer with a thickness of 25 nm and a doping concentration of 1E20 cm -3 , and the phosphorus-doped polysilicon layer is formed by annealing a phosphorus-doped amorphous silicon layer at 930 °C;

[0125] The second antireflection layer 262 is located on the first polysilicon layer 231. The second antireflection layer 262 is a silicon nitride + silicon oxynitride + silicon dioxide stack with a thickness of 100 nm.

[0126] The first electrode 271 is located on the light-receiving surface of the cell, and the first electrode 271 is in electrical contact with the P-type emitter 24 but does not penetrate the P-type emitter 24.

[0127] The second electrode 272 is located on the backlight surface of the cell, and the second electrode 272 is in electrical contact with the first polysilicon layer 231 but does not penetrate the first silicide layer 221 to avoid damaging the tunneling oxide layer 21.

[0128] Example 6:

[0129] Refer Figure 6 The following is a schematic diagram of the structure of the solar cell in this embodiment. This cell is a TOPCon cell and includes:

[0130] The silicon substrate 10 is an N-type silicon wafer with a resistivity of 1.5 Ω·cm. The surface of the silicon substrate is a pyramid texture structure with a pyramid size of 1 μm.

[0131] The P-type emitter 24 is located on the light-receiving surface of the silicon substrate 10. The P-type emitter 24 is a boron-doped emitter with a doping concentration of 7E18 cm -3 , and a thickness of 50 nm;

[0132] The passivation layer 25 is located on the P-type emitter 24. The passivation layer 25 is an alumina passivation layer with a thickness of 4.5 nm.

[0133] The first antireflection layer 261 is located on the passivation layer 25. The first antireflection layer 261 is a silicon nitride + silicon oxynitride + silicon dioxide stack with a thickness of 100 nm.

[0134] The tunneling oxide layer 21 is located on the backlight surface of the silicon substrate 10. The tunneling oxide layer 21 is a silicon dioxide layer with a thickness of 2 nm.

[0135] The second silicide layer 222 is located on the tunneling oxide layer 21. The second silicide layer 222 is an intrinsic silicon carbide layer with a thickness of 5 nm.

[0136] The first silicide layer 221 is located on the second silicide layer 222. The first silicide layer 221 is a phosphorus-doped silicon carbide layer with a thickness of 15 nm and a doping concentration of 5E20 cm -3 , and the silicon carbide layer is an amorphous silicon carbide layer formed by annealing the intrinsic silicon carbide layer at 940 °C;

[0137] The first polysilicon layer 231 is located on the first silicide layer 221. The first polysilicon layer 231 is a phosphorus-doped polysilicon layer with a thickness of 30 nm and a doping concentration of 1E21 cm -3 , and the phosphorus-doped polysilicon layer is formed by annealing a phosphorus-doped amorphous silicon layer at 940 °C;

[0138] The second antireflection layer 262 is located on the first polysilicon layer 231. The second antireflection layer 262 is a silicon nitride + silicon oxynitride + silicon dioxide stack with a thickness of 100 nm;

[0139] The first electrode 271 is located on the light-receiving surface of the battery, and the first electrode 271 is in electrical contact with the P-type emitter 24 but does not penetrate the P-type emitter 24;

[0140] The second electrode 272 is located on the backlight surface of the battery, and the second electrode 272 is in electrical contact with the first polysilicon layer 231 but does not penetrate the first silicide layer 221 to avoid damaging the tunneling oxide layer 21.

[0141] Comparative example:

[0142] Refer Figure 7 The structural schematic diagram of the solar cell in this comparative example is shown. This cell is a TOPCon cell, which includes:

[0143] A silicon substrate 10;

[0144] The P-type emitter 24 is located on the light-receiving surface of the silicon substrate 10;

[0145] The passivation layer 25 is located on the P-type emitter 24;

[0146] The first antireflection layer 261 is located on the passivation layer 25;

[0147] The tunneling oxide layer 21 is located on the backlight surface of the silicon substrate 10;

[0148] The polysilicon layer 23' is located on the tunneling oxide layer 21;

[0149] The second antireflection layer 262 is located on the polysilicon layer 23';

[0150] The first electrode 271 is located on the light-receiving surface of the battery, and the first electrode 271 is in electrical contact with the P-type emitter 24;

[0151] The second electrode 272 is located on the backlight surface of the battery, and the second electrode 272 is in electrical contact with the polysilicon layer 23'.

[0152] The silicon substrate 10, P-type emitter 24, passivation layer 25, tunneling oxide layer 21, first antireflection layer 261, second antireflection layer 262, first electrode 271, and second electrode 272 in this comparative example are exactly the same as those in Example 6, and will not be elaborated here.

[0153] Different from Example 6, in this comparative example, the passivation structure on the back of the silicon substrate only includes a layer of phosphorus-doped polysilicon layer 23', with a thickness of 120 nm.

[0154] After testing, the structures and electrical performance parameters of the TOPCon cells in Examples 5 and 6 and the comparative example are as follows in the table:

[0155]

[0156] It can be seen that by adding a phosphorus-doped silicon carbide layer to the passivation structure on the back of the cell, the thickness of the polysilicon layer on the back of the silicon substrate can be thinned to 100 nm. At the same time, it can avoid damaging the tunneling oxide layer during the paste sintering process, taking into account both the passivation performance and reducing parasitic absorption. The IV performance of the TOPCon cells has been improved to a certain extent, especially the conversion efficiency (EFF) has been significantly improved, with an increase range of 0.12% - 0.15%.

[0157] The solar cell in the above example is described by taking the TOPCon cell as an example. The passivation structure of the present invention is also applicable to other types of solar cells. Any technical solution using this passivation structure belongs to the scope protected by the present invention.

[0158] From the above technical solutions, it can be seen that the present invention has the following beneficial effects:

[0159] By adding an N-type doped silicide layer on the back of the silicon substrate, the present invention can thin the thickness of the N-type doped polysilicon layer without changing the paste, while taking into account the passivation performance and reducing parasitic absorption, and significantly improving the photoelectric conversion efficiency of the cell while increasing the sintering process window;

[0160] The preparation process is simple. The stacked structure in the passivation structure can be prepared in one step by PECVD, without adding new processes, effectively controlling the process cost.

[0161] It is apparent to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, in all respects, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Accordingly, all changes that fall within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be construed as limiting the claims concerned.

[0162] In addition, it should be understood that although this specification is described in terms of embodiments, not every embodiment contains only one independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should take the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A passivation structure is located on the backlight side of a silicon substrate. Characterized in that, The passivation structure includes a tunneling oxide layer, a first silicide layer, and a first polysilicon layer that are sequentially stacked on the backlight side of the silicon substrate. The first silicide layer and the first polysilicon layer are both N-type doped. The thickness of the first silicide layer is 5 nm to 50 nm, the thickness of the first polysilicon layer is 10 nm to 95 nm, and the total thickness of the first silicide layer and the first polysilicon layer is 15 nm to 100 nm.

2. The passivation structure according to claim 1, Characterized in that, The first silicide layer is any one or a combination of a silicon carbide layer, a silicon nitride layer, and a silicon oxide layer; and / or, The first silicide layer is a single N-type doped silicide layer, or a combination of multiple silicide layers with the same or different N-type doping concentrations; and / or, The first polysilicon layer is a single N-type doped polysilicon layer, or a combination of multiple polysilicon layers with the same or different N-type doping concentrations.

3. The passivation structure according to claim 1, Characterized in that, The silicide layer is phosphorus-doped, and the first polysilicon layer is phosphorus-doped; and / or, The doping concentration of the first silicide layer is 2E20 cm -3 ~3E21 cm -3 or 5E20 cm -3 ~2E21 cm -3 ; and / or, The doping concentration of the first polysilicon layer is 2E20 cm -3 ~3E21 cm -3 or 5E20 cm -3 ~2E21 cm -3 .

4. The passivation structure according to claim 1, Characterized in that, The passivation structure further includes a second silicide layer stacked between the tunneling oxide layer and the first silicide layer and / or stacked between the first silicide layer and the first polysilicon layer. The thickness of the second silicide layer is 0 to 50 nm, and the total thickness of the first silicide layer, the second silicide layer, and the first polysilicon layer is 15 nm to 100 nm.

5. The passivation structure according to claim 4, Characterized in that, The second silicide layer is any one or a combination of a silicon carbide layer, a silicon nitride layer, and a silicon oxide layer; and / or, The second silicide layer is a single intrinsic silicide layer, or a single N-type doped silicide layer, or a combination of multiple silicide layers with the same or different N-type doping concentrations.

6. The passivation structure according to claim 1, Characterized in that, The passivation structure further includes a second polysilicon layer stacked between the tunneling oxide layer and the silicide layer. The thickness of the second polysilicon layer is 0 to 70 nm, and the total thickness of the silicide layer, the first polysilicon layer, and the second polysilicon layer is 15 nm to 100 nm.

7. The passivation structure according to claim 6, Characterized in that, The second polysilicon layer is a single intrinsic polysilicon layer, or a single N-type doped polysilicon layer, or a combination of multiple polysilicon layers with the same or different N-type doping concentrations.

8. The passivation structure according to claim 1, Characterized in that, The tunneling oxide layer is any one or a combination of a silicon dioxide layer and a silicon oxynitride layer; and / or, The thickness of the tunneling oxide layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm; and / or, The silicon substrate is an N-type silicon substrate.

9. A solar cell, Characterized in that, The solar cell includes a silicon substrate, a P-type emitter is formed on the light-receiving surface of the silicon substrate, a passivation structure as described in any one of claims 1 to 8 is formed on the backlight surface of the silicon substrate, the solar cell further includes a first electrode and a second electrode, the first electrode is in electrical contact with the P-type emitter, and the second electrode is in electrical contact with the first polysilicon layer.

10. The solar cell according to claim 9, wherein, a passivation layer and / or a first antireflection layer are / is further formed on the P-type emitter; and / or, a second antireflection layer is further formed on the passivation structure.

11. A method for manufacturing a solar cell, wherein, the manufacturing method includes the following steps: providing a silicon substrate; sequentially depositing a tunneling oxide layer, a first silicide layer, and a first polysilicon layer on one side surface of the silicon substrate by PECVD process, both the first silicide layer and the first polysilicon layer are N-type doped, the thickness of the first silicide layer is 5 nm to 50 nm, the thickness of the first polysilicon layer is 10 nm to 95 nm, and the total thickness of the first silicide layer and the first polysilicon layer is 15 nm to 100 nm.

12. The manufacturing method according to claim 11, wherein, the tunneling oxide layer, the first silicide layer, and the first polysilicon layer are sequentially deposited in the same PECVD equipment.

13. The manufacturing method according to claim 11, wherein, before the PECVD process, it further includes: forming a P-type emitter on the other side surface of the silicon substrate; and, after the PECVD process, it further includes: fabricating a first electrode on the P-type emitter, and fabricating a second electrode on the first polysilicon layer.

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