Solar cell, preparation method of solar cell and photovoltaic module

Abstract

The invention discloses a solar cell, a preparation method of the solar cell and a photovoltaic module. The solar cell comprises a silicon substrate, a first semiconductor layer, a tunneling layer, a second semiconductor layer, an interface layer, a third semiconductor layer, a first electrode and a second electrode, the second semiconductor layer is arranged on the surface of the tunneling layer; the interface layer is arranged on the surface of the second semiconductor layer; and the third semiconductor layer is arranged on a part of the surface of the interface layer. The interface layer is arranged between the second semiconductor layer and the third semiconductor layer, when the third semiconductor layer in the non-electrode area is removed, the interface layer can serve as a barrier layer, the second semiconductor layer is prevented from being damaged, and the thickness of the second semiconductor layer in the non-electrode area can be conveniently controlled.

Description

Technical Field

[0001] The present invention belongs to the technical field of photovoltaics, and particularly relates to a solar cell, a preparation method of the solar cell, and a photovoltaic module. Background Art

[0002] The tunneling oxide passivated contact cell, abbreviated as TOPCon cell, is a high-efficiency N-type silicon solar cell technology based on the principle of selective carriers. The core feature of the TOPCon cell is to prepare a tunneling oxide layer with a thickness of 1 nm to 2 nm and a doped polysilicon layer with a thickness of 80 nm to 120 nm on the back surface of the cell, forming a passivated contact structure, which effectively reduces the surface recombination and metal contact recombination, thereby increasing the open-circuit voltage and short-circuit current of the cell, and further improving the conversion efficiency of the cell. In the prior art, the thickness of the doped polysilicon layer is relatively thick, aiming to prevent burning through the doped polysilicon layer when preparing the back electrode. Based on this, a Chinese patent application with the application number 201611117510.2 discloses a passivated contact structure of a selective polysilicon thin film. A silicon dioxide layer is provided on the surface of the crystalline silicon, and a doped polysilicon thin film is prepared on the surface of the silicon dioxide layer. The doped polysilicon thin film has a first thickness 3a in the non-metal contact area and a second thickness 3b in the metal contact area, and the first thickness 3a is less than the second thickness 3b. A metal electrode is formed on the surface of the second thickness area of the polysilicon thin film. This technical solution requires removing the doped polysilicon layer in the non-electrode area. When removing the polysilicon layer in the non-electrode area, if the removal is excessive, the polysilicon layer will be damaged, and the thickness of the doped polysilicon layer in the non-electrode area will be too thin; if the removal is insufficient, the thickness of the doped polysilicon layer in the non-electrode area will be too thick. Therefore, it is difficult to control the thickness of the polysilicon layer in the thinning area with this technical solution. Summary of the Invention

[0003] One of the purposes of the present invention is to provide a solar cell, which solves the problems raised in the above background art.

[0004] To achieve the above purpose, the technical solution adopted by the present invention is: a solar cell, comprising: a silicon substrate, a first semiconductor layer, a tunneling layer, a second semiconductor layer, an interface layer, a third semiconductor layer, a first electrode, and a second electrode;

[0005] The first semiconductor layer is disposed on one side of the silicon substrate;

[0006] The tunneling layer is disposed on the other side of the silicon substrate;

[0007] The second semiconductor layer is disposed on the surface of the tunneling layer, and the polarities of the first semiconductor layer and the second semiconductor layer are opposite;

[0008] The interface layer is disposed on the surface of the second semiconductor layer, and the thickness of the interface layer is from 0.1 nm to 2 nm;

[0009] The third semiconductor layer is disposed on a partial surface of the interface layer, and the third semiconductor layer has the same polarity as the second semiconductor layer;

[0010] The first electrode is in contact with the first semiconductor layer;

[0011] The second electrode is in contact with the third semiconductor layer.

[0012] Based on the above solution and as a preferred solution of the above solution, the material of the interface layer is silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide or silicon oxide.

[0013] Based on the above solution and as a preferred solution of the above solution, the interface layer contains doping elements, and the doping elements in the interface layer are the same as the doping elements in the second semiconductor layer and / or the third semiconductor layer.

[0014] Based on the above solution and as a preferred solution of the above solution, the doping concentration of the third semiconductor layer is greater than the doping concentration of the second semiconductor layer.

[0015] Based on the above solution and as a preferred solution of the above solution, the second semiconductor layer and the third semiconductor layer are one or more of a polysilicon layer, an amorphous silicon layer, a microcrystalline silicon layer and a nanocrystalline silicon layer.

[0016] Based on the above solution and as a preferred solution of the above solution, the type of the silicon substrate is N-type, the polarity of the first semiconductor layer is P-type, and the polarities of the second semiconductor layer and the third semiconductor layer are N-type.

[0017] Based on the above solution and as a preferred solution of the above solution, the width of the third semiconductor layer is greater than the width of the second electrode.

[0018] Based on the above solution and as a preferred solution of the above solution, a first passivation layer is disposed on the surface of the first semiconductor layer, and the first electrode passes through the first passivation layer to be in contact with the first semiconductor layer; a second passivation layer is disposed on the part of the second semiconductor layer not covered by the third semiconductor layer and on the surface of the third semiconductor layer, and the second electrode passes through the second passivation layer to be in contact with the third semiconductor layer.

[0019] The second object of the present invention is to provide a method for manufacturing a solar cell, comprising the following steps:

[0020] S1: Sequentially perform texturing and boron diffusion on the front surface to form a first semiconductor layer;

[0021] S2: Sequentially prepare a tunneling layer, a second intrinsic semiconductor layer, an interface layer, and a third intrinsic semiconductor layer on the back surface;

[0022] S3: Perform doping treatment on the back surface, and simultaneously form the second intrinsic semiconductor layer and the third intrinsic semiconductor layer into a doped second semiconductor layer and a doped third semiconductor layer respectively;

[0023] S4: Remove the third semiconductor layer in the non - electrode region;

[0024] S5: Prepare a first passivation layer on the front surface and a second passivation layer on the back surface respectively;

[0025] S6: Prepare a first electrode and a second electrode.

[0026] A photovoltaic module, said photovoltaic module includes the solar cell as described above.

[0027] The beneficial effects of the present invention are as follows:

[0028] 1. There is an interface layer between the second semiconductor layer and the third semiconductor layer in the present invention. When removing the third semiconductor layer in the non - electrode region, the interface layer can act as a barrier layer to prevent damage to the second semiconductor layer and facilitate controlling the thickness of the second semiconductor layer in the non - electrode region.

[0029] 2. The interface layer is made of silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide or silicon oxide. The remaining interface layer can both form a local TOPcon structure together with the third semiconductor layer, which can effectively improve the tunneling passivation effect and the conversion efficiency of the cell, and also facilitate the penetration of doping elements into the second semiconductor layer.

[0030] 3. When preparing the back - surface structure, first prepare the second intrinsic semiconductor layer, then prepare the interface layer, then prepare the third intrinsic semiconductor layer, and then simultaneously dope the second intrinsic semiconductor layer and the third intrinsic semiconductor layer by a single doping method. At the same time, the interface layer is also doped, saving one doping process step. Description of the Drawings

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0032] Figure 1 It is a schematic structural diagram after step S1 of the present invention.

[0033] Figure 2 It is a schematic structural diagram after step S2 of the present invention.

[0034] Figure 3 This is a schematic structural diagram after step S3 of the present invention.

[0035] Figure 4 This is a schematic structural diagram after step S4 of the present invention.

[0036] Figure 5 This is a schematic structural diagram after step S5 of the present invention.

[0037] Figure 6 This is a schematic structural diagram after step S6 of the present invention.

[0038] The reference numerals are as follows:

[0039] 1, silicon substrate; 2, first semiconductor layer; 3, tunneling layer; 4, second semiconductor layer; 5, interface layer; 6, third semiconductor layer; 7, first passivation layer; 8, second passivation layer; 9, first electrode; 10, second electrode; 11, second intrinsic semiconductor layer; 12, third intrinsic semiconductor layer. Detailed implementation manners

[0040] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0041] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0042] As shown in the Figure 6 accompanying drawings, a solar cell includes: a silicon substrate 1, a first semiconductor layer 2, a tunneling layer 3, a second semiconductor layer 4, an interface layer 5, a third semiconductor layer 6, a first electrode 9 and a second electrode 10;

[0043] The first semiconductor layer 2 is disposed on one side of the silicon substrate 1;

[0044] The tunneling layer 3 is disposed on the other side of the silicon substrate 1;

[0045] The second semiconductor layer 4 is disposed on the surface of the tunneling layer 3, and the first semiconductor layer 2 and the second semiconductor layer 4 have opposite polarities;

[0046] The interface layer 5 is disposed on the surface of the second semiconductor layer 4, and the thickness of the interface layer 5 is 0.1 nm to 2 nm;

[0047] The third semiconductor layer 6 is disposed on a partial surface of the interface layer 5, that is, the third semiconductor layer is only provided in the region corresponding to the second electrode, and there is no third semiconductor layer in the non-second electrode region. The third semiconductor layer 6 has the same polarity as the second semiconductor layer 4;

[0048] The first electrode 9 is in contact with the first semiconductor layer 2;

[0049] The second electrode 10 is in contact with the third semiconductor layer 6.

[0050] In this technical solution, an interface layer is provided between the second semiconductor layer and the third semiconductor layer. When removing the third semiconductor layer in the non-electrode region, the interface layer can act as a barrier layer to prevent damage to the second semiconductor layer and facilitate controlling the thickness of the second semiconductor layer in the non-electrode region.

[0051] The material of the interface layer 5 is silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide or silicon oxide. The above materials basically do not react with hydrofluoric acid-based and nitric acid-based etching solutions, while the hydrofluoric acid-based and nitric acid-based etching solutions can etch away the semiconductor layer well; and the above materials are easily tunneled through by carriers at 0.1 nm to 2 nm, and can achieve a tunneling passivation effect.

[0052] The interface layer 5 contains doping elements, and the doping elements in the interface layer 5 are the same as the doping elements in the second semiconductor layer 4 and / or the third semiconductor layer 6. When doping the second semiconductor layer and the third semiconductor layer, the doping elements can enter the interface layer at the same time, improving the conductive effect of the interface layer.

[0053] The doping concentration of the third semiconductor layer 6 is greater than that of the second semiconductor layer 4. The third semiconductor layer is in direct contact with the electrode, and a larger doping concentration can reduce the contact resistance between the third semiconductor layer and the electrode, thereby improving the conductivity; while the second semiconductor layer is close to the silicon substrate, and a lower doping concentration can increase the passivation ability.

[0054] The second semiconductor layer 4 and the third semiconductor layer 6 are one or more of a polysilicon layer, an amorphous silicon layer, a microcrystalline silicon layer and a nanocrystalline silicon layer.

[0055] The type of the silicon substrate 1 is N-type, and the silicon substrate can be single-crystalline silicon or polysilicon. The polarity of the first semiconductor layer 2 is P-type, and the polarities of the second semiconductor layer 4 and the third semiconductor layer 6 are N-type. Specifically, boron diffusion can be performed on the first semiconductor layer to form an emitter layer, and phosphorus element doping can be performed on the second semiconductor layer.

[0056] The width of the third semiconductor layer 6 is greater than the width of the second electrode 10. When screen-printing the second electrode, it is convenient for the second electrode to contact the third semiconductor layer and prevents the second electrode from contacting the interface layer.

[0057] A first passivation layer 7 is provided on the surface of the first semiconductor layer 2, and the first electrode 9 passes through the first passivation layer 7 to contact the first semiconductor layer 2; a second passivation layer 8 is provided on the portion of the second semiconductor layer 4 not covered by the third semiconductor layer 6 and on the surface of the third semiconductor layer 6, and the second electrode 10 passes through the second passivation layer 8 to contact the third semiconductor layer 6.

[0058] A method for manufacturing a solar cell, as shown in the attached Figure 1 to the attached Figure 6 figures, includes the following steps:

[0059] S1: Texturing and boron diffusion are sequentially performed on the front surface to form the first semiconductor layer 2.

[0060] S2: A tunneling layer 3, a second intrinsic semiconductor layer 11, an interface layer 5, and a third intrinsic semiconductor layer 12 are sequentially prepared on the back surface;

[0061] S3: Doping treatment is performed on the back surface, and at the same time, the second intrinsic semiconductor layer 11 and the third intrinsic semiconductor layer 12 are respectively formed into a doped second semiconductor layer 4 and a doped third semiconductor layer 6. By doping the second intrinsic semiconductor layer and the third intrinsic semiconductor layer simultaneously in one doping step, at the same time, the interface layer is also doped, saving one doping process step.

[0062] S4: Remove the third semiconductor layer 6 in the non-electrode region. The removal method can be etching. Use an HF / HNO 3 solution to etch the third semiconductor layer in the non-electrode region until reaching the interface layer. The interface layer has an etching blocking effect on the HF / HNO 3 solution, which can avoid over-etching and damaging the second semiconductor layer. To prevent the third semiconductor layer in the electrode region from being etched, a mask layer can be provided on the surface of the third semiconductor layer in the electrode region, and after etching is completed, the mask layer is removed.

[0063] S5: Prepare the first passivation layer 7 on the front surface and the second passivation layer 8 on the back surface respectively.

[0064] S6: Prepare the first electrode 9 and the second electrode 10.

[0065] A photovoltaic module, which includes the solar cell as described above.

[0066] The foregoing description of the disclosed embodiments enables those skilled in the art to practice or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A solar cell, characterized in that: include: A silicon substrate (1), a first semiconductor layer (2), a tunneling layer (3), a second semiconductor layer (4), an interface layer (5), a third semiconductor layer (6), a first electrode (9) and a second electrode (10); The first semiconductor layer (2) is arranged on one side of the silicon substrate (1); The tunneling layer (3) is arranged on the other side of the silicon substrate (1); The second semiconductor layer (4) is arranged on the surface of the tunneling layer (3), and the polarities of the first semiconductor layer (2) and the second semiconductor layer (4) are opposite; The interface layer (5) is arranged on the surface of the second semiconductor layer (4), and the thickness of the interface layer (5) is 0.1 nm to 2 nm; The third semiconductor layer (6) is provided on a portion of the surface of the interface layer (5), and the third semiconductor layer (6) has the same polarity as the second semiconductor layer (4); The first electrode (9) is in contact with the first semiconductor layer (2); The second electrode (10) is in contact with the third semiconductor layer (6).

2. A solar cell according to claim 1, characterized in that: The material of the interface layer (5) is silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide or silicon oxide.

3. A solar cell according to claim 1, characterized in that: The interface layer (5) contains a doping element, and the doping element in the interface layer (5) is the same as the doping element in the second semiconductor layer (4) and / or the third semiconductor layer (6).

4. A solar cell according to claim 3, characterized in that: The doping concentration of the third semiconductor layer (6) is greater than the doping concentration of the second semiconductor layer (4).

5. A solar cell according to claim 1, characterized in that: The second semiconductor layer (4) and the third semiconductor layer (6) are one or more of a polycrystalline silicon layer, an amorphous silicon layer, a microcrystalline silicon layer and a nanocrystalline silicon layer.

6. A solar cell according to claim 1, characterized in that: The type of the silicon substrate (1) is N-type, the polarity of the first semiconductor layer (2) is P-type, and the polarities of the second semiconductor layer (4) and the third semiconductor layer (6) are N-type.

7. A solar cell according to claim 6, characterized in that: The width of the third semiconductor layer (6) is greater than the width of the second electrode (10).

8. A solar cell according to claim 1, characterized in that: A first passivation layer (7) is provided on the surface of the first semiconductor layer (2), and the first electrode (9) passes through the first passivation layer (7) and is in contact with the first semiconductor layer (2); a second passivation layer (8) is provided on the portion of the second semiconductor layer (4) not covered by the third semiconductor layer (6) and on the surface of the third semiconductor layer (6), and the second electrode (10) passes through the second passivation layer (8) and is in contact with the third semiconductor layer (6).

9. A method for preparing a solar cell, characterized in that: The following steps are involved: S1: forming a first semiconductor layer (2) by sequentially performing texturing and boron diffusion on the front surface; S2: sequentially preparing a tunneling layer (3), a second intrinsic semiconductor layer (11), an interface layer (5) and a third intrinsic semiconductor layer (12) on the back side; S3: performing a doping process on the back surface, and simultaneously forming the second intrinsic semiconductor layer (11) and the third intrinsic semiconductor layer (12) into a doped second semiconductor layer (4) and a doped third semiconductor layer (6), respectively; S4: removing the third semiconductor layer (6) in the non-electrode region; S5: preparing a first passivation layer (7) on the front side and a second passivation layer (8) on the back side respectively; S6: preparing a first electrode (9) and a second electrode (10).

10. A photovoltaic module, characterized in that: The photovoltaic module comprises the solar cell according to any one of claims 1 to 8.

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