Integrated circuit integration of t-coil into communication link at interface

Abstract

An integrated circuit (IC) includes a first transceiver interface circuit extending longitudinally in a first direction, the first direction being substantially perpendicular to a second direction, the second direction being parallel to an edge of the IC, where the first transceiver interface circuit includes a first T-coil; and a second transceiver interface circuit extending longitudinally in the first direction, where the second transceiver interface circuit is interleaved with the first transceiver interface circuit along the second direction, where the second transceiver interface circuit includes a second T-coil, and where the second T-coil is offset from the first T-coil along the first direction.

Description

[0001] Cross - Reference to Related Applications

[0002] This patent application claims priority to pending U.S. non - provisional application Ser. No. 17 / 969,552, filed Oct. 19, 2022, which is assigned to the assignee of this application and is hereby incorporated by reference in its entirety as if fully set forth herein and for all applicable purposes. Technical Field

[0003] Aspects of the present disclosure generally relate to communication links, such as double - data - rate (DDR) and serializer - deserializer (SERDES) links, and more particularly to the integration of T - coils at an interface into an integrated circuit (IC) for a communication link. Background Art

[0004] Communication links, such as double - data - rate (DDR) and serializer - deserializer (SERDES) links, are used to transfer data signals between an integrated circuit (IC) and other components. Generally, a communication link includes a set of parallel transmission lines, some of which can be differential transmission lines, pseudo - differential transmission lines, and single - ended transmission lines. It is of interest to compensate the transmission lines of a communication link to increase the data rate and signal integrity. Summary of the Invention

[0005] A simplified summary of one or more implementations is presented below to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is neither intended to identify key or essential elements of all implementations nor to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description presented later.

[0006] An aspect of the present disclosure relates to an integrated circuit (IC) that includes: a first transceiver interface circuit longitudinally extending in a first direction that is substantially perpendicular to a second direction, the second direction being parallel to an edge of the IC, wherein the first transceiver interface circuit includes a first T - coil; and a second transceiver interface circuit longitudinally extending in the first direction, wherein the second transceiver interface circuit is interleaved with the first transceiver interface circuit along the second direction, wherein the second transceiver interface circuit includes a second T - coil, and wherein the second T - coil is offset from the first T - coil along the first direction.

[0007] Another aspect of the present disclosure relates to a wireless communication device, the wireless communication device comprising: at least one antenna; a transceiver coupled to the at least one antenna; a communication link comprising a set of transmission lines coupled to the transceiver; and an integrated circuit (IC) comprising a set of transceiver interface circuits respectively coupled to the set of transmission lines, wherein: a first transceiver interface circuit in the set of transceiver interface circuits extends longitudinally in a first direction, the first direction being substantially perpendicular to a second direction, the second direction being parallel to an edge of the IC, wherein the first transceiver interface circuit comprises a first T coil; and a second transceiver interface circuit in the set of transceiver interface circuits extends longitudinally in the first direction, wherein the second transceiver interface circuit is staggered from the first transceiver interface circuit along the second direction, wherein the second transceiver interface circuit comprises a second T coil, and wherein the second T coil is offset from the first T coil along the first direction.

[0008] To achieve the foregoing and related purposes, one or more implementations include the features that are fully described and particularly pointed out in the claims below. The following description and the drawings set forth in detail certain illustrative aspects of one or more implementations. However, these aspects merely indicate some of the various ways in which the principles of the various implementations may be employed, and the description of the implementations is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A block diagram of an example communication system in accordance with one aspect of the present disclosure is shown;

[0010] Figure 2A A schematic diagram of an example transceiver interface circuit in accordance with another aspect of the present disclosure is shown;

[0011] Figure 2B A layout or top view of an example integrated circuit (IC) in accordance with another aspect of the present disclosure is shown;

[0012] Figure 3A A schematic diagram of another example transceiver interface circuit in accordance with another aspect of the present disclosure is shown;

[0013] Figure 3B A layout or top view of another example integrated circuit (IC) in accordance with another aspect of the present disclosure is shown;

[0014] Figure 4 A layout or top view of another example integrated circuit (IC) in accordance with another aspect of the present disclosure is shown;

[0015] Figure 5 A layout or top view of another example integrated circuit (IC) in accordance with another aspect of the present disclosure is shown;

[0016] Figure 6Shows a schematic diagram of another example transceiver interface circuit according to another aspect of the present disclosure; and

[0017] Figure 7 Shows a block diagram of an example wireless communication device according to another aspect of the present disclosure. Detailed Description

[0018] The detailed description presented below in conjunction with the accompanying drawings is intended to describe various configurations and is not intended to represent the only configurations in which the concepts described herein can be practiced. The detailed description includes specific details for providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0019] Figure 1 Shows a block diagram of an example communication system 100 according to one aspect of the present disclosure. The communication system 100 includes a first integrated circuit (IC) 110, a second IC 120, and a communication link 130 that couples the signals of the first IC 110 to the second IC 120. In this example, the communication link 130 can be a double data rate (DDR) communication link having pseudo-differential transmission lines 132-1 to 132-N (where N can be a positive integer) formed on a printed circuit board (PCB) 134. It should be understood that the communication link 130 can be implemented as other types of communication links, such as a fully differential serial deserializer (SERDES) communication link.

[0020] The first IC 110 further includes a set of N transceivers 112-1 to 112-N respectively coupled to a set of N communication link interface circuits 114-1 to 114-N. The set of N interface circuits 114-1 to 114-N are respectively coupled to the set of transmission lines 132-1 to 132-N of the communication link 130 via a set of IC pads 116-1 to 116-N. Similarly, the second IC 120 further includes a set of N transceivers 122-1 to 122-N respectively coupled to a set of N communication link interface circuits 124-1 to 124-N. The set of N interface circuits 124-1 to 124-N are respectively coupled to the set of transmission lines 132-1 to 132-N of the communication link 130 via a set of IC pads 126-1 to 126-N. Each transceiver and the corresponding interface circuit may be collectively referred to as a transceiver interface circuit herein.

[0021] Figure 2AA schematic diagram of an example transceiver interface circuit 200 in accordance with another aspect of the present disclosure is shown. The transceiver interface circuit 200 may be an example implementation of one of the transceiver interface circuits 112-1 / 114-1 through 112-N / 114-N or 122-1 / 124-1 through 122-N / 124-N. In particular, the transceiver interface circuit 200 includes a decoupling capacitor 202, a transmitter 208, an electrostatic discharge (ESD) circuit 206, a clamper 204, and a receiver 212.

[0022] The transmitter 208 further includes a first transistor M1 (e.g., a field effect transistor (FET), or more specifically, an n-channel metal oxide semiconductor (NMOS) FET) and a second transistor M2 (e.g., an FET or NMOS FET) that are coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss (e.g., ground). That is, the first FET M1 includes a drain coupled to the upper voltage rail Vdd and is configured to receive a transmit pull-up signal Txu <m:0>the gate, and a source coupled to the drain of the second FET M2. The second FET M2 further includes being configured to receive a transmit pull-down signal Txd <m:0>The gate, and a source coupled to the lower voltage rail Vss. The node between transistors M1 and M2 can be the output of transmitter 208. Although a single slice of transmitter 208 is shown, it should be understood that transmitter 208 can be 2 M parallel slices of the M1 / M2 transistor configuration. Transmitter 208 can also be referred to as a digital-to-analog converter (DAC).

[0023] The transceiver interface circuit 200 can also include a transmitter-side resistor R coupled between the output of transmitter 208 and the IC pad TX , and the IC pad is in turn coupled to a transmission line (e.g., one of transmission lines 132-1 to 132-N of communication link 130). Resistor R TX can protect transmitter 208 from static charges from the IC pad. Decoupling capacitor 202 is coupled between the upper voltage rail Vdd and the lower voltage rail Vss.

[0024] The ESD circuit 206 further includes a first reverse-biased diode D1 coupled in series with a second reverse-biased diode D2 between the upper voltage rail Vdd and the lower voltage rail Vss. That is, the cathode of diode D1 is coupled to the upper voltage rail Vdd; the anodes of diode D1 and the cathode of diode D2 are coupled together at the IC pad; and the anode of diode D1 is coupled to the lower voltage rail Vss. Diodes D1 and D2 are sometimes referred to as human body model (HBM) diodes. A clamper 204 is coupled between the upper voltage rail Vdd and the lower voltage rail Vss.

[0025] The receiver 212 includes a first input coupled to the IC pad via a receiver-side resistor R RX . Resistor R RX can protect receiver 208 from static charges from the IC pad. For pseudo-differential signal detection, the receiver 212 includes a second input configured to receive a reference voltage vref. The receiver 212 includes an output Rx_out configured to generate a detected received signal; the output Rx_out can be coupled to the core of the IC. Similarly, the core of the IC can also be coupled to the gates of transistors M1 and M2 of transmitter 208 to provide transmission pull-up signals Txu <m:0>and transmit the pull-down signal Txd <m:0>the latter in

[0026] Figure 2B FIG.

[0026] shows a layout or top view of an exemplary integrated circuit (IC) 240 in accordance with another aspect of the present disclosure. In this example, the IC 240 includes five (5) transceiver interface circuits 250-1 to 250-5 that can be coupled to a communication link (e.g., 130), such as five (5) transmission lines (e.g., 132-1 to 132-5). Although five (5) transceiver interface circuits 250-1 to 250-5 are shown for illustrative purposes, it should be understood that the IC 240 can include a different number of transceiver interface circuits.

[0027] From a layout perspective, the transceiver interface circuits 250-1 to 250-5 are staggered (e.g., substantially adjacent or next to each other) along the IC edge (or boundary) direction (e.g., bit-to-bit direction or data channel direction). Various components of each of the transceiver interface circuits 250-1 to 250-5 extend longitudinally from the IC edge in a direction perpendicular (orthogonal) to the IC edge direction. For example, the transceiver interface circuit 250-1 includes a decoupling capacitor 252-1, a clamper 254-1, an ESD circuit 256-1, a transmitter 258-1, a receiver 260-1, and a core input 262-1, all of which together extend from the IC edge in a direction perpendicular to the IC edge direction. Similarly, the transceiver interface circuit 250-2 includes a decoupling capacitor 252-2, a clamper 254-2, an ESD circuit 256-2, a transmitter 258-2, a receiver 260-2, and a core input 262-2, all of which together extend longitudinally from the IC edge in a direction perpendicular to the IC edge direction.

[0028] The above arrangement continues along the IC edge direction. The transceiver interface circuit 250-3 is staggered (e.g., substantially adjacent or neighboring each other) along the IC edge direction with the transceiver interface circuit 250-2, and includes a decoupling capacitor 252-3, a clamper 254-3, an ESD circuit 256-3, a transmitter 258-3, a receiver 260-3, and a core input 262-3, all of which commonly extend longitudinally from the IC edge in a direction perpendicular to the IC edge direction. The transceiver interface circuit 250-4 is staggered (e.g., substantially adjacent or neighboring each other) along the IC edge direction with the transceiver interface circuit 250-3, and includes a decoupling capacitor 252-4, a clamper 254-4, an ESD circuit 256-4, a transmitter 258-4, a receiver 260-4, and a core input 262-4, all of which commonly extend longitudinally from the IC edge in a direction perpendicular to the IC edge direction. The transceiver interface circuit 250-5 is staggered (e.g., substantially adjacent or neighboring each other) along the IC edge direction with the transceiver interface circuit 250-4, and includes a decoupling capacitor 252-5, a clamper 254-5, an ESD circuit 256-5, a transmitter 258-5, a receiver 260-5, and a core input 262-5, all of which commonly extend longitudinally from the IC edge in a direction perpendicular to the IC edge direction.

[0029] In this layout arrangement, the decoupling capacitors 252-1 to 252-5 are substantially aligned along the IC edge direction; the clampers 254-1 to 252-5 are substantially aligned along the IC edge direction; the ESD circuits 256-1 to 256-5 are substantially aligned along the IC edge direction; the transmitters 258-1 to 258-5 are substantially aligned along the IC edge direction; and the receivers 260-1 to 260-4 are substantially aligned along the IC edge direction.

[0030] A disadvantage of the IC 240 including the transceiver interface circuit 200 is that the ESD circuits 256-1 to 256-5 and 206 may each introduce significant parasitic capacitance to the IC pads. For example, the reverse-biased diodes D1 and D2 of the ESD circuit 206 can be modeled as two parallel capacitors from a capacitance perspective. In addition, other components such as the output of the transceiver 208 and the input of the receiver 212 contribute additional parasitic capacitance to the IC pads. Therefore, the transmitted signal transmitted via the IC pad and / or the received signal received via the IC pad may lose significant signal integrity at the IC pad due to the parasitic capacitance. This is especially the case if the transmitted and received signals have a relatively high data rate.

[0031] Figure 3A FIG. 300 is a schematic diagram of another exemplary transceiver interface circuit in accordance with another aspect of the present disclosure. One solution for improving signal integrity at an IC pad (and improving / increasing the data rate of transmitted and received signals) is to add a T-coil to compensate for parasitic capacitance. The T-coil effectively eliminates or reduces the parasitic capacitance at the IC pad; thus improving signal integrity and data rate. The transceiver interface circuit 300 is similar to the transceiver interface circuit 200 discussed in detail previously and includes many similar elements identified by the same reference numerals. The most significant digit in the transceiver interface circuit 300 is "3" compared to "2" in the transceiver interface circuit 200.

[0032] As previously described, the transceiver interface circuit 300 also includes a T-coil 314 that includes a first inductor L 1 and a second inductor L 2 . The first inductor L 1 and the second inductor L 2 are serially coupled to the IC pad from the transmitter-side resistor R TX , where the node n1 between the inductors L 1 and L 2 coincides with the node n1 between the ESD diodes D1 and D2. As described above, the T-coil 314 compensates for the parasitic capacitance of the ESD diodes D1 and D2 as well as other parasitic capacitances to reduce the parasitic capacitance at the IC pad. This improves signal integrity and allows for higher data rate signals.

[0033] Figure 3B FIG. 340 is a layout or top view of an integrated circuit (IC) 340 in accordance with another aspect of the present disclosure. In this example, the IC 340 includes five (5) transceiver interface circuits 350-1 to 350-5 that can be coupled to a communication link (e.g., 130) via five (5) transmission lines (e.g., 132-1 to 132-5). Although five (5) transceiver interface circuits 350-1 to 350-5 are shown for illustrative purposes, it should be understood that the IC 340 can include a different number of transceiver interface circuits.

[0034] From a layout perspective, transceiver interface circuits 350-1 to 350-5 are staggered (e.g., substantially adjacent or next to each other) along the IC edge (or boundary) direction (e.g., bit-to-bit direction or data channel direction). Various components of each transceiver interface circuit among transceiver interface circuits 350-1 to 350-5 longitudinally extend from the IC edge in a direction perpendicular (orthogonal) to the IC edge direction. For example, transceiver interface circuit 350-1 includes decoupling capacitor 352-1, clamper 354-1, ESD circuit 356-1, T coil 364-1, transmitter 358-1, receiver 360-1, and core input 362-1, all of which together longitudinally extend from the IC edge in a direction perpendicular to the IC edge direction. Similarly, transceiver interface circuit 350-2 includes decoupling capacitor 352-2, clamper 354-2, ESD circuit 356-2, T coil 364-2, transmitter 358-2, receiver 360-2, and core input 362-2, all of which together longitudinally extend from the IC edge in a direction perpendicular to the IC edge direction.

[0035] The above arrangement continues along the IC edge direction. Transceiver interface circuit 350-3, which is staggered (e.g., substantially adjacent or next to each other) along the IC edge direction with transceiver interface circuit 350-2, includes decoupling capacitor 352-3, clamper 354-3, ESD circuit 356-3, T coil 364-3, transmitter 358-3, receiver 360-3, and core input 362-3, all of which together longitudinally extend from the IC edge in a direction perpendicular to the IC edge direction. Transceiver interface circuit 350-4, which is staggered (e.g., substantially adjacent or next to each other) along the IC edge direction with transceiver interface circuit 350-3, includes decoupling capacitor 352-4, clamper 354-4, ESD circuit 356-4, T coil 364-4, transmitter 358-4, receiver 360-4, and core input 362-4, all of which together longitudinally extend from the IC edge in a direction perpendicular to the IC edge direction. Transceiver interface circuit 350-5, which is staggered (e.g., substantially adjacent or next to each other) along the IC edge direction with transceiver interface circuit 350-2, includes decoupling capacitor 352-5, clamper 354-5, ESD circuit 356-4, T coil 364-5, transmitter 358-5, receiver 360-5, and core input 362-5, all of which together longitudinally extend from the IC edge in a direction perpendicular to the IC edge direction.

[0036] In this layout arrangement, the decoupling capacitors 352-1 to 352-5 are substantially aligned along the IC edge direction; the clampers 354-1 to 352-5 are substantially aligned along the IC edge direction; the ESD circuits 356-1 to 356-5 are substantially aligned along the IC edge direction; the T coils 364-1 to 364-5 are substantially aligned along the IC edge direction; the transmitters 358-1 to 358-5 are substantially aligned along the IC edge direction; and the receivers 360-1 to 360-4 are substantially aligned along the IC edge direction.

[0037] The disadvantage of the IC 340 stems from the fact that the T coils 364-1 to 364-5 are staggered (e.g., substantially adjacent or neighboring each other) along the IC edge direction. In such an arrangement, the close proximity of adjacent T coils (e.g., 364-1 and 364-2, 364-2 and 364-3, 364-3 and 364-4, and 364-4 and 364-5) in the IC edge direction causes their mutual inductance to interfere with each other. As a result, the transmission and / or reception signals of the transceiver interface circuits 350-1 to 350-5 cross-couple and interfere with each other; thus degrading the signal integrity across the data channels.

[0038] Figure 4 A layout or top view of another integrated circuit (IC) 400 according to another aspect of the present disclosure is shown. A layout method for reducing or eliminating the mutual coupling between T coils associated with different transceiver interface circuits is to arrange the T coils such that the T coils of adjacent transceiver interface circuits are not aligned along the IC edge direction. In other words, each T coil is offset from the T coil in the adjacent transceiver interface circuit in a direction orthogonal to the IC edge direction. Or, in other words, their respective distances from the IC edge are different. The particular T coil arrangement in the IC 400 can be referred to as a cell rotation arrangement because the T coils alternate between a first position (e.g., closest to the IC edge) and a second position (e.g., the sixth position from the IC edge) from one transceiver interface circuit to the adjacent transceiver interface circuit.

[0039] Similarly, in this example, the IC 400 includes five (5) transceiver interface circuits 450-1 to 450-5 that can be coupled to a communication link (e.g., 130) by five (5) transmission lines (e.g., 132-1 to 132-5); however, it can include more or less than five (5). From a layout perspective, the transceiver interface circuits 450-1 to 450-5 are staggered (e.g., and substantially adjacent or neighboring each other) along the IC edge (or boundary) direction (e.g., bit-to-bit direction or data channel direction). The various components of each transceiver interface circuit among the transceiver interface circuits 450-1 to 450-5 collectively extend longitudinally from the IC edge in a direction perpendicular (orthogonal) to the IC edge direction.

[0040] For example, the transceiver interface circuit 450-1 includes a T coil 464-1, a clamper 454-1, a first ESD circuit 456-1a, a transmitter 458-1, an optional second ESD circuit 456-1b, a decoupling capacitor 452-1, a receiver 460-1, and a core input 462-1, all of which extend longitudinally from the IC edge in a direction perpendicular to the direction of the IC edge. The transceiver interface circuit 450-2 includes a decoupling capacitor 452-2, a clamper 454-2, a first ESD circuit 456-2a, a transmitter 458-2, an optional second ESD circuit 456-2b, a T coil 464-2, a receiver 460-2, and a core input 462-2, all of which extend longitudinally from the IC edge in a direction perpendicular to the direction of the IC edge.

[0041] Similarly, the transceiver interface circuit 450-3 includes a T coil 464-3, a clamper 454-3, a first ESD circuit 456-3a, a transmitter 458-3, an optional second ESD circuit 456-3b, a decoupling capacitor 452-3, a receiver 460-3, and a core input 462-3, all of which extend longitudinally from the IC edge in a direction perpendicular to the direction of the IC edge. The transceiver interface circuit 450-4 includes a decoupling capacitor 452-4, a clamper 454-4, a first ESD circuit 456-4a, a transmitter 458-4, an optional second ESD circuit 456-4b, a T coil 464-4, a receiver 460-4, and a core input 462-4, all of which extend longitudinally from the IC edge in a direction perpendicular to the direction of the IC edge. Finally, the transceiver interface circuit 450-5 includes a T coil 464-5, a clamper 454-5, a first ESD circuit 456-5a, a transmitter 458-5, an optional second ESD circuit 456-5b, a decoupling capacitor 452-5, a receiver 460-5, and a core input 462-5, all of which extend longitudinally from the IC edge in a direction perpendicular to the direction of the IC edge.

[0042] As described above, the T coils exhibit unit rotation (rotation between a first position and a sixth position along the IC edge (bit or data channel direction)) according to the layout of the IC 400. For example, the T coil 464-1 of the transceiver interface circuit 450-1 is in the first position (closest to the IC edge); the T coil 464-2 of the next adjacent transceiver interface circuit 450-2 is in the sixth position (starting from the IC edge); the T coil 464-3 of the next adjacent transceiver interface circuit 450-3 is in the first position (closest to the IC edge); the T coil 464-4 of the next adjacent transceiver interface circuit 450-4 is in the sixth position (starting from the IC edge); and the T coil 464-5 of the next adjacent transceiver interface circuit 450-5 is in the sixth position (starting from the IC edge).

[0043] Similarly, the decoupling capacitors exhibit complementary unit rotation (rotation between a sixth position and a first position along the IC edge (bit or data channel direction)) according to the layout of the IC 400. For example, the decoupling capacitor 452-1 of the transceiver interface circuit 450-1 is in the sixth position (starting from the IC edge); the decoupling capacitor 452-2 of the next adjacent transceiver interface circuit 450-2 is in the first position (closest to the IC edge); the decoupling capacitor 452-3 of the next adjacent transceiver interface circuit 450-3 is in the sixth position (starting from the IC edge); the decoupling capacitor 452-4 of the next adjacent transceiver interface circuit 450-4 is in the first position (starting from the IC edge); and the decoupling capacitor 452-5 of the next adjacent transceiver interface circuit 450-5 is in the sixth position (starting from the IC edge).

[0044] Figure 5 A layout or top view of another integrated circuit (IC) 500 according to another aspect of the present disclosure is shown. Similarly, a layout method for reducing or eliminating mutual coupling between T coils associated with different transceiver interface circuits is to arrange the T coils such that the T coils of adjacent transceiver interface circuits are not aligned along the IC edge direction. In other words, each T coil is offset from the T coil in the adjacent transceiver interface circuit in a direction orthogonal to the IC edge direction. Or, in other words, their respective distances from the IC edge are different. The specific T coil arrangement in the IC 500 can be referred to as a checkerboard arrangement because the T coils alternate between a first position (e.g., closest to the IC edge) and a second position (e.g., the second position from the IC edge) from one transceiver interface circuit to the next adjacent transceiver interface circuit.

[0045] Similarly, in this example, the IC 500 includes five (5) transceiver interface circuits 550-1 to 550-5 that can be coupled to a communication link (e.g., 130) via five (5) transmission lines (e.g., 132-1 to 132-5); however, it can include more or fewer than five (5). From a layout perspective, the transceiver interface circuits 550-1 to 550-5 are staggered (e.g., substantially adjacent or next to each other) along the IC edge (or boundary) direction (e.g., bit-to-bit direction or data channel direction). The various components of each transceiver interface circuit among the transceiver interface circuits 550-1 to 550-5 extend longitudinally from the IC edge in a direction perpendicular (orthogonal) to the IC edge direction.

[0046] For example, the transceiver interface circuit 550-1 includes a T coil 564-1, a decoupling capacitor 552-1, a clamper 554-1, an ESD circuit 556-1, a transmitter 558-1, a receiver 560-1, and a core input 562-1, all of which extend longitudinally from the IC edge in a direction perpendicular to the IC edge direction. The transceiver interface circuit 550-2 includes a decoupling capacitor 552-2, a T coil 564-2, a clamper 554-2, an ESD circuit 556-2, a transmitter 558-2, a receiver 560-2, and a core input 562-2, all of which extend longitudinally from the IC edge in a direction perpendicular to the IC edge direction.

[0047] Similarly, the transceiver interface circuit 550-3 includes a T coil 564-3, a decoupling capacitor 552-3, a clamper 554-3, an ESD circuit 556-3, a transmitter 558-3, a receiver 560-3, and a core input 562-3, all of which extend longitudinally from the IC edge in a direction perpendicular to the IC edge direction. The transceiver interface circuit 550-4 includes a decoupling capacitor 552-4, a T coil 564-4, a clamper 554-4, an ESD circuit 556-4, a transmitter 558-4, a receiver 560-4, and a core input 562-4, all of which extend longitudinally from the IC edge in a direction perpendicular to the IC edge direction. The transceiver interface circuit 550-5 includes a T coil 564-5, a decoupling capacitor 552-5, a clamper 554-5, an ESD circuit 556-5, a transmitter 558-5, a receiver 560-5, and a core input 562-5, all of which extend longitudinally from the IC edge in a direction perpendicular to the IC edge direction.

[0048] As described above, the T coils exhibit a checkerboard arrangement according to the layout of the IC 500 (checkerboard arrangement between a first position and a second position along the IC edge (bit or data channel direction)). For example, the T coil 564-1 of the transceiver interface circuit 550-1 is in the first position (closest to the IC edge); the T coil 564-2 of the next adjacent transceiver interface circuit 550-2 is in the second position (starting from the IC edge); the T coil 564-3 of the next adjacent transceiver interface circuit 550-3 is in the first position (closest to the IC edge); the T coil 564-4 of the next adjacent transceiver interface circuit 550-4 is in the second position (starting from the IC edge); and the T coil 564-5 of the next adjacent transceiver interface circuit 550-5 is in the sixth position (starting from the IC edge).

[0049] Similarly, the decoupling capacitors exhibit a complementary checkerboard arrangement according to the layout of the IC 500 (checkerboard arrangement between a second position and a first position along the IC edge (bit or data channel direction)). For example, the decoupling capacitor 552-1 of the transceiver interface circuit 550-1 is in the second position (starting from the IC edge); the decoupling capacitor 552-2 of the next adjacent transceiver interface circuit 550-2 is in the first position (closest to the IC edge); the decoupling capacitor 552-3 of the next adjacent transceiver interface circuit 550-3 is in the second position (starting from the IC edge); the decoupling capacitor 552-4 of the next adjacent transceiver interface circuit 550-4 is in the first position (starting from the IC edge); and the decoupling capacitor 552-5 of the next adjacent transceiver interface circuit 550-5 is in the second position (starting from the IC edge).

[0050] Figure 6 A schematic diagram of another exemplary transceiver interface circuit 600 according to another aspect of the present disclosure is shown. The transceiver interface circuit 600 is similar to the previously discussed in detail transceiver interface circuit 300 including many similar elements identified by the same reference numerals. Compared with the "3" in the transceiver interface circuit 300, the most significant digit in the transceiver interface circuit 600 is "6".

[0051] The transceiver interface circuit 600 differs from the transceiver interface circuit 300 in that the transceiver interface circuit 600 includes additional protection diodes for the transmitter 608 and the receiver 612. For example, the transceiver interface circuit 600 includes transmitter protection reverse-biased diodes D3 and D4 serially coupled between the second upper voltage rail Vdd2 and the lower voltage rail Vss (e.g., ground). That is, diode D3 includes a cathode coupled to the second upper voltage rail Vdd2 and an anode coupled to the cathode of diode D4 at the output of the transmitter 608; and diode D4 includes an anode coupled to the lower voltage rail Vss. Note that in the transceiver interface circuit 600, the transmitter and the ESD circuit 606 are coupled between the first upper voltage rail Vdd1 and the lower voltage rail Vss.

[0052] Similarly, the transceiver interface circuit 600 also includes receiver protection reverse-biased diodes D5 and D6 serially coupled between the second upper voltage rail Vdd2 and the lower voltage rail Vss. That is, diode D5 includes a cathode coupled to the second upper voltage rail Vdd2 and an anode coupled to the cathode of diode D6 at the first input of the receiver 612; and diode D6 includes an anode coupled to the lower voltage rail Vss.

[0053] Figure 7 A block diagram of an example wireless communication device 700 is shown in accordance with another aspect of the present disclosure. The wireless communication device 700 can be a smart phone, a desktop computer, a laptop computer, a tablet device, an Internet of Things (IoT), a wearable wireless device (e.g., a wireless watch), and other types of wireless devices.

[0054] In particular, the wireless communication device 700 includes an integrated circuit (IC) 710 that can be implemented as a system-on-chip (SOC). The IC 710 includes one or more signal processing cores 720 configured to generate transmission baseband (BB) signals and process received baseband (BB) signals. The IC 710 further includes a set of transceiver interface circuits (TIC) 730-1 to 730-N that are coupled to a set of transmission lines 742-1 to 740-N of a baseband signal double data rate (DDR) communication link 740 that couples the IC 710 to a baseband / radio frequency (BB / RF) transceiver 750. The set of transceiver interface circuits (TIC) 730-1 to 730-N can be implemented in accordance with the previously discussed ICs 400 and 500.

[0055] The transceiver 750 is coupled to one or more signal processing cores 720 to receive transmitted BB signals therefrom and provide received BB signals thereto via the BB signal DDR communication interface 740. The transceiver 750 is configured to convert the transmitted BB signals into transmitted radio frequency (RF) signals and convert the received RF signals into received BB signals. The transceiver 750 is coupled to at least one antenna 760 to provide thereto the transmitted RF signals for electromagnetic radiation into the wireless medium for wireless transmission and receive the received RF signals electromagnetically picked up by the at least one antenna 760 from the wireless medium.

[0056] The following provides an overview of aspects of the present disclosure:

[0057] Aspect 1: An integrated circuit (IC) comprising: a first transceiver interface circuit extending longitudinally in a first direction that is substantially perpendicular to a second direction, the second direction being parallel to an edge of the IC, wherein the first transceiver interface circuit includes a first T coil; and a second transceiver interface circuit extending longitudinally in the second direction, wherein the second transceiver interface circuit is interleaved with the first transceiver interface circuit along the second direction, wherein the second transceiver interface circuit includes a second T coil, and wherein the second T coil is offset from the first T coil along the first direction.

[0058] Aspect 2. The IC according to aspect 1, wherein: the first transceiver interface circuit further includes a first decoupling capacitor, wherein the first T coil is located between the edge of the IC and the first decoupling capacitor; and the second transceiver interface circuit further includes a second decoupling capacitor, wherein the second decoupling capacitor is located between the edge of the IC and the second T coil.

[0059] Aspect 3. The IC according to aspect 2, wherein the first T coil and the second decoupling capacitor are substantially aligned along the second direction.

[0060] Aspect 4. The IC according to aspect 2 or 3, wherein the first decoupling capacitor and the second T coil are substantially aligned along the second direction.

[0061] Aspect 5. The IC according to any one of aspects 2 to 4, wherein: the first transceiver interface circuit further includes a first clamper, wherein the first clamper is located between the first T coil and the first decoupling capacitor; and the second transceiver interface circuit further includes a second clamper, wherein the second clamper is located between the second T coil and the second decoupling capacitor.

[0062] Aspect 6. The IC according to aspect 5, wherein the first clamper and the second clamper are substantially aligned along the second direction.

[0063] Aspect 7. The IC according to any one of Aspects 2 to 6, wherein: the first transceiver interface circuit further includes a first electrostatic discharge (ESD) circuit, where the first ESD circuit is located between the first T coil and the first decoupling capacitor; and the second transceiver interface circuit further includes a second ESD circuit, where the second ESD circuit is located between the second T coil and the second decoupling capacitor.

[0064] Aspect 8. The IC according to Aspect 7, wherein the first ESD circuit and the second ESD circuit are substantially aligned along a second direction.

[0065] Aspect 9. The IC according to Aspect 7 or 8, wherein: the first transceiver interface circuit further includes a third ESD circuit, where the first ESD circuit and the third ESD circuit are located between the first T coil and the first decoupling capacitor; and the second transceiver interface circuit further includes a fourth ESD circuit, where the second ESD circuit and the fourth ESD circuit are located between the second T coil and the second decoupling capacitor.

[0066] Aspect 10. The IC according to Aspect 9, wherein: the first transceiver interface circuit further includes a first transmitter, where the first transmitter is located between the first ESD circuit and the third ESD circuit; and the second transceiver interface circuit further includes a second transmitter, where the second transmitter is located between the second ESD circuit and the fourth ESD circuit.

[0067] Aspect 11. The IC according to any one of Aspects 2 to 10, wherein: the first transceiver interface circuit further includes a first transmitter, where the first transmitter is located between the first T coil and the first decoupling capacitor; and the second transceiver interface circuit further includes a second transmitter, where the second transmitter is located between the second T coil and the second decoupling capacitor.

[0068] Aspect 12. The IC according to any one of Aspects 2 to 11, wherein: the first transceiver interface circuit further includes a first receiver, where the first decoupling capacitor is located between the first T coil and the first receiver; and the second transceiver interface circuit further includes a second receiver, where the second T coil is located between the second decoupling capacitor and the second receiver.

[0069] Aspect 13. The IC according to any one of Aspects 2 to 12, wherein: a first group of one or more components is located between the first T coil and the first decoupling capacitor; and a second group of one or more components is located between the second T coil and the second decoupling capacitor.

[0070] Aspect 14. The IC according to Aspect 2, wherein: the first T coil is adjacent to the first decoupling capacitor; and the second T coil is adjacent to the second decoupling capacitor.

[0071] Aspect 15. The IC according to aspect 14, wherein: the first transceiver interface circuit further includes a first clamper, and a first decoupling capacitor is located between the first T coil and the first clamper; and the second transceiver interface circuit further includes a second clamper, and a second T coil is located between the second decoupling capacitor and the second clamper.

[0072] Aspect 16. The IC according to aspect 14 or 15, wherein:

[0073] the first transceiver interface circuit further includes a first electrostatic discharge (ESD) circuit, and a first decoupling capacitor is located between the first T coil and the first ESD circuit; and the second transceiver interface circuit further includes a second ESD circuit, and a second T coil is located between the second decoupling capacitor and the second ESD circuit.

[0074] Aspect 17. The IC according to any one of aspects 14 to 16, wherein: the first transceiver interface circuit further includes a first transmitter, and a first decoupling capacitor is located between the first T coil and the first transmitter; and the second transceiver interface circuit further includes a second transmitter, and a second T coil is located between the second decoupling capacitor and the second transmitter.

[0075] Aspect 18. The IC according to any one of aspects 14 to 17, wherein: the first transceiver interface circuit further includes a first receiver, and a first decoupling capacitor is located between the first T coil and the first receiver; and the second transceiver interface circuit further includes a second receiver, and a second T coil is located between the second decoupling capacitor and the second receiver.

[0076] Aspect 19. The IC according to any one of aspects 1 to 18 further includes: a third transceiver interface circuit longitudinally extending in a first direction, wherein the second transceiver interface circuit is located between the first transceiver interface circuit and the third transceiver interface circuit, and wherein the third transceiver interface circuit includes a third T coil; and a fourth transceiver interface circuit longitudinally extending in the first direction, wherein the third transceiver interface circuit is located between the second transceiver interface circuit and the fourth transceiver interface circuit, wherein the fourth transceiver interface circuit includes a fourth T coil, and the fourth T coil is offset from the third T coil along the first direction.

[0077] Aspect 20. The IC according to aspect 19, wherein: the first T coil and the third T coil are substantially aligned along a second direction; and the second T coil and the fourth T coil are substantially aligned along the second direction.

[0078] Aspect 21. A wireless communication device, comprising: at least one antenna; a transceiver coupled to the at least one antenna; a communication link including a set of transmission lines coupled to the transceiver; and an integrated circuit (IC) including a set of transceiver interface circuits respectively coupled to the set of transmission lines, wherein: a first transceiver interface circuit in the set of transceiver interface circuits extends longitudinally in a first direction that is substantially perpendicular to a second direction, the second direction being parallel to an edge of the IC, wherein the first transceiver interface circuit includes a first T coil; and a second transceiver interface circuit in the set of transceiver interface circuits extends longitudinally in the first direction, wherein the second transceiver interface circuit is staggered with the first transceiver interface circuit along the second direction, wherein the second transceiver interface circuit includes a second T coil, and wherein the second T coil is offset from the first T coil along the first direction.

[0079] The foregoing description of the disclosure has been provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated circuit (IC), comprising: A first transceiver interface circuit that extends longitudinally in a first direction that is substantially perpendicular to a second direction parallel to an edge of the IC, wherein the first transceiver interface circuit includes a first T coil; and A second transceiver interface circuit that extends longitudinally in the first direction, wherein the second transceiver interface circuit is staggered with the first transceiver interface circuit along the second direction, wherein the second transceiver interface circuit includes a second T coil, and wherein the second T coil is offset from the first T coil along the first direction.

2. The IC according to claim 1, wherein: The first transceiver interface circuit further includes a first decoupling capacitor, wherein the first T coil is located between the edge of the IC and the first decoupling capacitor; and The second transceiver interface circuit further includes a second decoupling capacitor, wherein the second decoupling capacitor is located between the edge of the IC and the second T coil.

3. The IC according to claim 2, wherein the first T coil and the second decoupling capacitor are substantially aligned along the second direction.

4. The IC according to claim 2, wherein the first decoupling capacitor and the second T coil are substantially aligned along the second direction.

5. The IC according to claim 2, wherein: The first transceiver interface circuit further includes a first clamper, wherein the first clamper is located between the first T coil and the first decoupling capacitor; and The second transceiver interface circuit further includes a second clamper, wherein the second clamper is located between the second T coil and the second decoupling capacitor.

6. The IC according to claim 5, wherein the first clamper and the second clamper are substantially aligned along the second direction.

7. The IC according to claim 2, wherein: The first transceiver interface circuit further includes a first electrostatic discharge (ESD) circuit, wherein the first ESD circuit is located between the first T coil and the first decoupling capacitor; and The second transceiver interface circuit further includes a second ESD circuit, wherein the second ESD circuit is located between the second T coil and the second decoupling capacitor.

8. The IC according to claim 7, wherein the first ESD circuit and the second ESD circuit are substantially aligned along the second direction.

9. The IC according to claim 7, wherein: The first transceiver interface circuit further includes a third ESD circuit, wherein the first ESD circuit and the third ESD circuit are located between the first T coil and the first decoupling capacitor; and The second transceiver interface circuit further includes a fourth ESD circuit, wherein the second ESD circuit and the fourth ESD circuit are located between the second T coil and the second decoupling capacitor.

10. The IC according to claim 9, wherein: The first transceiver interface circuit further includes a first transmitter, wherein the first transmitter is located between the first ESD circuit and the third ESD circuit; and The second transceiver interface circuit further includes a second transmitter, wherein the second transmitter is located between the second ESD circuit and the fourth ESD circuit.

11. The IC according to claim 2, wherein: The first transceiver interface circuit further includes a first transmitter, wherein the first transmitter is located between the first T coil and the first decoupling capacitor; and The second transceiver interface circuit further includes a second transmitter, wherein the second transmitter is located between the second T coil and the second decoupling capacitor.

12. The IC according to claim 2, wherein: The first transceiver interface circuit further includes a first receiver, wherein the first decoupling capacitor is located between the first T coil and the first receiver; and The second transceiver interface circuit further includes a second receiver, wherein the second T coil is located between the second decoupling capacitor and the second receiver.

13. The IC according to claim 2, wherein: A first group of one or more components is located between the first T coil and the first decoupling capacitor; and A second group of one or more components is located between the second T coil and the second decoupling capacitor.

14. The IC according to claim 2, wherein: The first T coil is adjacent to the first decoupling capacitor; and The second T coil is adjacent to the second decoupling capacitor.

15. The IC according to claim 14, wherein: The first transceiver interface circuit further includes a first clamper, wherein the first decoupling capacitor is located between the first T coil and the first clamper; and The second transceiver interface circuit further includes a second clamper, wherein the second T coil is located between the second decoupling capacitor and the second clamper.

16. The IC according to claim 14, wherein: The first transceiver interface circuit further includes a first electrostatic discharge (ESD) circuit, wherein the first decoupling capacitor is located between the first T coil and the first ESD circuit; and The second transceiver interface circuit further includes a second ESD circuit, wherein the second T coil is located between the second decoupling capacitor and the second ESD circuit.

17. The IC according to claim 14, wherein: The first transceiver interface circuit further includes a first transmitter, wherein the first decoupling capacitor is located between the first T coil and the first transmitter; and The second transceiver interface circuit further includes a second transmitter, wherein the second T coil is located between the second decoupling capacitor and the second transmitter.

18. The IC according to claim 14, wherein: The first transceiver interface circuit further includes a first receiver, wherein the first decoupling capacitor is located between the first T coil and the first receiver; and The second transceiver interface circuit further includes a second receiver, wherein the second T coil is located between the second decoupling capacitor and the second receiver.

19. The IC according to claim 1, further comprises: a third transceiver interface circuit longitudinally extending in the first direction, wherein the second transceiver interface circuit is located between the first transceiver interface circuit and the third transceiver interface circuit, and wherein the third transceiver interface circuit includes a third T coil; and a fourth transceiver interface circuit longitudinally extending in the first direction, wherein the third transceiver interface circuit is located between the second transceiver interface circuit and the fourth transceiver interface circuit, wherein the fourth transceiver interface circuit includes a fourth T coil, and wherein the fourth T coil is offset from the third T coil along the first direction.

20. The IC according to claim 19, wherein: the first T coil and the third T coil are substantially aligned along the second direction; and the second T coil and the fourth T coil are substantially aligned along the second direction.

21. A wireless communication device, comprising: at least one antenna; a transceiver coupled to the at least one antenna; a communication link including a set of transmission lines coupled to the transceiver; and an integrated circuit (IC) including a set of transceiver interface circuits respectively coupled to the set of transmission lines, wherein: a first transceiver interface circuit in the set of transceiver interface circuits longitudinally extends in a first direction, the first direction being substantially perpendicular to a second direction, the second direction being parallel to an edge of the IC, wherein the first transceiver interface circuit includes a first T coil; and a second transceiver interface circuit in the set of transceiver interface circuits longitudinally extends in the first direction, wherein the second transceiver interface circuit is staggered with the first transceiver interface circuit along the second direction, wherein the second transceiver interface circuit includes a second T coil, and wherein the second T coil is offset from the first T coil along the first direction.

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