Memory, manufacturing method thereof, memory system and electronic equipment

Abstract

The embodiment of the invention discloses a memory and a manufacturing method thereof, a memory system and electronic equipment. The memory includes a first semiconductor structure including a vertical transistor; the first insulating structure and the second insulating structure are sequentially stacked on the first semiconductor structure; a contact structure penetrating the first insulating structure and connected to the semiconductor body of the vertical transistor; the first electrode structure comprises a first electrode layer penetrating through at least part of the first insulation structure and a second electrode layer penetrating through the second insulation structure; wherein the first electrode layer covers at least part of the side wall of the contact structure and is connected with the contact structure; the second electrode layer is connected with the first electrode layer; the second electrode structure comprises a first part located in the first insulation structure and a second part located in the second insulation structure; wherein the first part covers part of the side wall of the first electrode layer; the second part covers part of the side wall of the second electrode layer; and the capacitor dielectric layer is located between the first electrode structure and the second electrode structure.

Description

Memory and manufacturing method thereof, memory system and electronic device Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a memory and a manufacturing method thereof, a memory system, and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used memory device in electronic systems. It consists of many repeated memory cells, which usually include a capacitor and a transistor.

[0003] With the development of semiconductor technology, dynamic random access memory is moving towards higher density and higher integration. The characteristic size of capacitors is decreasing, which leads to a decrease in the capacitance value of capacitors. Therefore, how to increase the capacitance value of capacitors has become a technical problem that needs to be solved urgently.

[0004] Summary of the Invention

[0005] According to a first aspect of an embodiment of the present disclosure, there is provided a memory, including:

[0006] The first semiconductor structure includes: a vertical transistor;

[0007] a first insulating structure and a second insulating structure sequentially stacked on the first semiconductor structure;

[0008] a contact structure, penetrating the first insulating structure and connected to the semiconductor body of the vertical transistor;

[0009] a first electrode structure comprising: a first electrode layer penetrating at least a portion of the first insulating structure and a second electrode layer penetrating the second insulating structure; wherein the first electrode layer covers at least a portion of a sidewall of the contact structure and is connected to the contact structure; and the second electrode layer is connected to the first electrode layer;

[0010] The second electrode structure includes: a first portion located in the first insulating structure and a second portion located in the second insulating structure; wherein the first portion covers a portion of the sidewall of the first electrode layer; and the second portion covers a portion of the sidewall of the second electrode layer.

[0011] The capacitor dielectric layer is located between the first electrode structure and the second electrode structure.

[0012] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a memory is provided, comprising:

[0013] Providing a first semiconductor structure; wherein the first semiconductor structure includes a vertical transistor;

[0014] forming a first insulating structure covering the first semiconductor structure;

[0015] forming a contact structure penetrating the first insulating structure; wherein the contact structure is connected to the semiconductor body of the vertical transistor;

[0016] forming a second insulating structure covering the contact structure and the first insulating structure;

[0017] forming a first electrode structure; wherein the first electrode structure includes a first electrode layer penetrating at least a portion of the first insulating structure and a second electrode layer penetrating the second insulating structure; the first electrode layer covers at least a portion of a sidewall of the contact structure and is connected to the contact structure; and the second electrode layer is connected to the first electrode layer;

[0018] forming a second electrode structure; wherein the second electrode structure includes a first portion located in the first insulating structure and a second portion located in the second insulating structure; the first portion covers a portion of the sidewall of the first electrode layer; and the second portion covers a portion of the sidewall of the second electrode layer;

[0019] A capacitor dielectric layer is formed; wherein the capacitor dielectric layer is located between the first electrode structure and the second electrode structure.

[0020] According to a third aspect of an embodiment of the present disclosure, there is provided a memory system, comprising: the memory as described in any one of the above embodiments;

[0021] A memory controller is coupled to the memory and configured to control the memory.

[0022] According to a fourth aspect of the embodiments of the present disclosure, there is provided an electronic device, comprising: the memory system as described in the above embodiments;

[0023] A host is coupled to the memory system.

[0024] In the embodiment of the present disclosure, the characteristic size of the first electrode structure can be increased by providing a first electrode layer that penetrates at least a portion of the first insulating structure and a second electrode layer that penetrates the second insulating structure; the characteristic size of the second electrode structure can be increased by providing a first portion of the side wall that covers a portion of the first electrode layer and a second portion of the side wall that covers a portion of the second electrode layer, so that the effective facing area between the first electrode structure and the second electrode structure is increased, which is beneficial to increasing the capacitance value of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1a is a schematic cross-sectional view of a memory according to an exemplary embodiment;

[0026] FIG1b is a schematic top view of a memory according to an exemplary embodiment;

[0027] FIG2 a is a first cross-sectional schematic diagram of a memory according to an embodiment of the present disclosure;

[0028] FIG2 b is a second cross-sectional schematic diagram of a memory according to an embodiment of the present disclosure;

[0029] FIG3 a is a third cross-sectional schematic diagram of a memory according to an embodiment of the present disclosure;

[0030] FIG3 b is a fourth cross-sectional schematic diagram of a memory according to an embodiment of the present disclosure;

[0031] FIG4 is a flow chart of a method for manufacturing a memory according to an embodiment of the present disclosure;

[0032] 5a to 5t are schematic diagrams 1 of a manufacturing process of a memory according to an embodiment of the present disclosure;

[0033] 6a to 6e are schematic diagrams 2 of a manufacturing process of a memory according to an embodiment of the present disclosure;

[0034] 7a to 7j are schematic diagrams 3 of a manufacturing process of a memory according to an embodiment of the present disclosure;

[0035] 8a to 8c are schematic diagrams 4 of the manufacturing process of the memory according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0037] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0038] In the embodiments of the present disclosure, the terms "first," "second," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0039] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0040] Figure 1a is a schematic cross-sectional view of a memory device according to an exemplary embodiment, and Figure 1b is a schematic top view of the memory device in Figure 1a taken along section line AA'. Referring to Figures 1a and 1b, the memory device includes a capacitor, which includes a lower electrode 150, an upper electrode 160, and a capacitor dielectric layer 170 located between the upper electrode 160 and the lower electrode 150.

[0041] As the integration density of dynamic random access memory increases, the characteristic size of the capacitor decreases, and the effective facing area between the upper electrode 160 and the lower electrode 150 decreases; and the capacitance value of the capacitor is related to the size of the capacitor and the effective facing area between the upper electrode 160 and the lower electrode 150. Specifically, as the characteristic size of the capacitor decreases and the effective facing area between the upper electrode 160 and the lower electrode 150 decreases, the capacitance value of the capacitor decreases.

[0042] It should be noted that the overlapping area between the upper electrode 160 and the lower electrode 150 is the effective facing area between the upper electrode 160 and the lower electrode 150 .

[0043] In view of this, embodiments of the present disclosure provide a memory and a manufacturing method thereof, a memory system, and an electronic device.

[0044] FIG2a is a cross-sectional schematic diagram of a memory 200 according to an embodiment of the present disclosure. Referring to FIG2a , the memory 200 includes:

[0045] The first semiconductor structure 210 includes: a vertical transistor 211;

[0046] A first insulating structure 220 and a second insulating structure 230 sequentially stacked on the first semiconductor structure 210;

[0047] a contact structure 240 penetrating the first insulating structure 220 and connected to the semiconductor body 211 b of the vertical transistor;

[0048] The first electrode structure 250 includes: a first electrode layer 251 that penetrates at least a portion of the first insulating structure 220 and a second electrode layer 252 that penetrates the second insulating structure 230; wherein the first electrode layer 251 covers at least a portion of the sidewall of the contact structure 240 and is connected to the contact structure 240; and the second electrode layer 252 is connected to the first electrode layer 251;

[0049] The second electrode structure 260 includes a first portion 261 located in the first insulating structure 220 and a second portion 262 located in the second insulating structure 230 . The first portion 261 covers a portion of the sidewall of the first electrode layer 251 , and the second portion 262 covers a portion of the sidewall of the second electrode layer 252 .

[0050] The capacitor dielectric layer 270 is located between the first electrode structure 250 and the second electrode structure 260 .

[0051] Memory 200 includes a memory cell array and peripheral circuits. The peripheral circuits are coupled to the memory cell array and are configured to control logical operations (e.g., writing or reading) of the memory cell array. Memory 200 includes, but is not limited to, dynamic random access memory. In the embodiments of this disclosure, memory 200 is described as a dynamic random access memory.

[0052] The memory cell array includes a plurality of memory cells, each memory cell including a storage node (SN) and a transistor. The storage node represents an electronic component used to store data in the memory. For example, in a dynamic random access memory, the storage node may be a capacitor. In some embodiments, the memory cell further includes a storage node contact (SNC). The storage node contact is used to realize the connection between the storage node and the transistor and reduce the contact resistance between the storage node and the transistor, thereby improving the electrical performance of the memory.

[0053] The vertical transistor 211 includes a semiconductor body 211b extending along the thickness of the first semiconductor structure 210. A source and a drain are disposed at each end of the semiconductor body 211b. The source and drain may be doped with a P-type dopant (e.g., boron or gallium) or an N-type dopant (e.g., phosphorus or arsenic). One or more channels (not shown) of the vertical transistor 211 are disposed in the semiconductor body 211b between the source and drain along the thickness of the first semiconductor structure 210. The semiconductor body 211b is at least partially surrounded by a gate 211a. A gate dielectric layer is disposed between the gate 211a and the channel. Shallow trench isolation is disposed between adjacent vertical transistors 211. In some embodiments, the semiconductor body 211b is connected to a bit line (not shown), which is located on a side of the semiconductor body 211b relatively away from the first electrode structure 250. In one specific embodiment, the semiconductor body 211b is connected to the bit line via a bit line contact structure (not shown), which is disposed between the semiconductor body 211b and the bit line.

[0054] On a plane perpendicular to the thickness of the first semiconductor structure 210 , the cross-sectional shape of the semiconductor body 211b includes: rectangular, trapezoidal, circular or other shapes. Those skilled in the art can choose according to actual needs, and this disclosure does not limit this.

[0055] The vertical transistor 211 includes a single-gate transistor or a multi-gate transistor. The multi-gate transistor includes a full-ring gate transistor, a triple-gate transistor or a double-gate transistor. It should be noted that the multi-gate transistor can have a larger gate control area to achieve better channel control with a smaller subthreshold swing, that is, to enhance the gate's control ability over the channel.

[0056] The first insulating structure 220 is located between the first semiconductor structure 210 and the second insulating structure 230. The first insulating structure 220 and the second insulating structure 230 may include a single insulating film layer or multiple insulating film layers. In the embodiments of the present disclosure, the first insulating structure 220 and the second insulating structure 230 are described as an example in which both the first insulating structure 220 and the second insulating structure 230 include multiple insulating film layers. The first insulating structure 220 and the second insulating structure 230 are described in detail below and are not repeated here.

[0057] The first end of the contact structure 240 is connected to the semiconductor body 211b of the vertical transistor 211, and the second end of the contact structure 240 is exposed from the first insulating structure 220 away from the surface of the first semiconductor structure 210. The first end and the second end of the contact structure 240 are relatively arranged along the thickness direction of the first semiconductor structure 210. The material of the contact structure 240 includes at least one of polysilicon, doped polysilicon, metal and metal silicide.

[0058] The first electrode structure 250 includes a first electrode layer 251 and a second electrode layer 252; in some embodiments, the first electrode layer 251 penetrates a portion of the first insulating structure 220, the bottom of the first electrode layer 251 is located in the first insulating structure 220, and the first electrode layer 251 covers a portion of the side wall of the contact structure 240, as shown in Figure 2a.

[0059] The second electrode structure 260 includes a first portion 261 and a second portion 262 . The first portion 261 covers a portion of the sidewall of the first electrode layer 251 , and the second portion 262 covers a portion of the sidewall of the second electrode layer 252 , as shown in FIG. 2 a .

[0060] The capacitor dielectric layer 270 includes a first sub-capacitor dielectric layer 271 and a second sub-capacitor dielectric layer 272 . The first sub-capacitor dielectric layer 271 is located between the first electrode layer 251 and the first portion 261 , and the second sub-capacitor dielectric layer 272 is located between the second electrode layer 252 and the second portion 262 .

[0061] The materials of the first electrode structure 250 and the second electrode structure 260 include conductive materials, for example, at least one of semiconductor materials (for example, polysilicon, doped polysilicon, etc.), metals (for example, tungsten, titanium, etc.), metal nitrides (for example, tungsten nitride, titanium nitride, tantalum nitride, etc.) and metal silicides (for example, titanium silicide, nickel silicide, titanium silicon nitride, etc.). The embodiment of the present disclosure is described using the example that the material of the first electrode structure 250 and the second electrode structure 260 is titanium nitride.

[0062] The material of the capacitor dielectric layer 270 includes a capacitor dielectric material, for example, at least one of a low dielectric constant material (for example, silicon oxide, etc.) and a high dielectric constant material (for example, aluminum oxide, etc.).

[0063] In some embodiments, the first electrode structure 250 , the capacitor dielectric layer 270 and the second electrode structure 260 constitute a storage node, and the first electrode structure 250 and the second electrode structure 260 serve as a lower electrode and an upper electrode respectively; the contact structure 240 is a storage node contact.

[0064] In some embodiments, in the direction along the thickness of the first semiconductor structure 210, the size of the first electrode structure 250 is greater than the size of the second insulating structure 230 and less than or equal to the sum of the sizes of the first insulating structure 220 and the second insulating structure 230, which is beneficial to increasing the characteristic size of the first electrode structure 250; in the direction along the thickness of the first semiconductor structure 210, the size of the second electrode structure 260 is greater than the size of the second insulating structure 230 and less than the sum of the sizes of the first insulating structure 220 and the second insulating structure 230, which is beneficial to increasing the characteristic size of the second electrode structure 260, thereby increasing the effective facing area between the first electrode structure 250 and the second electrode structure 260.

[0065] In the embodiment of the present disclosure, the characteristic size of the first electrode structure can be increased by providing a first electrode layer that penetrates at least a portion of the first insulating structure and a second electrode layer that penetrates the second insulating structure; the characteristic size of the second electrode structure can be increased by providing a first portion of the side wall that covers a portion of the first electrode layer and a second portion of the side wall that covers a portion of the second electrode layer, so that the effective facing area between the first electrode structure and the second electrode structure is increased, which is beneficial to increasing the capacitance value of the capacitor.

[0066] In some embodiments, the first insulating structure 220 includes a first insulating layer 221 and a first supporting layer 222 sequentially stacked on the first semiconductor structure 210; the first insulating layer 221 and the first supporting layer 222 are spaced apart; and the first portion 261 is located between the first insulating layer 221 and the first supporting layer 222. Here, the first insulating layer 221 includes a first sub-insulating layer 221a and a second sub-insulating layer 221b, and the first sub-insulating layer 221a and the second sub-insulating layer 221b are sequentially located on the first semiconductor structure 210.

[0067] In some embodiments, the contact structure 240 located on the first insulating layer 221, the first electrode layer 251 located on the first insulating layer 221, the second electrode layer 252, the second electrode structure 260 and the capacitor dielectric layer 270 constitute a storage node, the contact structure 240 located on the first insulating layer 221, the first electrode layer 251 located on the first insulating layer 221 and the second electrode layer 252 serve as lower electrodes, and the second electrode structure 260 serves as an upper electrode; the contact structure 240 and the first electrode layer 251 located in the first insulating layer 221 constitute a storage node contact.

[0068] The material of the first insulating layer 221 includes an insulating material, such as at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride boride, and silicon nitride carbide. The material of the first supporting layer 222 includes at least one of carbonitride, silicon nitride, or carbide. In one embodiment, the first insulating layer 221 includes a composite film layer formed of multiple layers. In other embodiments, the first insulating layer 221 includes a single film layer. This is not particularly limited in the embodiments of the present disclosure.

[0069] In some embodiments, the memory device 200 further includes a first filling layer 261a located between the first insulating layer 221 and the first supporting layer 222. A first sub-capacitor dielectric layer 271, a first portion 261, and a first filling layer 261a are sequentially arranged in the gap between the first insulating layer 221 and the first supporting layer 222, from radially outward to radially inward of the gap. The first filling layer 261a fills and covers a first side of the first portion 261, and a second side of the first portion 261 covers the first sub-capacitor dielectric layer 271. Here, the material of the first filling layer 261a includes polysilicon or silicon germanium.

[0070] In the embodiment of the present disclosure, by setting the first insulating structure including the first insulating layer and the first supporting layer arranged at intervals, the first part of the second electrode structure can be set in the interval between the first insulating layer and the first supporting layer, thereby increasing the characteristic size of the second electrode structure, and then increasing the effective facing area between the first electrode structure and the second electrode structure, which is beneficial to increasing the capacitance value of the capacitor.

[0071] In some embodiments, the contact structure 240 includes: a metal layer 241 and a semiconductor layer 243; wherein the metal layer 241 penetrates the first support layer 222 and extends into the first insulating layer 221; the semiconductor layer 243 is located between the semiconductor body 211b and the metal layer 241;

[0072] The first electrode layer 251 includes a first sub-electrode layer 251 a located on the semiconductor layer 243 and covering the sidewalls of the metal layer 241 .

[0073] The first end of the metal layer 241 is located within the first insulating layer 221, and the second end of the metal layer 241 is exposed from the surface of the first supporting layer 222 away from the first insulating layer 221. Along the thickness of the first semiconductor structure 210, the size of the metal layer 241 is larger than the sum of the size of the first supporting layer 222 and the size of the gap, and smaller than the size of the first insulating structure 220. The size of the semiconductor layer 243 is smaller than the size of the first insulating layer 221. In one embodiment, the first end of the metal layer 241 may be connected to the semiconductor layer 243, and the second end of the metal layer 241 may be connected to the second electrode layer 252.

[0074] The first sub-electrode layer 251a covers the sidewalls of the metal layer 241. In one embodiment, the orthographic projection of the metal layer 241 is circular or elliptical, and the first sub-electrode layer 251a is disposed around the metal layer 241.

[0075] The material of the metal layer 241 includes a conductive material, such as tungsten, copper, or aluminum, and the material of the semiconductor layer 243 includes polysilicon or doped polysilicon.

[0076] In the embodiment of the present disclosure, by setting the first sub-electrode layer to cover the side wall of the metal layer, it is beneficial to increase the characteristic size of the first electrode layer, thereby increasing the characteristic size of the first electrode structure; by setting the second electrode structure to cover the first electrode structure, the characteristic size of the second electrode structure is also increased, thereby increasing the effective facing area between the first electrode structure and the second electrode structure, which is beneficial to increase the capacitance value of the capacitor.

[0077] In some embodiments, the first electrode layer 251 further includes a second sub-electrode layer 251b located between the semiconductor layer 243 and the metal layer 241. Here, the second sub-electrode layer 251b covers the bottom of the metal layer 241 and is connected to the first sub-electrode layer 251a.

[0078] FIG2 b is a second cross-sectional schematic diagram of a memory device 300 according to an embodiment of the present disclosure. As shown in FIG2 b , the contact structure 240 includes a metal layer 241 and a semiconductor layer 243 . The metal layer 241 penetrates the first support layer 222 and extends between the first insulating layer 221 and the first support layer 222 . The semiconductor layer 243 is located between the semiconductor body 211 b and the metal layer 241 .

[0079] The first electrode layer 251 is located on the first semiconductor structure 210 and covers the sidewalls of the semiconductor layer 243 and the metal layer 241 .

[0080] The first end of the metal layer 241 is located between the first insulating layer 221 and the first supporting layer 222, and the second end of the metal layer 241 is exposed from the first supporting layer 222 away from the surface of the first insulating layer 221; in the direction along the thickness of the first semiconductor structure 210, the size of the metal layer 241 is smaller than the sum of the size of the first supporting layer 222 and the size of the gap; the size of the semiconductor layer 243 is larger than the size of the first insulating layer 221, the first end of the semiconductor layer 243 is connected to the semiconductor body 211b, and the second end of the semiconductor layer 243 is located in the gap between the first insulating layer 221 and the first supporting layer 222.

[0081] In some embodiments, the first electrode layer 251 penetrates the first insulating structure 220 , the bottom of the first electrode layer 251 is flush with the surface of the first insulating structure 220 close to the first semiconductor structure 210 , and the first electrode layer 251 covers the sidewalls of the contact structure 240 , as shown in FIG2 b .

[0082] In the embodiment of the present disclosure, by setting the first electrode layer to penetrate the first insulating layer and cover the side wall of the contact structure, the size of the first electrode structure is equal to the sum of the sizes of the first insulating structure and the second insulating structure in the direction along the thickness of the first semiconductor structure, which is conducive to further increasing the size of the first electrode structure, and the first portion covers the side wall of the first electrode layer located between the first insulating layer and the first supporting layer, which is conducive to further increasing the characteristic size of the second electrode structure, thereby further increasing the effective facing area between the first electrode structure and the second electrode structure, which is conducive to further increasing the capacitance value of the capacitor.

[0083] In some embodiments, as shown in FIG. 2a or FIG. 2b , the contact structure 240 includes a connection layer 242 located between the semiconductor layer 243 and the metal layer 241. The connection layer 242 is made of a metal silicide, such as cobalt silicide or titanium silicide. The connection layer 242 is used to reduce the contact resistance between the semiconductor layer 243 and the metal layer 241, thereby improving the electrical performance of the memory.

[0084] In one specific embodiment, as shown in FIG2 a , the second sub-electrode layer 251 b is located between the connection layer 242 and the metal layer 241. Along the thickness of the first semiconductor structure 210, the semiconductor layer 243, the connection layer 242, the second sub-electrode layer 251 b, and the metal layer 241 are sequentially connected. Of course, in other embodiments, the second sub-electrode layer 251 b between the connection layer 242 and the metal layer 241 may be omitted. Along the thickness of the first semiconductor structure 210, the semiconductor layer 243, the connection layer 242, and the metal layer 241 are sequentially connected, as shown in FIG2 b . This disclosure does not specifically limit this, and those skilled in the art may make their own choices based on actual needs.

[0085] In some embodiments, as shown in FIG. 2 a , the second insulating structure 230 includes: a second supporting layer 231 , wherein the second supporting layer 231 is spaced apart from the first insulating structure 220 ; and the second portion 262 is located between the first insulating structure 220 and the second supporting layer 231 .

[0086] In some embodiments, as shown in FIG. 2 a , the memory device 200 further includes a second filling layer 262 a located between the first supporting layer 222 and the second supporting layer 231 . In the gap between the first insulating structure 220 and the second supporting layer 231 , a second sub-capacitor dielectric layer 272 , a second portion 262 , and a second filling layer 262 a are sequentially arranged from radially outward to radially inward of the gap. The second filling layer 262 a fills and covers a first side of the second portion 262 , and a second side of the second portion 262 covers the second sub-capacitor dielectric layer 272 . The material of the second filling layer 262 a includes polysilicon or silicon germanium. The material of the second filling layer 262 a and the material of the first filling layer 261 a may be the same as or different from each other, and this disclosure is not particularly limited in this regard.

[0087] In some embodiments, as shown in FIG. 2 a , along the thickness direction of the first semiconductor structure 210 , a first insulating layer 221 , a first portion 261 , a first supporting layer 222 , a second portion 262 , and a second supporting layer 231 are sequentially disposed.

[0088] The material of the second supporting layer 231 includes at least one of carbonitride, silicon nitride or carbide. The material of the second supporting layer 231 and the material of the first supporting layer 222 can be the same or different. The present disclosure has no special restrictions on this. Those skilled in the art can make a selection according to actual needs.

[0089] In some embodiments, the first end of the second electrode layer 252 is connected to the first electrode layer 251, the second end of the second electrode layer 252 is exposed from the surface of the second supporting layer 231 away from the first insulating structure 220, and the second portion 262 covers the side wall of the second electrode layer 252 located between the first supporting layer 222 and the second supporting layer 231, that is, the second portion 262 covers a portion of the side wall of the second electrode layer 252.

[0090] In some embodiments, the first end of the second electrode layer 252 is further connected to the contact structure 240 . As shown in FIG. 2 a , the cross-section of the second electrode layer 252 is “U-shaped”.

[0091] In the embodiment of the present disclosure, by providing a second supporting layer spaced apart from the first insulating structure, the size of the second electrode layer can be further increased, thereby increasing the characteristic size of the first electrode structure; and the second portion covers the side wall of the second electrode layer located between the first insulating structure and the second supporting layer, which is conducive to further increasing the characteristic size of the second electrode structure, thereby further increasing the effective facing area between the first electrode structure and the second electrode structure, which is conducive to further increasing the capacitance value of the capacitor.

[0092] In some embodiments, as shown in FIG. 2 a , the second insulating structure 230 further includes a third supporting layer 232 , wherein the third supporting layer 232 and the second supporting layer 231 are spaced apart from each other; and the second portion 262 is further located between the second supporting layer 231 and the third supporting layer 232 .

[0093] In some embodiments, as shown in FIG. 2 a , the memory device 200 further includes a third filling layer 263 a located between the second supporting layer 231 and the third supporting layer 232. The capacitor dielectric layer 270 further includes a second sub-capacitor dielectric layer 272 located between the second supporting layer 231 and the third supporting layer 232. The second electrode structure 260 further includes a second portion 262 located between the second supporting layer 231 and the third supporting layer 232. In the gap between the second supporting layer 231 and the third supporting layer 232, the second sub-capacitor dielectric layer 272, the second portion 262, and the third filling layer 263 a are sequentially arranged from radially outward to radially inward of the gap. The third filling layer 263 a fills and covers a first side of the second portion 262, and a second side of the second portion 262 covers the second sub-capacitor dielectric layer 272. Here, the material of the third filling layer 263 a includes polysilicon or silicon germanium.

[0094] 2a , along the thickness direction of the first semiconductor structure 210 , a first insulating layer 221 , a first portion 261 , a first supporting layer 222 , a second portion 262 , a second supporting layer 231 , a second portion 262 and a third supporting layer 232 are sequentially arranged.

[0095] The material of the third supporting layer 232 includes at least one of carbonitride, silicon nitride or carbide. The materials of at least two of the first supporting layer 222, the second supporting layer 231 and the third supporting layer 232 can be the same or different. The present disclosure has no special restrictions on this, and those skilled in the art can make a selection according to actual needs.

[0096] In some embodiments, the first end of the second electrode layer 252 is connected to the first electrode layer 251, the second end of the second electrode layer 252 is exposed from the surface of the third supporting layer 232 away from the second supporting layer 231, and the second portion 262 covers the side wall of the second electrode layer 252 located between the first supporting layer 222 and the second supporting layer 231 and the side wall of the second electrode layer 252 between the second supporting layer 231 and the third supporting layer 232, that is, the second portion 262 covers a portion of the side wall of the second electrode layer 252.

[0097] In the embodiment of the present disclosure, by providing a third supporting layer spaced apart from the second supporting layer, the size of the second electrode layer can be further increased, thereby increasing the characteristic size of the first electrode structure; and the second portion covers the side walls of the second electrode layer between the first supporting layer and the second supporting layer and the side walls of the second electrode layer between the second supporting layer and the third supporting layer, which can further increase the characteristic size of the second electrode structure, thereby further increasing the effective facing area between the first electrode structure and the second electrode structure, which is beneficial to increasing the capacitance value of the capacitor.

[0098] FIG3 a is a third cross-sectional schematic diagram of a memory device 400 according to an embodiment of the present disclosure. The first semiconductor structure 310, vertical transistor 311, first insulating structure 320, second insulating structure 330, second electrode structure 360, and capacitor dielectric layer 370 in FIG3 a are similar to the first semiconductor structure 210, vertical transistor 211, first insulating structure 220, second insulating structure 230, second electrode structure 260, and capacitor dielectric layer 270 shown in the above-described embodiment, and are not further described herein. Unlike FIG2 , the contact structure 340 is located in the first insulating layer 321 and is connected to the semiconductor body 311b of the vertical transistor 311. The first electrode structure 350 extends through the second insulating structure 330 and at least a portion of the first insulating structure 320, and the contact surface between the first electrode structure 350 and the contact structure 340 is located in the first insulating layer 321.

[0099] In some embodiments, as shown in FIG. 3 a , a first insulating structure 320 and a second insulating structure 330 are sequentially provided along the thickness direction of the first semiconductor structure 310. The first insulating structure 320 includes a first insulating layer 321 and a first supporting layer 322 spaced apart from each other. The second insulating structure 330 includes a second supporting layer 331 spaced apart from the first insulating structure 320. The first electrode structure 350 penetrates the second insulating structure 330 and a portion of the first insulating structure 320. Here, the first electrode structure 350 penetrates the second insulating structure 330 and includes a first insulating layer 332. The second supporting layer 331, the size of the contact structure 340 is smaller than the size of the first insulating layer 321, and the contact structure 340 is located in the first insulating layer 321, the first end of the contact structure 340 is connected to the semiconductor body 311b, the second end of the contact structure 340 is connected to the first electrode structure 350, and the connection surface between the first electrode structure 350 and the contact structure 340 is located in the first insulating layer 321, the second electrode structure 360 ​​covers part of the first electrode structure 350, and the capacitor dielectric layer 370 is located between the first electrode structure 350 and the second electrode structure 360.

[0100] It should be noted that the first electrode structure 350 penetrates at least a portion of the first insulating structure 320 and the contact surface with the contact structure 340 is located in the first insulating layer 321, which is beneficial to increasing the characteristic size of the first electrode structure 350, thereby increasing the effective facing area between the first electrode structure 350 and the second electrode structure 360, and increasing the capacitance value of the capacitor.

[0101] Figure 3b is a fourth cross-sectional schematic diagram of a memory 500 according to an embodiment of the present disclosure. As shown in Figure 3b, in a direction along the thickness of the first semiconductor structure 310, the second insulating structure 330 further includes a third supporting layer 332 spaced apart from the second supporting layer 331. The first electrode structure 350 penetrates the second insulating structure 330 and a portion of the first insulating structure 320. The first electrode structure 350 penetrating the second insulating structure 330 includes penetrating the third supporting layer 332 and the second supporting layer 331. The size of the contact structure 340 is smaller than that of the first insulating layer 321, and the contact structure 340 is located in the first insulating layer 321. A first end of the contact structure 340 is connected to the semiconductor body 311b, and a second end of the contact structure 340 is connected to the first electrode structure 350. The connection surface between the first electrode structure 350 and the contact structure 340 is located in the first insulating layer 321. The second electrode structure 360 ​​covers a portion of the first electrode structure 350. The capacitor dielectric layer 370 is located between the first electrode structure 350 and the second electrode structure 360. Arranging the first electrode structure to pass through the third supporting layer is beneficial for further increasing the characteristic size of the first electrode structure, thereby further increasing the effective facing area between the first electrode structure and the second electrode structure, and increasing the capacitance value of the capacitor.

[0102] FIG4 is a flow chart of a method for manufacturing a memory according to an embodiment of the present disclosure. Referring to FIG4 , the method includes at least the following steps:

[0103] S401: providing a first semiconductor structure; wherein the first semiconductor structure includes a vertical transistor;

[0104] S402: forming a first insulating structure covering the first semiconductor structure;

[0105] S403: forming a contact structure penetrating the first insulating structure; wherein the contact structure is connected to the semiconductor body of the vertical transistor;

[0106] S404: forming a second insulating structure covering the contact structure and the first insulating structure;

[0107] S405: forming a first electrode structure; wherein the first electrode structure includes a first electrode layer penetrating at least a portion of the first insulating structure and a second electrode layer penetrating the second insulating structure; the first electrode layer covers at least a portion of a sidewall of the contact structure and is connected to the contact structure; and the second electrode layer is connected to the first electrode layer;

[0108] S406: forming a second electrode structure; wherein the second electrode structure includes a first portion located in the first insulating structure and a second portion located in the second insulating structure; the first portion covers a portion of a sidewall of the first electrode layer; and the second portion covers a portion of a sidewall of the second electrode layer;

[0109] S407: forming a capacitor dielectric layer; wherein the capacitor dielectric layer is located between the first electrode structure and the second electrode structure.

[0110] It should be noted that the steps shown in FIG4 are not exclusive, and other steps may be performed before, after or between any steps in the shown operation; the steps shown in FIG4 may be adjusted in order according to actual needs.

[0111] 5a to 5t are schematic diagrams showing a manufacturing process of a memory according to an embodiment of the present disclosure. The manufacturing method of the memory provided by the embodiment of the present disclosure will be described in detail below in conjunction with FIG4 and FIG5a to 5t.

[0112] In step S401 , referring to FIG. 5 a , a first semiconductor structure 410 is provided; wherein the first semiconductor structure 410 includes a vertical transistor (not shown in the figure).

[0113] The specific steps of providing the first semiconductor structure 410 include: providing a substrate; forming a semiconductor body above the substrate along the thickness of the first semiconductor structure 410. Here, the semiconductor body can be formed from the substrate (for example, by etching or epitaxy). Here, the substrate without the semiconductor body can be removed in a subsequent process. Doping the ends of the semiconductor body to form a source and a drain. The source and drain can be doped with P-type dopants (for example, boron or gallium) or N-type dopants (for example, phosphorus or arsenic). Forming a gate (not shown) on at least one side of the semiconductor body. Forming one or more channels (not shown) between the source and drain of the semiconductor body along the thickness of the first semiconductor structure 410. Forming a gate dielectric layer (not shown) between the channel and the gate. The vertical transistor includes the gate and the semiconductor body. Forming shallow trench isolation (not shown) between adjacent vertical transistors. Here, shallow trench isolation between adjacent semiconductor bodies can be formed by photolithography, etching, and thin film deposition.

[0114] In some embodiments, a gate is formed on one side of the semiconductor body, and the vertical transistor is a single-gate transistor; in other embodiments, a gate is formed on at least two sides of the semiconductor body, and the vertical transistor is a multi-gate transistor, and the multi-gate transistor includes a full-ring gate transistor, a triple-gate transistor, or a double-gate transistor. It should be noted that the multi-gate transistor can have a larger gate control area to achieve better channel control with a smaller subthreshold swing.

[0115] The substrate material includes: a single element semiconductor material (such as silicon, germanium), a III-V compound semiconductor material, a II-VI compound semiconductor material, an organic semiconductor material, or other semiconductor materials known in the art. The shallow trench isolation material includes: at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0116] In step S402 , a first insulating structure covering the first semiconductor structure is formed.

[0117] In some embodiments, as shown in FIG. 5 a , the fabrication method further includes forming a first insulating structural material layer 420 ′ covering the first semiconductor structure 410 ; wherein the first insulating structural material layer 420 ′ includes a first insulating material layer 421 ′, a first sacrificial material layer 423 ′, and a first supporting material layer 422 ′ stacked in sequence. For example, a thin film deposition process is used to sequentially form the first insulating material layer 421 ′, the first sacrificial material layer 423 ′, and the first supporting material layer 422 ′ covering the first semiconductor structure 410 .

[0118] Here, the first insulating structure material layer 420' is used to form the first insulating structure 420 in a subsequent process, the first insulating material layer 421' is used to form the first insulating layer 421 in a subsequent process, the first supporting material layer 422' is used to form the first supporting layer 422 in a subsequent process, and the first sacrificial material layer 423' will be removed in a subsequent process to form the second gap 4231. The material of the first sacrificial material layer 423' includes silicon oxide. In the embodiment of the present disclosure, the first sacrificial material layer 423' is described as tetraethyl orthosilicate (TEOS) as an example.

[0119] The material of the first insulating material layer 421 ′ includes insulating materials, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon nitrogen boride, and silicon nitrogen carbide; the material of the first supporting material layer 422 ′ includes at least one of carbonitride, silicon nitride, or carbide.

[0120] In one embodiment, the first insulating material layer 421 ′ includes a composite film layer formed by multiple film layers. In other embodiments, the first insulating material layer 421 ′ includes a single film layer. The present disclosure has no particular limitation on this.

[0121] In a specific embodiment, the formation of the first insulating material layer 421' covering the first semiconductor structure 410 includes: sequentially forming a first sub-insulating material layer 421a' and a second sub-insulating material layer 421b' covering the first semiconductor structure 410; and a first sacrificial material layer 423' covering the second sub-insulating material layer 421b'.

[0122] In steps S403 to S405, as shown in Figures 5c to 5i, a contact structure 440 is formed that penetrates the first insulating structure; wherein the contact structure 440 is connected to the semiconductor body of the vertical transistor; a second insulating structure covering the contact structure 440 and the first insulating structure is formed; a first electrode structure 450 is formed; wherein the first electrode structure 450 includes a first electrode layer 451 that penetrates at least part of the first insulating structure and a second electrode layer 452 that penetrates the second insulating structure; the first electrode layer 451 covers at least part of the side wall of the contact structure 440 and is connected to the contact structure 440; the second electrode layer 452 is connected to the first electrode layer 451.

[0123] In some embodiments, referring to Figure 5b, the above-mentioned manufacturing method also includes: forming a first through hole 481 penetrating the first insulating structural material layer 420'; wherein the bottom of the first through hole 481 exposes the semiconductor body (not shown in the figure), and here, the remaining first insulating material layer 421' constitutes the first insulating layer 421, the remaining first sub-insulating material layer 421a' constitutes the first sub-insulating layer 421a, and the remaining second sub-insulating material layer 421b' constitutes the second sub-insulating layer 421b.

[0124] In some embodiments, referring to Figures 5b to 5f, the above step S403 includes: forming a semiconductor layer 443 in the first through hole 481, and the semiconductor layer 443 is connected to the semiconductor body; wherein, along the thickness direction of the first semiconductor structure 410, the size of the semiconductor layer 443 is smaller than the size of the first insulating material layer 421'; forming a metal layer 441 on the semiconductor layer 443, and the metal layer 441 is connected to the semiconductor layer 443; wherein the contact structure 440 includes the semiconductor layer 443 and the metal layer 441.

[0125] In some embodiments, referring to FIG. 5 e and FIG. 5 f , the step S405 includes: after forming the semiconductor layer 443 , forming a first sub-through hole 481 a based on the morphology of the first through hole 481 , wherein the bottom of the first sub-through hole 481 a exposes the semiconductor layer 443 ;

[0126] forming a first electrode layer 451 covering the sidewall and bottom of the first sub-through hole 481 a;

[0127] The forming of the metal layer 441 on the semiconductor layer 443 includes forming the metal layer 441 in the first sub-through hole 481 a where the first electrode layer 451 is formed.

[0128] In some embodiments, referring to Figures 5c and 5d, a semiconductor material layer 443a is deposited in the first through hole 481, and the bottom of the semiconductor material layer 443a is connected to the semiconductor body. The semiconductor material layer 443a is etched along the thickness direction of the first semiconductor structure 410 until the size of the semiconductor material layer 443a is smaller than the size of the first insulating material layer 421'. The retained semiconductor material layer 443a constitutes the semiconductor layer 443. In a specific embodiment, referring to Figure 5d, along the thickness direction of the first semiconductor structure 410, the size of the semiconductor layer 443 is smaller than the size of the first sub-insulating material layer 421a'. Here, the material of the semiconductor material layer 443a includes polycrystalline silicon or doped polycrystalline silicon.

[0129] In some embodiments, as shown in FIG. 5e , step S403 further includes: after forming the semiconductor layer 443, forming a connection layer 442 on the semiconductor layer 443, wherein the sum of the dimensions of the connection layer 442 and the semiconductor layer 443 along the thickness of the first semiconductor structure 410 is smaller than the dimension of the first insulating material layer 421′. The material of the connection layer 442 includes a metal silicide, such as cobalt silicide or titanium silicide. The connection layer 442 is used to reduce the contact resistance between the semiconductor layer 443 and the metal layer 441, thereby improving the electrical performance of the memory device.

[0130] 5e and 5f, after the semiconductor layer 443 and the connection layer 442 are formed, the remaining portion of the first through hole 481 constitutes a first sub-through hole 481a, forming a first electrode layer 451 covering the sidewalls and bottom of the first sub-through hole 481a. The bottom of the first electrode layer 451 is located in the first insulating material layer 421'. After the first electrode layer 451 is formed, a metal conductive material is deposited into the first sub-through hole 481a to form a metal layer 441. The first end of the metal layer 441 is located in the first insulating material layer 421'. In the figure, the second end of the metal layer 441 is exposed from the surface of the first supporting material layer 422' away from the first insulating material layer 421'. In a specific embodiment, the orthographic projection of the metal layer 441 is circular or elliptical. In the direction along the thickness of the first semiconductor structure 410, the size of the metal layer 441 is larger than the sum of the sizes of the first supporting material layer 422' and the first sacrificial material layer 423', and smaller than the size of the first insulating structure material layer 420'. The first electrode layer 451 covers the sidewalls and bottom of the metal layer 441.

[0131] Here, the material of the first electrode layer 451 includes a conductive material, for example, at least one of a semiconductor material (for example, polysilicon, doped polysilicon, etc.), a metal (for example, tungsten, titanium, etc.), a metal nitride (for example, tungsten nitride, titanium nitride, tantalum nitride, etc.) and a metal silicide (for example, titanium silicide, nickel silicide, titanium silicon nitride, etc.). The embodiment of the present disclosure is described using the example of the material of the first electrode layer 451 being titanium nitride.

[0132] In some embodiments, referring to FIG. 5g , the manufacturing method further includes forming a second insulating structural material layer 430 ′ covering the first insulating structural material layer 420 ′, the first electrode layer 451 and the contact structure 440 ; wherein the second insulating structural material layer 430 ′ includes a second sacrificial material layer 431 b ′ and a second supporting material layer 431 a ′ stacked in sequence.

[0133] In some embodiments, as shown in FIG. 5g , forming the second insulating structural material layer 430′ includes sequentially forming a second sacrificial material layer 431b′ and a second supporting material layer 431a′ on the first insulating structural material layer 420′. The second insulating structural material layer 430′ is used to form the second insulating structure 430 in a subsequent process, the second supporting material layer 431a′ is used to form the second supporting layer 431 in a subsequent process, and the second sacrificial material layer 431b′ will be removed in a subsequent process to form the first gap 4312.

[0134] The material of the second support material layer 431a' includes at least one of carbonitride, nitride or carbide. The materials of the second support material layer 431a' and the first support material layer 422' can be the same or different. This disclosure does not specifically limit this, and those skilled in the art can make a selection according to actual needs.

[0135] In some embodiments, as shown in FIG. 5 h , the manufacturing method further includes: forming a second through hole 482 penetrating the second insulating structural material layer 430 ′; wherein the bottom of the second through hole 482 exposes the first electrode layer 451 and the contact structure 440 .

[0136] In some embodiments, as shown in FIG. 5i , the step S405 further includes: forming a second electrode layer 452 covering at least the sidewall of the second through hole 482 , and forming a second sub-through hole (not shown) based on the morphology of the second through hole 482 ;

[0137] In some embodiments, still referring to FIG. 5 i , the above manufacturing method further includes: filling the second sub-through hole to form an electrode contact layer 4820 .

[0138] In some embodiments, forming at least the second electrode layer 452 covering the sidewalls of the second through hole 482 includes: forming the second electrode layer 452 covering the sidewalls and the bottom of the second through hole 482 .

[0139] In other embodiments, the above-mentioned formation of at least the second electrode layer 452 covering the side walls of the second through hole 482 includes: forming a second electrode material layer covering the side walls and bottom of the second through hole 482, etching and removing the second electrode material layer covering the bottom of the second through hole 482, and the retained second electrode material layer constituting the second electrode layer 452, and the second electrode layer 452 covering the side walls of the second through hole 482.

[0140] Here, the second electrode layer 452 can be formed by atomic layer deposition process or plasma vapor process, the first end of the second electrode layer 452 is connected to the first electrode layer 451 and the contact structure 440, and the second end of the second electrode layer 452 is exposed from the surface of the second supporting material layer 431a' away from the second sacrificial material layer 431b'.

[0141] The material of the second electrode layer 452 includes a conductive material, for example, at least one of a semiconductor material (for example, polysilicon, doped polysilicon, etc.), a metal (for example, tungsten, titanium, etc.), a metal nitride (for example, tungsten nitride, titanium nitride, tantalum nitride, etc.) and a metal silicide (for example, titanium silicide, nickel silicide, titanium silicon nitride, etc.). The materials of the first electrode layer 451 and the second electrode layer 452 may be the same or different. The embodiment of the present disclosure is described using the example of the material of the second electrode layer 452 being titanium nitride.

[0142] After the second electrode layer 452 is formed, the remaining part of the second through hole 482 constitutes a second sub-through hole, and the electrode contact material is filled in the second sub-through hole to form the electrode contact layer 4820. The second electrode layer 452 covers the side walls and bottom of the electrode contact layer 4820. In other embodiments, the second electrode layer 452 covers the side walls of the electrode contact layer 4820. The embodiments of the present disclosure have no special restrictions on this. Those skilled in the art can make a choice according to actual needs. The material of the electrode contact layer 4820 includes polysilicon or doped polysilicon.

[0143] In some embodiments, as shown in Figures 5i to 51, the memory device includes multiple first electrode structures 450. The above-mentioned manufacturing method further includes: forming a third through hole 483 that penetrates the second insulating material layer 430', the first supporting material layer 422', and the first sacrificial material layer 423'; wherein the third through hole 483 is located between two adjacent first electrode structures 450; the sidewalls of the third through hole 483 expose a portion of the first electrode layer 451 and a portion of the second electrode layer 452, and the bottom of the third through hole 483 exposes the first insulating material layer 421'. Here, along the thickness direction of the first semiconductor structure 410, the first insulating material layer 420' and the second insulating material layer 430' are sequentially disposed between two adjacent first electrode structures 450, and the third through hole 483 penetrates the second insulating material layer 430', including the second supporting material layer 431a' and the second sacrificial material layer 431b'.

[0144] In some embodiments, as shown in FIG. 5i to FIG. 5l , forming a third through hole 483 penetrating the second insulating structure 430 ′, the first support material layer 422 ′ and the first sacrificial material layer 423 ′ includes:

[0145] The second support material layer 431a' is etched downward according to the mask pattern to form a first opening 4311; wherein the bottom of the first opening 4311 reveals the second sacrificial material layer 431b'; wherein the remaining second support material layer 431a' constitutes the second support layer 431;

[0146] The second sacrificial material layer 431b' is removed along the first opening 4311 to form a first gap 4312; wherein the sidewall of the first gap 4312 partially exposes the second electrode layer 452, and the bottom of the first gap 4312 exposes the first supporting material layer 422'; the second insulating structure 430 includes a second supporting layer 431;

[0147] The first support material layer 422' is etched downward according to the mask pattern to form a second opening 4221; wherein the bottom of the second opening 4221 reveals the first sacrificial material layer 423'; wherein the remaining first support material layer 422' constitutes the first support layer 422;

[0148] The first sacrificial material layer 423' is removed according to the second opening 4221 to form a second gap 4231; wherein, the sidewall of the second gap 4231 exposes part of the first electrode layer 451, and the bottom of the second gap 4231 exposes the first insulating material layer 421'; the remaining first insulating material layer 421' constitutes the first insulating layer 421, and the first insulating structure includes the first insulating layer 421 and the first supporting layer 422.

[0149] A mask structure is formed covering the second support material layer 431a'. The mask structure can be a single film layer or a composite film layer. The mask structure includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, or spin-on carbon. A mask pattern can be formed in the mask structure through a self-alignment process, and the second support material layer 431a' is etched downward according to the mask pattern to form a first opening 4311. The first opening 4311 reveals the second sacrificial material layer 431b'. The second sacrificial material layer 431b' can be subsequently removed through the first opening 4311. Here, the retained second support material layer 431a' constitutes the second support layer 431, as shown in Figure 5j.

[0150] The second sacrificial material layer 431b' is removed by wet etching to expose the first support material layer 422', thereby forming a first gap 4312. The first gap 4312 exposes the sidewall of the second electrode layer 452 between the second support layer 431 and the first support material layer 422', as shown in FIG5j.

[0151] After removing the second sacrificial material layer 431b', the exposed first support material layer 422' is further etched downward according to the mask pattern to form a second opening 4221. The second opening 4221 exposes the first sacrificial material layer 423', which can then be removed through the second opening 4221. Here, the remaining first support material layer 422' constitutes the first support layer 422, as shown in FIG5k.

[0152] The first sacrificial material layer 423' is removed by wet etching to expose the first insulating material layer 421', thereby forming a second gap 4231. The second gap 4231 exposes the side wall of the first electrode layer 451 between the first supporting layer 422 and the first insulating material layer 421'. The retained first insulating material layer 421' constitutes the first insulating layer 421, as shown in Figure 5l.

[0153] In some embodiments, the etch selectivity of the second sacrificial material layer is less than or equal to the etch selectivity of the first sacrificial material layer. Here, the materials of the first sacrificial material layer and the second sacrificial material layer include silicon oxide. In the embodiments of the present disclosure, the first sacrificial material layer and the second sacrificial material layer are described as tetraethyl orthosilicate (TEOS).

[0154] In some embodiments, the concentration of phosphorus and boron doped in the first sacrificial material layer is greater than the concentration of phosphorus and boron doped in the second sacrificial material layer, so that when the first sacrificial material layer and the second sacrificial material layer are etched, the closer to the first semiconductor structure, the greater the etching rate, which is beneficial to regulating the verticality of the side walls of the first gap and the second gap; in other embodiments, the concentration of phosphorus and boron doped in the first sacrificial material layer is equal to the concentration of phosphorus and boron doped in the second sacrificial material layer, so that when the first sacrificial material layer and the second sacrificial material layer are etched, they have the same etching rate.

[0155] In step S407 , as shown in FIG. 5 m , a capacitor dielectric layer 470 is formed; wherein the capacitor dielectric layer 470 is located between the first electrode structure 450 and the second electrode structure 460 .

[0156] In some embodiments, still referring to FIG. 5 m , step S407 includes: forming a first sub-capacitor dielectric layer 471 covering the exposed first electrode layer 451 ; forming a second sub-capacitor dielectric layer 472 covering the exposed second electrode layer 452 ; wherein the capacitor dielectric layer 470 includes the first sub-capacitor dielectric layer 471 and the second sub-capacitor dielectric layer 472 ;

[0157] In some embodiments, the formation of the first sub-capacitor dielectric layer 471 covering the exposed first electrode layer 451 includes: forming the first sub-capacitor dielectric layer 471 in the second gap 4231; the formation of the second sub-capacitor dielectric layer 472 covering the exposed second electrode layer 452 includes: forming the second sub-capacitor dielectric layer 472 in the first gap 4312.

[0158] In some embodiments, as shown in Figure 5m, a capacitor dielectric material is deposited in the first gap 4312 to form a second sub-capacitor dielectric layer 472, and a capacitor dielectric material is deposited in the second gap 4231 to form a first sub-capacitor dielectric layer 471. Here, the capacitor dielectric material includes at least one of a low dielectric constant material (for example, silicon oxide, etc.) and a high dielectric constant material (for example, aluminum oxide, etc.).

[0159] In some embodiments, the first gap 4312 and the second gap 4231 are connected, forming a first sub-capacitor dielectric layer 471 and a second sub-capacitor dielectric layer 472 connected. In other embodiments, the first gap 4312 and the second gap 4231 are not connected, forming a first sub-capacitor dielectric layer 471 and a second sub-capacitor dielectric layer 472 separated by a first supporting layer. Here, the first sub-capacitor dielectric layer 471 and the second sub-capacitor dielectric layer 472 can be formed in the same process or in separate processes. This is not particularly limited in this disclosure, and those skilled in the art can select the appropriate method based on actual needs.

[0160] In step S406, as shown in Figure 5m, a second electrode structure 460 is formed; wherein the second electrode structure 460 includes a first portion 461 located in the first insulating structure 420 and a second portion 462 located in the second insulating structure 430; the first portion 461 covers a portion of the side wall of the first electrode layer 451; and the second portion 462 covers a portion of the side wall of the second electrode layer 452.

[0161] In some embodiments, as shown in FIG. 5 m , step S406 includes: forming a first portion 461 covering the first sub-capacitor dielectric layer 471 ; and forming a second portion 462 covering the second sub-capacitor dielectric layer 472 .

[0162] In some embodiments, the forming of the first portion 461 covering the first sub-capacitor dielectric layer 471 includes forming the first portion 461 in the second gap 4231 in which the first sub-capacitor dielectric layer 471 is formed; and the forming of the second portion 462 covering the second sub-capacitor dielectric layer 472 includes forming the second portion 462 in the first gap 4312 in which the second sub-capacitor dielectric layer 472 is formed.

[0163] In some embodiments, still referring to Figure 5m, conductive materials are deposited on the first sub-capacitor dielectric layer 471 and the second sub-capacitor dielectric layer 472, respectively, to form a first part 461 and a second part 462. The conductive materials include: at least one of semiconductor materials (for example, polysilicon, doped polysilicon, etc.), metals (for example, tungsten, titanium, etc.), metal nitrides (for example, tungsten nitride, titanium nitride, tantalum nitride, etc.) and metal silicides (for example, titanium silicide, nickel silicide, titanium silicon nitride, etc.). The embodiment of the present disclosure is described using the material of the second electrode structure 460 being titanium nitride as an example.

[0164] In some embodiments, the above-mentioned manufacturing method also includes: forming a first filling layer 461a on the side of the first part 461 away from the first sub-capacitor dielectric layer 471, and forming a second filling layer 462a on the side of the second part 462 away from the second sub-capacitor dielectric layer 472. The materials of the first filling layer 461a and the second filling layer 462a include polycrystalline silicon or silicon germanium. The materials of the first filling layer 461a and the second filling layer 462a can be the same or different, and the present disclosure has no special restrictions on this.

[0165] In some embodiments, as shown in FIG. 5 n to FIG. 5 s , the second insulating structural material layer 430 ′ further includes a third sacrificial material layer 432 b ′ and a third supporting material layer 432 a ′ stacked sequentially; wherein the third sacrificial material layer 432 b ′ is located between the second supporting material layer 431 a ′ and the third supporting material layer 432 a ′;

[0166] The third through hole 483 formed through the second insulating structural material layer 430 ′, the first supporting material layer 422 ′ and the first sacrificial material layer 423 ′ includes:

[0167] The third support material layer 432a' is etched downward according to the mask pattern to form a third opening 4321; wherein the bottom of the third opening 4321 exposes the third sacrificial material layer 423b'; wherein the remaining third support material layer 432a' constitutes the third support layer 432;

[0168] The third sacrificial material layer 432b′ is removed according to the third opening 4321 to form a third gap 4322 ; wherein the sidewall of the third gap 4322 partially exposes the second electrode layer 452 , and the bottom of the third gap 4322 exposes the second supporting material layer 431a ′; the second insulating structure 430 also includes a third supporting layer 432 .

[0169] 5n , forming the second insulating structural material layer 430′ further includes, after forming the second supporting material layer 431a′, sequentially forming a third sacrificial material layer 432b′ and a third supporting material layer 432a′ on the second supporting material layer 431a′. Here, the method of forming the third sacrificial material layer 432b′ and the third supporting material layer 432a′ is similar to the method of forming the second sacrificial material layer 431b′ and the second supporting material layer 431a′ in the above-mentioned FIG. 5g , and is not repeated here.

[0170] In some embodiments, the above-mentioned etching of the second insulating structure material layer 430' to form the second through hole 482 also includes: etching downward the third support material layer 432a', the third sacrificial material layer 432b', the second support material layer 431a' and the second sacrificial material layer 431b' according to the mask pattern until the first electrode layer 451 and the contact structure 440 are exposed, as shown in Figure 5o.

[0171] The second electrode layer 452 is formed by atomic layer deposition or plasma vapor deposition. The first end of the second electrode layer 452 is connected to the first electrode layer 451 and the contact structure 440. The second end of the second electrode layer 452 is exposed from the surface of the third supporting material layer 432a' away from the third sacrificial material layer 432b', as shown in Figure 5p.

[0172] After the second electrode layer 452 is formed, the remaining part of the second through hole 482 constitutes a second sub-through hole, and the electrode contact material is filled in the second sub-through hole to form the electrode contact layer 4820. The second electrode layer 452 covers the side walls and bottom of the electrode contact layer 4820. In other embodiments, the second electrode layer 452 covers the side walls of the electrode contact layer 4280. The embodiments of the present disclosure have no special restrictions on this. Those skilled in the art can make a choice according to actual needs. The material of the electrode contact layer 4820 includes polysilicon or doped polysilicon.

[0173] The third supporting material layer 432a' is etched downward according to the mask pattern to form a third opening 4321. The third opening 4321 exposes the third sacrificial material layer 432b', which can subsequently be removed through the third opening 4321. Here, the remaining third supporting material layer 432a' constitutes the third supporting layer 432. The second insulating structure 430 includes the second supporting layer 431 and the third supporting layer 432, as shown in FIG5q.

[0174] The third sacrificial material layer 432b' is removed by wet etching to expose the second support material layer 431a', thereby forming a third gap 4322. The third gap 4322 exposes the sidewall of the second electrode layer 452 between the third support layer 432 and the second support material layer 431a', as shown in Figures 5p and 5q.

[0175] In Figures 5q to 5s, the method of forming the first opening 4311, the first gap 4312, the second opening 4221 and the second gap 4231 is similar to the method of forming the first opening 4311, the first gap 4312, the second opening 4221 and the second gap 4231 in Figures 5j to 5i, and will not be repeated here.

[0176] In some embodiments, the etch selectivity of the second sacrificial material layer is greater than the etch selectivity of the third sacrificial material layer. This facilitates controlling the perpendicularity between the third gap and the first gap. The third sacrificial material layer comprises silicon oxide. In the disclosed embodiments, the third sacrificial material layer is borophosphosilicate glass (BPSG) and the second sacrificial material layer is tetraethyl orthosilicate (TEOS).

[0177] In some embodiments, referring to Figures 5s and 5t, the above-mentioned formation of the second sub-capacitor dielectric layer 472 covering the exposed second electrode layer 452 further includes: forming the second sub-capacitor dielectric layer 472 in the third gap 4322; and the above-mentioned formation of the second portion 462 covering the second sub-capacitor dielectric layer 472 includes: forming the second portion 462 in the third gap 4322 in which the second sub-capacitor dielectric layer 472 is formed.

[0178] A capacitor dielectric material is deposited in the third gap 4322 to form a second sub-capacitor dielectric layer 472 , and a conductive material is deposited on the other side of the second sub-capacitor dielectric layer 472 to form a second portion 462 .

[0179] In some embodiments, the second gap 4231, the first gap 4312, and the third gap 4322 are connected, and the formed first sub-capacitor dielectric layer 471 and the second sub-capacitor dielectric layer 472 are connected, and the first part covering the first sub-capacitor dielectric layer 471 and the second part covering the second sub-capacitor dielectric layer 472 are connected; in other embodiments, the second gap 4231, the first gap 4312, and the third gap 4322 are not connected, and the first sub-capacitor dielectric layer 471 located in the second gap 4231 and the second sub-capacitor dielectric layer 472 located in the first gap 4312 are separated by the first supporting layer 422, and the second sub-capacitor dielectric layer 472 located in the first gap 4312 and the second sub-capacitor dielectric layer 472 located in the third gap 4322 are separated by the second supporting layer 431.

[0180] Figures 6a to 6e are schematic diagrams 2 of a manufacturing process of a memory according to an embodiment of the present disclosure. The manufacturing method of the memory provided by the embodiment of the present disclosure will be described in detail below in conjunction with Figures 5j to 5s and Figures 6a to 6e.

[0181] As shown in FIG6a , the specific steps of providing a first semiconductor structure 410 include providing a substrate, forming a semiconductor body over the substrate along the thickness of the first semiconductor structure 410. Here, the semiconductor body can be formed from the substrate (for example, by etching or epitaxy), and the substrate without the semiconductor body can be removed in a subsequent process. Doping is performed on both ends of the semiconductor body to form a source and a drain. The source and drain can be doped with a P-type dopant (for example, boron or gallium) or an N-type dopant (for example, phosphorus or arsenic). A gate (not shown) is formed on at least one side of the semiconductor body. One or more channels (not shown) are formed between the source and drain of the semiconductor body along the thickness of the first semiconductor structure 410. A gate dielectric layer (not shown) is formed between the channel and the gate. A vertical transistor includes a gate and a semiconductor body. Shallow trench isolation (not shown) is formed between adjacent vertical transistors. Shallow trench isolation between adjacent semiconductor bodies can be formed by photolithography, etching, and thin film deposition.

[0182] In some embodiments, a gate is formed on one side of the semiconductor body, and the vertical transistor is a single-gate transistor; in other embodiments, a gate is formed on at least two sides of the semiconductor body, and the vertical transistor is a multi-gate transistor, and the multi-gate transistor includes a full-ring gate transistor, a triple-gate transistor, or a double-gate transistor. It should be noted that the multi-gate transistor can have a larger gate control area to achieve better channel control with a smaller subthreshold swing.

[0183] The substrate material includes: a single element semiconductor material (such as silicon, germanium), a III-V compound semiconductor material, a II-VI compound semiconductor material, an organic semiconductor material, or other semiconductor materials known in the art. The shallow trench isolation material includes: at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0184] In some embodiments, still referring to Figure 6a, a first insulating material layer 421', a first sacrificial material layer 423' and a first supporting material layer 422' covering the semiconductor structure 410 are sequentially formed on the first semiconductor structure 410, and the first insulating material layer 421', the first sacrificial material layer 423' and the first supporting material layer 422' constitute a first insulating structural material layer 420'.

[0185] Here, the first insulating structure material layer 420' is used to form the first insulating structure 420 in a subsequent process, the first insulating material layer 421' is used to form the first insulating layer 421 in a subsequent process, the first supporting material layer 422' is used to form the first supporting layer 422 in a subsequent process, and the first sacrificial material layer 423' will be removed in a subsequent process to form the second gap 4231. The material of the first sacrificial material layer 423' includes silicon oxide. In the embodiment of the present disclosure, the first sacrificial material layer 423' is described as tetraethyl orthosilicate (TEOS) as an example.

[0186] The material of the first insulating material layer 421 ′ includes insulating materials, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon nitrogen boride, and silicon nitrogen carbide; the material of the first supporting material layer 422 ′ includes at least one of carbonitride, silicon nitride, or carbide.

[0187] In a specific embodiment, as shown in FIG. 6 a , the first insulating material layer 421 ′ includes a single film layer. In this embodiment, the first insulating material layer 421 ′ is silicon boron nitride as an example for description.

[0188] In some embodiments, the first insulating structural material layer 420' is etched to form a first through hole, the bottom of which exposes the semiconductor body (not shown). For details about the first through hole, refer to the first through hole 481 in FIG. 5b.

[0189] In some embodiments, as shown in FIG. 6 a , step S405 includes: forming a first electrode layer 451 covering the sidewall of the first through-hole, and forming a first sub-through-hole 481 b based on the morphology of the first through-hole; wherein the bottom of the first sub-through-hole 481 b exposes the semiconductor body (not shown in the figure);

[0190] In some embodiments, in combination with Figures 6a and 6b, the above step S403 includes: forming a semiconductor layer 443 in the first sub-through hole 481b, and the semiconductor layer 443 is connected to the semiconductor body; wherein, along the thickness direction of the first semiconductor structure 410, the size of the semiconductor layer 443 is larger than the size of the first insulating material layer 421' and smaller than the sum of the sizes of the first insulating material layer 421' and the first sacrificial material layer 423'; forming a metal layer 441 on the semiconductor layer 443, and the metal layer 441 is connected to the semiconductor layer 443; wherein the contact structure 440 includes the semiconductor layer 443 and the metal layer 441.

[0191] In some embodiments, referring to FIG6a , a first electrode material layer (not shown in the figure) is formed covering the sidewalls and bottom of the first through hole; the first electrode material layer at the bottom of the first through hole is etched away, and the retained first electrode material layer constitutes the first electrode layer 451; after the first electrode layer 451 is formed, the remaining portion of the first through hole constitutes the first sub-through hole 481b.

[0192] In some embodiments, referring to Figure 6a, a semiconductor material layer (not shown in the figure) is deposited in the first sub-through hole 481b, the bottom of the semiconductor material layer is connected to the semiconductor body, the first electrode layer 451 covers the sidewall of the semiconductor material layer, and the semiconductor material layer is etched along the thickness direction of the first semiconductor structure 410 to form a semiconductor layer 443. Here, along the thickness direction of the first semiconductor structure 410, the size of the semiconductor layer 443 is larger than the size of the first insulating material layer 421' and smaller than the sum of the sizes of the first insulating material layer 421' and the first sacrificial material layer 423'. The material of the semiconductor material layer includes polycrystalline silicon or doped polycrystalline silicon.

[0193] 6 b , a metal conductive material is deposited on the semiconductor layer 443 to form a metal layer 441. The first electrode layer 451 covers the sidewalls of the metal layer 441. The first end of the metal layer 441 is located in the first sacrificial material layer 423 ', and the second end of the metal layer 441 is exposed from the surface of the first supporting material layer 422 ' away from the first insulating material layer 421 '. In a specific embodiment, the orthographic projection of the formed metal layer 441 is circular or elliptical. In the direction along the thickness of the first semiconductor structure 410, the size of the metal layer 441 is larger than the size of the first supporting material layer 422 ' and smaller than the sum of the sizes of the first supporting material layer 422 ' and the first sacrificial material layer 423 '.

[0194] In some embodiments, still referring to FIG. 6 b , the fabrication method further includes forming a connection layer 442 on the semiconductor layer 443 before forming the metal layer 441. Along the thickness of the first semiconductor structure 410, the sum of the dimensions of the connection layer 442 and the semiconductor layer 443 is greater than the dimension of the first insulating material layer 421′ and smaller than the sum of the dimensions of the first insulating material layer 421′ and the first sacrificial material layer 423′. The connection layer 442 is made of a metal silicide, such as cobalt silicide or titanium silicide. The connection layer 442 is used to reduce the contact resistance between the semiconductor layer 443 and the metal layer 441, thereby improving the electrical performance of the memory device. In one specific embodiment, the semiconductor layer 443, the connection layer 442, and the metal layer 441 form a contact structure 440. A first electrode layer 451 covers the sidewalls of the contact structure 440, and the bottom of the first electrode layer 451 is connected to the first semiconductor structure 410.

[0195] In some embodiments, as shown in FIG. 6 c , a second insulating material layer 430 ′ is formed to cover the first insulating material layer 420 ′, the first electrode layer 451, and the contact structure 440. This includes sequentially forming a second sacrificial material layer 431 b ′ and a second supporting material layer 431 a ′ on the first insulating material layer 420 ′. The second insulating material layer 430 ′ is used to form the second insulating structure 430 in a subsequent process, the second supporting material layer 431 a ′ is used to form the second supporting layer 431 in a subsequent process, and the second sacrificial material layer 431 b ′ is removed in a subsequent process to form the first gap 4312.

[0196] The material of the second support material layer 431a' includes at least one of carbonitride, nitride or carbide. The materials of the second support material layer 431a' and the first support material layer 422' can be the same or different. This disclosure does not specifically limit this, and those skilled in the art can make a selection according to actual needs.

[0197] In some embodiments, as shown in Figure 6c, the second insulating structural material layer 430' is etched to form a second through hole, the second through hole penetrates the second insulating structural material layer 430', and the bottom of the second through hole exposes the first electrode layer 451 and the contact structure 440. For the second through hole, refer to the second through hole 482 in Figure 5h.

[0198] In some embodiments, referring to Figure 6c, after the second through hole is formed, a second electrode material layer (not shown in the figure) covering the side walls and bottom of the second through hole is formed in the second through hole, and the second electrode material layer covering the bottom of the second through hole is etched away. The retained second electrode material layer constitutes the second electrode layer 452, and the second electrode layer 452 covers the side walls of the second through hole.

[0199] Here, the second electrode layer 452 can be formed by atomic layer deposition or plasma vapor deposition. The first end of the second electrode layer 452 is connected to the first electrode layer 451 , and the second end of the second electrode layer 452 is exposed from the surface of the second supporting material layer 431 a ′ away from the second sacrificial material layer 431 b ′.

[0200] After the second electrode layer 452 is formed, the remaining part of the second through hole constitutes a second sub-through hole, the contact structure 440 is exposed at the bottom of the second sub-through hole, and the electrode contact material is filled in the second sub-through hole to form an electrode contact layer 4820. The electrode contact layer 4820 is connected to the contact structure 440, and the second electrode layer 452 covers the side wall of the electrode contact layer 4820. The material of the electrode contact layer 4820 includes polysilicon or doped polysilicon.

[0201] The material of the second electrode layer 452 includes a conductive material, for example, at least one of a semiconductor material (for example, polysilicon, doped polysilicon, etc.), a metal (for example, tungsten, titanium, etc.), a metal nitride (for example, tungsten nitride, titanium nitride, tantalum nitride, etc.) and a metal silicide (for example, titanium silicide, nickel silicide, titanium silicon nitride, etc.). The materials of the first electrode layer 451 and the second electrode layer 452 may be the same or different. The embodiment of the present disclosure is described using the example of the material of the second electrode layer 452 being titanium nitride.

[0202] In some embodiments, as shown in conjunction with FIG. 51 and FIG. 6c , the memory device includes a plurality of first electrode structures 450, forming a third through-hole 483 that penetrates the second insulating material layer 430', the first supporting material layer 422', and the first sacrificial material layer 423'. The third through-hole 483 is located between two adjacent first electrode structures 450. The sidewalls of the third through-hole 483 expose a portion of the first electrode layer 451 and the second electrode layer 452, and the bottom of the third through-hole 483 exposes the first insulating material layer 421'. Here, along the thickness direction of the first semiconductor structure 410, the first insulating material layer 420' and the second insulating material layer 430' are sequentially disposed between two adjacent first electrode structures 450. The third through-hole 483 penetrates the second insulating material layer 430', including the second supporting material layer 431a' and the second sacrificial material layer 431b'.

[0203] A mask structure (not shown) is formed to cover the second support material layer 431a'. The mask structure can be a single film layer or a composite film layer. The mask structure includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, or spin-on carbon. A mask pattern can be formed in the mask structure through a self-alignment process, and the second support material layer 431a' is etched downward according to the mask pattern to form a first opening 4311. The first opening 4311 reveals the second sacrificial material layer 431b', and the second sacrificial material layer 431b' can be subsequently removed through the first opening 4311. Here, the retained second support material layer 431a' constitutes the second support layer 431.

[0204] The second sacrificial material layer 431b' is removed by wet etching to expose the first supporting material layer 422', thereby forming a first gap 4312. The first gap 4312 exposes the sidewall of the second electrode layer 452 between the second supporting layer 431 and the first supporting material layer 422', and the bottom of the first gap 4312 exposes the first supporting material layer 422', as shown in Figure 5j.

[0205] After removing the second sacrificial material layer 431b', the exposed first support material layer 422' is further etched downward according to the mask pattern to form a second opening 4221. The second opening 4221 exposes the first sacrificial material layer 423', which can then be removed through the second opening 4221. Here, the remaining first support material layer 422' constitutes the first support layer 422, as shown in FIG5k.

[0206] The first sacrificial material layer 423' is removed by wet etching to expose the first insulating material layer 421', thereby forming a second gap 4231. The second gap 4231 exposes the side wall of the first electrode layer 451 between the first supporting layer 422 and the first insulating material layer 421'. The retained first insulating material layer 421' constitutes the first insulating layer 421, as shown in Figure 5l.

[0207] In some embodiments, the etch selectivity of the second sacrificial material layer is less than or equal to the etch selectivity of the first sacrificial material layer. Here, the materials of the first sacrificial material layer and the second sacrificial material layer include silicon oxide. In the embodiments of the present disclosure, the first sacrificial material layer and the second sacrificial material layer are described as tetraethyl orthosilicate (TEOS).

[0208] In some embodiments, the concentration of phosphorus and boron doped in the first sacrificial material layer is greater than the concentration of phosphorus and boron doped in the second sacrificial material layer, so that when the first sacrificial material layer and the second sacrificial material layer are etched, the closer to the first semiconductor structure, the greater the etching rate, which is beneficial to regulating the verticality of the side walls of the first gap and the second gap; in other embodiments, the concentration of phosphorus and boron doped in the first sacrificial material layer is equal to the concentration of phosphorus and boron doped in the second sacrificial material layer, so that when the first sacrificial material layer and the second sacrificial material layer are etched, they have the same etching rate.

[0209] In some embodiments, as shown in conjunction with FIG. 51 and FIG. 6 d , a capacitor dielectric layer 470 is formed, and the capacitor dielectric layer 470 is located between the first electrode structure 450 and the second electrode structure 460. Forming the capacitor dielectric layer 470 includes depositing a capacitor dielectric material in the first gap 4312 to form a second sub-capacitor dielectric layer 472, and depositing a capacitor dielectric material in the second gap 4231 to form a first sub-capacitor dielectric layer 471. The first sub-capacitor dielectric layer 471 covers the exposed first electrode layer 451, and the second sub-capacitor dielectric layer covers the exposed second electrode layer 452. Here, the capacitor dielectric material includes at least one of a low-k dielectric constant material (e.g., silicon oxide) and a high-k dielectric constant material (e.g., aluminum oxide).

[0210] In some embodiments, the first gap 4312 and the second gap 4231 are connected, forming a first sub-capacitor dielectric layer 471 and a second sub-capacitor dielectric layer 472 connected. In other embodiments, the first gap 4312 and the second gap 4231 are not connected, forming a first sub-capacitor dielectric layer 471 and a second sub-capacitor dielectric layer 472 separated by a first supporting layer. Here, the first sub-capacitor dielectric layer 471 and the second sub-capacitor dielectric layer 472 can be formed in the same process or in separate processes. This is not particularly limited in this disclosure, and those skilled in the art can make their own choices based on actual needs.

[0211] In some embodiments, as shown in Figure 6d, a second electrode structure 460 is formed; wherein the second electrode structure 460 includes a first portion 461 located in the first insulating structure 420 and a second portion 462 located in the second insulating structure 430; the first portion 461 covers a portion of the side wall of the first electrode layer 451; and the second portion 462 covers a portion of the side wall of the second electrode layer 452.

[0212] In some embodiments, still referring to Figure 6d, conductive materials are deposited on the first sub-capacitor dielectric layer 471 and the second sub-capacitor dielectric layer 472, respectively, to form a first part 461 and a second part 462. The conductive materials include: at least one of semiconductor materials (for example, polysilicon, doped polysilicon, etc.), metals (for example, tungsten, titanium, etc.), metal nitrides (for example, tungsten nitride, titanium nitride, tantalum nitride, etc.) and metal silicides (for example, titanium silicide, nickel silicide, titanium silicon nitride, etc.). The embodiment of the present disclosure is described by taking the material of the second electrode structure 460 as titanium nitride as an example.

[0213] A first filling layer 461a is formed on a side of the first portion 461 away from the first sub-capacitor dielectric layer 471, and a second filling layer 462a is formed on a side of the second portion 462 away from the second sub-capacitor dielectric layer 472. The materials of the first filling layer 461a and the second filling layer 462a include polysilicon or silicon germanium. The materials of the first filling layer 461a and the second filling layer 462a can be the same or different, and the present disclosure has no special restrictions on this.

[0214] In some embodiments, forming the second insulating structural material layer 430' further includes, after forming the second supporting material layer 431a', sequentially forming a third sacrificial material layer 432b' and a third supporting material layer 432a' on the second supporting material layer 431a', wherein the third sacrificial material layer 432b' is located between the second supporting material layer 431a' and the third supporting material layer 432a'.

[0215] In some embodiments, etching the second insulating structure material layer 430' to form the second through hole 482 further includes: etching downward the third support material layer 432a', the third sacrificial material layer 432b', the second support material layer 431a' and the second sacrificial material layer 431b' according to the mask pattern until the first electrode layer 451 and the contact structure 440 are exposed, as shown in Figure 5o.

[0216] In some embodiments, in combination with Figure 5p and Figure 6e, an atomic layer deposition process or a plasma vapor process is used to form a second electrode material layer (not shown in the figure) covering the side walls and bottom of the second through hole 482, and the second electrode material layer covering the bottom of the second through hole 482 is etched away. The retained second electrode material layer constitutes the second electrode layer 452, and the second electrode layer 452 covers the side walls of the second through hole 482. The first end of the second electrode layer 452 is connected to the first electrode layer 451, and the second end of the second electrode layer 452 is exposed from the surface of the third supporting material layer 432a' away from the third sacrificial material layer 432b'.

[0217] After the second electrode layer 452 is formed, the remaining part of the second through hole 482 constitutes a second sub-through hole, and the electrode contact material is filled in the second sub-through hole to form an electrode contact layer 4820. The second electrode layer 452 covers the side wall of the electrode contact layer 4280. The material of the electrode contact layer 4820 includes polysilicon or doped polysilicon.

[0218] The third support material layer 432a' is etched downward according to the mask pattern to form a third opening 4321. The third sacrificial material layer 432b' is exposed through the third opening 4321. The third sacrificial material layer 432b' can be subsequently removed through the third opening 4321. Here, the retained third support material layer 432a' constitutes the third support layer 432. The second insulating structure 430 includes the second support layer 431 and the third support layer 432, as shown in FIG5q.

[0219] The third sacrificial material layer 432b' is removed by wet etching to expose the second support material layer 431a', thereby forming a third gap 4322. The third gap 4322 exposes the sidewall of the second electrode layer 452 between the third support layer 432 and the second support material layer 431a', as shown in FIG5q.

[0220] It should be noted that, in the embodiment of the present disclosure, the method of forming the first opening 4311, the first gap 4312, the second opening 4221 and the second gap 4231 with reference to Figures 5q to 5s is similar to the method of forming the first opening 4311, the first gap 4312, the second opening 4221 and the second gap 4231 with reference to Figures 5j to 5i mentioned above, and will not be repeated here.

[0221] In some embodiments, the etch selectivity of the second sacrificial material layer is greater than that of the third sacrificial material layer. This facilitates controlling the perpendicularity between the third gap and the first gap. The third sacrificial material layer includes silicon oxide. In the disclosed embodiment, the third sacrificial material layer 432b' is made of borophosphosilicate glass (BPSG) and the second sacrificial material layer is made of tetraethyl orthosilicate (TEOS).

[0222] In some embodiments, as shown in FIG. 5S and FIG. 6E , a capacitor dielectric material is deposited in the third gap 4322 to form a second sub-capacitor dielectric layer 472 , and a conductive material is deposited on the other side of the second sub-capacitor dielectric layer 472 to form a second portion 462 .

[0223] In some embodiments, the second gap 4231, the first gap 4312, and the third gap 4322 are connected, and the formed first sub-capacitor dielectric layer 471 and the second sub-capacitor dielectric layer 472 are connected, and the first part covering the first sub-capacitor dielectric layer 471 and the second part covering the second sub-capacitor dielectric layer 472 are connected; in other embodiments, the second gap 4231, the first gap 4312, and the third gap 4322 are not connected, and the first sub-capacitor dielectric layer 471 located in the second gap 4231 and the second sub-capacitor dielectric layer 472 located in the first gap 4312 are separated by the first supporting layer 422, and the second sub-capacitor dielectric layer 472 located in the first gap 4312 and the second sub-capacitor dielectric layer 472 located in the third gap 4322 are separated by the second supporting layer 431.

[0224] 7a to 7j are schematic diagrams 3 of a manufacturing process of a memory according to an embodiment of the present disclosure. The manufacturing method of the memory provided by the embodiment of the present disclosure will be described in detail below based on FIG.

[0225] As shown in FIG7 a , the specific steps of providing a first semiconductor structure 410 include providing a substrate, forming a semiconductor body over the substrate along the thickness of the first semiconductor structure 410. Here, the semiconductor body can be formed from the substrate (e.g., by etching or epitaxy), and the substrate without the semiconductor body can be removed in a subsequent process. Doping is performed on both ends of the semiconductor body to form a source and a drain. The source and drain can be doped with a P-type dopant (e.g., boron or gallium) or an N-type dopant (e.g., phosphorus or arsenic). A gate (not shown) is formed on at least one side of the semiconductor body. One or more channels (not shown) are formed between the source and drain of the semiconductor body along the thickness of the first semiconductor structure 410. A gate dielectric layer (not shown) is formed between the channel and the gate. A vertical transistor includes the gate and the semiconductor body. Shallow trench isolation (not shown) is formed between adjacent vertical transistors. Shallow trench isolation between adjacent semiconductor bodies can be formed by photolithography, etching, and thin film deposition.

[0226] In some embodiments, a gate is formed on one side of the semiconductor body, and the vertical transistor is a single-gate transistor; in other embodiments, a gate is formed on at least two sides of the semiconductor body, and the vertical transistor is a multi-gate transistor, and the multi-gate transistor includes a full-ring gate transistor, a triple-gate transistor, or a double-gate transistor. It should be noted that the multi-gate transistor can have a larger gate control area to achieve better channel control with a smaller subthreshold swing.

[0227] The substrate material includes: a single element semiconductor material (such as silicon, germanium), a III-V compound semiconductor material, a II-VI compound semiconductor material, an organic semiconductor material, or other semiconductor materials known in the art. The shallow trench isolation material includes: at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0228] In some embodiments, referring to FIG. 7 a , a first insulating material layer 421 ′, a first sacrificial material layer 423 ′, and a first supporting material layer 422 ′ covering the semiconductor structure 410 are sequentially formed on the first semiconductor structure 410 , and the first insulating material layer 421 ′, the first sacrificial material layer 423 ′, and the first supporting material layer 422 ′ constitute a first insulating structural material layer 420 ′.

[0229] Here, the first insulating structure material layer 420' is used to form the first insulating structure 420 in a subsequent process, the first insulating material layer 421' is used to form the first insulating layer 421 in a subsequent process, the first supporting material layer 422' is used to form the first supporting layer 422 in a subsequent process, and the first sacrificial material layer 423' will be removed in a subsequent process to form the second gap 4231. The material of the first sacrificial material layer 423' includes silicon oxide. In the embodiment of the present disclosure, the first sacrificial material layer 423' is described as tetraethyl orthosilicate (TEOS) as an example.

[0230] The material of the first insulating material layer 421 ′ includes insulating materials, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon nitrogen boride, and silicon nitrogen carbide; the material of the first supporting material layer 422 ′ includes at least one of carbonitride, silicon nitride, or carbide.

[0231] In one embodiment, the first insulating material layer 421 ′ includes a composite film layer formed by multiple film layers.

[0232] In a specific embodiment, the above-mentioned formation of the first insulating material layer 421' covering the first semiconductor structure 410 includes: sequentially forming a first sub-insulating material layer 421a' and a second sub-insulating material layer 421b' covering the first semiconductor structure 410; a first sacrificial material layer 423' covering the second sub-insulating material layer 421b'. In this embodiment, the first sub-insulating material layer 421a' is silicon nitride and the second sub-insulating material layer 421b' is silicon boron nitride.

[0233] In some embodiments, referring to FIG7a , the first insulating structural material layer 420′ is etched to form a first through hole, and the bottom of the first through hole exposes the semiconductor body (not shown in the figure). Regarding the first through hole, reference can be made to the first through hole 481 in FIG5b . The remaining first insulating material layer 421′ constitutes the first insulating layer 421, the remaining first sub-insulating material layer 421a′ constitutes the first sub-insulating layer 421a, and the remaining second sub-insulating material layer 421b′ constitutes the second sub-insulating layer 421b.

[0234] In some embodiments, as shown in Figure 7a, a semiconductor material layer is deposited in the first through hole, and the bottom of the semiconductor material layer is connected to the semiconductor body. The semiconductor material layer is etched along the thickness direction of the first semiconductor structure 410 until the size of the semiconductor material layer is smaller than the size of the first insulating material layer 421'. The retained semiconductor material layer constitutes the semiconductor layer 443. In a specific embodiment, as shown in Figure 7a, along the thickness direction of the first semiconductor structure 410, the size of the semiconductor layer 443 is smaller than the size of the first sub-insulating material layer 421a'. Here, the material of the semiconductor material layer 443a includes polysilicon or doped polysilicon.

[0235] In some embodiments, still referring to FIG. 7 a , after forming the semiconductor layer 443, a connection layer 442 is formed on the semiconductor layer 443. Along the thickness of the first semiconductor structure 410, the sum of the dimensions of the connection layer 442 and the semiconductor layer 443 is smaller than the dimension of the first insulating material layer 421′. The material of the connection layer 442 includes a metal silicide, such as cobalt silicide or titanium silicide. The connection layer 442 is used to reduce the contact resistance between the semiconductor layer 443 and the metal layer 441, thereby improving the electrical performance of the memory device.

[0236] After the semiconductor layer 443 and the connecting layer 442 are formed, the remaining portion of the first through hole constitutes the first sub-through hole 481a. Still referring to Figure 7a, the metal layer 441 is deposited in the first sub-through hole 481a. In the direction along the thickness of the first semiconductor structure 410, the sum of the sizes of the metal layer 441, the connecting layer 442 and the semiconductor layer 443 is smaller than the size of the first insulating material layer 421'.

[0237] As shown in FIG7b , after forming the metal layer 441, a first sub-sacrificial material layer 490 is deposited in the first sub-via 481a. The first end of the first sub-sacrificial material layer 490 contacts the metal layer, and the second end of the first sub-sacrificial material layer 490 covers the surface of the first supporting material layer 422′ away from the first insulating material layer 421′. The material of the first sub-sacrificial material layer 490 includes a carbon material, such as spin-on carbon or amorphous carbon. Here, the first sub-sacrificial material layer 490 may also be planarized until the surface of the first sub-sacrificial material layer 490 is flush with the surface of the first supporting material layer 422′, as shown in FIG7c .

[0238] 7d and 7e , forming a second insulating structural material layer 430′ on the first supporting material layer 422′ includes sequentially forming a second sacrificial material layer 431b′ and a second supporting material layer 431a′ on the first supporting material layer 422′, forming a mask structure (not shown) covering the second supporting material layer 431a′. The mask structure may be a single film layer or a composite film layer. The mask structure may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, or spin-on carbon. A mask pattern can be formed in the mask structure through a self-alignment process, and the second insulating structure material layer 430' is etched downward according to the mask pattern until the first sub-sacrificial material layer 490 is exposed to form a second through hole 482. The first sub-sacrificial material layer 490 is removed by etching downward along the second through hole 482 to expose the metal layer 441. The second through hole 482 is connected to the first sub-through hole 481a, and the bottom of the connected second through hole 482 and the first sub-through hole 481a are located in the first insulating material layer 421', as shown in Figure 7f.

[0239] As shown in Figure 7g, an atomic layer deposition process or a plasma vapor process is used to form a first electrode structure 450 on the side walls and bottom of the connected second through-hole 482 and the first sub-through-hole 481a. The first electrode structure 450 penetrates the second insulating structure material layer 430' and a portion of the first insulating structure material layer 420'. The first end of the first electrode structure 450 is located in the first insulating material layer 421', and the second end of the first electrode structure 450 is exposed from the surface of the second supporting material layer 431a' away from the second sacrificial material layer 431b'. After the first electrode structure 450 is formed, the remaining part of the connected second through-hole 482 and the first sub-through-hole 481a constitute a second sub-through-hole, and the electrode contact material is filled in the second sub-through-hole to form an electrode contact layer 4820. The material of the electrode contact layer 4820 includes polysilicon or doped polysilicon.

[0240] In some embodiments, as shown in Figures 7g and 7h, a mask structure covering the second support material layer 431a' is formed. The mask structure can be a single film layer or a composite film layer. The mask structure includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, or spin-on carbon. A mask pattern can be formed in the mask structure through a self-alignment process, and the second support material layer 431a' is etched downward according to the mask pattern to form a first opening 4311. The first opening 4311 reveals the second sacrificial material layer 431b', and the second sacrificial material layer 431b' can be subsequently removed through the first opening 4311. Here, the retained second support material layer 431a' constitutes the second support layer 431.

[0241] The second sacrificial material layer 431b' is removed by wet etching to expose the first support material layer 422', thereby forming a first gap 4312. The first gap 4312 exposes the sidewall of the first electrode structure 450 between the second support layer 431 and the first support material layer 422', as shown in FIG7h.

[0242] In some embodiments, as shown in FIG. 7i , after removing the second sacrificial material layer 431b ′, the exposed first supporting material layer 422′ is further etched downward according to the mask pattern to form a second opening 4221. The second opening 4221 exposes the first sacrificial material layer 423′, which can then be removed through the second opening 4221. Here, the remaining first supporting material layer 422′ constitutes the first supporting layer 422.

[0243] The first sacrificial material layer 423' is removed by wet etching to expose the first insulating material layer 421', thereby forming a second gap 4231. The second gap 4231 exposes the sidewall of the first electrode structure 450 between the first supporting layer 422 and the first insulating layer 421. The remaining first insulating material layer 421' constitutes the first insulating layer 421, as shown in Figure 7i.

[0244] In some embodiments, the etch selectivity of the second sacrificial material layer is less than or equal to the etch selectivity of the first sacrificial material layer. Here, the materials of the first sacrificial material layer and the second sacrificial material layer include silicon oxide. In the embodiments of the present disclosure, the first sacrificial material layer and the second sacrificial material layer are described as tetraethyl orthosilicate (TEOS).

[0245] In some embodiments, the concentration of phosphorus and boron doped in the first sacrificial material layer is greater than the concentration of phosphorus and boron doped in the second sacrificial material layer, so that when the first sacrificial material layer and the second sacrificial material layer are etched, the closer to the first semiconductor structure, the greater the etching rate, which is beneficial to regulating the verticality of the side walls of the first gap and the second gap; in other embodiments, the concentration of phosphorus and boron doped in the first sacrificial material layer is equal to the concentration of phosphorus and boron doped in the second sacrificial material layer, so that when the first sacrificial material layer and the second sacrificial material layer are etched, they have the same etching rate.

[0246] In some embodiments, as shown in Figure 7j, a capacitor dielectric layer 470 is formed, and the capacitor dielectric layer 470 is located between the first electrode structure 450 and the second electrode structure 460; forming the capacitor dielectric layer 470 includes depositing a capacitor dielectric material in the first gap 4312 to form a second sub-capacitor dielectric layer 472, and depositing a capacitor dielectric material first sub-capacitor dielectric layer 471 in the second gap 4231. Here, the capacitor dielectric material includes at least one of a low dielectric constant material (for example, silicon oxide, etc.) and a high dielectric constant material (for example, aluminum oxide, etc.).

[0247] In some embodiments, the first gap 4312 and the second gap 4231 are connected, forming a first sub-capacitor dielectric layer 471 and a second sub-capacitor dielectric layer 472 connected. In other embodiments, the first gap 4312 and the second gap 4231 are not connected, forming a first sub-capacitor dielectric layer 471 and a second sub-capacitor dielectric layer 472 separated by a first supporting layer. Here, the first sub-capacitor dielectric layer 471 and the second sub-capacitor dielectric layer 472 can be formed in the same process or in separate processes. This is not particularly limited in this disclosure, and those skilled in the art can make their own choices based on actual needs.

[0248] In some embodiments, as shown in Figure 7j, a second electrode structure 460 is formed; wherein the second electrode structure 460 includes a first portion 461 located in the first insulating structure 420 and a second portion 462 located in the second insulating structure 430; the first portion 461 covers a portion of the side wall of the first electrode structure 450 located between the first supporting layer 422 and the first insulating layer 421; the second portion 462 covers a portion of the side wall of the first electrode structure 450 located between the second supporting layer 431 and the first supporting layer 422.

[0249] In some embodiments, still referring to Figure 7j, conductive materials are deposited on the first sub-capacitor dielectric layer 471 and the second sub-capacitor dielectric layer 472, respectively, to form a first part 461 and a second part 462. The conductive materials include: at least one of semiconductor materials (for example, polysilicon, doped polysilicon, etc.), metals (for example, tungsten, titanium, etc.), metal nitrides (for example, tungsten nitride, titanium nitride, tantalum nitride, etc.) and metal silicides (for example, titanium silicide, nickel silicide, titanium silicon nitride, etc.). The embodiment of the present disclosure is described using the material of the second electrode structure 460 being titanium nitride as an example.

[0250] A first filling layer 461a is formed on a side of the first portion 461 away from the first sub-capacitor dielectric layer 471, and a second filling layer 462a is formed on a side of the second portion 462 away from the second sub-capacitor dielectric layer 472. The materials of the first filling layer 461a and the second filling layer 462a include polysilicon or silicon germanium. The materials of the first filling layer 461a and the second filling layer 462a can be the same or different, and the present disclosure has no special restrictions on this.

[0251] 8a to 8c are schematic diagrams 4 of a memory manufacturing process according to an embodiment of the present disclosure. The manufacturing method of the memory provided by the embodiment of the present disclosure will be described in detail below with reference to FIG7a to FIG7c and FIG8a to FIG8d.

[0252] As shown in FIG7 a , the specific steps of providing a first semiconductor structure 410 include providing a substrate, forming a semiconductor body over the substrate along the thickness of the first semiconductor structure 410. Here, the semiconductor body can be formed from the substrate (e.g., by etching or epitaxy), and the substrate without the semiconductor body can be removed in a subsequent process. Doping is performed on both ends of the semiconductor body to form a source and a drain. The source and drain can be doped with a P-type dopant (e.g., boron or gallium) or an N-type dopant (e.g., phosphorus or arsenic). A gate (not shown) is formed on at least one side of the semiconductor body. One or more channels (not shown) are formed between the source and drain of the semiconductor body along the thickness of the first semiconductor structure 410. A gate dielectric layer (not shown) is formed between the channel and the gate. A vertical transistor includes the gate and the semiconductor body. Shallow trench isolation (not shown) is formed between adjacent vertical transistors. Shallow trench isolation between adjacent semiconductor bodies can be formed by photolithography, etching, and thin film deposition.

[0253] In some embodiments, a gate is formed on one side of the semiconductor body, and the vertical transistor is a single-gate transistor; in other embodiments, a gate is formed on at least two sides of the semiconductor body, and the vertical transistor is a multi-gate transistor, and the multi-gate transistor includes a full-ring gate transistor, a triple-gate transistor, or a double-gate transistor. It should be noted that the multi-gate transistor can have a larger gate control area to achieve better channel control with a smaller subthreshold swing.

[0254] The substrate material includes: a single element semiconductor material (such as silicon, germanium), a III-V compound semiconductor material, a II-VI compound semiconductor material, an organic semiconductor material, or other semiconductor materials known in the art. The shallow trench isolation material includes: at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0255] In some embodiments, referring to FIG. 7 a , a first insulating material layer 421 ′, a first sacrificial material layer 423 ′, and a first supporting material layer 422 ′ covering the semiconductor structure 410 are sequentially formed on the first semiconductor structure 410 , and the first insulating material layer 421 ′, the first sacrificial material layer 423 ′, and the first supporting material layer 422 ′ constitute a first insulating structural material layer 420 ′.

[0256] Here, the first insulating structure material layer 420' is used to form the first insulating structure 420 in a subsequent process, the first insulating material layer 421' is used to form the first insulating layer 421 in a subsequent process, the first supporting material layer 422' is used to form the first supporting layer 422 in a subsequent process, and the first sacrificial material layer 423' will be removed in a subsequent process to form the second gap 4231. The material of the first sacrificial material layer 423' includes silicon oxide. In the embodiment of the present disclosure, the first sacrificial material layer 423' is described as tetraethyl orthosilicate (TEOS) as an example.

[0257] The material of the first insulating material layer 421 ′ includes insulating materials, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon nitrogen boride, and silicon nitrogen carbide; the material of the first supporting material layer 422 ′ includes at least one of carbonitride, silicon nitride, or carbide.

[0258] In one embodiment, the first insulating material layer 421 ′ includes a composite film layer formed by multiple film layers. In other embodiments, the first insulating material layer 421 ′ includes a single film layer. The present disclosure has no particular limitation on this.

[0259] In a specific embodiment, the formation of the first insulating material layer 421' covering the first semiconductor structure 410 includes: sequentially forming a first sub-insulating material layer 421a' and a second sub-insulating material layer 421b' covering the first semiconductor structure 410; and a first sacrificial material layer 423' covering the second sub-insulating material layer 421b'.

[0260] In some embodiments, referring to FIG7a , the first insulating structural material layer 420 ′ is etched to form a first through hole, and the bottom of the first through hole exposes the semiconductor body (not shown in the figure), as shown in the first through hole 481 in FIG5b , the remaining first insulating material layer 421 ′ constitutes the first insulating layer 421, the remaining first sub-insulating material layer 421a ′ constitutes the first sub-insulating layer 421a, and the remaining second sub-insulating material layer 421b ′ constitutes the second sub-insulating layer 421b.

[0261] In some embodiments, as shown in Figure 7a, a semiconductor material layer is deposited in the first through hole 481, and the bottom of the semiconductor material layer is connected to the semiconductor body. The semiconductor material layer is etched along the thickness direction of the first semiconductor structure 410 until the size of the semiconductor material layer is smaller than the size of the first insulating material layer 421'. The retained semiconductor material layer constitutes the semiconductor layer 443. In a specific embodiment, as shown in Figure 7a, along the thickness direction of the first semiconductor structure 410, the size of the semiconductor layer 443 is smaller than the size of the first sub-insulating material layer 421a'. Here, the material of the semiconductor material layer 443a includes polycrystalline silicon or doped polycrystalline silicon.

[0262] In some embodiments, still referring to FIG. 7 a , after forming the semiconductor layer 443, a connection layer 442 is formed on the semiconductor layer 443. Along the thickness of the first semiconductor structure 410, the sum of the dimensions of the connection layer 442 and the semiconductor layer 443 is smaller than the dimension of the first insulating material layer 421′. The material of the connection layer 442 includes a metal silicide, such as cobalt silicide or titanium silicide. The connection layer 442 is used to reduce the contact resistance between the semiconductor layer 443 and the metal layer 441, thereby improving the electrical performance of the memory device.

[0263] After the semiconductor layer 443 and the connecting layer 442 are formed, the remaining portion of the first through hole 481 constitutes a first sub-through hole 481a. Still referring to Figure 7a, a metal layer 441 is deposited in the first sub-through hole 481a. In the direction along the thickness of the first semiconductor structure 410, the sum of the sizes of the metal layer 441, the connecting layer 442 and the semiconductor layer 443 is smaller than the size of the first insulating material layer 421'.

[0264] As shown in FIG7b , after forming the metal layer 441, a first sub-sacrificial material layer 490 is deposited in the first sub-via 481a. The first end of the first sub-sacrificial material layer 490 contacts the metal layer, and the second end of the first sub-sacrificial material layer 490 covers the surface of the first supporting material layer 422′ away from the first insulating material layer 421′. The material of the first sub-sacrificial material layer 490 includes a carbon material, such as spin-on carbon or amorphous carbon. Here, the first sub-sacrificial material layer 490 may also be planarized until the surface of the first sub-sacrificial material layer 490 is flush with the surface of the first supporting material layer 422′, as shown in FIG7c .

[0265] As shown in Figure 8a, forming the second insulating structural material layer 430' on the first supporting material layer 422' includes sequentially forming a first insulating structural material layer 431b', a second supporting material layer 431a', a third sacrificial material layer 432b', and a third supporting material layer 432a' on the first supporting material layer. The provision of the third sacrificial material layer 432b' and the third supporting material layer 432a' facilitates further increasing the effective height of the first electrode structure 450, thereby further increasing the effective facing area between the first electrode structure 450 and the second electrode structure 460, thereby increasing the capacitance value of the capacitor.

[0266] In some embodiments, in combination with FIG. 7f and FIG. 8a , a mask structure (not shown) covering the third support material layer 432a′ is formed. The mask structure may be a single film layer or a composite film layer. The mask structure includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, or spin-on carbon. A mask pattern may be formed in the mask structure by a self-alignment process, and the second insulating structure material layer 430′ is etched downward according to the mask pattern until the first sub-sacrificial material layer 490 is exposed to form a second through hole 482. The first sub-sacrificial material layer 490 is etched downward along the second through hole 482 to expose the metal layer 441. The second through hole 482 is connected to the first sub-through hole 481a, and the bottom of the connected second through hole 482 and the first sub-through hole 481a is located in the first insulating material layer 421′.

[0267] As shown in Figure 8a, an atomic layer deposition process or a plasma vapor process is used to form a first electrode structure 450 on the sidewalls and bottom of the connected second through-hole 482 and the first sub-through-hole 481a. The first electrode structure 450 penetrates the second insulating structure material layer 430' and a portion of the first insulating structure material layer 420'. The first end of the first electrode structure 450 is located in the first insulating material layer 421', and the second end of the first electrode structure 450 is exposed from the surface of the third supporting material layer 432a' away from the third sacrificial material layer 432b'. After the first electrode structure 450 is formed, the remaining portion of the connected second through-hole 482 and the first sub-through-hole 481a constitutes a second sub-through-hole, and the electrode contact material is filled in the second sub-through-hole to form an electrode contact layer 4820. The material of the electrode contact layer 4820 includes polysilicon or doped polysilicon.

[0268] In some embodiments, as shown in Figures 8a and 8b, a mask structure covering the third support material layer 432a' is formed. The mask structure can be a single film layer or a composite film layer. The mask structure includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, or spin-on carbon. A mask pattern can be formed in the mask structure through a self-aligned process, and the third support material layer 432a' is etched downward according to the mask pattern to form a third opening 4321. The third opening 4321 reveals the third sacrificial material layer 432b', and the third sacrificial material layer 432b' can be subsequently removed through the third opening 4321. Here, the retained third support material layer 432a' constitutes the third support layer 432, and the second insulating structure 430 includes the second support layer 431 and the third support layer 432.

[0269] The third sacrificial material layer 432 b ′ is removed by wet etching to expose the second support material layer 431 a ′, thereby forming a third gap 4322 . The third gap 4322 exposes the sidewall of the first electrode structure 450 between the third support layer 432 and the second support material layer 431 a ′.

[0270] In some embodiments, still referring to FIG. 8 a and FIG. 8 b , the second support material layer 431 a ′ is etched downward according to the mask pattern to form a first opening 4311. The first opening 4311 exposes the second sacrificial material layer 431 b ′, which can then be removed through the first opening 4311. Here, the remaining second support material layer 431 a ′ constitutes the second support layer 431.

[0271] The second sacrificial material layer 431 b ′ is removed by wet etching to expose the first support material layer 422 ′, thereby forming a first gap 4312 . The first gap 4312 exposes the sidewall of the first electrode structure 450 between the second support layer 431 and the first support material layer 422 ′.

[0272] In some embodiments, still referring to FIG. 8 a and FIG. 8 b , after removing the second sacrificial material layer 431 b ′, the exposed first supporting material layer 422 ′ is further etched downward according to the mask pattern to form a second opening 4221. The second opening 4221 exposes the first sacrificial material layer 423 ′, which can then be removed through the second opening 4221. Here, the remaining first supporting material layer 422 ′ constitutes the first supporting layer 422.

[0273] The first sacrificial material layer 423' is removed by wet etching to expose the first insulating material layer 421', thereby forming a second gap 4231. The second gap 4231 exposes the sidewall of the first electrode structure 450 between the first supporting layer 422 and the first insulating layer 421. The retained first insulating material layer 421' constitutes the first insulating layer 421, as shown in Figure 8b.

[0274] In some embodiments, the etch selectivity of the second sacrificial material layer is less than or equal to the etch selectivity of the first sacrificial material layer. Here, the materials of the first sacrificial material layer and the second sacrificial material layer include silicon oxide. In the embodiments of the present disclosure, the first sacrificial material layer and the second sacrificial material layer are described as tetraethyl orthosilicate (TEOS).

[0275] In some embodiments, the concentration of phosphorus and boron doped in the first sacrificial material layer is greater than the concentration of phosphorus and boron doped in the second sacrificial material layer, so that when the first sacrificial material layer and the second sacrificial material layer are etched, the closer to the first semiconductor structure, the greater the etching rate, which is beneficial to regulating the verticality of the side walls of the first gap and the second gap; in other embodiments, the concentration of phosphorus and boron doped in the first sacrificial material layer is equal to the concentration of phosphorus and boron doped in the second sacrificial material layer, so that when the first sacrificial material layer and the second sacrificial material layer are etched, they have the same etching rate.

[0276] In some embodiments, as shown in Figure 8c, a capacitor dielectric layer 470 is formed, and the capacitor dielectric layer 470 is located between the first electrode structure 450 and the second electrode structure 460; forming the capacitor dielectric layer 470 includes depositing a capacitor dielectric material in the first gap 4312 to form a second sub-capacitor dielectric layer 472, and depositing a capacitor dielectric material in the second gap 4231 to form a first sub-capacitor dielectric layer 471. Here, the capacitor dielectric material includes at least one of a low dielectric constant material (for example, silicon oxide, etc.) and a high dielectric constant material (for example, aluminum oxide, etc.).

[0277] In some embodiments, the first gap 4312 and the second gap 4231 are connected, forming a first sub-capacitor dielectric layer 471 and a second sub-capacitor dielectric layer 472 connected. In other embodiments, the first gap 4312 and the second gap 4231 are not connected, forming a first sub-capacitor dielectric layer 471 and a second sub-capacitor dielectric layer 472 separated by a first supporting layer. Here, the first sub-capacitor dielectric layer 471 and the second sub-capacitor dielectric layer 472 can be formed in the same process or in separate processes. This is not particularly limited in this disclosure, and those skilled in the art can make their own choices based on actual needs.

[0278] In some embodiments, as shown in Figure 8c, a second electrode structure 460 is formed; wherein the second electrode structure 460 includes a first portion 461 located in the first insulating structure 420 and a second portion 462 located in the second insulating structure 430; the first portion 461 covers a portion of the side wall of the first electrode structure 450 located between the first supporting layer 422 and the first insulating layer 421; the second portion 462 covers a portion of the side wall of the first electrode structure 450 located between the second supporting layer 431 and the first supporting layer 422.

[0279] In some embodiments, still referring to Figure 8c, conductive materials are deposited on the first sub-capacitor dielectric layer 471 and the second sub-capacitor dielectric layer 472, respectively, to form a first portion 461 and a second portion 462. The conductive materials include: at least one of semiconductor materials (for example, polysilicon, doped polysilicon, etc.), metals (for example, tungsten, titanium, etc.), metal nitrides (for example, tungsten nitride, titanium nitride, tantalum nitride, etc.) and metal silicides (for example, titanium silicide, nickel silicide, titanium silicon nitride, etc.). The embodiment of the present disclosure is described using the example of the material of the second electrode structure 460 being titanium nitride.

[0280] A first filling layer 461a is formed on a side of the first portion 461 away from the first sub-capacitor dielectric layer 471, and a second filling layer 462a is formed on a side of the second portion 462 away from the second sub-capacitor dielectric layer 472. The materials of the first filling layer 461a and the second filling layer 462a include polysilicon or silicon germanium. The materials of the first filling layer 461a and the second filling layer 462a can be the same or different, and the present disclosure has no special restrictions on this.

[0281] Based on the above memory, the present disclosure further provides a memory system, the memory system comprising:

[0282] One or more memories as in any of the above embodiments;

[0283] A memory controller is coupled to the memory and configured to control the memory.

[0284] The memory system includes: a mobile phone, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or other suitable electronic device having memory therein.

[0285] In some embodiments, the memory controller is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0286] In other embodiments, the memory controller is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0287] The memory controller may be configured to control memory operations, such as read, erase, and program operations. The memory controller may also be configured to manage various functions related to data stored or to be stored in the memory, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller is further configured to process error correction codes for data read from or written to the memory.

[0288] The memory controller may also perform any other suitable functions, such as formatting the memory. The memory controller may communicate with an external device (e.g., a host) according to a specific communication protocol. For example, the memory controller may communicate with the external device via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect protocol, a PCI Express protocol, an Advanced Technology Attachment protocol, a serial protocol, a parallel protocol, a Minicomputer Miniature Disk Interface protocol, an Enhanced Minidisk Interface protocol, an Integrated Drive Electronics protocol, a Firewire protocol, etc.

[0289] The memory controller and one or more memories may be integrated into various types of storage devices, for example, included in the same package (eg, a universal flash storage (UFS) package or an (eMMC) package).

[0290] Based on the above memory system, an embodiment of the present disclosure further provides an electronic device, the electronic device comprising: the memory system in the above embodiment;

[0291] A host is coupled to the memory system.

[0292] Electronic devices include mobile phones, desktop computers, tablets, laptops, servers, vehicle-mounted devices, wearable devices or mobile power supplies, etc.

[0293] The host may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host may be configured to send data to the memory. Alternatively, the host may be configured to receive data from the memory.

[0294] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory, comprising: The first semiconductor structure includes: a vertical transistor; a first insulating structure and a second insulating structure sequentially stacked on the first semiconductor structure; a contact structure penetrating the first insulating structure and connected to the semiconductor body of the vertical transistor; A first electrode structure, comprising: a first electrode layer penetrating at least a portion of the first insulating structure and a second electrode layer penetrating the second insulating structure; wherein the first electrode layer covers at least a portion of a sidewall of the contact structure and is connected to the contact structure; and the second electrode layer is connected to the first electrode layer; The second electrode structure comprises: a first portion located in the first insulating structure and a second portion located in the second insulating structure; wherein the first portion covers a portion of the sidewall of the first electrode layer; and the second portion covers a portion of the sidewall of the second electrode layer; The capacitor dielectric layer is located between the first electrode structure and the second electrode structure.

2. The memory according to claim 1, wherein: The first insulating structure comprises a first insulating layer and a first supporting layer sequentially stacked on the first semiconductor structure; wherein the first insulating layer and the first supporting layer are spaced apart; The first portion is located between the first insulating layer and the first supporting layer.

3. The memory according to claim 2, wherein: The contact structure comprises: a metal layer and a semiconductor layer; wherein the metal layer penetrates the first supporting layer and extends into the first insulating layer; and the semiconductor layer is located between the semiconductor body and the metal layer; The first electrode layer includes: a first sub-electrode layer, which is located on the semiconductor layer and covers the side wall of the metal layer.

4. The memory according to claim 3, wherein: The first electrode layer further includes: a second sub-electrode layer located between the semiconductor layer and the metal layer.

5. The memory according to claim 2, wherein: The contact structure comprises: a metal layer and a semiconductor layer; wherein the metal layer penetrates the first supporting layer and extends between the first insulating layer and the first supporting layer; and the semiconductor layer is located between the semiconductor body and the metal layer; The first electrode layer is located on the first semiconductor structure and covers the sidewalls of the semiconductor layer and the metal layer.

6. The memory according to claim 3 or 5, wherein: The contact structure includes: a connection layer located between the semiconductor layer and the metal layer.

7. The memory according to claim 1, wherein: The second insulating structure comprises: a second supporting layer, wherein the second supporting layer is spaced apart from the first insulating structure; The second portion is located between the first insulating structure and the second supporting layer.

8. The memory according to claim 7, wherein: The second insulating structure further includes: a third supporting layer, wherein the third supporting layer and the second supporting layer are spaced apart; The second portion is also located between the second supporting layer and the third supporting layer.

9. A method for manufacturing a memory, comprising: Providing a first semiconductor structure; wherein the first semiconductor structure comprises a vertical transistor; forming a first insulating structure covering the first semiconductor structure; forming a contact structure penetrating the first insulating structure; wherein the contact structure is connected to the semiconductor body of the vertical transistor; forming a second insulating structure covering the contact structure and the first insulating structure; forming a first electrode structure; wherein the first electrode structure comprises a first electrode layer penetrating at least a portion of the first insulating structure and a second electrode layer penetrating the second insulating structure; the first electrode layer covers at least a portion of the sidewall of the contact structure and is connected to the contact structure; the second electrode layer is connected to the first electrode layer; forming a second electrode structure; wherein the second electrode structure comprises a first portion located in the first insulating structure and a second portion located in the second insulating structure; the first portion covers a portion of the sidewall of the first electrode layer; and the second portion covers a portion of the sidewall of the second electrode layer; A capacitor dielectric layer is formed; wherein the capacitor dielectric layer is located between the first electrode structure and the second electrode structure.

10. The method according to claim 9, wherein: The production method further comprises: Forming a first insulating structure material layer covering the first semiconductor structure; wherein the first insulating structure material layer comprises a first insulating material layer, a first sacrificial material layer and a first supporting material layer stacked in sequence; Forming a first through hole penetrating the first insulating structure material layer; wherein the bottom of the first through hole exposes the semiconductor body; The forming of a contact structure penetrating the first insulating structure comprises: forming a semiconductor layer in the first through hole, wherein the semiconductor layer is connected to the semiconductor body; wherein, along the thickness direction of the first semiconductor structure, the size of the semiconductor layer is smaller than the size of the first insulating material layer; forming a metal layer on the semiconductor layer, wherein the metal layer is connected to the semiconductor layer; wherein the contact structure includes the semiconductor layer and the metal layer; The forming of the first electrode structure comprises: After forming the semiconductor layer, forming a first sub-through hole based on the morphology of the first through hole, wherein the bottom of the first sub-through hole exposes the semiconductor layer; forming the first electrode layer covering the sidewall and bottom of the first sub-through hole; The step of forming a metal layer on the semiconductor layer comprises: The metal layer is formed in the first sub-via hole in which the first electrode layer is formed.

11. The method according to claim 9, wherein: The production method further comprises: Forming a first insulating structure material layer covering the first semiconductor structure; wherein the first insulating structure material layer comprises a first insulating material layer, a first sacrificial material layer and a first supporting material layer stacked in sequence; Forming a first through hole penetrating the first insulating structure material layer; wherein the bottom of the first through hole exposes the semiconductor body; The forming of the first electrode structure comprises: Forming the first electrode layer covering the sidewall of the first through hole, and forming a first sub-through hole based on the morphology of the first through hole; wherein the bottom of the first sub-through hole exposes the semiconductor body; The forming of a contact structure penetrating the first insulating structure comprises: A semiconductor layer is formed in the first sub-through hole, wherein the semiconductor layer is connected to the semiconductor body; wherein, along the thickness direction of the first semiconductor structure, the size of the semiconductor layer is larger than the size of the first insulating material layer and smaller than the sum of the sizes of the first insulating material layer and the first sacrificial material layer; A metal layer is formed on the semiconductor layer, and the metal layer is connected to the semiconductor layer; wherein the contact structure includes the semiconductor layer and the metal layer.

12. The production method according to claim 10 or 11, wherein: The production method further comprises: Forming a second insulating structure material layer covering the first insulating structure material layer, the first electrode layer and the contact structure; wherein the second insulating structure material layer comprises a second sacrificial material layer and a second supporting material layer stacked in sequence; Forming a second through hole penetrating the second insulating structure material layer; wherein the first electrode layer and the contact structure are exposed at the bottom of the second through hole; The forming of the first electrode structure further includes: At least forming the second electrode layer covering the sidewall of the second through hole, and forming a second sub-through hole based on the morphology of the second through hole; The manufacturing method further includes: filling the second sub-through hole to form an electrode contact layer.

13. The method according to claim 12, wherein: The memory includes a plurality of the first electrode structures; and the manufacturing method further includes: Forming a third through hole penetrating the second insulating structure material layer, the first supporting material layer and the first sacrificial material layer; wherein the third through hole is located between two adjacent first electrode structures; the sidewall of the third through hole exposes a portion of the first electrode layer and a portion of the second electrode layer, and the bottom of the third through hole exposes the first insulating material layer; The forming of the capacitor dielectric layer comprises: forming a first sub-capacitor dielectric layer covering the exposed first electrode layer; forming a second sub-capacitor dielectric layer covering the exposed second electrode layer; wherein the capacitor dielectric layer includes the first sub-capacitor dielectric layer and the second sub-capacitor dielectric layer; The forming of the second electrode structure comprises: forming the first portion covering the first sub-capacitor dielectric layer; The second portion covering the second sub-capacitor dielectric layer is formed.

14. The method according to claim 13, wherein: The forming of a third through hole penetrating the second insulating structure material layer, the first supporting material layer and the first sacrificial material layer comprises: Etching the second supporting material layer downwards according to the mask pattern to form a first opening; wherein the bottom of the first opening exposes the second sacrificial material layer; wherein the remaining second supporting material layer constitutes a second supporting layer; The second sacrificial material layer is removed according to the first opening to form a first gap; wherein the sidewall of the first gap exposes part of the second electrode layer, and the bottom of the first gap exposes the first supporting material layer; and the second insulating structure includes the second supporting layer; Etching the first supporting material layer downwards according to the mask pattern to form a second opening; wherein the bottom of the second opening exposes the first sacrificial material layer; wherein the remaining first supporting material layer constitutes a first supporting layer; The first sacrificial material layer is removed according to the second opening to form a second gap; wherein the sidewall of the second gap exposes part of the first electrode layer, and the bottom of the second gap exposes the first insulating material layer; the remaining first insulating material layer constitutes a first insulating layer, and the first insulating structure includes the first insulating layer and the first supporting layer.

15. The method according to claim 14, wherein: The forming of the first sub-capacitor dielectric layer covering the exposed first electrode layer comprises: forming the first sub-capacitor dielectric layer in the second gap; The forming of the first portion covering the first sub-capacitor dielectric layer comprises: forming the first portion in the second gap where the first sub-capacitor dielectric layer is formed; The forming of the second sub-capacitor dielectric layer covering the exposed second electrode layer comprises: forming the second sub-capacitor dielectric layer in the first gap; The forming of the second portion covering the second sub-capacitor dielectric layer comprises: The second portion is formed in the first gap where the second sub-capacitor dielectric layer is formed.

16. The method according to claim 15, wherein: The second insulating structure material layer further includes a third sacrificial material layer and a third supporting material layer stacked in sequence; wherein the third sacrificial material layer is located between the second supporting material layer and the third supporting material layer; The forming of a third through hole penetrating the second insulating structure material layer, the first supporting material layer and the first sacrificial material layer comprises: Etching the third support material layer downwards according to the mask pattern to form a third opening; wherein the bottom of the third opening exposes the third sacrificial material layer; wherein the remaining third support material layer constitutes a third support layer; The third sacrificial material layer is removed according to the third opening to form a third gap; wherein, The sidewall of the third gap exposes part of the second electrode layer, and the bottom of the third gap exposes the second supporting material layer; the second insulating structure also includes the third supporting layer.

17. The method according to claim 16, wherein: The second sub-capacitor dielectric layer formed to cover the exposed second electrode layer further includes: forming the second sub-capacitor dielectric layer in the third gap; The forming of the second portion covering the second sub-capacitor dielectric layer comprises: The second portion is formed in the third gap where the second sub-capacitor dielectric layer is formed.

18. The method according to claim 16, wherein: The etching selectivity of the second sacrificial material layer is greater than the etching selectivity of the third sacrificial material layer.

19. A memory system comprising: The memory as claimed in any one of claims 1 to 8; A memory controller is coupled to the memory and is configured to control the memory.

20. An electronic device, comprising: The memory system as claimed in claim 19; A host is coupled to the memory system.

Images