Charge transport devices for room temperature applications implemented by topological states

Abstract

The use of room temperature MIS (Metal-Insulator-Semiconductor) capacitive structures provides for abnormally large charge transfer. The conductance may be 10 times or more (typically several orders of magnitude greater) of the conductance expected according to the classical properties of the structure. This abnormal behavior is attributed to a topological state formed in the MIS structure under bias when both in-plane and out-of-plane components of the bias electric field exist. One feature of this new physical effect is lateral supercurrent between MIS structures. Another feature of this new physical effect is that the quantum Hall effect is observed at room temperature and without a significant magnetic field.

Description

[0001] Inventors: F.B. Prinz

[0002] S. Chackathessing

[0003] T.T. Howard

[0004] D.L. Kuester

[0005] Zhang Xiting

[0006] G.D. Han

[0007] Ren Rongxuan

[0008] A.K. Bolton-McKean Field of the Invention

[0009] The present invention relates to charge storage and transfer devices. Background Art

[0010] Non-classical electrical effects (such as superconductivity, quantum Hall effect, etc.) are known in the art to require low temperature, strong magnetic field, or both. Although there have been various theoretical proposals for possible room-temperature non-classical electrical effects, there has been very little experimental proof of such effects to date. Therefore, providing room-temperature non-classical electrical effects would be an advancement in the art. Summary of the Invention

[0011] We have discovered experimental evidence of non-classical behavior in capacitive MIS (metal / insulator / semiconductor) structures. Specifically, in our experimental results, room-temperature charge storage, charge release, and current transfer can be much higher (i.e., several orders of magnitude higher) than what would be expected from the classical capacitance of the MIS structure for room-temperature charge storage, charge release, and current transfer.

[0012] Currently, without being bound by theory, it is believed that in these and similar geometries, certain electric and / or magnetic field distributions enable the conversion of conventional electronic charges with random phases into a state of matter with a topological phase. Finite element simulations using Maxwell's equations reveal that the polarization of transient electric and / or magnetic fields gives rise to regions of high electron density, which may in turn lead to topological surface states. Topological electronic phases are characterized by non-trivial topological invariants and represent a state of matter with unique physical properties. For example, Maxwell's equations that govern the behavior of conventional charges and the associated electric and magnetic fields are modified in the presence of a topological phase. Simulations using density functional theory indicate that the emergence of such a phase leads to non-trivial topological invariants.

[0013] Compared with traditional capacitors, this topological phase can lead to enhanced charge accumulation, enabling the creation of topological capacitors with a higher charge density that can be released. The electronic charge is stored and can be retrieved upon voltage reversal. Compared with traditional capacitors, the retrieved charge is significantly higher. The charge density retrieved from smaller devices is higher compared to that retrieved from larger devices.

[0014] The topological phase difference in these capacitors can lead to the formation of a supercurrent to balance the phase difference between the anode and the cathode. Without any observed sample damage, this supercurrent can significantly exceed 1000 amperes / cm 2 . FEM (finite element method) calculations show that conventional charge transport with the observed supercurrent density would result in the instantaneous melting of the sample. In contrast, the capacitors in this study work can deliver high current density pulses without significant damage. Additionally, the current capacitors show higher current density pulses in smaller devices compared to current pulses from larger devices, which is contrary to traditional capacitive devices. Conventional capacitive current is proportional to the area but not to the reciprocal of the area (as observed here).

[0015] Therefore, in the remainder of this specification, a "topological state" is phenomenologically defined such that any capacitive device with room-temperature charge storage, charge release, and / or current transport that is at least 10 times that expected of the corresponding classical capacitor is considered to have a "topological state" that leads to these excellent observations. We also consider the observation of the quantum Hall effect at room temperature and in the absence of a significant magnetic field as a signature of the presence of a topological state.

[0016] This offers significant advantages. Currently, energy density and power density devices are performance-limited. The architectures considered herein can significantly improve both of these metrics. Josephson-type transport is known to occur only at extremely low temperatures. We may have observed supercurrents at room temperature. Some of our devices exhibit a current density of at least 1000 amperes per cm 2 .

[0017] Early experimental work by our research group found anomalously high charge storage behavior in devices called "all-electronic batteries." An exemplary reference for this study work is U.S. Patent Application 12 / 798,102, filed on March 29, 2010. However, the concept of forming topological electronic states in room-temperature semiconductors using in-plane and out-of-plane electrical biasing of a low-dimensional electron gas was not considered in U.S. Patent Application 12 / 798,102. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A - 1D Schematically shows the operation of a non - classical MIS device in accordance with the principles of the present invention.

[0019] Figure 2A - 2B Shows a non - classical MIS device configured to exhibit lateral supercurrent.

[0020] Figure 3 Is an exemplary I - V curve showing lateral supercurrent.

[0021] Figure 4A - 4B Schematically shows two options for lateral transport using non - classical MIS device operation.

[0022] Figure 5A - 5B Shows the effect of disrupting non - classical MIS device operation on lateral current transport.

[0023] Figure 6 Shows the disruption of non - classical MIS device operation by voltage offset.

[0024] Figure 7A - 7B Shows the disruption of non - classical MIS device operation by temperature deviation.

[0025] Figure 8A - 8D Schematically shows several options for controlling lateral supercurrent using an applied perturbation.

[0026] Figure 9 Is a histogram showing the measured quantum Hall filling factor with a main filling factor of 1 / 3.

[0027] Figure 10 Shows the measured impedance spectrum of a device in a state with a quantum Hall filling factor of 1. DETAILED DESCRIPTION

[0028] Part A describes the general principles related to embodiments of the present invention. Part B describes several experimental examples.

[0029] A) General Principles

[0030] An exemplary embodiment of the present invention is a method for providing lateral supercurrent transport between two MIS structures, the method comprising:

[0031] Forming a first low - dimensional electron gas in a first MIS (metal - insulator - semiconductor) structure (e.g., Figure 2A 204 in

[0032] ), wherein a first applied voltage to the first MIS structure creates a first electric - field component parallel to and perpendicular to the first low - dimensional electron gas; and Figure 2AA second two-dimensional electron gas is formed in (e.g., 206), wherein a second applied voltage to the second MIS structure generates a second electric field component parallel to and perpendicular to the second two-dimensional electron gas; and

[0033] Laterally couple the first MIS structure to the second MIS structure (e.g., via Figure 2B the edge field 210 in). Here, the first MIS structure has a first topological state formed by injecting charge carriers, and the second MIS structure has a second topological state formed by injecting charge carriers.

[0034] The method may further include: cycling the laterally applied voltage until the lateral transport between the first MIS structure and the second MIS structure shows an anomalously low resistance. Here, we define "an anomalously low resistance" as a resistance that is 10 times or more lower than the resistance expected by conventional device physics.

[0035] Turning off the laterally transported anomalously low resistance can be accomplished by applying a perturbation to the first MIS structure and / or the second MIS structure sufficient to disrupt the topological state. Suitable perturbations include: applying an electrical bias, applying a temperature rise, applying a magnetic field, applying an electromagnetic field, applying a radio frequency signal, and applying a laser beam.

[0036] The first MIS structure may be laterally connected to the second MIS structure by direct lateral contact (e.g., as Figure 4A ).

[0037] Alternatively, the first MIS structure may be laterally connected to the second MIS structure with a connecting element (e.g., as Figure 4B ). Here, turning off the laterally transported anomalously low resistance can be accomplished by applying a perturbation to the connecting element sufficient to disrupt the topological state. Suitable perturbations include: applying an electrical bias, applying a temperature rise, applying a magnetic field, applying an electromagnetic field, applying a radio frequency signal, and applying a laser beam.

[0038] The first topological state may be formed by: cycling the voltage of the first MIS structure until the vertical transport through the first MIS structure exhibits one or more characteristics of quantum Hall conduction. Similarly, the second topological state may be formed by: cycling the voltage of the second MIS structure until the vertical transport through the second MIS structure exhibits one or more characteristics of quantum Hall conduction.

[0039] More generally, another embodiment of the present invention is a method of forming topological quantum states in a metal-insulator-semiconductor (MIS) structure, wherein the method includes:

[0040] Cycling the voltage of the MIS structure until the vertical transport through the MIS structure exhibits one or more characteristics of quantum Hall conduction;

[0041] The MIS structure includes a two-dimensional electron gas, and an applied voltage to the MIS structure generates electric field components parallel and perpendicular to the two-dimensional electron gas.

[0042] The MIS structure can be at a temperature of 25 °C to 40 °C, and quantum Hall conduction is observed in the absence of an applied magnetic field. As Figure 7A shown, superconducting current behavior is observed from 25 °C to 40 °C, indicating that this anomalous quantum Hall conduction should also exist in a similar temperature range. This room-temperature quantum Hall conduction can be observed under DC bias or AC bias in the frequency range from 1 Hz to 10 kHz (see Figure 9 and Figure 10 ).

[0043] B) Experimental examples

[0044] B1) Non-classical MIS device

[0045] Figure 1A An exemplary capacitive device is shown, which includes a high-mobility semiconductor 106 and a high-breakdown-strength dielectric 104. The high-mobility semiconductor 106 and the high-breakdown-strength dielectric 104 are formed into plate shapes and are sandwiched between a top electrode 102 and a bottom electrode 108. For example, the dielectric 104 can be a three-layer alumina / silica / alumina composite. Figure 1B - 1C is a cross-sectional view of the device, which shows two components of the applied electric field: an out-of-plane component 114 and an in-plane component 112. Both the out-of-plane component 114 and the in-plane component 112 can come from the edge field 110, potentially causing Figure 1B 1D electron surface states 116 on Figure 1C or 2D electron gas 118 on

[0046] We unexpectedly found that, as in the example in Figure 1A - 1C , the device can exhibit the characteristics of quantum charge storage and quantum charge transport at room temperature. As shown in Figure 1B and Figure 1C , the applied electric field has both an out-of-plane and an in-plane component (114 and 112 respectively), thus triggering electron boundary states. A part of the injected electrons is converted into a topological phase in the form of 1D electron surface states or 2D electron gas states. This device operates at room temperature and only uses the applied electric field to trigger 1D or 2D electron gas. The resulting unique state can be driven as in Figure 1DThe indicated topological state or chargeless Majorana phase. More specifically, Figure 1D 120 in Figure 1D is a schematic representation of the topological state, and

[0047] Typical geometric parameters of such a device are as follows. The dielectric 104 can be a 100 nm thick three-layer alumina / silica / alumina composite material. The semiconductor layer 106 preferably has a conductivity of at least 0.001 S / cm and is typically at least 150 nm thick. In the following example, the semiconductor 106 is p-doped silicon. The exemplary rectangular device has a width of 0.2 μm to 250 μm and a length of 1 μm to 250 μm. The exemplary circular device has a diameter of 2 μm to 100 μm.

[0048] An exemplary charging method is to connect the positive and negative electrodes of the source measurement unit to the top electrode and the bottom electrode of the device, respectively. Then, a linear voltage sweep is applied: starting from 0 V, reaching a maximum voltage of 15 V, and then sweeping back to 0 V. The typical ramp rate of this sweep is 10 - 500 mV / s. The current-voltage characteristics from the sweep usually show a "peak current" at the "critical voltage" (i.e., we see an abnormal feature where the current does not increase monotonically with voltage). This critical voltage typically varies in the range from 3 V to 8 V. These high-current characteristics at the critical voltage allow a supercurrent to pass through the sample. A current sweep can also be performed instead of a voltage sweep.

[0049] B2) Lateral transport

[0050] In this research work, we also considered the lateral coupling of two devices, as considered above. Figure 2A - 2B An example is shown. Here, 204 is the central island and 206 is the surrounding ring, both of which are devices as described above in the vertical direction. They are fabricated via photolithography and etching processes on a highly conductive p-type Si wafer 106 with a conductivity of at least 0.001 S / cm. Figure 2B A detailed cross-sectional view is shown. Here, both electrodes 102a and 102b are on the top, and the relevant edge fields include the edge fields 110 from island to island and from ring to ring, as well as the edge field 210 coupling the island and the ring. The details of the edge fields mainly depend on the gap width or distance between the structures. So far, we have experimentally seen that the gap width between two devices with non-classical coupling is from 1 μm to 450 μm. In the case of a short gap width (e.g., on the order of 1 μm), the adjacent edge field 210 will be very important. In the case of a large gap width, there will be no influence from the adjacent edge field 210. It is currently believed that this is why a large gap width requires repeated cycling.

[0051] For such a set of two structures that independently exhibit high vertical currents (such as Figure 2A - 2B the loop 206 and the island 204 in

[0052] ), charge can be laterally driven by connecting one structure to ground and simultaneously biasing the other structure (e.g., using top electrodes 102a and 102b). During this process, high currents are observed in both structures, even extending over longer lateral distances with little current loss. If one structure does not exhibit a large vertical current, this phenomenon is not observed. Figure 2B More specifically, in these examples, the setup for achieving lateral supercurrent begins with using semiconductor 106 as the bottom electrode and vertically biasing 204 and 206 individually to their respective critical voltages (which can be the same or different). Then, the electrical connection to semiconductor 106 is removed and the applied voltage is between the two top electrodes (e.g.,

[0053] in Figure 2B 102a and 102b). Thus, there is a memory effect where devices 204 and 206 maintain their non-classical behavior even when they are not vertically biased. As shown below, the lateral supercurrent depends on these devices being in their non-classical states, and when these states are disrupted (e.g., perturbed), the lateral supercurrent is also disrupted. Figure 2B As

[0054] shown, each independent structure will self-initiate an edge field 110 with respect to the charge passing through it. However, the edge fields will also interact with each other ( Figure 3 210 in

[0055] Figure 2B ), which helps initiate the formation of topological electrons on each device. This current transfer is not instantaneous in all cases. For structures separated by a long distance, the in-plane charge transfer must be cycled several times before the structure connected to ground shows a near-lossless current transfer from the first structure. The number of cycles required to establish the current transfer is related to the distance between the structures. For example, for a distance of about 450 μm, at least 10 cycles of voltage cycling are required.

[0054] When this transfer, measured as current, varies with time, the resulting I-V curve shows that the voltage remains relatively stable while the current continues to increase, as Figure 3 shown. This trend will continue, where the voltage oscillates basically within a small range until the current reaches its maximum value. After exceeding this value, the current will decrease and the voltage will maximize to the limit value of the system measurement unit.

[0055] An exemplary charging method for lateral current conduction is to apply a linear current sweep, such as starting with a current of 0 A, a maximum current in the range of 40 - 800 μA, and a ramp rate of 16 nA / s - 16 μA / s. In the case of repeatedly performing the current sweep, the scans used so far have a sawtooth waveform (i.e., a sudden transition from the maximum current to no current to start the next iteration).

[0056] Figure 3 An exemplary I - V curve from such a device is shown. In the range of 4.0 V to 4.8 V, the current steadily rises continuously. This eventually stops after the current exceeds 60 μA.

[0057] By serially connecting or joining such devices in series, we can be able to accommodate the transport of superconducting current at room temperature. To utilize the supercurrent from surface states or from topological surface states (including Majorana modes), we can connect multiple capacitors (e.g., 402a, 402b...) together in a loop by contact or having dedicated bridges (e.g., 404a, 404b...) respectively, as Figure 4A and Figure 4B shown. With this connected capacitor geometry, we expect that the supercurrent observed in a single capacitor can travel laterally in - plane direction through multiple connected capacitors. In this way, the in - plane transport will not be limited by the conductivity of the material, but by the effectiveness of promoting superconducting surface states.

[0058] Note that the bridges or contact points of the continuous loop can vary. In particular, an annular structure with one or more bridges that are symmetric or asymmetric (including overlapping) with respect to the center line can be beneficial for the superconducting transport mode.

[0059] B3) Shut off lateral transport via perturbation

[0060] The applied perturbation can destabilize the protected state and terminate the coherence of the superconducting state. More specifically, the disruption of the protected state means that one or two adjacent semiconductor devices lose their superconducting state coherence.

[0061] Figure 5A and Figure 5B respectively depict the device behavior with and without communication (i.e., before and after perturbation).

[0062] Suitable perturbation methods include but are not limited to: applying an externally generated electric field above the critical voltage, operating temperature control, magnetic field, radio frequency, and laser beam processing. Two examples are as follows.

[0063] As Figure 6 shown, applying a sudden voltage ramp above the critical voltage (V 临界 ) can turn off the device. As Figure 7A - 7BAs shown, applying high-temperature heating can turn off the device. Figure 7A It is shown that this particular device is in the on-state from 25 °C to 40 °C, Figure 7B and it is shown that a temperature of 50 °C turns the device into the off-state.

[0064] Figure 8A - 8D Some examples of how such a perturbation can be applied to laterally connected devices are schematically shown. In Figure 8A the example, the perturbation 802 is applied at the contact point between devices 402a and 402b. In Figure 8B the example, the perturbation 802 is applied to the bridge 404 connecting devices 402a and 402b. In Figure 8C the example, the perturbation 802 is applied directly to one of the devices (device 402a). In Figure 8D the example, the connecting devices 804a and 804b are a multi-ring structure, and the perturbation 802 is applied to the inner ring of one of the devices.

[0065] B4) Observation of the room-temperature quantum Hall effect

[0066] By applying a linear DC voltage sweep to our metal-insulator-semiconductor (MIS) device in the vertical direction, an anomalously high current is generated due to the formation and transport of topological chargeless edge / surface states at and through the conductor / insulator interface at several critical voltages. When a constant DC bias is applied in the vertical direction at these critical voltages, the device exhibits integer and fractional quantum Hall resistance values. Figure 9 Shows the resistance values centered around the fractional quantum Hall state, where the quantum Hall filling factor is

[0067] When another device with the same MIS structure is perturbed by an AC voltage centered at the critical voltage in the vertical direction, it shows resistance values within 0.5% of the integer quantum Hall resistance corresponding to ν = 1, which is also due to the topological edge / surface states induced by the previous linear voltage and current sweeps. As Figure 10 shown, during an AC frequency sweep varying in the range from 1 Hz to 10 kHz, this impedance value stabilizes at the quantum Hall resistance level of ν = 1.

[0068] An exemplary charging method for demonstrating such a quantum Hall effect is as follows:

[0069] 1) Apply a constant bias voltage at the "critical voltage". The critical voltages of the two devices shown in this observation are 7.7 V ( Figure 9 ) and 3.5 V ( Figure 10 ), respectively.

[0070] 2) Then, observe the change in the current response to calculate the device resistance (voltage divided by current). Alternatively, apply a small sinusoidal voltage (AC voltage) and sweep through different frequencies to obtain the impedance spectrum of the device. Here, the root mean square value of the AC voltage can be in the range of 50 - 200 mV, with frequencies ranging from 1 Hz to 10 kHz.

Claims

1. A method for providing lateral supercurrent transport between two MIS structures, the method comprising: forming a first low-dimensional electron gas in a first MIS (metal-insulator-semiconductor) structure, wherein a first applied voltage to the first MIS structure generates a first electric field component parallel to and perpendicular to the first low-dimensional electron gas; forming a second low-dimensional electron gas in a second MIS structure, wherein a second applied voltage to the second MIS structure generates a second electric field component parallel to and perpendicular to the second low-dimensional electron gas; wherein the first MIS structure has a first topological state formed by injecting charge carriers; wherein the second MIS structure has a second topological state formed by injecting charge carriers; and laterally coupling the first MIS structure to the second MIS structure.

2. The method according to claim 1, further comprising: cycling a laterally applied voltage until the lateral transport between the first MIS structure and the second MIS structure exhibits an anomalously low resistance.

3. The method according to claim 2, further comprising: turning off the lateral transport with an anomalously low resistance by applying a perturbation to the first MIS structure and / or the second MIS structure sufficient to disrupt the topological state.

4. The method according to claim 3, wherein the perturbation is selected from the group consisting of: applying an electrical bias, applying a temperature rise, applying a magnetic field, applying an electromagnetic field, applying a radio frequency signal, and applying a laser beam.

5. The method according to claim 1, wherein the first MIS structure is laterally connected to the second MIS structure by direct lateral contact.

6. The method according to claim 1, wherein the first MIS structure is laterally connected to the second MIS structure with a connecting element.

7. The method according to claim 6, the method further comprising: turning off the lateral transport with an anomalously low resistance by applying a perturbation to the connecting element sufficient to disrupt the topological state.

8. The method according to claim 7, wherein the perturbation is selected from the group consisting of: applying an electrical bias, applying a temperature rise, applying a magnetic field, applying an electromagnetic field, applying a radio frequency signal, and applying a laser beam.

9. The method according to claim 1, wherein the first topological state is formed by: cycling the voltage of the first MIS structure until the vertical transport through the first MIS structure exhibits one or more characteristics of quantum Hall conduction.

10. The method according to claim 1, wherein the second topological state is formed by: cycling the voltage of the second MIS structure until the vertical transport through the second MIS structure exhibits one or more characteristics of quantum Hall conduction.

11. A method for forming a topological quantum state in a metal-insulator-semiconductor (MIS) structure, the method comprising: cycling the voltage of the MIS structure until the vertical transport through the MIS structure exhibits one or more characteristics of quantum Hall conduction; wherein the MIS structure includes a two-dimensional electron gas, and wherein an applied voltage to the MIS structure generates electric field components parallel and perpendicular to the two-dimensional electron gas.

12. The method of claim 11, wherein the MIS structure can be at a temperature of 25°C to 40°C, and wherein the quantum Hall conduction is observed in the absence of an applied magnetic field.

13. The method of claim 11, wherein the quantum Hall conduction is observed under a DC bias or an AC bias in a frequency range from 1 Hz to 10 kHz.

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