High-voltage avalanche detection circuit applied to Geiger APD array

Abstract

The invention relates to the technical field of integrated circuit testing, in particular to a high-voltage avalanche detection circuit applied to a Geiger avalanche photodiode (APD) array, which comprises a high-voltage N-channel metal oxide semiconductor (NMOS) tube NMOS1, three high-voltage P-channel metal oxide semiconductor (PMOS) tubes PMOS1-PMOS3, a Geiger avalanche photodiode (APD), two high-voltage junction field effect transistor (JFET) tubes JFET1 and JFET2 and a resistor R1, in the high-voltage avalanche detection process, the use of a capacitor element is avoided, and a direct-coupled current mirror shunt structure is adopted, so that single-chip integration is easy; by selecting circuit elements with specific parameters, current-limiting and voltage-limiting protection is respectively carried out on a current mirror input branch and a voltage sampling branch, so that the damage risk of a high-voltage pulse signal to an avalanche detection circuit and a rear-end processing circuit is effectively eliminated.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and particularly to a high-voltage avalanche detection circuit applied to a Geiger APD array. Background Art

[0002] Geiger avalanche photodiodes (APDs) are widely used in the detection of weak optical signals such as single photons due to their high sensitivity and fast detection capabilities. However, they need to operate in an overbias state above the breakdown voltage. When a photon avalanche trigger occurs and the device is in an overly high overbias state for a long time, it will shorten the device life and even cause component damage. Therefore, an external control module is required to achieve avalanche quenching and reset. The key technical problems in this field include: High-voltage detection challenges: The avalanche detection circuit needs to be isolated from the high-voltage APD. The overbias voltage reaches dozens of volts. Traditional AC coupling schemes rely on nF-level large-capacitance capacitors to transfer voltage pulses, but it is difficult to implement high-voltage withstand and large-capacitance capacitors within a limited area in the integrated circuit process; Integration bottleneck: When APDs develop towards focal plane arrays, the control circuit needs to be monolithically integrated. However, the process limitations of capacitors and high-voltage devices in the existing technologies hinder the integration; Negative voltage risk: During the quenching process, the high-voltage NMOS transistor pulling down the cathode voltage will generate a negative high-voltage pulse at the detection end through the coupling capacitor, which may break down the integrated control circuit.

[0003] Figure 1 As a common high-voltage avalanche detection circuit in the prior art, the existing technical solutions have the following problems: The contradiction between the large-capacitance requirement and the integration process, and the insufficient high-voltage tolerance; The negative voltage pulse caused by the quenching action threatens the circuit reliability, especially for monolithic integrated systems.

[0004] Therefore, there is an urgent need for a detection circuit that can safely and effectively detect the high-voltage avalanche current of a large array of Geiger APDs in a limited space. Summary of the Invention

[0005] In view of this, the present invention discloses a high-voltage avalanche detection circuit applied to a Geiger APD array to solve the above problems, including: 1 high-voltage NMOS transistor NMOS1, 3 high-voltage PMOS transistors PMOS1 to PMOS3, 1 Geiger avalanche photodiode APD, 2 high-voltage JFET transistors JFET1 and JFET2, and a resistor R1; The connection method is as follows: The drain of NMOS1 is respectively connected to the drain of PMOS1, the cathode of APD, the source of JFET1, and the gate of JFET1; The source of PMOS1 is respectively connected to the sources of PMOS2 and PMOS3; The drain of JFET1 is respectively connected to the drain of PMOS2, the gate of PMOS2, and the gate of PMOS3; The drain of PMOS3 is connected to the drain of JFET2; The gate of JFET2 is respectively connected to the source of JFET2 and one end of R1.

[0006] In the high-voltage avalanche detection process of the present invention, the use of capacitive elements is avoided, and a directly coupled current mirror shunt structure is adopted, which is easy for chip integration; by selecting circuit elements with specific parameters, current limiting and voltage limiting protection are respectively carried out on the input branch of the current mirror and the voltage sampling branch, thereby effectively eliminating the damage risk of high-voltage pulse signals to the avalanche detection circuit itself and the subsequent processing circuit. Description of the Drawings

[0007] Figure 1 is the high-voltage avalanche detection circuit in the prior art;

[0008] Figure 2 is the high-voltage avalanche detection circuit applied to the Geiger APD array in the present invention. Detailed Embodiment

[0009] In order to make the purpose, technical solution, features and advantages of the present invention clearer, the present invention will be further described below in conjunction with the drawings and embodiments.

[0010] This embodiment includes a high-voltage avalanche detection circuit applied to a Geiger APD array, including: 1 high-voltage NMOS transistor NMOS1, 3 high-voltage PMOS transistors PMOS1 to PMOS3, 1 Geiger avalanche photodiode APD, 2 high-voltage JFET transistors JFET1 and JFET2, and a resistor R1. Among them, JFET1 and JFET2 are N-type channel.

[0011] As Figure 2 shown, the connection method is as follows: the drain of NMOS1 is respectively connected to the drain of PMOS1, the cathode of APD, the source of JFET1, and the gate of JFET1; the source of PMOS1 is respectively connected to the source of PMOS2 and the source of PMOS3; the drain of JFET1 is respectively connected to the drain of PMOS2, the gate of PMOS2, and the gate of PMOS3; the drain of PMOS3 is connected to the drain of JFET2; the gate of JFET2 is respectively connected to the source of JFET2 and one end of R1.

[0012] Further, the gate of NMOS1 is used to receive a quenching control signal, and the drain of NMOS1 is used to quench the APD; PMOS1 is used to receive a reset control signal and reset the APD; the source of PMOS1 is connected to the high level VH, serving as the power supply terminal of the circuit; the anode of the APD is connected to the negative high level VB; PMOS2 and PMOS3 form a current mirror circuit structure for current shunt sampling; JFET1 is used for voltage division and current limiting; the source of JFET2 is connected to a subsequent pulse voltage detection module, which is used to compare and shape the input voltage pulse and output a standard digital pulse signal available for signal processing; the other end of R1 is grounded; JFET2 and R1 form a voltage sampling circuit for converting the sampling current into a sampling voltage and sending the sampling voltage to the subsequent pulse voltage detection module.

[0013] Further, the source of PMOS2 serves as the power supply terminal of the current mirror circuit, the drain of PMOS2 serves as the input terminal, and the drain of PMOS3 serves as the output terminal.

[0014] Further, the drain of JFET2 serves as the input terminal of the voltage sampling circuit, the common terminal of JFET2 and R1 serves as the voltage output terminal, and the other end of R1 serves as the current output terminal.

[0015] The working principle of the present invention is as follows:

[0016] As Figure 2 shown, the drain of NMOS1 is connected to the drain of PMOS1 and is connected to the cathode of the APD to form an overbias node X; the drain of JFET1 is connected to the drain of PMOS2 to form a node Y; the common terminal of JFET2 and R1 forms a sampling voltage node Z.

[0017] When the reset control signal is valid and the quenching control signal is invalid, PMOS1 is turned on, and the voltage at node X is set to the positive high level VH. At this time, the voltage difference VH - VB across the APD is higher than the breakdown voltage, so it is in the Geiger mode of operation. At the same time, since the potential at node X is the positive high level VH and the potential at node Y is equal to that at node X, JFET1 and the current mirror circuit are both in the off state, and no current flows through the voltage sampling circuit. Therefore, the voltage at the sampling voltage node Y is the ground potential.

[0018] When the APD detects a photon and avalanches, a rapidly rising avalanche current is formed inside it, and the avalanche current pulls down the potential at the overbias node X. Since JFET1 is N-type and in a normally-on connection state, the voltage at node Y also decreases as the voltage at node X decreases. When the voltage difference between the voltage at node Y and the high voltage VH reaches the threshold turn-on voltage of PMOS2, the current mirror circuit is turned on, and the mirror current flows through PMOS3 into the voltage sampling circuit, thereby increasing the voltage at the sampling voltage node Y.

[0019] When the voltage at the sampling voltage node Y rises to reach the detection threshold of the pulse voltage detection module, the quenching control signal turns on NMOS1, quickly pulling down the potential at the overbias node X to the ground potential. At this time, the voltage difference 0 - VB across the APD is lower than the breakdown voltage, and the APD exits the avalanche multiplication state.

[0020] In the integrated circuit process, to improve the switching speed of high-voltage MOS transistors and reduce the on-resistance, the drain drift region of high-voltage MOS transistors is usually used to withstand high voltages, while the source uses a common MOS transistor structure. Therefore, generally, dozens of volts of high voltage can be withstood between the source and drain, and between the gate and drain, while only a few volts of voltage can be withstood between the gate and source. In this embodiment, the maximum saturation current of the selected JFET1 is less than or equal to the drain current of PMOS2 when it reaches the maximum gate-source breakdown voltage. Under the above design conditions, whether the voltage at the overbias node X is affected by the avalanche current or the quenching pull-down, the voltage difference between the voltage at node Y and the high voltage VH will not exceed the maximum gate-source breakdown voltage of PMOS2. Therefore, the risk of the current mirror circuit being broken down and burned out is effectively eliminated.

[0021] The signal processing circuit of the APD array usually needs to adopt a single-chip integration solution, otherwise its power consumption and volume will be very large. To reduce the power consumption of the circuit and improve the signal processing rate of the circuit, the pulse voltage detection module and other subsequent processing circuits all adopt a low-voltage design system. Due to the unit area limitation of the chip array, and at the same time, the area of high-voltage devices with a breakdown voltage of dozens of volts is relatively large, the current mirror ratio of the current mirror circuit is usually small. Therefore, during implementation, to prevent the voltage at the sampling voltage node Z from exceeding the maximum breakdown voltage at the input end of the pulse voltage detection module, that is, the product of the maximum saturation current of JFET2 and R1 is less than or equal to the maximum breakdown voltage at the input end of the pulse voltage detection module.

[0022] Compared with the prior art, the present invention avoids using a large high-voltage-resistant capacitor during the high-voltage avalanche detection process. Instead, it adopts a directly coupled current mirror shunt structure, which is easy to integrate on a single chip. By selecting circuit elements with specific parameters, current limiting and voltage limiting protection are respectively carried out on the input branch of the current mirror and the voltage sampling branch, eliminating the risk of damage to the avalanche detection circuit itself and the subsequent processing circuit caused by high-voltage pulse signals.

[0023] Finally, it should be noted that the above description only depicts some embodiments of the present invention. For those skilled in the art, various changes, modifications, substitutions, and deformations can be conceived without departing from the principle and spirit of the present invention. The protection scope of the present invention is defined by the appended claims and their equivalents, and the above actions should all be covered within the protection scope of the present invention.

Claims

1. A high voltage avalanche detection circuit for a Geiger APD array, characterized in that: include: 1 high-voltage NMOS tube NMOS1, 3 high-voltage PMOS tubes PMOS1~PMOS3, 1 Geiger avalanche photodiode APD, 2 high-voltage JFET tubes JFET1 and JFET2, and a resistor R1; The connection method is as follows: the drain of NMOS1 is respectively connected to the drain of PMOS1, the cathode of APD, the source of JFET1, and the gate of JFET1; the source of PMOS1 is respectively connected to the source of PMOS2 and the source of PMOS3; the drain of JFET1 is respectively connected to the drain of PMOS2, the gate of PMOS2, and the gate of PMOS3; the drain of PMOS3 is connected to the drain of JFET2; the gate of JFET2 is respectively connected to the source of JFET2 and one end of R1.

2. The high voltage avalanche detection circuit for use with a Geiger APD array according to claim 1, characterized in that: The gate of NMOS1 is used to receive a quenching control signal, and the drain of NMOS1 is used to quench the APD.

3. The high voltage avalanche detection circuit for use with a Geiger APD array according to claim 1, characterized in that: PMOS1 is used to receive a reset control signal and reset the APD.

4. The high voltage avalanche detection circuit for Geiger APD array according to claim 1, characterized in that: PMOS2 and PMOS3 form a current mirror circuit structure; the source of PMOS2 serves as a power supply terminal of the current mirror circuit, the drain of PMOS2 serves as an input terminal, and the drain of PMOS3 serves as an output terminal.

5. The high voltage avalanche detection circuit for use with a Geiger APD array according to claim 4, characterized in that: JFET2 and R1 form a voltage sampling circuit, which serves as the output end of the high-voltage avalanche detection circuit applied to the Geiger APD array; the drain of JFET2 serves as the input end of the voltage sampling circuit, and the common end of R1 and JFET2 serves as the voltage output end.

6. The high voltage avalanche detection circuit for use in a Geiger APD array according to claim 1, characterized in that: JFET1 and JFET2 are N-type channel high voltage JFET tubes.

7. The high voltage avalanche detection circuit for use in a Geiger APD array according to claim 1, characterized in that: The maximum saturation current of JFET1 is less than or equal to the drain current of PMOS2 when the maximum gate-source withstand voltage is reached.

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