Multi-channel weak current time-sharing detection system

Abstract

The invention discloses a multi-channel weak current time-sharing detection system, and relates to the technical field of current detection. The detection system comprises N transimpedance amplifiers, a multi-stage multiplexer, a filter amplification circuit, an ADC analog-to-digital converter and a single-chip microcomputer. Through time-sharing detection, circuit composition is simplified, multi-channel time-sharing detection is realized, and hardware complexity and cost of a multi-channel weak current signal acquisition system are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of current detection, and particularly relates to a multi-channel weak current time-sharing detection system. Background Art

[0002] In many applications, such as biomedical signal detection, chemical sensor signal acquisition, optoelectronic sensor signal acquisition, etc., it is necessary to perform high-precision measurement on weak current signals of multiple channels. Traditional multi-channel measurement schemes often have problems such as large noise interference, low measurement accuracy, and complex systems. In particular, traditional multi-channel current detection systems often require multiple sets of repeated circuits for measurement. Each channel is the same and independent. Its advantage is that each channel can be measured simultaneously, and in scenarios where the signal changes rapidly over time, the current signals of multiple channels at the same time can be measured, with a relatively high time resolution. However, its disadvantage is that the independent repetition of multiple channels results in low system integration, causing waste of space and resources. At the same time, weak current signals are sensitive to noise, and more complex circuits will deepen the mutual interference within the system. Therefore, a multi-channel weak current detection system with higher integration and greater simplicity is needed.

[0003] In summary, traditional multi-channel weak current detection systems have problems of high repeatability, high complexity, and large mutual interference. Summary of the Invention

[0004] In view of the deficiencies of the prior art, the present invention provides a multi-channel weak current time-sharing detection system. Through time-sharing detection, the present invention simplifies the circuit composition and solves the problems of high repeatability, high complexity, and large mutual interference existing in traditional multi-channel weak current detection systems.

[0005] The technical solution adopted by the present invention is as follows: A multi-channel weak current time-sharing detection system includes N transimpedance amplifiers, a multi-stage multiplexer, a filter amplification circuit, an ADC analog-to-digital converter, and a single-chip microcomputer; Wherein, the N transimpedance amplifiers are used to convert N current input signals to be detected into voltage signals and input them into the multi-stage multiplexer; The multi-stage multiplexer includes stages of multiplexers; wherein, two of the N voltage signals are input into a first-stage multiplexer as a group and output one voltage signal as the input signal of the next-stage multiplexer; and so on until only one voltage signal is output; The filter amplification circuit is used to filter and amplify the voltage signal output by the multi-stage multiplexer to obtain an amplified voltage signal and input it into the ADC analog-to-digital converter; The ADC analog-to-digital converter is used to perform analog-to-digital conversion on the amplified voltage signal, obtain a digital signal and input it into the single-chip microcomputer; The single-chip microcomputer is used to control the channel selection of each multiplexer in the multi-stage multiplexer, so that the N voltage signals enter the filter amplification circuit in sequence and cyclically; it is also used to receive and store the digital signal for subsequent reading and calling.

[0006] Preferably, N is a positive integer greater than 4.

[0007] Preferably, [ ] represents rounding up. When is not an integer, the remaining one voltage signal directly skips and enters the next-level multiplexer.

[0008] Preferably, the transimpedance amplifier includes an operational amplifier, resistor R1, resistor R2, resistor R3, feedback resistor Rf, capacitor C1, capacitor C2, capacitor C3, and capacitor Cf; Among them, the model of the operational amplifier is OPA627; the non-inverting pin 2 of the operational amplifier is grounded through resistor R1 and parallel capacitor C1; the inverting pin 1 accesses the current input signal to be detected; the output pin 5 is connected to the inverting input pin 1 through feedback resistor Rf and parallel capacitor Cf. At the same time, the output pin 5 is connected to the input pin of the first-level multiplexer to output the voltage signal Vout; the positive voltage input pin 3 is connected to the positive voltage P+ through resistor R2 and grounded through capacitor C2 at the same time; the negative voltage input pin 4 is connected to the negative voltage P- through resistor R3 and grounded through capacitor C3 at the same time.

[0009] The beneficial effects of the present invention are as follows: 1. The present invention realizes multi-channel time-sharing detection, reducing the hardware complexity and cost of the multi-channel weak current signal acquisition system.

[0010] 2. The present invention improves the anti-noise ability of the signal link and enhances the signal-to-noise ratio.

[0011] 3. The present invention monolithically integrates the multiplexing filter amplification circuit and the ADC module, reducing the system volume by at least 50%. Description of the Drawings

[0012] Figure 1 It is the structural block diagram of the four-channel weak current time-sharing detection system in the embodiment; Figure 2 It is the circuit diagram of the transimpedance amplifier in the embodiment; Figure 3 It is the circuit diagram of the two-stage cascade structure of the multiplexer in the embodiment; Figure 4 It is the circuit diagram of the filter amplification circuit in the embodiment; Figure 5 This is the circuit diagram of the ADC analog-to-digital converter in the embodiment. Specific Embodiment

[0013] To better illustrate the purpose, advantages, and technical concept of the present invention, the following further elaborates on the present invention in combination with specific embodiments. It should be noted that the specific examples given below only serve to explain the present invention in detail and do not limit the present invention.

[0014] This embodiment provides a four-channel weak current time-sharing detection system, as Figure 1 shown, including: four transimpedance amplifiers: transimpedance amplifier 1, transimpedance amplifier 2, transimpedance amplifier 3, transimpedance amplifier 4, two first-level multiplexers: first-level multiplexer 1, first-level multiplexer 2, one second-level multiplexer, one filter amplification circuit, one ADC analog-to-digital converter, and one single-chip microcomputer.

[0015] The signal flow mode is that the weak current input signals of the four channels: signal 1, signal 2, signal 3, and signal 4 are respectively amplified and converted into voltage signals 1, voltage signals 2, voltage signals 3, and voltage signals 4 after passing through transimpedance amplifier 1, transimpedance amplifier 2, transimpedance amplifier 3, and transimpedance amplifier 4; among them, voltage signal 1 and voltage signal 2 enter first-level multiplexer 1, and voltage signal 3 and voltage signal 4 enter first-level multiplexer 2; under the control of the single-chip microcomputer (MCU), at each moment, one voltage signal in first-level multiplexer 1 is selected and output to the second-level multiplexer, and one voltage signal in first-level multiplexer 2 is selected and output to the second-level multiplexer. At the same time, the second-level multiplexer is controlled to select one voltage signal and output it to the filter amplification circuit; the filter amplification circuit filters and further amplifies the input voltage signal and then outputs it to the ADC analog-to-digital converter for analog-to-digital conversion; subsequently, the single-chip microcomputer receives and stores the data through the I2C protocol. Thus, one of the weak current signals of the four channels is converted, amplified, and read.

[0016] At different moments, by controlling the selection of first-level multiplexer 1, first-level multiplexer 2, and the second-level multiplexer, time-sharing detection of the weak current signals of all four channels can be achieved.

[0017] Next, specifically describe the specific composition and connection method of each part of the circuit, including: The model of the single-chip microcomputer can be the STM32F1XX series.

[0018] The transimpedance amplifier, as Figure 2As shown in the figure, it includes an operational amplifier, resistor R1, resistor R2, resistor R3, feedback resistor Rf, capacitor C1, capacitor C2, capacitor C3, and capacitor Cf. The model of the operational amplifier can be OPA627. The non-inverting pin 2 of the operational amplifier is grounded through resistor R1 and parallel capacitor C1. The inverting pin 1 is connected to the weak current signal to be detected. The output pin 5 is connected to the inverting input pin 1 through feedback resistor Rf and parallel capacitor Cf. At the same time, the output pin 5 is connected to the input pin of the first-stage multiplexer to output the voltage signal Vout. The positive voltage input pin 3 is connected to the positive voltage P+ through resistor R2 and grounded through capacitor C2. The negative voltage input pin 4 is connected to the negative voltage P- through resistor R3 and grounded through capacitor C3.

[0019] The two-stage cascaded structure of the multiplexer, taking the first-stage multiplexer and the second stage as an example, as Figure 3 shown. The models of the first-stage multiplexer and the second-stage multiplexer can be SN74LVC1G3157. In the first-stage multiplexer, the input pins 1, 3, 7, and 9 are respectively connected to the voltage signals of four channels. The GND pin 2 is grounded. The VCC pins 5 and 11 are respectively connected to the power supply P. The control switch pins 4 and 10 are respectively connected to the output pins of the single-chip microcomputer. The output pins 6 and 12 are respectively connected to the input pins 13 and 15 of the second-stage multiplexer. In the second-stage multiplexer, the GND pin 14 is grounded. The VCC pin 17 is connected to the power supply P. The control switch is connected to the output pin of the single-chip microcomputer. The output pin 18 is connected to the filter amplification circuit to output the voltage signal Vslc to the filter amplification circuit.

[0020] The said filter amplification circuit, as Figure 4 shown, includes an operational amplifier, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, capacitor C4, capacitor C5, capacitor C6, and capacitor C7. The model of the operational amplifier can be OPA627. Its non-inverting input pin 1 is connected to the voltage signal Vslc through series resistor R5 and capacitor C4. At the same time, between capacitor C4 and resistor R5, it is grounded through resistor R4. The inverting input pin 2 is grounded. The output pin 5 is connected to the non-inverting input pin 1 through resistor R6. At the same time, the output pin 5 is grounded through resistor R8 and capacitor C6. Between resistor R8 and capacitor C6, it is connected to the non-inverting input pin of the ADC analog-to-digital converter, set to output the second-stage amplified voltage signal Vt to the ADC analog-to-digital converter. At the same time, the positive voltage input pin 3 is connected to the positive voltage P+ through resistor R7 and grounded through capacitor C7. The negative voltage input pin 4 is connected to the negative voltage P- through resistor R9 and grounded through capacitor C5.

[0021] The said ADC analog-to-digital converter, as Figure 5As shown in the figure, it includes an ADC analog-to-digital conversion unit, resistor R10, resistor R11, capacitor C8, and capacitor C9. The model of the ADC analog-to-digital conversion unit can be MCP3421. Its non-inverting input terminal pin 4 is connected to the secondary amplified voltage signal Vt, the inverting input terminal 1 and the Vss pin 2 are grounded, the Vdd pin is connected to the power supply P, and at the same time, it is grounded through two parallel capacitors C8 and C9. At the same time, the SCL pin 3 is connected to the pin of the single-chip microcomputer configured with the I2C protocol and is connected to the power supply P through the pull-up resistor R11. The SCL pin 6 is connected to the pin of the single-chip microcomputer configured with the I2C protocol and is connected to the power supply P through the pull-up resistor R10. The ADC analog-to-digital converter is configured to convert the input secondary amplified voltage signal Vt into a digital signal and input it into the single-chip microcomputer for reading and storage.

[0022] The model of the single-chip microcomputer can be the STM32F1XX series; it can control the channel selection of each multiplexer in the multi-stage multiplexer, so that the four-channel voltage signals enter the filter amplification circuit in sequence and cyclically; it is also used to receive and store digital signals for subsequent reading and calling.

Claims

1. A multi-channel weak current time-sharing detection system, characterized in that: It includes N transimpedance amplifiers, a multi-stage multiplexer, a filter amplifier circuit, an ADC analog-to-digital converter, and a single-chip microcomputer; Wherein, the N transimpedance amplifiers are used to convert the N current input signals to be detected into voltage signals and input them into the multi-stage multiplexer; The multi-stage multiplexer comprises A multiplexer of the first stage; wherein two of the N voltage signals are input into a multiplexer of the first stage in a group, and one voltage signal is output as an input signal of the next multiplexer; and so on and so forth, until only one voltage signal is output; The filtering and amplifying circuit is used to filter and amplify the voltage signal output by the multi-stage multiplexer, obtain the amplified voltage signal and input it into the ADC analog-to-digital converter; The ADC is used to convert the amplified voltage signal into a digital signal and input the digital signal into the single chip microcomputer; The single chip microcomputer is used to control the channel selection of each multiplexer in the multi-stage multiplexer, so that N-channel voltage signals enter the filter amplifier circuit in sequence and cyclically; it is also used to receive and store digital signals for subsequent reading and calling.

2. A multi-channel weak current time-sharing detection system as claimed in claim 1, characterized in that: N is a positive integer greater than 4.

3. A multi-channel weak current time-sharing detection system as claimed in claim 2, characterized in that: [ ] means rounding up. When it is not an integer, the remaining voltage signal directly enters the next-level multiplexer.

4. A multi-channel weak current time-sharing detection system as claimed in claim 3, characterized in that: The transimpedance amplifier comprises an operational amplifier, a resistor R1, a resistor R2, a resistor R3, a feedback resistor Rf, a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor Cf; Among them, the operational amplifier model is OPA627; the non-phase pin 2 of the operational amplifier is grounded through a resistor R1 and a parallel capacitor C1; the reverse pin 1 is connected to the current input signal to be detected; the output pin 5 is connected to the inverting input pin 1 through a feedback resistor Rf and a parallel capacitor Cf, and at the same time, the output pin 5 is connected to the input pin of a first-level multiplexer, and the output voltage signal Vout; the positive voltage input pin 3 is connected to the forward voltage P+ through a resistor R2, and is grounded through a capacitor C2; the negative voltage input pin 4 is connected to the reverse voltage P- through a resistor R3, and is grounded through a capacitor C3.

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