A multi-channel parallel data processing system based on FPGA and suitable for various SAR imaging algorithms

Abstract

The application discloses a multi-channel parallel data processing system based on FPGA and suitable for various SAR imaging algorithms, and belongs to the technical field of radar imaging signals.The system is suitable for the multi-channel parallel data processing system of various SAR imaging algorithms, has three different data writing and reading operations, can be flexibly adjusted through parameters, and can use single DDR or multiple DDRs, so that the system has strong universality and is suitable for various SAR imaging algorithms with azimuth and range processing; eight-way parallel processing in the intermediate data processing process guarantees high-speed real-time imaging of the system.

Description

Technical Field

[0001] This invention belongs to the field of radar imaging signal technology, specifically relating to a multi-channel parallel data processing system based on FPGA suitable for various SAR imaging algorithms. Background Technology

[0002] Synthetic Aperture Radar (SAR), as a high-resolution imaging radar, boasts all-weather, all-day operation and the unique advantage of penetrating clouds and fog. It can acquire high-resolution radar images comparable to optical images under low visibility conditions and has been widely applied in military and civilian fields such as topographic mapping, resource surveys, and battlefield situational awareness. With the rapid development of hardware manufacturing technology, research on real-time SAR imaging systems continues to advance. However, the multi-dimensional transmission and storage of massive amounts of data involved in its imaging signal processing directly restricts the imaging processing speed, becoming a key challenge for current technological breakthroughs.

[0003] SAR imaging faces the challenge of processing large amounts of data. Traditional ground-based post-processing methods suffer from delays ranging from minutes to hours, failing to meet the high real-time requirements of scenarios such as UAV disaster monitoring and missile-borne image guidance. While DSP chips offer high-precision imaging advantages for real-time processing, their serial processing architecture struggles to overcome speed bottlenecks. In contrast, FPGAs are the preferred solution due to three core advantages: first, their hardware-level parallel processing architecture overcomes the limitations of traditional sequential operations; second, they incorporate abundant lookup table registers and programmable logic units, meeting the demands of high-speed sampling (up to GSps) and high-throughput data processing; and third, through pipelined design and hardware acceleration modules, they achieve microsecond-level latency, improving processing speed by 1-2 orders of magnitude compared to DSPs, thus meeting the stringent timeliness requirements of various application scenarios.

[0004] Currently, there are many types and forms of SAR imaging algorithms implemented using FPGA. For example, a single DDR is used to implement a SAR imaging algorithm, while multiple DDRs are used. A single system is only suitable for implementing a specific SAR imaging algorithm and is only applicable to a single imaging scenario. For example, the CS SAR algorithm is suitable for scenarios such as small squint / frontal side-view, medium resolution, and point target imaging, which has significant limitations. Furthermore, the speed of processing radar echo data varies greatly when using different system architectures. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a multi-channel parallel data processing system based on FPGA that is suitable for various SAR imaging algorithms.

[0006] The technical problem addressed by this invention is solved as follows:

[0007] A multi-channel parallel data processing system based on FPGA suitable for various SAR imaging algorithms includes a serial-to-parallel conversion module, a DDR state control module, and a DDR and RAM data ping-pong conversion module;

[0008] The DDR status control module is used to control the status of the DDR. There are four statuses: 1) 00 indicates that the DDR is not performing read or write operations; 2) 01 indicates that the DDR is sequentially writing and reading data; 3) 10 indicates that the DDR is performing a transpose operation from azimuth to range; 4) 11 indicates that the DDR is performing a transpose operation from range to azimuth.

[0009] Let the bit width of radar echo data be N bits, where the horizontal direction is range and the vertical direction is azimuth, and N is a positive integer; the bit width of DDR read / write is 16N bits.

[0010] When the DDR state is 01, the serial-to-parallel conversion module receives 8Nbits of input data at a time and converts it into 16Nbits of data, which is then input to the DDR group state control module. The DDR group state control module sequentially stores the 16Nbits of data into the DDR, and then sequentially reads the 16Nbits of data out to the RAM data ping-pong conversion module. The RAM ping-pong conversion module converts the 16Nbits of data into 8Nbits of data, and then the 8Nbits of data are divided into 8 parallel outputs.

[0011] When the DDR state is 10, the horizontal direction of the input data is the azimuth direction and the vertical direction is the range direction. The serial-to-parallel conversion module receives 8Nbits of input data and converts it into 16Nbits of data, which is then input to the DDR group state control module. The DDR group state control module transposes the 16Nbits of data and stores it in the DDR. Then, it transposes and reads the 16Nbits of data to the RAM data ping-pong conversion module to complete the transposition of the data from the azimuth direction to the range direction. The RAM ping-pong conversion module converts the 16Nbits of data into 8Nbits of data, which is then divided into 8 parallel outputs.

[0012] When the DDR state is 11, the horizontal direction of the input data is the range direction and the vertical direction is the azimuth direction. The serial-to-parallel conversion module receives 8Nbits of input data and converts it into 16Nbits of data, which is then input to the DDR group state control module. The DDR group state control module transposes the 16Nbits of data and stores it in the DDR, and then transposes and reads the 16Nbits of data to the RAM data ping-pong conversion module to complete the transposition of the input data from the range direction to the azimuth direction. The RAM ping-pong conversion module converts the 16Nbits of data into 8Nbits of data, and the 8Nbits of data are divided into 8 parallel outputs.

[0013] When the DDR status is 00, the DDR does not perform any operations.

[0014] Furthermore, when the multi-channel parallel data processing system implements an algorithm that includes M write and read operations, it inputs a 2Mbits parameter to the DDR status control module of the multi-channel parallel data processing system to control the different read and write states of the DDR and their sequential changes; in the 2Mbits parameter, the 2m-1th bit and the 2mth bit represent the mth DDR read and write state, and 1≤m≤M.

[0015] Furthermore, when the system is used to implement the Chirp Scaling SAR imaging algorithm, it includes three data write and read operations, M=3, which are range to azimuth transpose, azimuth to range transpose, and range to azimuth transpose, respectively; the 6-bit parameter input to the DDR status control module of the multi-channel parallel data processing system is 111011.

[0016] Furthermore, when the system is used to implement the Chirp Scaling SAR imaging algorithm, it includes three data write and read operations, M=3, which are sequential write and read data, range to azimuth transpose, and azimuth to range transpose, respectively; the 6-bit parameter input to the DDR status control module of the multi-channel parallel data processing system is 011110.

[0017] The beneficial effects of this invention are:

[0018] The system described in this invention is applicable to multi-channel parallel data processing systems for various SAR imaging algorithms. It has three different data write and read operations, which can be flexibly adjusted by parameters and can use either a single DDR chip or multiple DDR chips. This makes the system highly versatile and suitable for various SAR imaging algorithms with azimuth and range processing. The intermediate data processing process uses eight-channel parallel processing to ensure high-speed real-time imaging of the system. Attached Figure Description

[0019] Figure 1 This is a block diagram illustrating the implementation of the multi-channel parallel data processing system described in this invention.

[0020] Figure 2 This is a flowchart illustrating the specific process of using the Chirp Scaling SAR imaging algorithm in the system described in this invention.

[0021] Figure 3 This is a schematic diagram of data transformation used in the Chirp Scaling SAR imaging algorithm of the system described in this invention;

[0022] Figure 4 This is a flowchart illustrating the specific process of the PCS SAR imaging algorithm used in the system described in this invention.

[0023] Figure 5This is a schematic diagram of data transformation used in the PCS SAR imaging algorithm of the system described in this invention. Detailed Implementation

[0024] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0025] This embodiment provides a multi-channel parallel data processing system based on FPGA suitable for various SAR imaging algorithms. There are three different data write and read operations for processing a single radar image frame. One of the read and write operations is sequential, one is azimuth to range transpose, and one is range to azimuth transpose. The existence and order of these three read and write operations can be adjusted by parameters. By flexibly adjusting the three data write and read operations by using parameters, it can be made suitable for various SAR imaging algorithms with azimuth and range processing.

[0026] The multi-channel parallel data processing system described in this embodiment includes a serial-to-parallel conversion module, a DDR status control module, and a DDR and RAM data ping-pong conversion module.

[0027] The DDR status control module is used to control the status of the DDR, and there are four statuses: 1) 00 indicates that the DDR does not perform read or write operations; 2) 01 indicates that the DDR sequentially writes and reads data; 3) 10 indicates that the DDR performs a transpose operation from azimuth to range; 4) 11 indicates that the DDR performs a transpose operation from range to azimuth.

[0028] The bit width of radar echo data is N bits, with the horizontal direction representing range and the vertical direction representing azimuth; the bit width of a single DDR read / write operation is 16 N bits.

[0029] When the DDR state is 01, the serial-to-parallel conversion module receives 8Nbits of input data at a time and converts it into 16Nbits of data, which is then input to the DDR group state control module. The DDR group state control module sequentially stores the 16Nbits of data into the DDR, and then sequentially reads the 16Nbits of data out to the RAM data ping-pong conversion module. The RAM ping-pong conversion module converts the 16Nbits of data into 8Nbits of data, and then the 8Nbits of data are divided into 8 parallel outputs.

[0030] When the DDR state is 10, the horizontal direction of the input data is the azimuth direction and the vertical direction is the range direction. The serial-to-parallel conversion module receives 8Nbits of input data and converts it into 16Nbits of data, which is then input to the DDR group state control module. The DDR group state control module transposes the 16Nbits of data and stores it in the DDR. Then, it transposes and reads the 16Nbits of data to the RAM data ping-pong conversion module to complete the transposition of the data from the azimuth direction to the range direction. The RAM ping-pong conversion module converts the 16Nbits of data into 8Nbits of data, which is then divided into 8 parallel outputs.

[0031] When the DDR state is 11, the horizontal direction of the input data is the range direction and the vertical direction is the azimuth direction. The serial-to-parallel conversion module receives 8Nbits of input data and converts it into 16Nbits of data, which is then input to the DDR group state control module. The DDR group state control module transposes the 16Nbits of data and stores it in the DDR, and then transposes and reads the 16Nbits of data to the RAM data ping-pong conversion module to complete the transposition of the input data from the range direction to the azimuth direction. The RAM ping-pong conversion module converts the 16Nbits of data into 8Nbits of data, and the 8Nbits of data are divided into 8 parallel outputs.

[0032] When the DDR status is 00, the DDR does not perform any operations.

[0033] When a multi-channel parallel data processing system implements an algorithm involving three data write and read operations, it inputs a 6-bit parameter to the DDR status control module of the multi-channel parallel data processing system to control the different read and write states of the DDR and their sequential changes. In the 6-bit parameter, the first two bits control the first DDR read and write state, the middle two bits control the second DDR read and write state, and the last two bits control the third DDR read and write state.

[0034] Example 1

[0035] The radar echo data used in this embodiment has 32 bits per point, of which the first 16 bits represent the real part and the last 16 bits represent the imaginary part. In order to realize a radar imaging system with high real-time performance, eight parallel data processing channels are used and the DDR throughput data width is 512 bits.

[0036] The specific process of implementing the Chirp Scaling SAR imaging algorithm in the system described in this embodiment is as follows: Figure 2 As shown, there are three data write and read operations: range to azimuth transpose, azimuth to range transpose, and range to azimuth transpose. The 6-bit parameter input to the DDR status control module of the multi-channel parallel data processing system is 111011.

[0037] For a single frame of radar echo data, the serial-to-parallel conversion module receives 256 bits of input data and converts it into 512 bits, which are then input to the DDR group status control module. The DDR group control module performs range-to-azimuth transposition, storing the 512 bits of transposed data in the DDR, and then reading the transposed 512 bits into the RAM data ping-pong conversion module. The RAM ping-pong conversion module converts the 512 bits of data into 256 bits, which are then divided into eight parallel outputs. The output data from the RAM data ping-pong conversion module undergoes an eight-channel parallel azimuth FFT, followed by chirp scaling multiple multiplication, and the eight parallel data streams then enter the serial-to-parallel conversion module. The serial-to-parallel conversion module receives 256 bits of input data and converts it into 512 bits, which are then input to the DDR group status control module. The DDR group control module performs a transpose from azimuth to range, storing the 512 bits of transposed data in the DDR memory. The transposed 512 bits are then read out and sent to the RAM data ping-pong conversion module. The RAM ping-pong conversion module converts the 512 bits of data into 256 bits, which are then divided into eight parallel outputs. The RAM data ping-pong conversion module outputs data for an eight-channel parallel range-direction FFT, followed by RCMC and range-direction compressed multiplication, and then a range-direction IFFT. The eight parallel data streams then enter the serial-to-parallel conversion module. The serial-to-parallel conversion module receives 256 bits of input data and converts it into 512 bits, which are then input to the DDR group status control module. The DDR group control module performs range-to-azimuth transposition, storing the 512 bits of transposed data in the DDR memory, and then reading the transposed 512 bits into the RAM data ping-pong conversion module. The RAM ping-pong conversion module converts the 512 bits of data into 256 bits, which are then divided into eight parallel outputs. The output data from the RAM data ping-pong conversion module undergoes an eight-channel parallel azimuth IFFT to obtain the final imaging result.

[0038] The system described in this embodiment is used for data transformation in the Chirp Scaling SAR imaging algorithm, as follows: Figure 3 As shown, the size of a single frame of radar echo data is 8192*8192. The original radar echo data is in the range direction horizontally and the azimuth direction vertically. After the first range-to-azimuth transpose, the data becomes in the azimuth direction horizontally and the range direction vertically. After the second azimuth-to-range transpose, the data becomes in the range direction horizontally and the azimuth direction vertically. After the third range-to-azimuth transpose, the data becomes in the azimuth direction horizontally and the azimuth direction vertically.

[0039] Example 2

[0040] The specific process of implementing the PCS SAR imaging algorithm in the system described in this embodiment is as follows: Figure 4 As shown, there are three data write and read operations: sequential write and read, range to azimuth transpose, and azimuth to range transpose. The 6-bit parameter input to the DDR status control module of the multi-channel parallel data processing system is 011110.

[0041] The system described in this embodiment uses two DDR chips. After reading data from one DDR chip, the data is processed and sent to the other DDR chip for writing. While one DDR chip is reading, the other DDR chip is always writing data. This high-speed pipelined multi-channel parallel data processing greatly saves time and ensures the high real-time performance of the entire radar imaging system.

[0042] For a single frame of radar echo data, the serial-to-parallel conversion module receives 256 bits of input data at a time and converts it into 512 bits of data, which is then input to the DDR group status control module. The DDR group control module sequentially writes and reads the radar echo data, storing the 512 bits of data sequentially into the DDR, and then sequentially reading the 512 bits of data into the RAM data ping-pong conversion module. The RAM ping-pong conversion module converts the 512 bits of data into 256 bits of data, which is then divided into eight parallel outputs. The data output from the RAM data ping-pong conversion module undergoes eight parallel operations in sequence: complex multiplication, range-directed FFT, complex multiplication, range-directed IFFT, and complex multiplication. The eight parallel data streams then enter the serial-to-parallel conversion module. The serial-to-parallel conversion module receives 256 bits of input data and converts it into 512 bits, which are then input to the DDR group status control module. The DDR group control module performs range-to-azimuth transposition, transposes the 512 bits of data into the DDR, and then reads the transposed 512 bits into the RAM data ping-pong conversion module. The RAM ping-pong conversion module converts the 512 bits of data into 256 bits, which are then divided into eight parallel outputs. The output data from the RAM data ping-pong conversion module undergoes eight parallel operations in sequence: complex multiplication, azimuth FFT, complex multiplication, azimuth IFFT, complex multiplication, azimuth FFT, and complex multiplication. The eight parallel data streams then enter the serial-to-parallel conversion module. The serial-to-parallel conversion module receives 256 bits of input data and converts it into 512 bits, which are then input to the DDR group status control module. The DDR group control module performs azimuth-to-range transposition, storing the 512 bits of transposed data in the DDR memory, and then reading the transposed 512 bits into the RAM data ping-pong conversion module. The RAM ping-pong conversion module converts the 512 bits of data into 256 bits, which are then divided into eight parallel outputs. An eight-channel parallel range FFT is performed on the output data from the RAM data ping-pong conversion module to obtain the final imaging result.

[0043] The system described in this embodiment is used to implement data transformation for the PCS SAR imaging algorithm, such as... Figure 5 As shown, the size of a radar echo data frame is 8192*8192. The original radar echo data is in the range direction horizontally and the azimuth direction vertically. After the first sequential write and readout of the radar echo data, it becomes in the range direction horizontally and the azimuth direction vertically. After the second range-to-azimuth transpose data, it becomes in the azimuth direction horizontally and the range direction vertically. After the third azimuth-to-range transpose data, it becomes in the range direction horizontally and the azimuth direction vertically.

Claims

1. A multi-channel parallel data processing system based on FPGA suitable for various SAR imaging algorithms, characterized in that, Includes a serial-to-parallel conversion module, a DDR status control module, and a DDR and RAM data ping-pong conversion module; The DDR status control module is used to control the status of the DDR. There are four statuses: 1) 00 indicates that the DDR is not performing read or write operations; 2) 01 indicates that the DDR is sequentially writing and reading data; 3) 10 indicates that the DDR is performing a transpose operation from azimuth to range; 4) 11 indicates that the DDR is performing a transpose operation from range to azimuth. Let the bit width of radar echo data be N bits, where the horizontal direction is range and the vertical direction is azimuth, and N is a positive integer; the bit width of DDR read / write is 16N bits. When the DDR state is 01, the serial-to-parallel conversion module receives 8Nbits of input data at a time and converts it into 16Nbits of data, which is then input to the DDR group state control module. The DDR group state control module sequentially stores the 16Nbits of data into the DDR, and then sequentially reads the 16Nbits of data out to the RAM data ping-pong conversion module. The RAM ping-pong conversion module converts the 16Nbits of data into 8Nbits of data, and then the 8Nbits of data are divided into 8 parallel outputs. When the DDR state is 10, the horizontal direction of the input data is the azimuth direction and the vertical direction is the range direction. The serial-to-parallel conversion module receives 8Nbits of input data and converts it into 16Nbits of data, which is then input to the DDR group state control module. The DDR group state control module transposes the 16Nbits of data and stores it in the DDR. Then, it transposes and reads the 16Nbits of data to the RAM data ping-pong conversion module to complete the transposition of the data from the azimuth direction to the range direction. The RAM ping-pong conversion module converts the 16Nbits of data into 8Nbits of data, which is then divided into 8 parallel outputs. When the DDR state is 11, the horizontal direction of the input data is the range direction and the vertical direction is the azimuth direction. The serial-to-parallel conversion module receives 8Nbits of input data and converts it into 16Nbits of data, which is then input to the DDR group state control module. The DDR group state control module transposes the 16Nbits of data and stores it in the DDR, and then transposes and reads the 16Nbits of data to the RAM data ping-pong conversion module to complete the transposition of the input data from the range direction to the azimuth direction. The RAM ping-pong conversion module converts the 16Nbits of data into 8Nbits of data, and the 8Nbits of data are divided into 8 parallel outputs. When the DDR status is 00, the DDR does not perform any operations.

2. The FPGA-based multi-channel parallel data processing system applicable to various SAR imaging algorithms according to claim 1, characterized in that, When a multi-channel parallel data processing system implements an algorithm that includes M write and read operations, it inputs a 2Mbits parameter to the DDR status control module of the multi-channel parallel data processing system to control the different read and write states of the DDR and their sequential changes. In the 2Mbits parameter, the 2m-1th bit and the 2mth bit represent the mth DDR read and write state, and 1≤m≤M.

3. The FPGA-based multi-channel parallel data processing system applicable to various SAR imaging algorithms according to claim 2, characterized in that, When the system is used to implement the Chirp Scaling SAR imaging algorithm, it includes three data write and read operations, M=3, which are range to azimuth transpose, azimuth to range transpose, and range to azimuth transpose, respectively; the 6-bit parameter input to the DDR status control module of the multi-channel parallel data processing system is 111011.

4. The FPGA-based multi-channel parallel data processing system applicable to various SAR imaging algorithms according to claim 3, characterized in that, When the system is used to implement the Chirp Scaling SAR imaging algorithm, each point of the radar echo data is 32 bits, of which the first 16 bits represent the real part and the last 16 bits represent the imaginary part; the system uses eight parallel processing channels and the DDR throughput data width is 512 bits. For a single frame of radar echo data, the serial-to-parallel conversion module receives 256 bits of input data and converts it into 512 bits, which are then input to the DDR group status control module. The DDR group control module performs range-to-azimuth transposition, storing the 512 bits of transposed data in the DDR memory, and then reading the transposed 512 bits into the RAM data ping-pong conversion module. The RAM ping-pong conversion module converts the 512 bits of data into 256 bits, which are then divided into eight parallel outputs. The output data from the RAM data ping-pong conversion module undergoes an eight-channel parallel azimuth FFT, followed by chirp processing. Scaling multiplexing: Eight parallel data streams enter the serial-to-parallel conversion module; the serial-to-parallel conversion module receives 256 bits of input data and converts it into 512 bits of data, which is then input to the DDR group status control module; the DDR group control module performs azimuth-to-range transposition, transposes the 512 bits of data into the DDR, and then reads the transposed 512 bits into the RAM data ping-pong conversion module; the RAM ping-pong conversion module converts the 512 bits of data into 256 bits of data, which is then divided into eight parallel output streams; the output data from the RAM data ping-pong conversion module undergoes eight parallel range FFTs, followed by RCMC and range compression multiplexing. The data is multiplied, then subjected to a range-oriented IFFT, and the eight parallel data streams enter the serial-to-parallel conversion module. The serial-to-parallel conversion module receives 256 bits of input data and converts it into 512 bits of data, which is then input to the DDR group state control module. The DDR group control module performs a range-to-azimuth transpose, transposes the 512 bits of data and stores it in the DDR, and then reads the transposed 512 bits of data to the RAM data ping-pong conversion module. The RAM ping-pong conversion module converts the 512 bits of data into 256 bits of data, which is then divided into eight parallel output streams. The output data from the RAM data ping-pong conversion module undergoes an eight-channel parallel azimuth-oriented IFFT to finally obtain the imaging result.

5. The FPGA-based multi-channel parallel data processing system applicable to various SAR imaging algorithms according to claim 2, characterized in that, When the system is used to implement the Chirp Scaling SAR imaging algorithm, it includes three data write and read operations, M=3, which are sequential write and read data, range to azimuth transpose, and azimuth to range transpose, respectively; the 6-bit parameter input to the DDR status control module of the multi-channel parallel data processing system is 011110.

6. The FPGA-based multi-channel parallel data processing system applicable to various SAR imaging algorithms according to claim 5, characterized in that, When the system is used to implement the Chirp Scaling SAR imaging algorithm, each point of the radar echo data is 32 bits, of which the first 16 bits represent the real part and the last 16 bits represent the imaginary part; the system uses eight parallel processing channels and the DDR throughput data width is 512 bits. For a single frame of radar echo data, the serial-to-parallel conversion module receives 256 bits of input data at a time and converts it into 512 bits of data, which is then input to the DDR group status control module. The DDR group control module sequentially writes and reads the radar echo data. The DDR group status control module sequentially stores the 512 bits of data into the DDR, and then sequentially reads the 512 bits of data into the RAM data ping-pong conversion module. The RAM ping-pong conversion module converts the 512 bits of data into 256 bits of data, which is then divided into eight parallel outputs. The data output from the RAM data ping-pong conversion module undergoes eight parallel operations: complex multiplication, range-direction FFT, complex multiplication, range-direction IFFT, and complex multiplication. The eight parallel data streams then enter the serial-to-parallel conversion module. The serial-to-parallel conversion module receives 256 bits of input data and converts it into 512 bits of data, which is then input to the DDR group status control module. The DDR group control module performs range-to-azimuth transposition, and the DDR group status control module transposes the 512 bits of data into the DDR, and then transposes the data... The system reads 512 bits of data from the RAM ping-pong conversion module. The RAM ping-pong conversion module converts the 512 bits of data into 256 bits, which are then divided into eight parallel outputs. The output data from the RAM ping-pong conversion module undergoes eight parallel operations: complex multiplication, azimuth FFT, complex multiplication, azimuth IFFT, complex multiplication, azimuth FFT, and complex multiplication. This eight-channel parallel data then enters the serial-to-parallel conversion module. The serial-to-parallel conversion module receives the 256 bits of input data and converts it into 512 bits, which are then input to the DDR group state control module. The DDR group control module performs an azimuth-to-range transpose, storing the transposed 512 bits of data in the DDR. The transposed 512 bits are then read from the RAM ping-pong conversion module. The RAM ping-pong conversion module converts the 512 bits of data into 256 bits, which are then divided into eight parallel outputs. The output data from the RAM ping-pong conversion module undergoes an eight-channel parallel range FFT to obtain the final imaging result.

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