Array substrate and display panel

Abstract

The present application discloses an array substrate and a display panel, mainly relating to the field of display technologies. A first gate, a first source, a first connection electrode, a first drain, and a pixel electrode are all disposed on a substrate. A first semiconductor structure is disposed between the first source and the first connection electrode, and a second semiconductor structure is disposed between the first connection electrode and the first drain. The first source, the first semiconductor structure, the first connection electrode, the second semiconductor structure, and the first drain are connected in sequence, and the pixel electrode is connected to the first drain. A channel between the first source and the first connection electrode is defined as a first source channel, and a channel between the first drain and the first connection electrode is defined as a first drain channel. The length directions of the first source channel and the first drain channel have an included angle. Through the above design, the problem of gray level drop when displaying a picture in a folding area is avoided, and uneven display of the picture on the display panel is avoided.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to an array substrate and a display panel. Background Art

[0002] Electronic paper display technology has advantages such as low power consumption, power-off display, ultra-wide viewing angle, no blue light and no light pollution. It is precisely due to such prominent advantages of electronic paper display technology that electronic paper products are so popular in the world. In recent years, foldable electronic paper display panels have gradually come into the public eye due to their flexible and foldable advantages.

[0003] However, during use, when displaying an image in the folding area, there will be a problem of gray level drop, resulting in uneven image display on the display panel. Summary of the Invention

[0004] The purpose of the present application is to provide an array substrate and a display panel, to avoid the problem of gray level drop when displaying an image in the folding area, and to avoid uneven image display on the display panel.

[0005] The present application discloses an array substrate, which includes a substrate, a first active switch, and a pixel electrode; the first active switch includes a first gate, a first source, a first connection electrode, and a first drain, the first gate, the first source, the first connection electrode, the first drain, and the pixel electrode are all disposed on the substrate, a first semiconductor structure is disposed between the first source and the first connection electrode, a second semiconductor structure is disposed between the first connection electrode and the first drain, the first source, the first semiconductor structure, the first connection electrode, the second semiconductor structure, and the first drain are connected in sequence, and the pixel electrode is connected to the first drain;

[0006] Define the channel between the first source and the first connection electrode as the first source channel, and define the channel between the first drain and the first connection electrode as the first drain channel. The length directions of the first source channel and the first drain channel have an included angle.

[0007] Optionally, the length directions of the first source channel and the first drain channel are perpendicular.

[0008] Optionally, the first connection electrode includes a first connection electrode portion and a second connection electrode portion, and the first connection electrode portion and the second connection electrode portion are perpendicularly connected;

[0009] The first semiconductor structure connects the first source and the first connection electrode portion, and the second semiconductor structure connects the first drain and the second connection electrode portion;

[0010] The first source electrode and the first connection electrode part are parallel; the first drain electrode and the second connection electrode part are parallel.

[0011] Optionally, the array substrate includes a second active switch, and the second active switch includes a second gate electrode, a second source electrode, a second connection electrode, and a second drain electrode; the second gate electrode, the second source electrode, the second connection electrode, and the second drain electrode are all disposed on the substrate, and the pixel electrode is further connected to the second drain electrode;

[0012] A third semiconductor structure is disposed between the second source electrode and the second connection electrode part, and a fourth semiconductor structure is disposed between the second connection electrode and the second drain electrode part. The second source electrode, the third semiconductor structure, the second connection electrode, the fourth semiconductor structure, and the second drain electrode are connected in sequence;

[0013] Define the channel between the second source electrode and the second connection electrode part as the second source channel, and define the channel between the second drain electrode and the second connection electrode part as the second drain channel. The length direction of the second source channel is perpendicular to the length direction of the second drain channel;

[0014] The second connection electrode includes a third connection electrode part and a fourth connection electrode part, and the third connection electrode part and the fourth connection electrode part are perpendicularly connected;

[0015] The third semiconductor structure is connected to the second source electrode and the third connection electrode part, and the fourth semiconductor structure is connected to the second drain electrode and the fourth connection electrode part;

[0016] The second source electrode and the third connection electrode part are parallel; the second drain electrode and the fourth connection electrode part are parallel.

[0017] Optionally, the first gate electrode and the second gate electrode are disposed on the same layer, and the first source electrode, the first connection electrode, the first drain electrode, the second source electrode, the second connection electrode, and the second drain electrode are disposed on the same layer;

[0018] The first connection electrode part and the fourth connection electrode part are parallel, the first connection electrode part and the third connection electrode part are perpendicular, the second connection electrode part and the third connection electrode part are parallel, and the second connection electrode part and the fourth connection electrode part are perpendicular;

[0019] The first source electrode and the first drain electrode are respectively located on two sides of the first connection electrode portion, and the second source electrode and the second drain electrode are respectively located on two sides of the fourth connection electrode portion; or the first source electrode and the first drain electrode are respectively located on two sides of the second connection electrode portion, and the second source electrode and the second drain electrode are respectively located on two sides of the third connection electrode portion.

[0020] Optionally, the first connection electrode includes a first connection electrode portion and a second connection electrode portion, and the first connection electrode portion and the second connection electrode portion are perpendicularly connected;

[0021] The first source electrode includes a first source electrode portion, a second source electrode portion, and a third source electrode portion. The first source electrode portion, the second source electrode portion, and the third source electrode portion are sequentially connected, and the first source electrode portion and the third source electrode portion are located on two sides of the first connection electrode portion;

[0022] The first drain electrode includes a first drain electrode portion, a second drain electrode portion, and a third drain electrode portion. The first drain electrode portion, the second drain electrode portion, and the third drain electrode portion are sequentially connected, and the first drain electrode portion and the third drain electrode portion are located on two sides of the second connection electrode portion.

[0023] Optionally, the array substrate includes a second active switch. The second active switch includes a second gate electrode, a second source electrode, a second connection electrode, and a second drain electrode; the second gate electrode, the second source electrode, the second connection electrode, and the second drain electrode are all disposed on the substrate, and the pixel electrode is further connected to the second drain electrode;

[0024] A third semiconductor structure is disposed between the second source electrode and the second connection electrode, and a fourth semiconductor structure is disposed between the second connection electrode and the second drain electrode. The second source electrode, the third semiconductor structure, the second connection electrode, the fourth semiconductor structure, and the second drain electrode are sequentially connected;

[0025] Define the channel between the second source electrode and the second connection electrode as the second source channel, and define the channel between the second drain electrode and the second connection electrode as the second drain channel. The length direction of the second source channel and the length direction of the second drain channel are perpendicular;

[0026] The second connection electrode includes a third connection electrode portion and a fourth connection electrode portion, and the third connection electrode portion and the fourth connection electrode portion are perpendicularly connected;

[0027] The second source electrode includes a fourth source electrode portion, a fifth source electrode portion, and a sixth source electrode portion. The fourth source electrode portion, the fifth source electrode portion, and the sixth source electrode portion are sequentially connected, and the fourth source electrode portion and the sixth source electrode portion are located on two sides of the third connection electrode portion;

[0028] The second drain includes a fourth drain portion, a fifth drain portion, and a sixth drain portion. The fourth drain portion, the fifth drain portion, and the sixth drain portion are connected in sequence, and the fourth drain portion and the sixth drain portion are located on both sides of the fourth connection electrode portion.

[0029] Optionally, the first gate and the second gate are disposed in the same layer, and the first source, the first connection electrode, the first drain, the second source, the second connection electrode, and the second drain are disposed in the same layer;

[0030] The first connection electrode portion and the fourth connection electrode portion are parallel, the first connection electrode portion and the third connection electrode portion are perpendicular, the second connection electrode portion and the third connection electrode portion are parallel, and the second connection electrode portion and the fourth connection electrode portion are perpendicular.

[0031] Optionally, the array substrate further includes a data line and a scan line. The data line and the scan line are both disposed on the substrate. The data line is connected to the first source of the first active switch, and the scan line is connected to the first gate of the first active switch.

[0032] This application also discloses a display panel. The display panel includes a driving circuit and an array substrate. The driving circuit is connected to the array substrate and is used to drive the array substrate.

[0033] Compared with the existing array substrate solution, in this application, an included angle exists between the length direction of the first source channel and the length direction of the first drain channel. Thus, when the length of the first source channel becomes longer, the width of the first drain channel will become larger; when the length of the first source channel becomes shorter, the width of the first drain channel will become shorter; when the width of the first source channel becomes longer, the length of the first drain channel will become larger; when the width of the first source channel becomes shorter, the length of the first drain channel will become shorter; thereby realizing the mutual compensation of changes, avoiding the problem of gray level drop when displaying a picture in the folding area, and avoiding uneven display of the picture on the display panel. Description of the Drawings

[0034] The included drawings are used to provide a further understanding of the embodiments of the present application. They form a part of the specification, are used to illustrate the implementation manners of the present application, and are used to explain the principles of the present application together with the text description. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0035] Figure 1Schematic diagram of a display panel according to an embodiment of the present application;

[0036] Figure 2 Cross-sectional schematic diagram of a display panel according to an embodiment of the present application;

[0037] Figure 3 Schematic diagram of an array substrate according to the first embodiment of the present application;

[0038] Figure 4 Schematic diagram of a structure including a second active switch according to the first embodiment of the present application;

[0039] Figure 5 It is Figure 4 Partial enlarged schematic diagram of the active switch in;

[0040] Figure 6 Schematic diagram of a first gate and a second gate according to the first embodiment of the present application;

[0041] Figure 7 Schematic diagram of a plane of a laterally folded array substrate according to the first embodiment of the present application;

[0042] Figure 8 Schematic diagram of an active switch located in a first folding area according to the first embodiment of the present application;

[0043] Figure 9 Schematic diagram of an active switch located in a second folding area according to the first embodiment of the present application;

[0044] Figure 10 Schematic diagram of a plane of a laterally folded array substrate according to the first embodiment of the present application;

[0045] Figure 11 Schematic diagram of an active switch located in a first folding area according to the first embodiment of the present application;

[0046] Figure 12 Schematic diagram of an active switch located in a second folding area according to the first embodiment of the present application;

[0047] Figure 13 Schematic diagram of a plane of an array substrate according to the second embodiment of the present application;

[0048] Figure 14 Schematic diagram of a plane of a dual active switch according to the second embodiment of the present application;

[0049] Figure 15 It is Figure 14 Partial enlarged schematic diagram of the active switch in.

[0050] Among them, 10 is a display panel; 20 is a driving circuit; 30 is an array substrate; 40 is a folding area; 41 is a first folding area; 42 is a second folding area; 43 is a folding line; 51 is a first direction; 52 is a second direction; 100 is a substrate; 200 is a first active switch; 210 is a first gate; 220 is a first source; 221 is a first source portion; 222 is a second source portion; 223 is a third source portion; 240 is a first connection electrode; 241 is a first connection electrode portion; 242 is a second connection electrode portion; 250 is a first drain; 251 is a first drain portion; 252 is a second drain portion; 253 is a third drain portion; 261 is a first semiconductor structure; 262 is a second semiconductor structure; 271 is a first source channel; 272 is a first drain channel; 300 is a second active switch; 310 is a second gate; 320 is a second source; 324 is a fourth source portion; 325 is a fifth source portion; 326 is a sixth source portion; 340 is a second connection electrode; 343 is a third connection electrode portion; 344 is a fourth connection electrode portion; 350 is a second drain; 354 is a fourth drain portion; 355 is a fifth drain portion; 356 is a sixth drain portion; 363 is a third semiconductor structure; 364 is a fourth semiconductor structure; 371 is a second source channel; 372 is a second drain channel; 400 is a pixel electrode; 510 is a data line; 520 is a scan line; 610 is a first metal layer, 620 is a first insulating layer, 630 is a second metal layer, 640 is a second insulating layer, 650 is a passivation layer; 660 is a pixel electrode layer; 670 is a reflective film layer; 671 is a microcapsule; 672 is an electrophoretic particle; 680 is a common electrode layer; 710 is a common electrode; 810 is an X axis; 820 is a Y axis. Detailed implementation manners

[0051] It should be understood that the terms, specific structures and functional details disclosed here are only for the purpose of describing specific embodiments, which are representative. However, the present application can be specifically implemented in many alternative forms and should not be construed as being limited only to the embodiments described herein.

[0052] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating relative importance or implicitly indicating the quantity of the indicated technical features. Thus, unless otherwise specified, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features; the meaning of "a plurality" is two or more. The term "comprising" and any deformation thereof means non-exclusive inclusion, and there may be or add one or more other features, integers, steps, operations, units, components and / or their combinations.

[0053] In addition, terms indicating orientation or positional relationships such as "center", "horizontal", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are described based on the orientation or relative positional relationships shown in the drawings, and are only for the purpose of facilitating the simplified description of the present application, rather than indicating that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0054] In addition, unless otherwise clearly specified and defined, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, or it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0055] The present application will be described in detail below with reference to the drawings and optional embodiments.

[0056] Figure 1 is a schematic diagram of a display panel according to an embodiment of the present application. Figure 2 is a cross-sectional schematic diagram of a display panel according to an embodiment of the present application. As Figure 1 - Figure 2 shown, the present application discloses a display panel 10, and the display panel 10 includes a driving circuit 20 and an array substrate 30. The driving circuit 20 is connected to the array substrate 30 and is used to drive the array substrate 30.

[0057] The technical solution of the present application can be widely used in various display panels 10, such as TN (Twisted Nematic) display panels, IPS (In-Plane Switching) display panels, VA (Vertical Alignment) display panels, MVA (Multi-Domain Vertical Alignment) display panels. Of course, it can also be other types of display panels, such as OLED (Organic Light-Emitting Diode) display panels, such as electronic paper display panels, and the above solutions are all applicable.

[0058] Exemplarily, for the electronic paper display panel 10, the array substrate 30 includes a substrate 100, a first metal layer 610, a first insulating layer 620, a second metal layer 630, a second insulating layer 640, a passivation layer 650, and a pixel electrode layer 660. The display panel 10 further includes a reflective film layer 670 and a common electrode layer 680. The first metal layer 610, the first insulating layer 620, the second metal layer 630, the second insulating layer 640, the passivation layer 650, and the pixel electrode layer 660 are sequentially disposed on the substrate 100, and the reflective film layer 670 is disposed between the pixel electrode layer 660 and the common electrode layer 680.

[0059] The reflective film layer 670 includes microcapsules 671 filled with electrophoretic particles 672. An electric field is formed between the pixel electrode layer 660 and the common electrode layer 680 to drive the electrophoretic particles 672 to move up and down, so as to reflect or absorb light and realize the display of the picture.

[0060] The array substrate 30 further includes a common electrode 710 located in the first metal layer 610 or the second metal layer 630, and a storage capacitor is formed between the common electrode 710 and the pixel electrode layer 660.

[0061] This application also discloses an array substrate 30, which can be used in the display panel 10 described above. For the array substrate 30, the following design is provided in this application and is specifically introduced through several embodiments:

[0062] Embodiment 1:

[0063] Figure 3 is a schematic diagram of an array substrate according to the first embodiment of this application. With reference to Figure 3 as shown, this application discloses an array substrate 30, which includes a substrate 100, a first active switch 200, and a pixel electrode 400; the first active switch 200 includes a first gate 210, a first source 220, a first connection electrode 240, and a first drain 250. The first gate 210, the first source 220, the first connection electrode 240, the first drain 250, and the pixel electrode 400 are all disposed on the substrate 100.

[0064] A first semiconductor structure 261 is disposed between the first source electrode 220 and the first connection electrode 240, and a second semiconductor structure 262 is disposed between the first connection electrode 240 and the first drain electrode 250. The first source electrode 220, the first semiconductor structure 261, the first connection electrode 240, the second semiconductor structure 262, and the first drain electrode 250 are connected in sequence, and the pixel electrode 400 is connected to the first drain electrode 250.

[0065] Define the channel between the first source electrode 220 and the first connection electrode 240 as the first source channel 271, and define the channel between the first drain electrode 250 and the first connection electrode 240 as the first drain channel 272. The length directions of the first source channel 271 and the first drain channel 272 have an included angle. In other words, the length directions of the first source channel 271 and the first drain channel 272 are not parallel.

[0066] The array substrate 30 further includes a data line 510 and a scan line 520. The data line 510 and the scan line 520 are both disposed on the substrate 100. The data line 510 is connected to the first source electrode 220 of the first active switch 200, and the scan line 520 is connected to the first gate electrode 210 of the first active switch 200. The pixel electrode 400 is located in the pixel electrode layer 660.

[0067] Exemplarily, the data line 510 is located in the first metal layer 610, and the scan line 520 is located in the second metal layer 630.

[0068] Exemplarily, the data line 510 is located in the second metal layer 630, and the scan line 520 is located in the first metal layer 610.

[0069] Exemplarily, the first active switch 200 is a bottom-gate type active switch. The first gate electrode 210 is located in the first metal layer 610, the first source electrode 220, the first connection electrode 240, and the first drain electrode 250 are located in the second metal layer 630, and the first semiconductor structure 261 and the second semiconductor structure 262 are located between the first insulating layer 620 and the second metal layer 630.

[0070] Exemplarily, the first active switch 200 is a top-gate type active switch. The first gate electrode 210 is located in the second metal layer 630, the first source electrode 220, the first connection electrode 240, and the first drain electrode 250 are located in the first metal layer 610, and the first semiconductor structure 261 and the second semiconductor structure 262 are located between the substrate 100 and the first metal layer 610.

[0071] When the display panel 10 is bent, the length or width of the channel of the active switch on the existing array substrate 30 will change.

[0072] When the channel length of the active switch becomes longer, the charging ability of the active switch decreases, and the electrophoretic particles 672 above the pixel electrode 400 connected to the active switch cannot move to the target position, and the gray level of this area will decrease during display; when the channel length of the active switch becomes shorter, the leakage current of the active switch will increase, and the electrophoretic particles 672 above the pixel electrode 400 connected to the active switch still cannot move to the target position, and the gray level of this area will decrease during display.

[0073] When the channel width of the active switch becomes shorter, the charging ability of the active switch decreases, and the electrophoretic particles 672 above the pixel electrode 400 connected to the active switch cannot move to the target position, and the gray level of this area will decrease during display; when the channel width of the active switch becomes longer, the leakage current of the active switch will increase, and the electrophoretic particles 672 above the pixel electrode 400 connected to the active switch still cannot move to the target position, and the gray level of this area will decrease during display.

[0074] As a result, when the display panel 10 in the folding area 40 displays a picture, the gray level decreases, resulting in uneven picture display of the entire display panel 10.

[0075] Compared with the existing array substrate solution, in the present application, the length direction of the first source channel 271 and the length direction of the first drain channel 272 have an included angle. In this way, when the length of the first source channel 271 becomes longer, the width of the first drain channel 272 will become larger; when the length of the first source channel 271 becomes shorter, the width of the first drain channel 272 will become shorter; when the width of the first source channel 271 becomes longer, the length of the first drain channel 272 will become larger; when the width of the first source channel 271 becomes shorter, the length of the first drain channel 272 will become shorter; thereby realizing mutual compensation of the changes, avoiding the problem of gray level drop when the picture is displayed in the folding area 40, and avoiding uneven picture display of the display panel 10.

[0076] It is defined that the display panel 10 can be folded along the X-axis 810 direction or along the Y-axis 820 direction. The length direction of the X-axis 810 is the same as the width direction of the first source channel 271 and the length of the first drain channel 272; the length direction of the Y-axis 820 is the same as the length direction of the first source channel 271 and the width direction of the first drain channel 272.

[0077] Exemplarily, the length directions of the first source channel 271 and the first drain channel 272 are perpendicular. Since the length directions of the first source channel 271 and the first drain channel 272 are perpendicular, when the display panel 10 is folded along the X-axis 810 direction, the length of the first source channel 271 and the width of the first drain channel 272 increase or decrease synchronously, and the width of the first source channel 271 and the length of the first drain channel 272 remain unchanged.

[0078] When the display panel 10 is folded along the Y-axis 820 direction, the width of the first source channel 271 and the length of the first drain channel 272 increase or decrease synchronously, and the length of the first source channel 271 and the width of the first drain channel 272 remain unchanged; thus, the effect of offsetting the change amount of the first source channel 271 and the change amount of the first drain channel 272 is better.

[0079] See Figure 3 , the first source 220 and the first drain 250 of this embodiment are both U-shaped, specifically as follows: the first connection electrode 240 includes a first connection electrode portion 241 and a second connection electrode portion 242, and the first connection electrode portion 241 and the second connection electrode portion 242 are perpendicularly connected.

[0080] The first source 220 includes a first source portion 221, a second source portion 222, and a third source portion 223. The first source portion 221, the second source portion 222, and the third source portion 223 are connected in sequence, and the first source portion 221 and the third source portion 223 are located on both sides of the first connection electrode portion 241.

[0081] The first drain 250 includes a first drain portion 251, a second drain portion 252, and a third drain portion 253. The first drain portion 251, the second drain portion 252, and the third drain portion 253 are connected in sequence, and the first drain portion 251 and the third drain portion 253 are located on both sides of the second connection electrode portion 242.

[0082] The first active switch 200 is an active switch with double gates and occupies a relatively large area of a single pixel unit region. It should be understood that the pixel unit region is the region defined by the crisscross arrangement of the data line 510 and the scan line 520. By setting the shapes of the first source 220 and the first drain 250 to be U-shaped, the area of the first active switch 200 can be reduced, so that the common electrode 710 can have more space, and thus the common electrode 710 can be set large enough to increase the size of the storage capacitor.

[0083] Figure 4It is a schematic diagram of a first embodiment of the present application, including a second active switch. Figure 5 It is Figure 4 a partial enlarged schematic diagram of the active switch in Figure 4 - Figure 5 as shown, Figure 5 The dotted arrow in

[0084] indicates the width of the channel, and the solid arrow indicates the length of the channel; The present application also provides a second active switch 300, and both the second source electrode 320 and the second drain electrode 350 are U-shaped.

[0085] Specifically, the array substrate 30 includes a second active switch 300, and the second active switch 300 includes a second gate electrode 310, a second source electrode 320, a second connection electrode 340, and a second drain electrode 350; The second gate electrode 310, the second source electrode 320, the second connection electrode 340, and the second drain electrode 350 are all disposed on the substrate 100, and the pixel electrode 400 is also connected to the second drain electrode 350.

[0085] A third semiconductor structure 363 is disposed between the second source electrode 320 and the second connection electrode 340, and a fourth semiconductor structure 364 is disposed between the second connection electrode 340 and the second drain electrode 350. The second source electrode 320, the third semiconductor structure 363, the second connection electrode 340, the fourth semiconductor structure 364, and the second drain electrode 350 are connected in sequence.

[0086] The channel between the second source electrode 320 and the second connection electrode 340 is defined as the second source channel 371, and the channel between the second drain electrode 350 and the second connection electrode 340 is defined as the second drain channel 372. The length direction of the second source channel 371 is perpendicular to the length direction of the second drain channel 372.

[0087] The second connection electrode 340 includes a third connection electrode portion 343 and a fourth connection electrode portion 344, and the third connection electrode portion 343 and the fourth connection electrode portion 344 are perpendicularly connected.

[0088] The second source electrode 320 includes a fourth source portion 324, a fifth source portion 325, and a sixth source portion 326. The fourth source portion 324, the fifth source portion 325, and the sixth source portion 326 are connected in sequence, and the fourth source portion 324 and the sixth source portion 326 are located on both sides of the third connection electrode portion 343.

[0089] The second drain 350 includes a fourth drain portion 354, a fifth drain portion 355, and a sixth drain portion 356. The fourth drain portion 354, the fifth drain portion 355, and the sixth drain portion 356 are connected in sequence, and the fourth drain portion 354 and the sixth drain portion 356 are located on both sides of the fourth connection electrode portion 344.

[0090] Exemplarily, the second active switch 300 is a bottom-gate active switch. The second gate 310 is located in the first metal layer 610. The second source 320, the second connection electrode 340, and the second drain 350 are located in the second metal layer 630. The third semiconductor structure 363 and the fourth semiconductor structure 364 are located between the first insulating layer 620 and the second metal layer 630.

[0091] Exemplarily, the second active switch 300 is a top-gate active switch. The second gate 310 is located in the first metal layer 610. The second source 320, the second connection electrode 340, and the second drain 350 are located in the first metal layer 610. The third semiconductor structure 363 and the fourth semiconductor structure 364 are located between the substrate 100 and the first metal layer 610.

[0092] Among them, the data line 510 is connected to the first source 220 and the second source 320 at the same time. The scan line 520 is connected to the first gate 210 and the second gate 310 at the same time. By adding the second active switch 300, the first active switch 200 and the second active switch 300 are equivalent to being connected in parallel, which can improve the charging ability of the pixel electrode 400. When one of the first active switch 200 and the second active switch 300 is damaged, the other one can still work, and it will not cause the failure of the pixel unit area, avoiding the problem of black dots or white dots.

[0093] Moreover, the first gate 210 and the second gate 310 are arranged in the same layer and can be directly set as one piece. The first source 220, the first connection electrode 240, the first drain 250, the second source 320, the second connection electrode 340, and the second drain 350 are arranged in the same layer; this can save the manufacturing process and reduce the manufacturing difficulty.

[0094] The first connection electrode portion 241 is parallel to the fourth connection electrode portion 344. The first connection electrode portion 241 is perpendicular to the third connection electrode portion 343. The second connection electrode portion 242 is parallel to the third connection electrode portion 343. The second connection electrode portion 242 is perpendicular to the fourth connection electrode portion 344.

[0095] Exemplarily, the first gate 210 and the second gate 310 can be directly connected, the first connection electrode 240 and the second connection electrode 340 can be directly connected, and the first connection electrode 240 and the second connection electrode 340 are in a cross shape.

[0096] Exemplarily, when the display panel 10 is folded along the X-axis 810 direction, the length of the first source channel 271 and the width of the first drain channel 272 increase or decrease synchronously, and the width of the first source channel 271 and the length of the first drain channel 272 remain unchanged; the width of the second source channel 371 and the length of the second drain channel 372 increase or decrease synchronously; the length of the second source channel 371 remains unchanged and the width of the second drain channel 372 remains unchanged synchronously; thereby achieving a better mutual cancellation effect.

[0097] Exemplarily, when the display panel 10 is folded along the Y-axis 820 direction, the width of the first source channel 271 and the length of the first drain channel 272 increase or decrease synchronously, and the length of the first source channel 271 and the width of the first drain channel 272 remain unchanged; the length of the second source channel 371 and the width of the second drain channel 372 increase or decrease synchronously, and the width of the second source channel 371 and the length of the second drain channel 372 remain unchanged; thereby achieving a better mutual cancellation effect.

[0098] Figure 6 It is a schematic diagram of a first gate and a second gate according to the first embodiment of the present application. As Figure 6 shown, since the first source 220, the first drain 250, the second source 320, and the second drain 350 are all U-shaped, the orthographic projection of the first gate 210 of the present application on the substrate 100 only covers the projection of the channel between the first source portion 221 and the first connection electrode portion 241 on the substrate 100, the projection of the channel between the third source portion 223 and the first connection electrode portion 241 on the substrate 100, the projection of the channel between the first drain portion 251 and the second connection electrode portion 242 on the substrate 100, and the projection of the channel between the third drain portion 253 and the second connection electrode portion 242 on the substrate 100.

[0099] Thereby avoiding the influence of the channel change between the second source portion 222 and the first connection electrode portion 241 and the channel change between the second drain portion 252 and the second connection electrode portion 242.

[0100] The positive projection of the second gate 310 on the substrate 100 only covers the projection on the substrate 100 of the channel between the fourth source portion 324 and the third connection electrode portion 343, the projection on the substrate 100 of the channel between the sixth source portion 326 and the third connection electrode portion 343, the projection on the substrate 100 of the channel between the fourth drain portion 354 and the fourth connection electrode portion 344, and the projection on the substrate 100 of the channel between the sixth drain portion 356 and the fourth connection electrode portion 344.

[0101] Thereby, the influence of the channel change between the fifth source portion 325 and the third connection electrode portion 343 and the channel change between the fifth drain portion 355 and the fourth connection electrode portion 344 is avoided.

[0102] Figure 7 FIG. is a schematic plan view of the lateral folding of an array substrate according to the first embodiment of the present application. Figure 8 FIG. is a schematic view of an active switch located in the first folding region according to the first embodiment of the present application. Figure 9 FIG. is a schematic view of an active switch located in the second folding region according to the first embodiment of the present application. As Figure 7 - Figure 9 shown, the array substrate 30 includes a folding region 40, the folding region 40 is located in the middle of the array substrate 30, the middle of the folding region 40 is defined as a folding line 43, within the folding region 40, the directions extending from both sides along the width of the folding line 43 are respectively defined as a first direction 51 and a second direction 52, the extension region of the folding line 43 along the first direction 51 is a first folding region 41, and the extension region of the folding line 43 along the second direction 52 is a second folding region 42; the smaller the change in the length and width of the first source channel 271, the first drain channel 272, the second source channel 371, and the second drain channel 372 is as the distance from the folding line 43 increases.

[0103] Since the length of the first source channel 27l is less than the width of the first drain 250, when folding along the length direction of the X-axis 810, the change amount of the length of the first source channel 271 is less than the change amount of the width of the first drain channel 272.

[0104] See Figure 8 , when the array substrate 30 is used for a display panel 10 that folds along the length direction of the X-axis 810, within the first folding region 41, the first drain channel 272 is located on the side of the first source channel 271 away from the folding line 43; see Figure 9 , within the second folding region 42, the first drain channel 272 is located on the side of the first source channel 271 away from the folding line 43.

[0105] Thus, whether in the first folding region 41 or the second folding region 42, when folding along the length direction of the X-axis 810, the length change of the first source channel 271 and the width change of the first drain channel 272 can be better complementary, avoiding the situation of excessive differences.

[0106] Correspondingly, in the first folding region 41, the second drain channel 372 is located on the side of the second source channel 371 away from the folding line 43; in the second folding region 42, the second drain channel 372 is located on the side of the second source channel 371 away from the folding line 43.

[0107] Thus, whether in the first folding region 41 or the second folding region 42, when folding along the length direction of the X-axis 810, the length change of the second source channel 371 and the width change of the second drain channel 372 can be better complementary; avoiding the situation of excessive differences.

[0108] Figure 10 It is a schematic plan view of the lateral folding of an array substrate according to the first embodiment of the present application. Figure 11 It is a schematic view of an active switch located in the first folding region according to the first embodiment of the present application. Figure 12 It is a schematic view of an active switch located in the second folding region according to the first embodiment of the present application. As Figure 10 - Figure 12 shown, when the array substrate 30 is used for a display panel 10 that folds along the length direction of the Y-axis 820, refer to Figure 11 , in the first folding region 41, the first drain channel 272 is located on the side of the first source channel 271 close to the folding line 43; refer to Figure 12 , in the second folding region 42, the first drain channel 272 is located on the side of the first source channel 271 close to the folding line 43.

[0109] In the first folding region 41, the second drain channel 372 is located on the side of the second source channel 371 close to the folding line 43; in the second folding region 42, the second drain channel 372 is located on the side of the second source channel 371 close to the folding line 43.

[0110] Thus, whether in the first folding region 41 or the second folding region 42, when folding along the length direction of the X-axis 810, the channel change of the first source 220, the channel change of the first drain 250, the change of the second source channel 371, and the width change of the second drain channel 372 can be better complementary.

[0111] Embodiment 2

[0112] Figure 13 It is a schematic plan view of an array substrate according to the second embodiment of the present application. AsFigure 13 As shown, different from the first embodiment, the first source electrode 220 and the first drain electrode 250 in this embodiment are both of type I, specifically as follows: the first connection electrode 240 includes a first connection electrode portion 241 and a second connection electrode portion 242, and the first connection electrode portion 241 and the second connection electrode portion 242 are perpendicularly connected.

[0113] The first semiconductor structure 261 is connected to the first source electrode 220 and the first connection electrode portion 241, and the second semiconductor structure 262 is connected to the first drain electrode 250 and the second connection electrode portion 242.

[0114] The first source electrode 220 and the first connection electrode portion 241 are parallel; the first drain electrode 250 and the second connection electrode portion 242 are parallel.

[0115] In other words, both the first source electrode 220 and the second source electrode 320 are of type I. Compared with the solution of the first embodiment, the occupied area of the first active switch 200 can be reduced, thereby giving a larger area to the common electrode 710 to increase the size of the storage capacitor.

[0116] Figure 14 is a schematic plan view of a dual active switch according to the second embodiment of the present application. Figure 15 is Figure 14 a partially enlarged schematic view of the active switch in Figure 15 The dotted arrow in Figure 14 - Figure 15 represents the width of the channel, and the solid arrow represents the length of the channel. As shown in

[0117] In the second embodiment, a second active switch 300 may also be provided. The array substrate 30 includes the second active switch 300. The second active switch 300 includes a second gate electrode 310, a second source electrode 320, a second connection electrode 340, and a second drain electrode 350; the second gate electrode 310, the second source electrode 320, the second connection electrode 340, and the second drain electrode 350 are all disposed on the substrate 100, and the pixel electrode 400 is further connected to the second drain electrode 350.

[0118] Define the channel between the second source electrode 320 and the second connection electrode 340 as the second source channel 371, and define the channel between the second drain electrode 350 and the second connection electrode 340 as the second drain channel 372. The length direction of the second source channel 371 is perpendicular to the length direction of the second drain channel 372.

[0119] The second connection electrode 340 includes a third connection electrode portion 343 and a fourth connection electrode portion 344, and the third connection electrode portion 343 and the fourth connection electrode portion 344 are perpendicularly connected.

[0120] The third semiconductor structure 363 connects the second source electrode 320 and the third connection electrode portion 343, and the fourth semiconductor structure 364 connects the second drain electrode 350 and the fourth connection electrode portion 344; the second source electrode 320 and the third connection electrode portion 343 are parallel; the second drain electrode 350 and the fourth connection electrode portion 344 are parallel.

[0121] Among them, the data line 510 is connected to the first source electrode 220 and the second source electrode 320 at the same time, and the scan line 520 is connected to the first gate electrode 210 and the second gate electrode 310 at the same time. By adding the second active switch 300, the first active switch 200 and the second active switch 300 are equivalent to being connected in parallel, which can improve the charging ability of the pixel electrode 400. When one of the first active switch 200 and the second active switch 300 is damaged, the other can still work, and it will not cause the failure of the pixel unit area, avoiding the problem of black dots or white dots.

[0122] The first gate electrode 210 and the second gate electrode 310 are arranged on the same layer, and the first source electrode 220, the first connection electrode 240, the first drain electrode 250, the second source electrode 320, the second connection electrode 340 and the second drain electrode 350 are arranged on the same layer.

[0123] The first connection electrode portion 241 and the fourth connection electrode portion 344 are parallel, the first connection electrode portion 241 and the third connection electrode portion 343 are perpendicular, the second connection electrode portion 242 and the third connection electrode portion 343 are parallel, and the second connection electrode portion 242 and the fourth connection electrode portion 344 are perpendicular.

[0124] The first source electrode 220 and the first drain electrode 250 are respectively located on both sides of the first connection electrode portion 241, and the second source electrode 320 and the second drain electrode 350 are respectively located on both sides of the fourth connection electrode portion 344; or the first source electrode 220 and the first drain electrode 250 are respectively located on both sides of the second connection electrode portion 242, and the second source electrode 320 and the second drain electrode 350 are respectively located on both sides of the third connection electrode portion 343.

[0125] It is possible to prevent any two of the first source electrode 220, the first drain electrode 250, the second source electrode 320, and the second drain electrode 350 from being too close to each other, thereby simplifying the manufacturing difficulty and improving the manufacturing yield. Moreover, it is also possible to avoid the breakdown risk between any two of the first source electrode 220, the first drain electrode 250, the second source electrode 320, and the second drain electrode 350.

[0126] It should be noted that the inventive concept of the present application can form a very large number of embodiments. However, due to the limited space of the application documents, it is impossible to list them all. Therefore, on the premise of not conflicting, the above-described embodiments or technical features can be combined arbitrarily to form new embodiments. After the combination of the embodiments or technical features, the original technical effect will be enhanced.

[0127] The above content is a further detailed description of the present application in combination with specific optional embodiments. It cannot be determined that the specific implementation of the present application is limited only to these descriptions. For those of ordinary skill in the technical field to which the present application belongs, without departing from the concept of the present application, several simple deductions or substitutions can still be made, which should all be regarded as belonging to the protection scope of the present application.

Claims

1. An array substrate, characterized in that, The array substrate includes a substrate, a first active switch, and a pixel electrode; the first active switch includes a first gate, a first source, a first connection electrode, and a first drain. The first gate, the first source, the first connection electrode, the first drain, and the pixel electrode are all disposed on the substrate. A first semiconductor structure is disposed between the first source and the first connection electrode, and a second semiconductor structure is disposed between the first connection electrode and the first drain. The first source, the first semiconductor structure, the first connection electrode, the second semiconductor structure, and the first drain are connected in sequence, and the pixel electrode is connected to the first drain; Define the channel between the first source and the first connection electrode as the first source channel, and define the channel between the first drain and the first connection electrode as the first drain channel. The length directions of the first source channel and the first drain channel have an included angle; The length directions of the first source channel and the first drain channel are perpendicular; the first connection electrode includes a first connection electrode portion and a second connection electrode portion, and the first connection electrode portion and the second connection electrode portion are perpendicularly connected; The first semiconductor structure connects the first source and the first connection electrode portion, and the second semiconductor structure connects the first drain and the second connection electrode portion; The first source and the first connection electrode portion are parallel; the first drain and the second connection electrode portion are parallel; both the first source and the first drain are of type I.

2. The array substrate according to claim 1, wherein The array substrate includes a second active switch, and the second active switch includes a second gate, a second source, a second connection electrode, and a second drain; the second gate, the second source, the second connection electrode, and the second drain are all disposed on the substrate, and the pixel electrode is further connected to the second drain; A third semiconductor structure is disposed between the second source and the second connection electrode, and a fourth semiconductor structure is disposed between the second connection electrode and the second drain. The second source, the third semiconductor structure, the second connection electrode, the fourth semiconductor structure, and the second drain are connected in sequence; Define the channel between the second source and the second connection electrode as the second source channel, and define the channel between the second drain and the second connection electrode as the second drain channel. The length directions of the second source channel and the second drain channel are perpendicular; The second connection electrode includes a third connection electrode portion and a fourth connection electrode portion, and the third connection electrode portion and the fourth connection electrode portion are perpendicularly connected; The third semiconductor structure connects the second source and the third connection electrode portion, and the fourth semiconductor structure connects the second drain and the fourth connection electrode portion; The second source and the third connection electrode portion are parallel; the second drain and the fourth connection electrode portion are parallel.

3. The array substrate according to claim 2, wherein The first gate and the second gate are arranged on the same layer, and the first source electrode, the first connection electrode, the first drain electrode, the second source electrode, the second connection electrode and the second drain electrode are arranged on the same layer; The first connection electrode portion and the fourth connection electrode portion are parallel, the first connection electrode portion and the third connection electrode portion are perpendicular, the second connection electrode portion and the third connection electrode portion are parallel, and the second connection electrode portion and the fourth connection electrode portion are perpendicular; The first source electrode and the first drain electrode are respectively located on both sides of the first connection electrode portion, and the second source electrode and the second drain electrode are respectively located on both sides of the fourth connection electrode portion; or the first source electrode and the first drain electrode are respectively located on both sides of the second connection electrode portion, and the second source electrode and the second drain electrode are respectively located on both sides of the third connection electrode portion.

4. The array substrate according to claim 1, wherein The array substrate further includes a data line and a scan line, both the data line and the scan line are arranged on the substrate, the data line is connected to the first source electrode of the first active switch, and the scan line is connected to the first gate of the first active switch.

5. An array substrate, characterized in that, The array substrate includes a substrate, a first active switch and a pixel electrode; the first active switch includes a first gate, a first source electrode, a first connection electrode and a first drain electrode, the first gate, the first source electrode, the first connection electrode, the first drain electrode and the pixel electrode are all arranged on the substrate, a first semiconductor structure is arranged between the first source electrode and the first connection electrode, a second semiconductor structure is arranged between the first connection electrode and the first drain electrode, the first source electrode, the first semiconductor structure, the first connection electrode, the second semiconductor structure and the first drain electrode are connected in sequence, and the pixel electrode is connected to the first drain electrode; Define the channel between the first source electrode and the first connection electrode as the first source channel, and define the channel between the first drain electrode and the first connection electrode as the first drain channel. The length directions of the first source channel and the first drain channel have an included angle; The length directions of the first source channel and the first drain channel are perpendicular; The first connection electrode includes a first connection electrode portion and a second connection electrode portion, and the first connection electrode portion and the second connection electrode portion are perpendicularly connected; The first source electrode includes a first source electrode portion, a second source electrode portion and a third source electrode portion. The first source electrode portion, the second source electrode portion and the third source electrode portion are connected in sequence, and the first source electrode portion and the third source electrode portion are located on both sides of the first connection electrode portion; The first drain electrode includes a first drain electrode portion, a second drain electrode portion and a third drain electrode portion. The first drain electrode portion, the second drain electrode portion and the third drain electrode portion are connected in sequence, and the first drain electrode portion and the third drain electrode portion are located on both sides of the second connection electrode portion.

6. The array substrate according to claim 5, wherein The array substrate includes a second active switch, and the second active switch includes a second gate, a second source, a second connection electrode, and a second drain; the second gate, the second source, the second connection electrode, and the second drain are all disposed on the substrate, and the pixel electrode is further connected to the second drain; A third semiconductor structure is disposed between the second source and the second connection electrode, and a fourth semiconductor structure is disposed between the second connection electrode and the second drain, and the second source, the third semiconductor structure, the second connection electrode, the fourth semiconductor structure, and the second drain are connected in sequence; Define the channel between the second source and the second connection electrode as the second source channel, and define the channel between the second drain and the second connection electrode as the second drain channel, and the length direction of the second source channel is perpendicular to the length direction of the second drain channel; The second connection electrode includes a third connection electrode portion and a fourth connection electrode portion, and the third connection electrode portion and the fourth connection electrode portion are perpendicularly connected; The second source includes a fourth source portion, a fifth source portion, and a sixth source portion, and the fourth source portion, the fifth source portion, and the sixth source portion are connected in sequence, and the fourth source portion and the sixth source portion are located on both sides of the third connection electrode portion; The second drain includes a fourth drain portion, a fifth drain portion, and a sixth drain portion, and the fourth drain portion, the fifth drain portion, and the sixth drain portion are connected in sequence, and the fourth drain portion and the sixth drain portion are located on both sides of the fourth connection electrode portion.

7. The array substrate according to claim 6, wherein The first gate and the second gate are disposed in the same layer, and the first source, the first connection electrode, the first drain, the second source, the second connection electrode, and the second drain are disposed in the same layer; The first connection electrode portion and the fourth connection electrode portion are parallel, the first connection electrode portion and the third connection electrode portion are perpendicular, the second connection electrode portion and the third connection electrode portion are parallel, and the second connection electrode portion and the fourth connection electrode portion are perpendicular.

8. The array substrate according to claim 5, wherein The array substrate further includes a data line and a scan line, and the data line and the scan line are both disposed on the substrate, the data line is connected to the first source of the first active switch, and the scan line is connected to the first gate of the first active switch.

9. A display panel, characterized in that, The display panel includes a driving circuit and the array substrate according to any one of claims 1-8, and the driving circuit is connected to the array substrate for driving the array substrate.

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