MCU self-checking coverage rate optimization system and method

Abstract

The invention relates to the technical field of MCU self-inspection, and discloses an MCU self-inspection coverage rate optimization system and method, and the system comprises a core MCU module which serves as a control center; the self-checking circuit module is used for detecting a core hardware component in the core MCU module according to the detection instruction and sending the detection instruction to the core MCU module; the sensor module is used for collecting physical parameters of the core MCU module in real time and sending the physical parameters to the core MCU module; the fault diagnosis module is used for determining a current fault mode according to a support vector machine algorithm and a preset neural network algorithm, and is also used for predicting a possible fault according to the preset neural network algorithm; and the core MCU module is used for generating a self-checking report. According to the system predictive maintenance unit provided by the embodiment of the invention, faults possibly occurring in the future and corresponding to the detection results and the physical parameters are predicted through a neural network algorithm, the situation that processing is carried out only after the faults occur is avoided, early warning is realized, the self-inspection coverage rate is improved, and thus the safety and stability of the system are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of self - testing of Microcontroller Units (MCUs), and particularly to a system and method for optimizing the self - testing coverage rate of an MCU. Background Art

[0002] With the rapid development of hardware technology, currently, MCU hardware plays a core role in modern electronic systems and is widely used in various fields. The MCU self - testing technology is used to detect the operating status of key components inside the MCU to ensure the system stability of the MCU.

[0003] However, the self - testing of MCUs in related technologies often has a low coverage rate. Therefore, how to improve the self - testing coverage rate of MCUs and enhance the monitoring ability of MCU self - testing has become an urgent problem to be solved. Summary of the Invention

[0004] In view of this, the present invention provides a system and method for optimizing the self - testing coverage rate of an MCU to solve the problem of how to improve the self - testing coverage rate of MCUs and enhance the monitoring ability of MCU self - testing.

[0005] On one hand, the present disclosure provides a system for optimizing the self - testing coverage rate of an MCU. The system includes: a core MCU module, as a control center, is communicatively connected to a self - testing circuit module, a sensor module, and a fault diagnosis module respectively, and is used for receiving inputs from external devices and scheduling self - testing tasks; a self - testing circuit module, connected to the core MCU module, is used for detecting the core hardware components in the core MCU module according to the detection instructions of the core MCU module and sending the detection results to the core MCU module; wherein, the core hardware components include at least one of the following: internal registers, memories, clock circuits, power management components; a sensor module, connected to the core MCU module, is used for real - time collecting physical parameters of the core MCU module during operation and sending the physical parameters to the core MCU module; a fault diagnosis module, connected to the core MCU module, includes a fault mode recognition unit and a predictive maintenance unit, and is used for determining the current fault mode corresponding to the detection results and physical parameters respectively according to the support vector machine algorithm and a preset neural network algorithm, and is also used for predicting possible faults corresponding to the detection results and physical parameters according to the preset neural network algorithm; the core MCU module obtains the current fault mode and possible faults from the fault diagnosis module and generates a self - testing report based on the current fault mode and possible faults.

[0006] On the other hand, the present disclosure also provides an MCU self - testing method, which includes: receiving external inputs through the core MCU module and scheduling self - testing tasks; receiving detection instructions from the core MCU module through the self - testing circuit module, detecting core hardware components in the core MCU module, and sending the detection results to the core MCU module; wherein, the core hardware components include at least one of the following: internal registers, memories, clock circuits, power management components; collecting physical parameters of the core MCU module during operation in real - time through the sensor module, and sending the physical parameters to the core MCU module; determining the current fault mode corresponding to the detection results and the physical parameters according to the support vector machine algorithm through the fault mode recognition unit in the fault diagnosis module; predicting possible future faults corresponding to the detection results and the physical parameters according to the preset neural network algorithm through the predictive maintenance unit in the fault diagnosis module; and generating a self - testing report based on the current fault mode and the possible faults by the core MCU module from the fault diagnosis module.

[0007] On the other hand, the present disclosure also provides a computer - readable storage medium, on which computer instructions are stored, and the computer instructions are used to cause a computer to implement the above - mentioned MCU self - testing method.

[0008] On the other hand, the present disclosure also provides a computer program product, including computer instructions, and the computer instructions are used to cause a computer to execute the above - mentioned MCU self - testing method.

[0009] Through the MCU self - testing coverage optimization system and method of the above - mentioned embodiments of the present disclosure, the predictive maintenance unit predicts possible future faults corresponding to the detection results and the physical parameters through the neural network algorithm, avoids dealing with problems only after faults occur, realizes early warning, improves the self - testing coverage rate, and thus improves the security and stability of the system. The self - testing circuit module covers key components such as internal registers, memories, clock circuits, power management components, etc., can comprehensively detect hardware faults, improves the detection coverage of key components, and ensures the reliability of core components.

[0010] In addition, based on the support vector machine algorithm, the fault mode recognition unit can accurately identify different types of fault modes, make up for the limitations of judging through thresholds in the traditional MCU self - testing process, and improve the recognition ability of complex faults. Brief Description of the Drawings

[0011] To more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the related art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the related art. Obviously, the drawings in the following description are some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0012] Figure 1 Fig. shows an exemplary schematic diagram of the architecture of an MCU self - test coverage optimization system 100 according to an embodiment of the present disclosure;

[0013] Figure 2 Fig. shows an exemplary schematic diagram of the architecture of another MCU self - test coverage optimization system 100 according to an embodiment of the present disclosure;

[0014] Figure 3 Fig. shows an exemplary schematic diagram of the architecture of yet another MCU self - test coverage optimization system 100 according to an embodiment of the present disclosure;

[0015] Figure 4 Fig. shows an exemplary schematic diagram of the architecture of still another MCU self - test coverage optimization system 100 according to an embodiment of the present disclosure;

[0016] Figure 5 Fig. shows an exemplary schematic diagram of the architecture of still another MCU self - test coverage optimization system 100 according to an embodiment of the present disclosure;

[0017] Figure 6 is a flowchart of an MCU self - test method provided by an embodiment of the present disclosure;

[0018] Figure 7 is a schematic diagram of the structure of an MCU self - test coverage optimization system provided by an embodiment of the present disclosure. Specific Embodiments

[0019] As a chip integrating functions such as a central processing unit, a memory, and various peripheral interfaces, the MCU plays a core role in modern electronic systems. Its application fields are extremely wide, covering many fields such as industrial automation, automotive electronics, smart home, medical devices, aerospace, and consumer electronics.

[0020] In the field of industrial automation, MCUs are used to control various devices on the production line to achieve precise motion control and process monitoring. In automotive electronics, MCUs are responsible for controlling key functions such as vehicle engine management, anti-lock braking systems, and electronic stability control systems. Smart home devices such as smart locks and smart home appliances also rely on MCUs to achieve intelligent control and interaction. In medical devices, MCUs ensure the accurate measurement and stable operation of devices such as blood glucose meters, blood pressure monitors, and patient monitors. The aerospace field has extremely high requirements for the reliability and performance of MCUs, which are used in key systems such as aircraft navigation and flight control.

[0021] However, the MCU self-checking methods in related technologies often have the following problems:

[0022] 1. Related technologies mainly rely on simple threshold judgment and basic function tests, which can only detect some obvious and static faults. For some complex fault modes, it is difficult to effectively cover them, resulting in a low coverage rate of MCU self-checking.

[0023] 2. Related technologies usually detect and diagnose after a fault occurs (i.e., the post-processing method), and cannot perform real-time trend analysis and prediction on the operating state of the MCU, and cannot detect potential fault hazards in advance. This makes the maintenance work often in a passive state, and only repairs when obvious fault symptoms appear in the system, which may lead to an extended downtime of the device and affect production efficiency. In applications with high reliability requirements (such as medical and aerospace), it may also lead to serious safety risks due to the failure to detect faults in advance.

[0024] To solve the above problems, various embodiments of the present disclosure provide an MCU self - test coverage optimization system. The system includes: a core MCU module, serving as a control center, communicatively connected to a self - test circuit module, a sensor module, and a fault diagnosis module respectively, for receiving inputs from external devices and scheduling self - test tasks; a self - test circuit module, connected to the core MCU module, for detecting core hardware components in the core MCU module according to the detection instructions of the core MCU module and sending the detection results to the core MCU module; wherein, the core hardware components include at least one of the following: internal registers, memories, clock circuits, power management components; a sensor module, connected to the core MCU module, for real - time collecting physical parameters of the core MCU module during operation and sending the physical parameters to the core MCU module; a fault diagnosis module, connected to the core MCU module, including a fault mode recognition unit and a predictive maintenance unit, for respectively determining the current fault mode corresponding to the detection results and physical parameters according to the support vector machine algorithm and a preset neural network algorithm, and also for predicting possible faults corresponding to the detection results and physical parameters according to the preset neural network algorithm; the core MCU module, obtaining the current fault mode and possible faults from the fault diagnosis module and generating a self - test report based on the current fault mode and possible faults.

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0026] Please refer to Figure 1 , Figure 1 , which shows an exemplary schematic diagram of the architecture of an MCU self - test coverage optimization system 100 according to an embodiment of the present disclosure. As Figure 1 shown, the system includes:

[0027] A core MCU module 101, serving as a control center, is communicatively connected to a self - test circuit module, a sensor module, and a fault diagnosis module respectively, for receiving inputs from external devices and scheduling self - test tasks.

[0028] In this embodiment, the core MCU module 101, serving as a control center, can be used to undertake scheduling, control, and data - processing tasks. The core MCU module 101 can receive instructions from external devices, trigger each module according to the instructions, and execute detection tasks. Among them, the external devices can include at least one of the following: diagnostic tools, host computers, network interfaces. The instructions can include at least one of the following: request for self - test, adjustment of self - test strategy, reading of self - test report.

[0029] Further, the core MCU module 101 can be used to receive the data of the self-checking circuit module and the sensor module respectively, and send the data to the fault diagnosis module.

[0030] The self-checking circuit module 102 is connected to the core MCU module 101 and is used to detect the core hardware components in the core MCU module 101 according to the detection instruction of the core MCU module 101, and send the detection result to the core MCU module 101.

[0031] In this embodiment, the core MCU module 101 is used to send a detection instruction to the self-checking circuit module 102 based on a preset triggering method; wherein, the preset triggering method can include: timing trigger, instruction trigger, manual trigger. For example, the timing trigger can be to trigger the detection task at a preset self-checking period, the event trigger can be to trigger the detection task based on an external instruction, and the manual trigger can be triggered by the command of the maintenance personnel.

[0032] The core hardware components include at least one of the following: internal register, memory, clock circuit, power management component.

[0033] In a possible implementation manner of the above embodiment, the self-checking circuit module 102 can specifically be used for:

[0034] Access the internal register and detect whether the value of the internal register conforms to the expected value;

[0035] Perform at least one of cyclic redundancy check (CRC) verification, error correcting code (ECC) verification, or read / write test on the memory;

[0036] Monitor the clock circuit, read the clock source and measure the actual working frequency of the clock source, calculate the clock deviation, and check whether it is within the preset allowable range;

[0037] Detect the access voltage, working voltage and other data of the power management component to ensure that the voltage is stable within the expected range.

[0038] Further, the self-checking circuit module 102 can also specifically be used to process at least one piece of detection data, pack the data, and send it to the core MCU module 101. Wherein, processing the detection data can include: identifying abnormal situations and / or errors, and marking the levels of abnormal situations and / or errors; the levels can include at least one of the following: ignorable level, warning level, or severe fault level.

[0039] The sensor module 103 is connected to the core MCU module 101 and is used to collect in real time the physical parameters of the core MCU module 101 during operation based on the acquisition instruction of the core MCU module 101, and send the physical parameters to the core MCU module 101.

[0040] In this embodiment, the sensor module 103 can be used to collect in real time the temperature data of the core sensor, collect the supply voltage of the power monitoring chip, and collect the working current through the current sensor, etc.

[0041] The fault diagnosis module 104 is connected to the core MCU module 101 and includes a fault mode recognition unit 1041 and a predictive maintenance unit 1042. It is used to determine the current fault mode corresponding to the detection result and the physical parameters respectively according to the support vector machine algorithm and the preset neural network algorithm, and is also used to predict the possible faults corresponding to the detection result and the physical parameters according to the preset neural network algorithm.

[0042] In this embodiment, the fault mode recognition unit 1041 is used to determine the current fault mode corresponding to the detection result and the physical parameters according to the support vector machine algorithm and the preset neural network algorithm;

[0043] The predictive maintenance unit 1042 is used to predict the possible faults corresponding to the detection result and the physical parameters according to the preset neural network algorithm.

[0044] Among them, the support vector machine algorithm (Support Vector Machine, SVM) can be a supervised learning algorithm for classification and regression tasks. By finding an optimal hyperplane in the high-dimensional feature space to maximize the interval between different category samples, efficient classification can be achieved.

[0045] As an example, the formula of the SVM algorithm adopted by the fault mode recognition unit 1041 is as follows:

[0046]

[0047] Furthermore, the constraint conditions of the SVM algorithm can be as follows:

[0048] y i =(w T x 1 +b)≥1,i=1,2,…,n

[0049] Among them, w can be the normal vector of the hyperplane, b is the bias term, x 1 is the data sample, y iis the class label of the sample (usually +1 or -1), n is the number of samples. For the non-linearly separable case, the data can be mapped to a high-dimensional space through a kernel function to make it linearly separable in the high-dimensional space.

[0050] In a possible implementation of the above embodiment, the predictive maintenance unit 1042 is configured to perform time series analysis on the operation data of the MCU, establish a fault prediction model, and predict possible future faults.

[0051] Specifically, the operation data may include at least one of the following: key physical parameters, historical fault labels, operation status logs; sort the operation data by timestamp, and preprocess the operation data and divide it into a training set, a validation set, and a test set. Adopt a preset deep learning architecture to perform model training and establish a fault prediction model.

[0052] As an example, the preset deep learning architecture may be a Long Short Term Memory (LSTM) network.

[0053] Furthermore, the predictive maintenance unit 1042 is configured to input the operation data collected from the core MCU module 101 into the fault prediction model to determine the type and probability of possible faults.

[0054] Here, as an example, when the fault probability of a possible fault is less than 50%, it can be determined that the core MCU module 101 is in a normal operation state; when the fault probability of a possible fault is greater than 50% and less than 80%, the core MCU module 101 is put into a warning state to notify relevant personnel for manual inspection; when the fault probability of a possible fault is greater than 80%, the core MCU module 101 triggers a fault warning and automatically executes a maintenance task.

[0055] The core MCU module 101 is configured to obtain the current fault mode and possible faults from the fault diagnosis module 104, and generate a self-check report based on the current fault mode and possible faults.

[0056] In this embodiment, the core MCU module 101 is configured to obtain the current fault mode from the fault mode recognition unit 1041, and obtain the type and probability of possible faults from the predictive maintenance unit 1042.

[0057] In a possible implementation, the core MCU module 101 is further configured to set the priority of the faults in the self-check report according to the severity and impact range of the current fault mode and possible faults.

[0058] As an example, the priorities may include: high priority, medium priority, and low priority. Among them, high priority may characterize a fault that may cause the system to crash and needs to be repaired immediately; medium priority may characterize a fault that may affect the stability of the MCU but does not affect the function temporarily and can be continuously monitored; low priority may characterize a fault that will not affect the function of the MCU in the short term.

[0059] Furthermore, the self-check report generated by the core MCU module 101 may include at least one of the following: basic information, current faults, possible faults, and recommended measures.

[0060] Even further, the core MCU module 101 can be used to send the self-check report to an external device in a preset format for storage and analysis.

[0061] For example, the preset format may include: JavaScript Object Notation (JSON), Extensible Markup Language (XML).

[0062] Through the MCU self-check coverage optimization system and method of the above embodiments of the present disclosure, the predictive maintenance unit 1042 predicts possible future faults corresponding to the detection results and physical parameters through a neural network algorithm, avoiding dealing with problems only after a fault occurs, achieving early warning, improving the self-check coverage rate, and thus improving the security and stability of the system. The self-check circuit module 102 covers key components such as internal registers, memories, clock circuits, and power management components, and can comprehensively detect hardware faults, improve the detection coverage of key components, and ensure the reliability of core components. The fault mode recognition unit 1041 is based on the support vector machine algorithm and can accurately identify different types of fault modes, making up for the limitations of traditional MCU self-checking through threshold judgment and enhancing the recognition ability of complex faults.

[0063] In a possible implementation manner of the above embodiment, please refer to Figure 2 , Figure 2 shows an exemplary schematic diagram of the architecture of another MCU self-check coverage optimization system 100 according to an embodiment of the present disclosure. As Figure 2 shown, the system further includes a redundancy design module 105. The redundancy design module 105 includes:

[0064] A hardware redundancy unit 1051, which adopts a dual MCU architecture or a multi-MCU architecture, includes a main MCU and at least one standby MCU. The main MCU is the core MCU module 101. The main MCU is communicatively connected to at least one standby MCU. The main MCU is configured to run simultaneously with at least one standby MCU and detect each other through heartbeat signals;

[0065] The hardware redundancy unit 1051 is also used to perform redundant configuration on the core hardware components and sensors in the main MCU.

[0066] The software redundancy unit 1052 is used to configure the core MCU module 101 to schedule at least one software module with the same function but different implementation codes, run at least one software module in parallel, compare the output results of at least one software module, and trigger an alarm when the difference is greater than a preset threshold.

[0067] In this embodiment, the hardware redundancy unit 1051 is used to establish an MCU redundant architecture, enable the main MCU and the standby MCU to run synchronously, and detect each other through heartbeat signals.

[0068] Among them, the hardware redundancy unit 1051 is specifically used to, during the initialization process of the system, enable the main MCU and at least one standby MCU to complete power-on self-check, establish a communication connection, determine its own role (main MCU or standby MCU), and complete data synchronization between the main MCU and the standby MCU through a hardware bus or a shared memory.

[0069] Furthermore, the hardware redundancy unit 1051 is specifically used to enable the main MCU and the standby MCU to run simultaneously, execute the same control logic or task calculation, and enable the main MCU and the standby MCU to detect each other through heartbeat signals to ensure that the other party is in a normal operating state.

[0070] Among them, if a certain MCU fails to respond to the heartbeat signal on time, the hardware redundancy unit 105 can determine that the above MCU may have a fault and trigger a redundant switch.

[0071] Furthermore, the core MCU module 101 can be used to schedule multiple software modules with the same function but different implementation methods. Among them, the software modules run in parallel and calculate the same input data respectively.

[0072] The core MCU module 101 can also be used to calculate the output results of multiple software modules and compare the differences between the output results.

[0073] Specifically, if each output result is consistent, the core MCU module 101 determines that the result is valid; if some output results are different, the core MCU module 101 performs multiple checks for decision-making; if the output difference is greater than a preset threshold, the core MCU module 101 determines that the system may have an abnormality.

[0074] Furthermore, when it is detected that the difference in the output results of the software modules exceeds the threshold, the core MCU module 101 can be used to perform the following operations:

[0075] Record abnormal data and store logs;

[0076] Trigger a fault alarm to prompt the maintenance personnel to check the problem.

[0077] Through the MCU self-check coverage optimization system and method of the above embodiments of the present disclosure, through a dual-MCU or multi-MCU architecture, in this embodiment, when multiple MCUs are running synchronously, they can monitor each other's states, and achieve real-time fault detection through heartbeat signals. Once a certain MCU fails, the standby MCU can quickly take over the task to avoid system failure, thereby improving the self-check coverage. Traditional self-checks often rely on periodic detection, while this system can detect abnormalities in the first time when problems occur through real-time heartbeat detection, improving the stability of the system. Through the software redundancy unit, this system supports the parallel operation of multiple software modules with the same function but different implementation methods, and can effectively detect abnormalities at the software level.

[0078] In a possible implementation manner of the above embodiment, please refer to Figure 3 , Figure 3 FIG. shows an exemplary schematic diagram of the architecture of another MCU self-check coverage optimization system 100 according to an embodiment of the present disclosure. As Figure 3 shown, the system further includes an on-line debugging and simulation module 106. The on-line debugging and simulation module 106 includes:

[0079] An on-chip debugging unit 1061, connected to the core MCU module 101, is used to, according to the real-time monitoring instruction of the core MCU module 101, adopt the on-chip debugging interface in the core MCU module 101 to monitor the status information of the registers, memories and program counters in the core MCU module 101 in real time, and send the status information to the core MCU module 101;

[0080] A real-time simulation unit 1062, connected to the core MCU module 101, is used to simulate the operating environment of the core MCU module 101 based on an external real-time emulator, capture the operating status of the core MCU module 101 in the development and test stages and the actual operation stage, and generate a status analysis result, and send the status analysis result to the core MCU module 101.

[0081] In this embodiment, after the MCU is powered on or reset, the core MCU module 101 sends an initialization instruction to the on-chip debugging unit 1061 to activate the on-chip debugging unit 1061;

[0082] The on-chip debugging unit 1061 configures the on-chip debugging interface, establishes a communication connection with the MCU internal bus, determines the monitoring target and sets the sampling strategy;

[0083] The on-chip debugging unit 1061 is specifically used to read the register status, monitor the memory data and obtain the program counter value, and send the monitored data to the core MCU module 101.

[0084] Here, when there is an abnormality in the value of the register, the memory data is unexpectedly modified, or the program counter jumps to an illegal address, the on-chip debug unit 1061 triggers an alarm and sends the abnormal status to the fault diagnosis module 104 for analysis.

[0085] Furthermore, the on-chip debug unit 1061 can also be used for remote online debugging through the on-chip debug interface to modify the internal state of the MCU; it can also be used to optimize the code and troubleshoot problems of the MCU in combination with the debug information.

[0086] In a possible implementation manner of the above embodiment, after the core MCU module 101 is powered on or reset, it sends an initialization instruction to the real-time simulation unit 1062. The real-time simulation unit 1062 can establish a connection with an external real-time emulator, and the real-time simulation unit 1062 sets the simulation mode of the MCU and synchronizes the key parameters of the MCU to the emulator.

[0087] Furthermore, the external emulator simulates the MCU peripherals, memory, bus interaction, and sensor signals, and provides the input signals flowing to the simulation environment in real time data to the core MCU module 101, enabling the core MCU module 101 to execute tasks in the simulation environment, and the real-time simulation unit 1062 records the MCU operation data.

[0088] Specifically, the real-time simulation unit 1062 is used for instruction execution tracking, memory status monitoring, external response monitoring, and real-time interrupt analysis. The real-time simulation unit 1062 analyzes the behavior consistency of the MCU in the simulation environment and the actual operating environment through data comparison, counts the abnormal behaviors, and sends them to the core MCU module 101.

[0089] Through the MCU self-check coverage optimization system and method of the above embodiments of the present disclosure, the on-chip debug unit 1061 effectively captures potential abnormalities inside the system by real-time reading the register status, memory data, and program counter. These monitoring results can be timely fed back to the core MCU module 101 to help it determine whether the MCU is in a normal operating state, thereby improving the real-time performance of monitoring. By combining the on-chip debug unit and the real-time simulation unit, the system can not only perform comprehensive debugging and testing during the development stage, but also capture various situations that may cause faults during the actual operation stage, further improving the self-check coverage of the MCU.

[0090] In a possible implementation manner of the above embodiment, please refer to Figure 4 , Figure 4 shows an exemplary schematic diagram of the architecture of another MCU self-check coverage optimization system 100 according to an embodiment of the present disclosure. As Figure 4 shown, the system further includes a bus monitoring and diagnosis module 107, and the bus monitoring and diagnosis module 107 includes:

[0091] The bus signal monitoring unit 1071 is connected to the core MCU module 101 and is used to set up a monitoring circuit for the bus where the core MCU module 101 is connected to external devices, and to monitor the signal level, data transmission rate, and timing parameters of the bus in real time, and send the monitoring results to the core MCU module 101;

[0092] The bus fault diagnosis protocol unit 1072 is connected to the core MCU module 101 and is used to locate and diagnose faults on the bus based on a preset bus fault diagnosis protocol, generate corresponding diagnostic measures based on the type and severity of the faults, and send the diagnostic measures to the core MCU module 101.

[0093] In this embodiment, when the system starts up, the core MCU module 101 sends an initialization instruction to the bus monitoring and diagnosis module 107 to activate the bus signal monitoring unit 1071 and the bus fault diagnosis protocol unit 1072. After receiving the initialization instruction, the bus signal monitoring unit 1071 starts to configure the monitoring circuit and connects it to the bus between the core MCU module 101 and external devices, and is ready to start real-time signal monitoring.

[0094] Furthermore, the bus signal monitoring unit 1071 can be used to monitor the voltage transformation on the bus to ensure that the level is within the normal operating range, can be used to check the data transmission speed on the bus to ensure that the packet speed meets the design standard, and can also be used to monitor the timing parameters of data transmission to ensure that the data is transmitted within a predetermined time window. The bus signal monitoring unit 1071 can also be used to send the monitoring results to the core MCU module 101.

[0095] Even further, the bus fault diagnosis protocol unit 1072 can be used to locate and diagnose bus faults according to the bus fault diagnosis protocol. Among them, the specific type of the fault can be identified, and the severity of the fault can be evaluated according to the specific type.

[0096] According to the type and severity of the fault, the bus fault diagnosis protocol unit 1072 can generate specific diagnostic measures and send the diagnostic measures to the core MCU module 101 so that the system can take corresponding actions.

[0097] Through the MCU self-check coverage rate optimization system and method of the above embodiments of the present disclosure, through the real-time monitoring and diagnosis of the bus monitoring and diagnosis module 107, the system can comprehensively check the health status of the bus, timely identify abnormalities on the bus, and take appropriate measures for repair or alarm. This mechanism ensures that the communication between the MCU and external devices will not be interrupted due to bus faults, thereby improving the self-check coverage rate and the reliability of the system.

[0098] In a possible implementation of the above embodiment, the self-checking circuit module 102 is further configured to, according to the fault simulation signal of the core MCU module 101, simulate at least one fault condition in the core hardware components of the core MCU module 101 based on the preset fault injection and simulation functions, and send the fault simulation result to the core MCU module 101.

[0099] In this embodiment, after the core MCU module 101 is powered on or reset, it can send an initialization instruction to the self-checking circuit module 102 to activate the fault simulation function of the self-checking circuit module 102. The self-checking circuit module 102 can configure the necessary hardware and software resources to ensure that it can receive the fault simulation signal from the core MCU module 101 and can perform the simulation operation normally.

[0100] Further, after receiving the fault simulation signal, the self-checking circuit module 102 can be used for specific fault simulation. According to the preset fault injection scheme, the fault signal is injected into the core hardware components. In addition, the self-checking circuit module 102 can also simulate complex faults such as intermittent faults and delay faults to test the response ability of the system to various abnormal situations.

[0101] Furthermore, the self-checking circuit module 102 monitors the fault status in real time, generates the fault simulation result, and sends the fault simulation result to the core MCU module 101; wherein, the fault simulation result may include at least one of the following: the moment, type, location and duration of the fault occurrence, the influence range of the fault and the possible consequences, the system response and state change after the fault simulation.

[0102] Through the MCU self-checking coverage rate optimization system and method of the above embodiments of the present disclosure, through the fault simulation and injection process, the self-checking circuit module 102 can simulate various possible fault scenarios and verify the self-checking mechanism and response ability of the core MCU module 101. This process can improve the fault detection rate of the system during actual operation, ensure that various potential faults can be identified and responded to in advance, and significantly improve the self-checking coverage rate and the reliability of the system.

[0103] In a possible implementation of the above embodiment, please refer to Figure 5 , Figure 5 which shows an exemplary schematic diagram of the architecture of another MCU self-checking coverage rate optimization system 100 according to an embodiment of the present disclosure. As Figure 5 shown, the system further includes a communication interface module 108 and a display module 109, wherein:

[0104] The communication interface module 108 is connected to the core MCU module 101 and is used to implement the communication between the core MCU module 101 and external devices, receive the instruction information of the external devices, and send the self-checking report to the external devices;

[0105] The display module 109 is connected to the core MCU module 101 and is used to display the self - test report and diagnostic measures of the core MCU module 101.

[0106] In this embodiment, the core MCU module 101 can be connected to the communication interface module 108 through a physical communication interface to establish a communication channel. The communication interface module 108 initializes and prepares to receive the instruction information sent by the core MCU module 101 and prepares to send the self - test report.

[0107] The external device communicates with the core MCU module 101 through the communication interface module 108 and sends a self - test control instruction. After the self - test task is completed, the core MCU module 101 sends the self - test report to the external device through the communication interface module 108.

[0108] Furthermore, the core MCU module 101 is connected to the display module 109 through a display interface to establish a display channel; the display module 109 is initialized and prepares to receive the self - test report and diagnostic measures from the core MCU module 101.

[0109] After receiving the self - test report, the display module 109 can display the information visually to the operator or maintenance personnel.

[0110] Through the MCU self - test coverage rate optimization system and method of the above - mentioned embodiments of the present disclosure, through the cooperation of the communication interface module 108 and the display module 109, the system can effectively transmit the self - test report and fault diagnosis information to the external device or display it to the user. This not only facilitates the remote monitoring and maintenance of the device, but also improves the self - test efficiency and coverage rate of the system, ensuring that when potential faults are detected, the maintenance personnel can be notified in a timely manner, thereby shortening the fault handling time and improving the reliability and stability of the device.

[0111] In one embodiment, further referring to Figure 6 , Figure 6 is a flowchart of a MCU self - test method provided by an embodiment of the present disclosure, which is applied to the MCU self - test coverage rate optimization system 100 shown in any one of the above Figures 1 - 5 , and the process of this method can include the following steps:

[0112] Step S601: Receive external input through the core MCU module 101 and schedule the self - test task.

[0113] Step S602: Receive the detection instruction from the core MCU module 101 through the self - test circuit module 102, detect the core hardware components in the core MCU module 101, and send the detection result to the core MCU module 101.

[0114] In this embodiment, the core hardware components include at least one of the following: internal registers, memories, clock circuits, and power management components.

[0115] Step S603: The sensor module 103 is used to collect the physical parameters of the core MCU module 101 in real time during operation and send the physical parameters to the core MCU module 101.

[0116] Step S604: The fault mode recognition unit 1041 in the fault diagnosis module 104 determines the current fault mode corresponding to the detection result and the physical parameters according to the support vector machine algorithm.

[0117] Step S605: The predictive maintenance unit 1042 in the fault diagnosis module 104 predicts the possible faults corresponding to the detection result and the physical parameters according to the preset neural network algorithm.

[0118] Step S606: The core MCU module 101 obtains the current fault mode and possible faults from the fault diagnosis module 104 and generates a self-check report based on the current fault mode and possible faults.

[0119] Through the MCU self-check coverage optimization system and method of the above embodiments of the present disclosure, the predictive maintenance unit 1042 predicts the possible future faults corresponding to the detection result and the physical parameters through the neural network algorithm, avoiding dealing with problems only after faults occur, realizing early warning, improving the self-check coverage rate, and thus improving the security and stability of the system. The self-check circuit module 102 covers key components such as internal registers, memories, clock circuits, and power management components, can comprehensively detect hardware faults, improve the detection coverage of key components, and ensure the reliability of core components. The fault mode recognition unit 1041 is based on the support vector machine algorithm and can accurately identify different types of fault modes, making up for the limitations of the traditional MCU self-check process through threshold judgment and improving the recognition ability of complex faults.

[0120] In a possible implementation manner of the above embodiment, the method further includes: the hardware redundancy unit 1051 adopts a dual-MCU architecture or a multi-MCU architecture, sets the core MCU module 101 as the main MCU, enables the main MCU to communicate with at least one standby MCU, and configures the main MCU and at least one standby MCU to run simultaneously and detect each other through heartbeat signals;

[0121] The hardware redundancy unit 1051 performs redundant configuration on the core hardware components and sensors in the main MCU;

[0122] Through the software redundancy unit 1052, at least one software module with the same function but different implementation codes is generated, enabling the core MCU module 101 to run at least one software module in parallel, comparing the output results of at least one software module for differences, and triggering an alarm when the difference is greater than a preset threshold.

[0123] Through the MCU self - test coverage optimization system and method of the above - mentioned embodiments of the present disclosure, with a dual - MCU or multi - MCU architecture, in this embodiment, when multiple MCUs are running synchronously, they can monitor each other's states, and real - time fault detection can be achieved through heartbeat signals. Once a certain MCU fails, the standby MCU can quickly take over the task to avoid system failure, thereby improving the self - test coverage rate. Traditional self - tests often rely on periodic detection, while this system can detect abnormalities at the first moment when problems occur through real - time heartbeat detection, enhancing the stability of the system. Through the software redundancy unit, this system supports the parallel operation of multiple software modules with the same function but different implementation methods, and can effectively detect software - level abnormalities.

[0124] In a possible implementation manner of the above - mentioned embodiment, the method further includes: through the on - chip debugging unit 1061, according to the real - time monitoring instructions of the core MCU module 101, using the on - chip debugging interface in the core MCU module 101, the status information of the registers, memories, and program counters in the core MCU module 101 is monitored in real time, and the status information is sent to the core MCU module 101;

[0125] Through the real - time simulation unit 1062, based on an external real - time emulator, the operating environment of the core MCU module 101 is simulated, the operating status of the core MCU module 101 is captured in the development and test stages and the actual operation stage, and a status analysis result is generated, and the status analysis result is sent to the core MCU module 101.

[0126] Through the MCU self - test coverage optimization system and method of the above - mentioned embodiments of the present disclosure, the on - chip debugging unit 1061 can effectively capture potential abnormalities inside the system by reading the register status, memory data, and program counter in real time. These monitoring results can be timely fed back to the core MCU module 101 to help it determine whether the MCU is in a normal operating state, thereby improving the real - time performance of monitoring. By combining the on - chip debugging unit and the real - time simulation unit, the system can not only conduct comprehensive debugging and testing during the development stage, but also capture various situations that may cause failures during the actual operation stage, further improving the self - test coverage rate of the MCU.

[0127] In a possible implementation of the above embodiment, the method further includes: through the bus signal monitoring unit 1071, a monitoring circuit is set on the bus where the core MCU module 101 is connected to external devices, to monitor the signal level, data transmission rate, and timing parameters of the bus in real time, and send the monitoring results to the core MCU module 101;

[0128] Through the bus fault diagnosis protocol unit 1072, based on a preset bus fault diagnosis protocol, locate and diagnose faults on the bus, generate corresponding diagnostic measures based on the type and severity of the faults, and send the diagnostic measures to the core MCU module 101.

[0129] Through the MCU self-check coverage rate optimization system and method of the above embodiment of the present disclosure, through the real-time monitoring and diagnosis of the bus monitoring and diagnosis module 107, the system can comprehensively check the health status of the bus, timely identify abnormalities on the bus, and take appropriate measures for repair or warning. This mechanism ensures that the communication between the MCU and external devices will not be interrupted due to bus faults, thereby improving the self-check coverage rate and the reliability of the system.

[0130] In a possible implementation of the above embodiment, the method further includes: through the self-check circuit module 102, according to the fault simulation signal of the core MCU module 101, based on the preset fault injection and simulation functions, simulate at least one fault condition in the core hardware components of the core MCU module 101, and send the fault simulation results to the core MCU module 101.

[0131] Through the MCU self-check coverage rate optimization system and method of the above embodiment of the present disclosure, through the fault simulation and injection process, the self-check circuit module 102 can simulate various possible fault scenarios and verify the self-check mechanism and response ability of the core MCU module 101. This process can improve the fault detection rate during actual operation of the system, ensure early identification and response under various potential fault conditions, and significantly improve the self-check coverage rate and the reliability of the system.

[0132] In a possible implementation of the above embodiment, the method further includes: through the communication interface module 108, implement communication between the core MCU module 101 and external devices, receive instruction information from external devices, and send a self-check report to external devices;

[0133] Through the display module 109, display the self-check report and diagnostic measures of the core MCU module 101.

[0134] Through the MCU self - test coverage optimization system and method of the above - mentioned embodiments of the present disclosure, through the cooperation of the communication interface module 108 and the display module 109, the system can effectively transmit the self - test report and fault diagnosis information to external devices or display them to users. This not only facilitates the remote monitoring and maintenance of the device, but also improves the self - test efficiency and coverage rate of the system, ensuring that maintenance personnel can be notified in a timely manner when potential faults are detected, thereby shortening the fault handling time and improving the reliability and stability of the device.

[0135] It should be noted that when the above - mentioned embodiment provides an MCU self - test coverage optimization system to implement the corresponding MCU self - test method, only the above - mentioned division of each program module is used for illustration. In actual applications, the above - mentioned processing can be allocated to different program modules according to needs, that is, the internal structure of the above - mentioned system is divided into different program modules to complete all or part of the above - described processing. In addition, the system provided in the above - mentioned embodiment and the corresponding Figure 6 The embodiment of the method shown belongs to the same concept, and the specific implementation process can be seen in the method embodiment, which will not be elaborated here.

[0136] The embodiments of the present disclosure also provide a computer device having the MCU self - test coverage optimization system shown in any one of the above Figures 1 - 5 items.

[0137] Please refer to Figure 7 , Figure 7 which is a schematic structural diagram of an MCU self - test coverage optimization system provided by an embodiment of the present disclosure. As shown in Figure 7 , the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high - speed interfaces and low - speed interfaces. Each component communicates with each other using different buses and can be installed on a common main board or installed in other ways according to needs. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a set of blade servers, or a multi - processor system). Figure 7 In

[0138] The processor 10 may be a central processing unit, a network processor, or a combination thereof. Among them, the processor 10 may further include a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The above-mentioned programmable logic device may be a complex programmable logic device, a field programmable gate array, a generic array logic, or any combination thereof.

[0139] Among them, the memory 20 stores instructions that can be executed by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiments.

[0140] The memory 20 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may further include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 may optionally include a memory remotely provided with respect to the processor 10, and these remote memories may be connected to the computer device through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0141] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk, or a solid-state drive; the memory 20 may further include a combination of the above types of memories.

[0142] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30, and the output device 40 may be connected through a bus or other means. Figure 7 Taking connection through a bus as an example.

[0143] The input device 30 can receive input digital or character information, and generate key signal inputs related to the user settings and function controls of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (such as an LED), and a tactile feedback device (such as a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display, and a plasma display. In some alternative embodiments, the display device may be a touch screen.

[0144] The computer device further includes a communication interface for the computer device to communicate with other devices or communication networks.

[0145] Embodiments of the present disclosure also provide a computer-readable storage medium. The methods according to the embodiments of the present disclosure can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code that is originally stored in a remote storage medium or a non-transitory machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the methods described herein can be processed by such software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods shown in the above embodiments are implemented.

[0146] A part of the present disclosure can be applied as a computer program product, for example, computer program instructions, which when executed by a computer, can call or provide the methods and / or technical solutions according to the present disclosure through the operation of the computer. Those skilled in the art should understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Herein, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible by the computer.

[0147] Although the embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A MCU self-test coverage optimization system, characterized in that: The system comprises: The core MCU module, as the control center, is connected to the self-checking circuit module, the sensor module and the fault diagnosis module respectively, and is used to receive input from external devices and schedule self-checking tasks; The self-test circuit module is connected to the core MCU module and is used to test the core hardware components in the core MCU module according to the detection instructions of the core MCU module, and send the test results to the core MCU module; wherein the core hardware components include at least one of the following: internal registers, memory, clock circuits, and power management components; The sensor module is connected to the core MCU module and is used to collect physical parameters of the core MCU module in real time during operation and send the physical parameters to the core MCU module; The fault diagnosis module is connected to the core MCU module, and includes a fault mode recognition unit and a predictive maintenance unit, which are used to determine the current fault mode corresponding to the detection result and the physical parameter according to a support vector machine algorithm and a preset neural network algorithm, respectively, and to predict the possible fault corresponding to the detection result and the physical parameter according to the preset neural network algorithm; The core MCU module obtains the current fault mode and the possible faults from the fault diagnosis module, and generates a self-test report based on the current fault mode and the possible faults.

2. The system according to claim 1, characterized in that The system further includes a redundant design module, the redundant design module including: A hardware redundancy unit adopts a dual MCU architecture or a multi-MCU architecture, including a main MCU and at least one backup MCU, wherein the main MCU is a core MCU module, the main MCU is communicatively connected with the at least one backup MCU, and the main MCU is configured to run simultaneously with the at least one backup MCU and detect each other through a heartbeat signal; The hardware redundancy unit is also used to perform redundant configuration on the core hardware components and sensors in the main MCU; The software redundancy unit is used to configure the core MCU module to schedule at least one software module with the same function and different implementation code, run the at least one software module in parallel, compare the output results of the at least one software module, and trigger an alarm when the difference is greater than a preset threshold.

3. The system according to claim 2, characterized in that The system also includes an online debugging and simulation module, which includes: An on-chip debugging unit is connected to the core MCU module and is used to monitor the status information of the registers, memory and program counter in the core MCU module in real time according to the real-time monitoring instruction of the core MCU module and adopt the on-chip debugging interface in the core MCU module, and send the status information to the core MCU module; A real-time simulation unit is connected to the core MCU module and is used to simulate the operating environment of the core MCU module based on an external real-time simulator, capture the operating status of the core MCU module and generate status analysis results during the development and testing phase and the actual operation phase, and send the status analysis results to the core MCU module.

4. The system according to claim 3, characterized in that The system further comprises a bus monitoring and diagnosis module, wherein the bus monitoring and diagnosis module comprises: A bus signal monitoring unit is connected to the core MCU module and is used to set a monitoring circuit on the bus connecting the core MCU module and the external device, monitor the signal level, data transmission rate and timing parameters of the bus in real time, and send the monitoring result to the core MCU module; The bus fault diagnosis protocol unit is connected to the core MCU module and is used to locate and diagnose the fault on the bus based on a preset bus fault diagnosis protocol, generate corresponding diagnostic measures based on the type and severity of the fault, and send the diagnostic measures to the core MCU module.

5. The system according to claim 1, characterized in that The self-test circuit module is also used to simulate at least one fault condition in the core hardware components of the core MCU module according to the fault simulation signal of the core MCU module based on preset fault injection and simulation functions, and send the fault simulation result to the core MCU module.

6. The system according to any one of claims 1 to 5, characterized in that: The system also includes a communication interface module and a display module, wherein: A communication interface module, connected to the core MCU module, is used to realize communication between the core MCU module and an external device, receive command information from the external device, and send a self-test report to the external device; The display module is connected to the core MCU module and is used to display the self-test report and diagnostic measures of the core MCU module.

7. An MCU self-checking method, applied to the MCU self-checking coverage optimization system according to any one of claims 1 to 6, characterized in that: The method comprises: Through the core MCU module, it receives external input and schedules self-check tasks; Receiving the detection instruction of the core MCU module through the self-test circuit module, detecting the core hardware components in the core MCU module, and sending the detection results to the core MCU module; wherein the core hardware components include at least one of the following: internal registers, memory, clock circuits, and power management components; By means of a sensor module, physical parameters of the core MCU module during operation are collected in real time, and the physical parameters are sent to the core MCU module; Determine the current fault mode corresponding to the detection result and the physical parameter through a fault mode recognition unit in the fault diagnosis module according to a support vector machine algorithm; By means of a predictive maintenance unit in the fault diagnosis module, a possible fault corresponding to the detection result and the physical parameter is predicted according to a preset neural network algorithm; The core MCU module obtains the current fault mode and the possible fault from the fault diagnosis module, and generates a self-test report based on the current fault mode and the possible fault.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the MCU self-test method described in claim 7 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the MCU self-test method described in claim 7.

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