Miniature digital transceiver module

Abstract

The invention relates to the field of digital signal processing, in particular to a miniature digital transceiver module which comprises a signal processing board and a power clock board. The signal processing board and the power supply clock board are stacked and interconnected through a high-speed connector; the signal processing board integrates multiple ADC acquisition channels and DAC output channels, and is internally provided with an RFSOC chip to realize multichannel digital down-conversion, waveform generation and signal processing functions. The power supply clock board integrates a power supply conversion module and a clock frequency synthesizer, provides various power supply varieties for the module, and generates a time sequence, a sampling clock and a reference clock. The stacking design of the two board cards forms a high-integration digital transceiver module, thereby saving a large amount of space and improving the system integration. The scheme is obviously superior to a traditional design method in the aspects of volume, power consumption, performance and the like, and is particularly suitable for equipment sensitive to an outer envelope.

Description

Technical Field

[0001] The present invention relates to the field of digital signal processing, and particularly to a micro digital transceiver module, which can be widely applied to the fields of phased array radar and communication countermeasure. Background Art

[0002] As the core unit of the transceiver system of a digital phased array radar, the digital transceiver module mainly undertakes the functions of direct digital signal generation in the transmitting channel and intermediate frequency signal sampling in the receiving channel. To meet the task requirements, traditional digital transceiver modules usually integrate many functional units such as FPGA, multi-channel transceiver circuits, clock distribution units, power conversion, and external interface connectors on a printed circuit board. This design realizes a high degree of functional integration, but it is difficult to balance in terms of volume, power consumption, cost, number of channels, etc. In particular, in airborne and missile-borne platforms, the design of digital transceiver modules is often restricted by strict outer envelope requirements, which restricts the development of transceiver systems towards high integration, miniaturization, and lightweight. Summary of the Invention

[0003] Through optimized design, the micro digital transceiver module of the present invention realizes digital transceiver functions with small volume, low power consumption, and high integration, meeting application scenarios with strict requirements for space and weight such as airborne and missile-borne platforms. The specific technical solutions adopted are as follows: The present invention provides a micro digital transceiver module, including: a signal processing board and a power supply and clock board; The signal processing board and the power supply and clock board are stacked and interconnected through a high-speed connector; The signal processing board integrates multiple ADC acquisition channels and DAC output channels, and internally incorporates an RFSOC chip to implement multi-channel digital down-conversion, waveform generation, and signal processing functions; The power supply and clock board integrates a power conversion module and a clock frequency synthesizer to provide various power varieties for the module and generate timing, sampling, and reference clocks.

[0004] In an optional implementation manner, the signal processing board and the power supply and clock board are interconnected by using an FMA series high-speed connector, and the transmission rate of the FMA connector is not less than 20 Gbps, and the mating height is not greater than 5 mm.

[0005] In an optional implementation manner, the RFSoC chip supports eight-channel reception and eight-channel transmission, and realizes intermediate frequency signal digitization, multi-rate signal processing, and digital beamforming functions through programmable logic.

[0006] In an optional implementation manner, the power supply and clock board only needs to externally input a single 10 MHz clock signal, and generates the timing clock, sampling clock, and reference clock required by the module through an internal clock frequency synthesizer.

[0007] In an alternative embodiment, the external data interaction interface of the signal processing board uses an MC110 high-speed ultra-thin coaxial cable connector to achieve the upload of echo data and parameter interaction.

[0008] In an alternative embodiment, the power supply and clock board is provided with a debugging interface and an external power input interface. The debugging interface and the external power input interface respectively use anti-misinsertion J63A-2F2 connectors and J63A-2E2 connectors, and their mechanical structures are incompatible with each other.

[0009] In an alternative embodiment, the ADC acquisition channels, DAC output channels, and external clock input interfaces all use SMP connectors and are directly connected to external devices through blind mating.

[0010] In an alternative embodiment, the clock input SMP connector corresponding to the external clock input interface is provided on the power supply and clock board; The signal processing board is provided with an opening at the position corresponding to the clock input SMP connector, so that the clock input SMP connector passes through the signal processing board and is blindly mated and aligned with the external device.

[0011] In an alternative embodiment, the signal processing board and the power supply and clock board are provided with guiding holes to achieve precise positioning between the boards and between the modules and external devices, and eliminate the risk of connection offset.

[0012] In an alternative embodiment, the module supports the cascading expansion of multiple similar modules, and the number of transceiver channels can be flexibly configured by increasing or decreasing the number of modules. Beneficial Effects

[0013] 1. The stacked design of the two boards forms a highly integrated digital transceiver module, saving a large amount of space and improving the system integration.

[0014] 2. The blind mating connection between the two boards and between the digital transceiver module and external devices maximally forms a cable-free system, reducing the volume and weight of the transceiver system and meeting the requirements of various payload platforms for high integration and lightweight of the radar.

[0015] 3. Replacing the traditional FPGA+AD+DA architecture, the signal processing board can achieve eight-channel reception and eight-channel transmission with a single RFSoC chip, having great advantages in terms of volume, power consumption, and design complexity.

[0016] 4. Usually, the digital transceiver module requires at least three clocks. The power supply and clock board of the present invention generates timing, sampling, and reference clocks, and the entire digital transceiver module only requires a 10MHz clock input. This greatly reduces the design requirements for the frequency source and also reduces the complexity of the entire radar's clock system.

[0017] 5. The MC110 high-speed ultra-thin coaxial cable connector is adopted to replace the traditional optical module for echo data uploading and parameter interaction, which can not only save the occupied area and power consumption of the optical module, but also avoid the disadvantages such as the easy damage of the optical cable and the small bending radius of the wiring.

[0018] 6. The digital transceiver module forms a standard module, and the number of transceiver channels can be increased or decreased flexibly, which is beneficial to the two-dimensional expansion of the antenna array surface, applicable to a variety of layout schemes, and avoids inefficient and repeated design. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0020] Figure 1 It is a schematic diagram of the external structure of the WeChat digital transceiver module in the embodiment.

[0021] Figure 2 It is a schematic diagram of the internal structure of the WeChat digital transceiver module in the embodiment.

[0022] Figure 3 It is a schematic diagram of the perforation of the clock input SMP connector in the embodiment.

[0023] In the figure: 1. Power and clock board; 2. Signal processing board; 3. FMA connector; 4. DC / DC power module; 5. LDO power module; 6. Clock frequency synthesizer; 7. Power input interface; 8. Debugging interface; 9. Guide hole; 10. MC110 high-speed ultra-thin coaxial cable connector; 11. Clock input SMP connector; 12. RFSoC chip. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] In order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0025] As the core unit of the digital transceiver system of a digital phased array radar, the digital transceiver module mainly undertakes the functions of direct digital signal generation in the transmit channel and intermediate frequency signal sampling in the receive channel. To meet the task requirements, traditional digital transceiver modules usually integrate many functional units such as FPGA, multi-channel transceiver circuits, clock distribution units, power conversion, and external interface connectors on a printed circuit board. This design achieves a high degree of integration of functions, but it is difficult to balance in terms of volume, power consumption, cost, number of channels, etc. In particular, in airborne and missile-borne platforms, the design of digital transceiver modules is often restricted by strict outer envelope requirements, which restricts the development of transceiver systems towards high integration, miniaturization, and lightweight.

[0026] Therefore, this embodiment provides a micro digital transceiver module. The embodiments of the present invention will be described below in conjunction with Figures 1 to 3 to describe the embodiments of the present invention.

[0027] According to an embodiment of the present invention, there is provided a micro digital transceiver module, as Figures 1 to 3 shown, including a signal processing board 2 and a power supply and clock board 1; the signal processing board 2 and the power supply and clock board 1 are stacked and interconnected through a high-speed connector; the signal processing board 2 integrates multiple ADC acquisition channels and DAC output channels, and internally integrates an RFSOC chip to implement multi-channel digital down-conversion, waveform generation, and signal processing functions; the power supply and clock board 1 integrates a power conversion module and a clock frequency synthesizer 6 to provide multiple power varieties and generate timing, sampling, and reference clocks for the module.

[0028] In this embodiment, the signal processing board 2 and the power supply and clock board 1 adopt a stacked design, and electrical connection and signal transmission are achieved through a high-speed connector. This design not only saves space but also improves the integration and reliability of the system. The signal processing board 2 is responsible for signal acquisition, processing, and output, while the power supply and clock board 1 provides stable power and accurate clock signals for the entire module.

[0029] The signal processing board 2 is the core part of the module, integrating multiple ADC acquisition channels and DAC output channels. These channels are used to receive and transmit intermediate frequency signals and perform digital processing through the RFSoC chip 12. The RFSoC chip 12 is a highly integrated chip with powerful signal processing capabilities, capable of implementing multi-channel digital down-conversion, waveform generation, and signal processing functions. It replaces the traditional FPGA + AD + DA architecture, greatly reducing the number of chips and peripheral circuits, thereby reducing the volume and power consumption of the module.

[0030] The power supply and clock board 1 is responsible for providing multiple power supply types and clock signals for the entire module. Optionally, it integrates multiple DC / DC power supply modules 4 and LDO power supply modules 5, converting the DC 12V input voltage into voltage values such as 0.85V, 1.2V, 0.9V, 3.3V, 1.8V, 1.3V, 2.1V, 3.6V, etc., or converting 1.3V into 0.925V, and converting 3.6V into 3.3V and 2.5V. These voltage types are all the voltage values required for the RFSoC and clock circuits in the digital transceiver module. At the same time, the power supply and clock board 1 also includes a clock frequency synthesizer 6, which can generate the timing clock, sampling clock, and reference clock required by the module according to an externally input 10MHz clock signal. This design greatly simplifies the complexity of the clock system and reduces the design requirements for the frequency source.

[0031] In an alternative embodiment, the signal processing board 2 and the power supply and clock board 1 are interconnected using FMA series high-speed connectors. The transmission rate of the FMA connector 3 is not less than 20Gbps, and the mating height is not greater than 5mm. The FMA series high-speed connectors feature high transmission rates and low mating heights, capable of meeting the requirements for high-speed signal transmission inside the module. At the same time, they are suitable for the stacked design of the module, further reducing the volume of the module.

[0032] In another alternative embodiment, the RFSoC chip 12 supports eight-channel reception and eight-channel transmission, and realizes functions such as digitization of intermediate frequency signals, multi-rate signal processing, and digital beamforming through programmable logic. The multi-channel processing ability of the RFSoC chip 12 enables the module to process signals from multiple channels simultaneously, meeting the requirements for multi-channel signal processing in fields such as phased array radars and communication countermeasures. Through programmable logic, the RFSoC chip 12 can be flexibly configured according to different application scenarios to implement various signal processing algorithms.

[0033] In addition, the power supply and clock board 1 only needs to externally input a single 10MHz clock signal, and generates the timing clock, sampling clock, and reference clock required by the module through the internal clock frequency synthesizer 6. This design greatly simplifies the complexity of the clock system, reduces the design requirements for the frequency source, and also reduces the number of external interfaces of the module, improving the reliability and integration of the system.

[0034] In terms of data interaction, the external data interaction interface of the signal processing board 2 uses an MC110 high-speed ultra-thin coaxial connector 10 to achieve the upload of echo data and parameter interaction. The MC110 connector features high-speed transmission and small size, capable of meeting the requirements for high-speed data transmission between the module and external devices, while saving the area and power consumption of the printed circuit board.

[0035] For the debugging and power input interface 7, the power clock board 1 is provided with a debugging interface 8 and an external power input interface 7. The debugging interface 8 and the external power input interface 7 respectively adopt anti-misinsertion J63A-2F2 connectors and J63A-2E2 connectors, and their mechanical structures are incompatible with each other. This anti-misinsertion design can effectively avoid damage caused by misinsertion during the connection process, improving the reliability and safety of the system.

[0036] In terms of signal connection, the ADC acquisition channel, the DAC output channel, and the external clock input interface all adopt SMP connectors and are directly connected to external devices through a blind mating method. The SMP connector has good electrical and mechanical properties and can achieve stable transmission of high-speed signals. The blind mating method makes the module more convenient and fast during installation and maintenance, without the need for complex alignment operations.

[0037] Specifically, the clock input SMP connector 11 corresponding to the external clock input interface is arranged on the power clock board 1; the signal processing board 2 is provided with an opening at the position corresponding to the clock input SMP connector 11, so that the clock input SMP connector 11 passes through the signal processing board 2 and is blindly mated and aligned with external devices. This design enables the clock signal to be directly transmitted from the power clock board 1 to external devices, reducing the length of the signal transmission path and the risk of signal loss and interference.

[0038] To achieve precise positioning and connection of the module, the signal processing board 2 and the power clock board 1 are provided with guiding holes 9 to achieve precise positioning between the boards and between the module and external devices, and eliminate the risk of connection offset. The design of the guiding holes 9 ensures accurate alignment of the module during stacking and installation, improving the reliability and stability of the connection.

[0039] In addition, the module supports cascading expansion of multiple similar modules, and the number of transceiver channels can be flexibly configured by increasing or decreasing the number of modules. This flexible expansion ability enables the module to adapt to different application scenarios and requirements. By increasing the number of modules, the number of transceiver channels can be easily expanded to meet the requirements of large phased array radar systems for multiple channels.

[0040] In summary, through optimized design, the micro digital transceiver module of the present invention has significant advantages in terms of volume, power consumption, integration, etc., and can meet application scenarios with strict requirements for space and weight such as airborne and missile-borne platforms. Its innovative design and flexible configuration ability make it have broad application prospects in the fields of phased array radar and communication countermeasure.

[0041] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A miniature digital transceiver module, characterized in that: include: A signal processing board (2) and a power clock board (1); The signal processing board (2) and the power clock board (1) are interconnected by stacking high-speed connectors; The signal processing board (2) integrates multiple ADC acquisition channels and DAC output channels, and has a built-in RFSoC chip (12) to realize multi-channel digital down-conversion, waveform generation and signal processing functions; The power clock board (1) integrates a power conversion module and a clock frequency synthesizer (6), provides a variety of power supply types for the module and generates timing, sampling and reference clocks.

2. The micro digital transceiver module according to claim 1, characterized in that: The signal processing board (2) and the power clock board (1) are interconnected using an FMA series high-speed connector, the transmission rate of the FMA connector (3) is not less than 20 Gbps, and the insertion height is not greater than 5 mm.

3. The micro digital transceiver module according to claim 1, characterized in that: The RFSoC chip (12) supports eight-channel reception and eight-channel transmission, and implements intermediate frequency signal digitization, multi-rate signal processing and digital beamforming functions through programmable logic.

4. The micro digital transceiver module according to claim 1, characterized in that: The power clock board (1) only needs to input a single 10 MHz clock signal externally, and generates the timing clock, sampling clock and reference clock required by the module through an internal clock frequency synthesizer (6).

5. The micro digital transceiver module according to claim 1, characterized in that: The signal processing board (2) uses an MC110 high-speed ultra-fine coaxial line connector (10) as an external data interaction interface to achieve echo data upload and parameter interaction.

6. The micro digital transceiver module according to claim 1, characterized in that: The power clock board (1) is provided with a debugging interface (8) and an external power input interface (7), wherein the debugging interface (8) and the external power input interface (7) respectively adopt a J63A-2F2 connector and a J63A-2E2 connector that prevent mis-insertion, and the mechanical structures of the two are incompatible with each other.

7. The micro digital transceiver module according to claim 1, characterized in that: The ADC acquisition channel, DAC output channel and external clock input interface all use SMP connectors and are directly connected to external devices through blind matching.

8. The micro digital transceiver module according to claim 7, characterized in that: The clock input SMP connector (11) corresponding to the external clock input interface is arranged on the power clock board (1); the signal processing board (2) has a hole corresponding to the position of the clock input SMP connector (11), so that the clock input SMP connector (11) passes through the signal processing board (2) and is blindly aligned with the external device.

9. The micro digital transceiver module according to claim 1, characterized in that: The signal processing board (2) and the power clock board (1) are provided with guide holes (9) to achieve accurate positioning between boards and between modules and external devices, and to eliminate the risk of connection deviation.

10. The micro digital transceiver module according to claim 1, characterized in that: The module supports cascading expansion of multiple similar modules, and flexible configuration of the number of transceiver channels can be achieved by increasing or decreasing the number of modules.

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