Multi-output high-performance low dropout linear regulator

Abstract

The invention discloses a multi-output high-performance low-dropout linear voltage regulator, and belongs to the technical field of linear voltage regulators. The low dropout linear regulator comprises a first-stage amplifying circuit, a second-stage amplifying circuit and a power-stage circuit. According to the invention, the stability and transient characteristic of the whole circuit are improved by using the super source follower circuit in the second-stage circuit and cooperating with the current detection function. In addition, a multi-output function is realized at the power stage through a resistor array and an inverter.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a multi-output high-performance low-dropout linear regulator. Background Art

[0002] As an important power management device, the low-dropout linear regulator has a wide range of applications in scenarios with requirements for low power consumption, low noise, and high stability. Its technological development has also been continuously promoting the progress of the power management field.

[0003] With the rapid development of semiconductor technology, chip design is evolving towards high integration and miniaturization. In the design of traditional low-dropout linear regulators, a large capacitor in the microfarad range usually needs to be externally connected to the chip output. This capacitor plays a crucial role in the system: it can not only improve the stability of the system but also effectively improve the transient response performance, especially suppressing the voltage fluctuation of the output when the load current changes suddenly. However, with the continuous improvement of the integration level of devices, especially the increasingly stringent requirements for volume and cost in portable electronic devices and Internet of Things devices, designers hope to reduce or even completely remove this externally connected large capacitor to achieve a more compact circuit layout and lower system cost. However, after removing the output capacitor, the design of the LDO faces severe challenges: First, the stability of the system will decrease significantly because the output capacitor originally played a key role in loop stability, and its removal will lead to insufficient phase margin and easily cause oscillation; Second, the transient characteristics will also deteriorate. Due to the lack of the energy buffering effect of the large capacitor, the voltage fluctuation of the output will be more obvious when the load current changes suddenly, making it difficult to meet the requirements of high-performance applications.

[0004] In view of this, how to solve the problems of poor stability and poor transient characteristics of the capacitorless low-dropout linear regulator is a major technical problem in this field. Summary of the Invention

[0005] The purpose of the present invention is to propose a multi-output high-performance low-dropout linear regulator in view of the problems existing in the prior art.

[0006] The present invention is implemented as follows. A multi-output high-performance low-dropout linear regulator, the circuit includes a first-stage amplifier circuit, a second-stage amplifier circuit, and a power stage circuit.

[0007] The first-stage amplifier circuit is used to provide high gain, so that the circuit can output a stable voltage value through the feedback loop.

[0008] The second-stage amplifier circuit, connected to the first-stage amplifier circuit, is used to improve the stability of the circuit and can detect the power stage current to adjust the output voltage, thereby enhancing the transient response of the circuit.

[0009] The power stage circuit is connected to the second-stage amplifier circuit. Its function is that when the output voltage changes, the feedback circuit detects the output voltage jump and feeds the signal back to the positive port of the first-stage circuit, stabilizing the voltage through the entire loop. In addition, the resistor network is also combined with the inverter circuit. By the control of the selection signal, some resistors are turned on or off, changing the resistor ratio, thereby changing the output voltage and achieving the multi-output function.

[0010] Furthermore, the first-stage amplifier circuit includes:

[0011] A first NMOS transistor, whose gate is connected to the supply voltage Vref1, whose drain is connected to the drains of the fourth PMOS transistor, the gates of the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the fifteenth PMOS transistor, the sixteenth PMOS transistor, the twenty-first PMOS transistor, and the twenty-second PMOS transistor, and whose source is connected to the supply voltage GND;

[0012] A second NMOS transistor, whose gate is connected to the gate and drain of the third NMOS transistor and the drain of the fifth PMOS transistor, whose drain is connected to the source of the third NMOS transistor, and whose source is connected to the supply voltage GND;

[0013] A third NMOS transistor, whose drain is connected to the drain of the fifth PMOS transistor;

[0014] A fourth PMOS transistor, whose gate is connected to the gates of the fifth PMOS transistor and the ninth PMOS transistor, whose drain is connected to the gates of the sixth PMOS transistor and the seventh PMOS transistor, and whose source is connected to the drain of the sixth PMOS transistor;

[0015] A fifth PMOS transistor, whose source is connected to the drain of the seventh PMOS transistor;

[0016] A sixth PMOS transistor, whose source is connected to the supply voltage VDD;

[0017] A seventh PMOS transistor, whose source is connected to the supply voltage VDD;

[0018] An eighth PMOS transistor, whose drain is connected to the source of the ninth PMOS transistor, and whose source is connected to the supply voltage VDD;

[0019] A ninth PMOS transistor, whose drain is connected to the gates of the tenth NMOS transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor;

[0020] A tenth NMOS transistor, whose source is connected to the gates of the eleventh NMOS transistor, the nineteenth NMOS transistor, the twentieth NMOS transistor, the twenty-fifth NMOS transistor, and the twenty-sixth NMOS transistor;

[0021] The eleventh NMOS transistor, whose source is connected to the power supply voltage GND;

[0022] The twelfth PMOS transistor, whose drain is connected to the sources of the thirteenth PMOS transistor and the fourteenth PMOS transistor, and whose source is connected to the power supply voltage VDD;

[0023] The thirteenth PMOS transistor, whose gate is connected to the source of the thirtieth NMOS transistor, the lower end of the fourth resistor, and the upper end of the fifth circuit, and whose drain is connected to the source of the seventeenth NMOS transistor and the drain of the nineteenth NMOS transistor;

[0024] The fourteenth PMOS transistor, whose gate is connected to the power supply voltage Vref2, and whose drain is connected to the source of the eighteenth NMOS transistor, the drain of the twentieth NMOS transistor, and one end of the first capacitor.

[0025] The fifteenth PMOS transistor, whose drain is connected to the drain of the seventeenth NMOS transistor, and whose source is connected to the power supply voltage VDD;

[0026] The sixteenth PMOS transistor, whose drain is connected to the drain of the eighteenth NMOS transistor and the gate of the twenty-fourth PMOS transistor, and whose source is connected to the power supply voltage VDD;

[0027] The seventeenth NMOS transistor, whose source is connected to the drain of the nineteenth NMOS transistor;

[0028] The eighteenth NMOS transistor, whose source is connected to the drain of the twentieth NMOS transistor;

[0029] The nineteenth NMOS transistor, whose source is connected to the power supply voltage GND;

[0030] The twentieth NMOS transistor, whose source is connected to the power supply voltage GND;

[0031] Further, the second-stage amplifying circuit includes:

[0032] The twenty-first PMOS transistor, whose drain is connected to the drain of the twenty-third PMOS transistor, the drain and gate of the twenty-fifth NMOS transistor, and the gate of the twenty-sixth NMOS transistor, and whose source is connected to the power supply voltage VDD;

[0033] The twenty-second PMOS transistor, whose drain is connected to the gate of the twenty-seventh PMOS transistor, the gate of the twenty-third PMOS transistor, and the source of the twenty-fourth PMOS, and whose source is connected to the power supply voltage VDD;

[0034] The twenty-third PMOS transistor, whose source is connected to the power supply voltage VDD;

[0035] The twenty-fourth PMOS transistor, whose drain is connected to the drain of the twenty-sixth NMOS transistor;

[0036] The twenty-fifth NMOS transistor has its source connected to the supply voltage GND;

[0037] The twenty-sixth NMOS transistor has its source connected to the supply voltage GND;

[0038] Furthermore, the power stage circuit includes:

[0039] The twenty-seventh PMOS transistor has its drain connected to the upper end of the first resistor and the other end of the first capacitor, and its source connected to the supply voltage VDD;

[0040] The twenty-eighth NMOS transistor has its gate connected to the supply voltage S0, its drain connected to the lower end of the first resistor and the upper end of the second resistor, and its source connected to the lower end of the second resistor, the upper end of the third resistor, and the drain of the twenty-ninth NMOS;

[0041] The twenty-ninth NMOS transistor has its gate connected to the drain of the thirty-first PMOS transistor and the drain of the thirty-second NMOS transistor, and its source connected to the lower end of the third resistor, the upper end of the fourth resistor, and the drain of the thirtieth NMOS;

[0042] The thirtieth NMOS transistor has its gate connected to the drain of the thirty-third PMOS transistor and the drain of the thirty-fourth NMOS transistor, and its source connected to the lower end of the fourth resistor and the upper end of the fifth resistor;

[0043] The thirty-first PMOS transistor has its gate connected to the supply voltage S1, its drain connected to the drain of the thirty-second NMOS transistor, and its source connected to the supply voltage VDD;

[0044] The thirty-second NMOS transistor has its gate connected to the supply voltage S1 and its source connected to the supply voltage GND;

[0045] The thirty-third PMOS transistor has its gate connected to the supply voltage S2, its drain connected to the drain of the thirty-fourth NMOS transistor, and its source connected to the supply voltage VDD;

[0046] The thirty-fourth NMOS transistor has its gate connected to the supply voltage S2 and its source connected to the supply voltage GND;

[0047] The beneficial effects of the present invention are:

[0048] (1) By introducing Cascode frequency compensation, additional poles or zeros are introduced into the circuit, which can effectively adjust the frequency response of the loop, improve the phase margin, and thus enhance the stability of the system. By reasonably designing the compensation network, the high-frequency response range of the circuit can be extended without affecting the low-frequency gain, thereby improving the dynamic performance of the circuit.

[0049] (2) The second - stage amplifier circuit uses a super source follower, which makes the output resistance of the second - stage amplifier circuit smaller. As a result, it is less affected by the large output capacitance of the power stage, pushing the pole at this point outside the bandwidth and improving the stability of the circuit.

[0050] (3) Add a current - detection function to detect the current of the power - stage PMOS transistor, dynamically adjust the input voltage of the power stage, stabilize the output voltage, and enhance the transient performance of the circuit.

[0051] (4) Combine the resistor - network inverter circuit. Through the control of the selection signal, some resistors are turned on or off, changing the resistance ratio, thus changing the output voltage and realizing the multi - output function.

[0052] (5) The current mirror adopts the Cascode common - source common - gate form, reducing the influence of the channel - length modulation effect, thereby improving the current - matching accuracy and providing a more stable output current. Description of the Drawings

[0053] Figure 1 is the basic circuit diagram of the low - dropout linear regulator provided by the embodiment of the present invention.

[0054] Figure 2 is a circuit diagram of a multi - output high - performance low - dropout linear regulator provided by the embodiment of the present invention. Detailed Embodiments

[0055] Next, the technical solutions of the present invention will be clearly and completely described in conjunction with the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0056] As Figure 1 shown, the embodiment of the present invention provides a multi - output high - performance low - dropout linear regulator. The circuit includes a first - stage amplifier circuit, a second - stage amplifier circuit, and a power - stage circuit;

[0057] The first - stage amplifier circuit is used to provide high gain, enabling the circuit to output a stable voltage value through the feedback loop.

[0058] The second - stage amplifier circuit, connected to the first - stage amplifier circuit, is used to improve the stability of the circuit and can detect the power - stage current to adjust the output voltage, thereby enhancing the transient response of the circuit.

[0059] The power stage circuit is connected to the second-stage amplification circuit. Its function is that when the output voltage changes, the feedback circuit detects the output voltage jump and feeds the signal back to the positive port of the first-stage circuit, stabilizing the voltage through the entire loop. In addition, the resistor network is also combined with the inverter circuit. By the control of the selection signal, some resistors are turned on or off, changing the resistor ratio, thereby changing the output voltage and realizing the multi-output function.

[0060] A PMOS transistor refers to an MOS transistor with an N-type substrate and a P-type channel, which transports current by the flow of holes.

[0061] An NMOS transistor refers to an MOS transistor with a P-type substrate and an N-type channel, which transports current by the flow of electrons.

[0062] As Figure 2 shown, the first-stage amplification circuit includes:

[0063] A first NMOS transistor, whose gate is connected to the supply voltage Vref1, whose drain is connected to the drains of the fourth PMOS transistor, the gates of the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the fifteenth PMOS transistor, the sixteenth PMOS transistor, the twenty-first PMOS transistor and the twenty-second PMOS transistor, and whose source is connected to the supply voltage GND;

[0064] A second NMOS transistor, whose gate is connected to the gate and drain of the third NMOS transistor and the drain of the fifth PMOS transistor, whose drain is connected to the source of the third NMOS transistor, and whose source is connected to the supply voltage GND;

[0065] A third NMOS transistor, whose drain is connected to the drain of the fifth PMOS transistor;

[0066] A fourth PMOS transistor, whose gate is connected to the gates of the fifth PMOS transistor and the ninth PMOS transistor, whose drain is connected to the gates of the sixth PMOS transistor and the seventh PMOS transistor, and whose source is connected to the drain of the sixth PMOS transistor;

[0067] A fifth PMOS transistor, whose source is connected to the drain of the seventh PMOS transistor;

[0068] A sixth PMOS transistor, whose source is connected to the supply voltage VDD;

[0069] A seventh PMOS transistor, whose source is connected to the supply voltage VDD;

[0070] An eighth PMOS transistor, whose drain is connected to the source of the ninth PMOS transistor, and whose source is connected to the supply voltage VDD;

[0071] The ninth PMOS transistor, whose drain is connected to the gates of the tenth NMOS transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor;

[0072] The tenth NMOS transistor, whose source is connected to the gates of the eleventh NMOS transistor, the nineteenth NMOS transistor, the twentieth NMOS transistor, the twenty-fifth NMOS transistor, and the twenty-sixth NMOS transistor;

[0073] The eleventh NMOS transistor, whose source is connected to the power supply voltage GND;

[0074] The twelfth PMOS transistor, whose drain is connected to the sources of the thirteenth PMOS transistor and the fourteenth PMOS transistor, and whose source is connected to the power supply voltage VDD;

[0075] The thirteenth PMOS transistor, whose gate is connected to the source of the thirtieth NMOS transistor, the lower end of the fourth resistor, and the upper end of the fifth circuit, and whose drain is connected to the sources of the seventeenth NMOS transistor and the nineteenth NMOS transistor;

[0076] The fourteenth PMOS transistor, whose gate is connected to the power supply voltage Vref2, and whose drain is connected to the source of the eighteenth NMOS transistor, the drain of the twentieth NMOS transistor, and one end of the first capacitor.

[0077] The fifteenth PMOS transistor, whose drain is connected to the drain of the seventeenth NMOS transistor, and whose source is connected to the power supply voltage VDD;

[0078] The sixteenth PMOS transistor, whose drain is connected to the drain of the eighteenth NMOS transistor and the gate of the twenty-fourth PMOS transistor, and whose source is connected to the power supply voltage VDD;

[0079] The seventeenth NMOS transistor, whose source is connected to the drain of the nineteenth NMOS transistor;

[0080] The eighteenth NMOS transistor, whose source is connected to the drain of the twentieth NMOS transistor;

[0081] The nineteenth NMOS transistor, whose source is connected to the power supply voltage GND;

[0082] The twentieth NMOS transistor, whose source is connected to the power supply voltage GND;

[0083] As Figure 2 shown, the second-stage amplifier circuit includes:

[0084] The twenty-first PMOS transistor, whose drain is connected to the drains of the twenty-third PMOS transistor, the twenty-fifth NMOS transistor, the gate of the twenty-fifth NMOS transistor, and the gate of the twenty-sixth NMOS transistor, and whose source is connected to the power supply voltage VDD;

[0085] The twenty-second PMOS transistor, whose drain is connected to the gate of the twenty-seventh PMOS transistor, the gate of the twenty-third PMOS transistor and the source of the twenty-fourth PMOS transistor, and whose source is connected to the supply voltage VDD;

[0086] The twenty-third PMOS transistor, whose source is connected to the supply voltage VDD;

[0087] The twenty-fourth PMOS transistor, whose drain is connected to the drain of the twenty-sixth NMOS transistor;

[0088] The twenty-fifth NMOS transistor, whose source is connected to the supply voltage GND;

[0089] The twenty-sixth NMOS transistor, whose source is connected to the supply voltage GND;

[0090] As Figure 2 shown, the power stage circuit includes:

[0091] The twenty-seventh PMOS transistor, whose drain is connected to the upper end of the first resistor and the other end of the first capacitor, and whose source is connected to the supply voltage VDD;

[0092] The twenty-eighth NMOS transistor, whose gate is connected to the supply voltage S0, whose drain is connected to the lower end of the first resistor and the upper end of the second resistor, and whose source is connected to the lower end of the second resistor, the upper end of the third resistor, and the drain of the twenty-ninth NMOS transistor;

[0093] The twenty-ninth NMOS transistor, whose gate is connected to the drain of the thirty-first PMOS transistor and the drain of the thirty-second NMOS transistor, and whose source is connected to the lower end of the third resistor, the upper end of the fourth resistor, and the drain of the thirtieth NMOS transistor;

[0094] The thirtieth NMOS transistor, whose gate is connected to the drain of the thirty-third PMOS transistor and the drain of the thirty-fourth NMOS transistor, and whose source is connected to the lower end of the fourth resistor and the upper end of the fifth resistor;

[0095] The thirty-first PMOS transistor, whose gate is connected to the supply voltage S1, whose drain is connected to the drain of the thirty-second NMOS transistor, and whose source is connected to the supply voltage VDD;

[0096] The thirty-second NMOS transistor, whose gate is connected to the supply voltage S1 and whose source is connected to the supply voltage GND;

[0097] The thirty-third PMOS transistor, whose gate is connected to the supply voltage S2, whose drain is connected to the drain of the thirty-fourth NMOS transistor, and whose source is connected to the supply voltage VDD;

[0098] The thirty-fourth NMOS transistor, whose gate is connected to the supply voltage S2 and whose source is connected to the supply voltage GND;

[0099] The above are only the preferred embodiments of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be changed within the scope of the concept described herein through the above teachings or the technology or knowledge in the relevant field. As long as the changes and variations made by those skilled in the art do not depart from the spirit and scope of the present invention, they should all be within the protection scope of the appended claims of the present invention.

Claims

1. A multi-output high-performance low-dropout linear regulator, comprising a first-stage amplifier circuit, characterized in that: The first stage amplifier circuit is connected in sequence to a second stage amplifier circuit and a power stage circuit; The first-stage amplifier circuit is used to provide high gain, so that the circuit can output a stable voltage value through a feedback loop. The second-stage amplifier circuit is connected to the first-stage amplifier circuit to improve the stability of the circuit and can detect the power stage current to adjust the output voltage, thereby enhancing the transient response of the circuit. The power stage circuit is connected to the second stage amplifier circuit. Its function is that when the output voltage changes, the feedback circuit detects the output voltage jump and feeds the signal back to the positive port of the first stage circuit, so that the voltage is stabilized through the entire loop. In addition, the resistor network is also combined with the inverter circuit. Through the control of the selection signal, part of the resistor is turned on or off, so that the resistor ratio changes, thereby changing the output voltage and realizing the multi-output function.

2. The multi-output high-performance low-dropout linear regulator according to claim 1, characterized in that: The first-stage amplifier circuit comprises: a first NMOS transistor, whose gate is connected to the power supply voltage Vref1, whose drain is connected to the drain of the fourth PMOS transistor, the gate of the sixth PMOS transistor, the gate of the seventh PMOS transistor, the gate of the eighth PMOS transistor, the gate of the fifteenth PMOS transistor, the gate of the sixteenth PMOS transistor, the gate of the twenty-first PMOS transistor and the gate of the twenty-second PMOS transistor, and whose source is connected to the power supply voltage GND; A second NMOS tube, whose gate is connected to the gate and drain of the third NMOS tube and the drain of the fifth PMOS tube, whose drain is connected to the source of the third NMOS tube, and whose source is connected to the power supply voltage GND; A third NMOS tube, a drain of which is connected to the drain of the fifth PMOS tube; a fourth PMOS tube, whose gate is connected to the gate of the fifth PMOS tube and the gate of the ninth PMOS tube, whose drain is connected to the gate of the sixth PMOS tube and the gate of the seventh PMOS tube, and whose source is connected to the drain of the sixth PMOS tube; a fifth PMOS tube, whose source is connected to the drain of the seventh PMOS tube; A sixth PMOS tube, a source of which is connected to a power supply voltage VDD; A seventh PMOS tube, a source of which is connected to the power supply voltage VDD; an eighth PMOS tube, a drain of which is connected to the source of the ninth PMOS tube, and a source of which is connected to the power supply voltage VDD; a ninth PMOS tube, a drain of which is connected to the gate of the tenth NMOS tube, the gate of the seventeenth NMOS tube, and the gate of the eighteenth NMOS tube; a tenth NMOS tube, whose source is connected to the gate of the eleventh NMOS tube, the gate of the nineteenth NMOS tube, the gate of the twentieth NMOS tube, the gate of the twenty-fifth NMOS tube, and the gate of the twenty-sixth NMOS tube; An eleventh NMOS tube, a source of which is connected to a power supply voltage GND; A twelfth PMOS tube, a drain of which is connected to the source of the thirteenth PMOS tube and the source of the fourteenth PMOS tube, and a source of which is connected to the power supply voltage VDD; a thirteenth PMOS tube, whose gate is connected to the source of the thirtieth NMOS tube, the lower end of the fourth resistor and the upper end of the fifth circuit, and whose drain is connected to the source of the seventeenth NMOS tube and the drain of the nineteenth NMOS tube; The gate of the fourteenth PMOS tube is connected to the power supply voltage Vref2, and the drain of the fourteenth PMOS tube is connected to the source of the eighteenth NMOS tube, the drain of the twentieth NMOS tube, and one end of the first capacitor. A fifteenth PMOS tube, a drain of which is connected to the drain of the seventeenth NMOS tube, and a source of which is connected to the power supply voltage VDD; A sixteenth PMOS tube, a drain of which is connected to the drain of the eighteenth NMOS tube and the gate of the twenty-fourth PMOS tube, and a source of which is connected to the power supply voltage VDD; A seventeenth NMOS tube, a source of which is connected to a drain of a nineteenth NMOS tube; An eighteenth NMOS tube, whose source is connected to the drain of the twentieth NMOS tube; A nineteenth NMOS tube, a source of which is connected to a power supply voltage GND; The source of the twentieth NMOS tube is connected to the power supply voltage GND.

3. The multi-output high-performance low-dropout linear regulator according to claim 1, characterized in that: The second stage amplifier circuit comprises: A twenty-first PMOS tube, a drain of which is connected to the drain of the twenty-third PMOS tube, the drain and the gate of the twenty-fifth NMOS tube, and the gate of the twenty-sixth NMOS tube, and a source of which is connected to the power supply voltage VDD; A twenty-second PMOS tube, a drain of which is connected to the gate of the twenty-seventh PMOS tube, the gate of the twenty-third PMOS tube and the source of the twenty-fourth PMOS tube, and a source of which is connected to the power supply voltage VDD; A twenty-third PMOS tube, a source of which is connected to the power supply voltage VDD; A twenty-fourth PMOS tube, a drain of which is connected to the drain of the twenty-sixth NMOS tube; A twenty-fifth NMOS tube, whose source is connected to the power supply voltage GND; The twenty-sixth NMOS tube has a source connected to the power supply voltage GND.

4. The multi-output high-performance low-dropout linear regulator according to claim 1, characterized in that: The power stage circuit comprises: a twenty-seventh PMOS tube, a drain of which is connected to the upper end of the first resistor and the other end of the first capacitor, and a source of which is connected to the power supply voltage VDD; A twenty-eighth NMOS transistor, whose gate is connected to the power supply voltage S0, whose drain is connected to the lower end of the first resistor and the upper end of the second resistor, and whose source is connected to the lower end of the second resistor, the upper end of the third resistor, and the drain of the twenty-ninth NMOS; a twenty-ninth NMOS tube, whose gate is connected to the drain of the thirty-first PMOS tube and the drain of the thirty-second NMOS tube, and whose source is connected to the lower end of the third resistor, the upper end of the fourth resistor, and the drain of the thirtieth NMOS tube; a 30th NMOS transistor, whose gate is connected to the drain of the 33rd PMOS transistor and the drain of the 34th NMOS transistor, and whose source is connected to the lower end of the fourth resistor and the upper end of the fifth resistor; A thirty-first PMOS transistor, whose gate is connected to the power supply voltage S1, whose drain is connected to the drain of the thirty-second NMOS transistor, and whose source is connected to the power supply voltage VDD; A thirty-second NMOS transistor, a gate of which is connected to the power supply voltage S1, and a source of which is connected to the power supply voltage GND; A thirty-third PMOS transistor, whose gate is connected to the power supply voltage S2, whose drain is connected to the drain of the thirty-fourth NMOS transistor, and whose source is connected to the power supply voltage VDD; The thirty-fourth NMOS tube has a gate connected to the power supply voltage S2 and a source connected to the power supply voltage GND.

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