Rapid network camera FPGA program upgrading method

Abstract

The invention relates to a quick network camera FPGA (Field Programmable Gate Array) program upgrading method, which belongs to the technical field of industrial cameras and comprises the following steps that: an upper computer sends an upgrading starting and erasing instruction to a camera; the upper computer reads the file content and packages the file content; the upper computer sends file content to the camera DDR3 storage module; the FPGA confirms that the command is correct and feeds back to the upper computer; the upper computer reads back the sending content to the camera; and the FPGA reads the content of the DDR3 storage module and then writes the content into the FLASH. According to the method, the working efficiency of FPGA software upgrading is improved, and the risks of power failure, static electricity, mistaken touch, computer system crash and the like in the upgrading process are reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of industrial cameras and relates to a method for quickly upgrading the FPGA program of a network camera. Background Art

[0002] In the context of the rapid development of the industrial camera industry, various problems have been encountered in the research and development and production processes of industrial cameras. How to upgrade the FPGA program of the camera without using the Jtag port is one of these problems. Solving this problem enables the FPGA program to be upgraded while keeping the camera housing intact and using the built-in interfaces.

[0003] Existing program upgrade technologies include FPGA upgrade based on serial communication, upgrade in the FPGA+DSP mode, ARM serial port upgrade, etc. These methods all write program files to the internal circuit through the serial port, and the steps mostly include FLASH erasure, reception of multi-packet program files, FLASH reading, etc.

[0004] Existing technologies such as a patent for an FPGA+DSP online upgrade method based on serial communication, a method for remotely programming an FPGA, and a communication and program serial port upgrade method for a serial port time-division multiplexing type infrared thermal imager system all have the disadvantage of slow programming speed. Usually, the size of the FPGA files (in formats such as bin, jic, sfc, etc.) to be programmed ranges from several M to several hundred M. For a large file of 100M, with a normal serial port baud rate of 115200bps, the transmission duration is Time = 100*1024*1024 / 115200*0.8 = 728 seconds. Adding steps such as FLASH erasure and verification, the upgrade time will be further extended. A long upgrade time not only has low efficiency but also increases the probability of external influences such as power failure, static electricity, and accidental touch, increasing the working risk and resulting in problems such as ultimate upgrade failure and the camera being unable to start normally. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a method for quickly upgrading the FPGA program of a network camera to address the disadvantage of slow upgrade speed. The method uses gigabit Ethernet+DDR3 cache for upgrade to reduce the time consumed in the entire upgrade process.

[0006] To achieve the above objective, the present invention provides the following technical solution:

[0007] A method for quickly upgrading the FPGA program of a network camera includes the following steps:

[0008] S1: The host computer connects to the FPGA module of the camera through gigabit Ethernet and sends an upgrade start instruction and a FLASH erasure instruction;

[0009] S2: The host computer selects file reading, automatically identifies the file type, reads and divides the content into packets according to different types, with a total of N packets; according to the communication protocol, the host computer adds a frame header and a frame tail checksum to the file content of each packet and continuously sends N instructions to the FPGA module of the camera;

[0010] S3: The FPGA module caches the original data of the instructions in the DDR3 storage module until all instructions are received;

[0011] S4: The FPGA module reads the instruction content in the DDR3 storage module, judges whether the formats of the N instructions and the frame tail checksum are correct. If correct, it returns a correct instruction to the host computer and proceeds to the next step; if incorrect, it returns an incorrect instruction to the host computer, and the host computer resends the correct instruction;

[0012] S5: The host computer sends a read-back command, and the FPGA module sends the content in the DDR3 storage module to the host computer in N packets; the host computer compares the received content with the content sent in step S2. If they are consistent, it proceeds to the next step; otherwise, it repeats steps S2 - S5;

[0013] S6: The FPGA module receives the correct comparison instruction sent by the host computer, removes the frame header and frame tail checksum of the original upgrade data, writes the program file into the FLASH, and sends a write completion instruction to the host computer;

[0014] S7: The host computer receives the write completion instruction, and this upgrade ends.

[0015] Further, if the formats of the N instructions and the frame tail checksum are incorrect in step S4, an incorrect instruction is returned to the host computer. After receiving the instruction, the host computer sends an incorrect instruction query instruction to the FPGA module, and the FPGA module returns multiple instructions to the host computer. Each instruction contains the following content: a total of M instructions are sent this time, the current is the Qth instruction, and the serial number of the incorrect instruction packet; after receiving it, the host computer sends the correct instruction corresponding to the serial number of the incorrect packet to the FPGA module again, and the FPGA module re - judges whether the formats of the N instructions and the frame tail checksum are correct until they are correct.

[0016] Further, the camera consists of three parts: an image sensor circuit board, an FPGA circuit board, and a power supply circuit board;

[0017] The image sensor circuit board is used to generate image data;

[0018] The FPGA circuit board includes an FPGA module, and a DDR3 storage module, a FLASH module, an image sensor interface module, and a gigabit Ethernet interface module respectively connected to the FPGA module;

[0019] The FPGA module is used to control and manage each module, and is connected to the host computer through a gigabit Ethernet interface module to receive instructions sent by the host computer;

[0020] The DDR3 storage module is used to store the upgrade file data sent by the host computer;

[0021] The FLASH module is used to run the upgrade file to realize the upgrade of the camera program;

[0022] The image sensor interface module is used to connect to the image sensor circuit board;

[0023] The power supply circuit board is used to supply power to each module.

[0024] Furthermore, the communication protocol is the UDP protocol.

[0025] The beneficial effects of the present invention are as follows: For large-scale files of several hundred M, with the sending speed of gigabit Ethernet and the reading and writing speed of the DDR3 storage module, the sending duration can be controlled within 1-2 seconds. And in this method, the program file of the host computer is read and written only once, and the program file of the DDR3 storage module is read and written only once. Adding the time of the remaining instructions, the total time consumed for the upgrade can be controlled within 10 seconds, greatly improving the working efficiency of the FPGA software upgrade, which is obvious in the large-scale production of cameras. At the same time, it also reduces the risks such as power failure, static electricity, accidental touch, and computer system crash during the upgrade process.

[0026] Other advantages, objectives, and features of the present invention will be described to some extent in the subsequent description, and to some extent, will be obvious to those skilled in the art based on the study of the following text, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be described in detail preferably with reference to the accompanying drawings, where:

[0028] Figure 1 is the Ethernet frame encapsulation format;

[0029] Figure 2 is the datagram encapsulation format;

[0030] Figure 3 is the camera circuit system diagram;

[0031] Figure 4 is the flowchart of the fast network camera FPGA program upgrade method. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0033] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0034] In the following description, a large number of details are explored to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0035] This method adopts two methods to solve the problem of slow upgrade speed: 1. Use gigabit Ethernet for camera and host computer software development, which can accelerate the file writing speed; 2. In the camera circuit design, a DDR3 storage module is adopted. First, all files are written into the DDR3 storage module, and then read and processed by the FPGA. The steps are as follows: a. The host computer reads the file content; b. The host computer sends an upgrade and erase instruction to the camera; c. The host computer sends the file content to the camera DDR3 storage module; d. The FPGA confirms that the command is correct and sends feedback to the host computer; e. The host computer reads back and sends the content to the camera; f. The FPGA reads the content of the DDR3 storage module and writes it into the FLASH. The details are as follows.

[0036] Gigabit Ethernet is defined by the IEEE 802.3-2005 standard, which allows half-duplex connections through hubs. The Ethernet frame encapsulation format is as Figure 1 shown. The present invention takes the UDP protocol as an example. UDP is a simple datagram-oriented transport layer protocol: each output operation of a process exactly generates one UDP datagram and assembles it into an IP datagram to be sent. This is different from stream-oriented character protocols such as TCP, where the entire data generated by an application may have no connection with the individual IP datagrams actually sent. The datagram encapsulation format and parsing are asFigure 2 as shown in Table 1.

[0037] Table 1

[0038]

[0039] The UDP camera circuit system consists of three parts: an image sensor circuit board, an FPGA circuit board, and a power supply board. Image data is generated by the image sensor and transmitted to the FPGA circuit board. After being processed, it communicates with the computer host through a gigabit Ethernet interface for sending and receiving image data and control data. The power supply board is responsible for powering the entire system. For the FPGA program upgrade function described in this method, the host communicates with the FPGA through the gigabit Ethernet for sending and receiving control commands and upgrade data. The FPGA first temporarily stores the received original upgrade data in the DDR3 storage module, and then reads it out, processes it, and writes it into the FLASH after confirmation.

[0040] As Figure 3 shown, the camera consists of three parts: an image sensor circuit board, an FPGA circuit board, and a power supply circuit board; the image sensor circuit board is used to generate image data; the FPGA circuit board includes an FPGA module, as well as a DDR3 storage module, a FLASH module, an image sensor interface module, and a gigabit Ethernet interface module respectively connected to the FPGA module; the FPGA module is used to control and manage each module, and is connected to the host through the gigabit Ethernet interface module to receive instructions sent by the host; the DDR3 storage module is used to store the upgrade file data sent by the host; the FLASH module is used to run the upgrade file to implement camera program upgrade; the image sensor interface module is used to connect to the image sensor circuit board; the power supply circuit board is used to supply power to each module.

[0041] The overall process proposed by this method is as Figure 4 shown, and the steps are as follows:

[0042] 1. The host connects to the camera and sends an upgrade start instruction and an instruction to erase the FLASH.

[0043] 2. The host selects file reading, automatically identifies the file type (bin, jic, sfc, etc.), reads and divides the content according to different types, and divides it into N packets in total.

[0044] 3. According to the communication protocol, add a frame header and a frame tail checksum to the file content of each packet, and continuously send N instructions to the FPGA. The FPGA does not perform any processing and caches the original data of the instructions in the DDR3 storage module.

[0045] 4. The FPGA reads the instruction content of the DDR3 storage module, verifies whether the formats of N instructions and the frame tail checksum are correct, and returns the instructions to the host computer. If it is correct, go to step 7; if it is incorrect, go to step 5;

[0046] 5. The host computer sends an error instruction query instruction to the camera, and the camera returns multiple instructions to the host computer. Each instruction contains the following content: a total of M instructions are sent this time, the current is the Qth instruction, and the sequence number of the error instruction packet in step 3. After receiving, the host computer sends the correct instruction corresponding to the error packet number to the camera again;

[0047] 6. Repeat step 4;

[0048] 7. The host computer sends a read-back command, and the FPGA sends the content in the DDR3 storage module to the host computer in N packets. The host computer compares the received content with the sent content in step 3. If the comparison is consistent, go to step 8; if the comparison is incorrect, repeat steps 3 to 7;

[0049] 8. The FPGA receives the comparison correct instruction sent by the host computer, removes the frame header and frame tail checksum of the original upgrade data, writes the program file into the FLASH, and sends a write completion instruction to the host computer;

[0050] 9. The host computer receives the write completion instruction, and this upgrade ends.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the purpose and scope of the present technical solution, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A fast network camera FPGA program upgrade method, characterized by: The following steps are involved: S1: The host computer connects to the camera's FPGA module via Gigabit Ethernet and sends the start upgrade command and the erase FLASH command; S2: The host computer selects the file to read, automatically identifies the file type, completes content reading and divides it into N packets according to different types; the host computer adds a header and a footer checksum to the file content of each packet according to the communication protocol, and continuously sends N instructions to the camera's FPGA module; S3: The FPGA module caches the original data of the instruction into the DDR3 storage module until all instructions are received; S4: The FPGA module reads the instruction content of the DDR3 storage module, determines whether the format and frame end checksum of the N instructions are correct, and if correct, returns the correct instruction to the host computer and proceeds to the next step; if wrong, returns the wrong instruction to the host computer, and the host computer resends the correct instruction; S5: The host computer sends a read-back command, and the FPGA module sends the content in the DDR3 storage module to the host computer in N packets; the host computer compares the received content with the content sent in step S2, and if the comparison is consistent, it proceeds to the next step, otherwise repeats steps S2-S5; S6: The FPGA module receives the correct comparison instruction sent by the host computer, removes the frame header and frame footer checksum of the original upgrade data, writes the program file into the FLASH, and sends a write completion instruction to the host computer; S7: The host computer receives the write completion instruction and the upgrade is completed.

2. The fast network camera FPGA program upgrade method according to claim 1, characterized in that: In step S4, if there are errors in the format and frame tail checksum of N instructions, the error instruction is returned to the host computer. After receiving the instruction, the host computer sends an error instruction query instruction to the FPGA module. The FPGA module returns multiple instructions to the host computer, and each instruction contains the following content: a total of M instructions are sent this time, the current is the Qth instruction, and the error instruction package number; after receiving the instruction, the host computer sends the correct instruction corresponding to the error packet number to the FPGA module again, and the FPGA module re-judges whether the format and frame tail checksum of the N instructions are correct until they are correct.

3. The fast network camera FPGA program upgrade method according to claim 1, characterized in that: The camera consists of three parts: an image sensor circuit board, an FPGA circuit board and a power supply circuit board; The image sensor circuit board is used to generate image data; The FPGA circuit board includes an FPGA module, and a DDR3 storage module, a FLASH module, an image sensor interface module, and a Gigabit Ethernet interface module respectively connected to the FPGA module; The FPGA module is used to control and manage each module, and is connected to the host computer through the Gigabit Ethernet interface module to receive instructions sent by the host computer; The DDR3 storage module is used to store the upgrade file data sent by the host computer; The FLASH module is used to run the upgrade file to implement the camera program upgrade; The image sensor interface module is used to connect to the image sensor circuit board; The power circuit board is used to supply power to each module.

4. The fast network camera FPGA program upgrade method according to claim 1, characterized in that: The communication protocol is UDP protocol.

Images