Cache capacity solver for non-volatile compute-in-memory architecture

Abstract

The application discloses a cache capacity solver for a nonvolatile storage and computing integrated architecture, comprising a configuration port, a CNN model loading interface, an operator analysis and fusion module, a weight splitting and mapping module, a communication network mapping module, a Tile model interface and a cache capacity iteration module; the application simulates a runtime peak demand according to a cache type divided according to a demand source, facilitates a user to customize an optimization scheme according to the cache type, abstracts a specific Tile implementation and only provides a Tile design principle and a template, and allows the user to flexibly adjust according to a self architecture without changing the entire accelerator.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of cache capacity solvers, and in particular to a cache capacity solver for a non-volatile memory-computing integrated architecture. BACKGROUND

[0002] Chips using non-volatile memory-computing integrated technology are currently commonly used for neural network inference. In the chip architecture design process, the setting of the cache specification often depends on engineering practical experience, or a functional model is built at the beginning of chip architecture formulation to simulate and determine. There is generally a lack of scientific methods to classify on-chip caches according to their different demand sources, and tools to iteratively calculate the size of each type of cache under specified workloads, thereby causing the inability to finely control the reduction of on-chip cache redundancy during chip design. At the same time, since the functional modeling needs to simulate the internal functions of the chip in detail, a chip-modeling scheme is often used, which lacks adaptability to various computing units, and the detailed simulation takes a long time and provides a lot of feedback information, making it difficult to efficiently analyze cache-related problems. SUMMARY

[0003] The application is proposed to solve the above problems, and provides a cache capacity solver for a non-volatile memory-computing integrated architecture.

[0004] The technical scheme of the application is as follows: a cache capacity solver for a non-volatile memory-computing integrated architecture comprises a configuration port, a CNN model loading interface, an operator analysis and fusion module, a weight splitting and mapping module, a communication network mapping module, a Tile model interface and a cache capacity iteration module.

[0005] The configuration port is used to control the configuration process.

[0006] The CNN model loading interface is used to generate the dependency relationship between operators after the configuration process is completed.

[0007] The operator analysis and fusion module is used to analyze the dependency relationship between operators and generate fused operators.

[0008] The weight splitting and mapping module is used to generate a Tile intercommunication graph according to the fused operators.

[0009] The communication network mapping module is used to generate a task block communication graph according to the Tile intercommunication graph.

[0010] The Tile model interface is used to generate an intercache communication graph according to the task block communication graph.

[0011] The cache capacity iteration module is used to generate an on-chip data flow graph according to the intercache communication graph and perform iterative solving.

[0012] Further, the configuration port controls the configuration process, which comprises the following steps:

[0013] A1, generating a key-value pair according to a hardware parameter configured by a user;

[0014] A2, performing legal detection on a configuration item and a specific value of the key-value pair, and entering A3 after the legal detection;

[0015] A3, determining whether all necessary parameters for running the cache capacity solver are configured as valid values by using a configuration port, and if yes, completing the configuration process, otherwise interrupting the configuration process.

[0016] Further, in A1, the expression of the key-value pair is:

[0017] ;

[0018] In the formula, represents a first configuration item of hardware, represents a specific value of the first configuration item of hardware, represents a second configuration item of hardware, represents a specific value of the second configuration item of hardware, represents an nth configuration item of hardware, represents a specific value of the nth configuration item of hardware.

[0019] Further, the CNN model loading interface determines a directed graph according to a model format of the to-be-tested model, and generates a dependency relationship between operators, wherein a node set of the directed graph represents an operator set of the to-be-tested model, and an edge set of the directed graph represents a dependency relationship between operators of the to-be-tested model.

[0020] The expression of a parameter of an operator corresponding to each node in the node set of the directed graph is:

[0021] ;

[0022] In the formula, represents an input feature map size, represents an output feature map size, represents a calculation mode, represents a window size, represents a step length.

[0023] Further, the operator analysis and fusion module generates a fusion operator including the following steps:

[0024] B1, constructing an operator optimization template library;

[0025] B2, constructing a node and a corresponding successor node ​​The fusion node is constructed , it is judged whether the calculation mode of the fusion node belongs to the operator optimization template library, if yes, the node is replaced by the fusion node , and an edge between the node and the subsequent node is generated ;

[0026] B3, repeat B2 until all nodes in the directed graph are replaced, and a fusion operator is generated.

[0027] Further, in B1, the expression of the operator optimization template library is as follows:

[0028] ;

[0029] In the formula, represents that the convolution and activation operations are completed in a Tile in the order of convolution first and then activation, represents that the convolution, activation, and pooling operations are completed in a Tile in the order of convolution first, then activation, and then pooling, represents that the convolution, activation, and residual sum operations are completed in a Tile in this order.

[0030] Further, the weight splitting mapping module generates the inter-Tile communication graph including the following steps:

[0031] C1, based on the fusion operator, the calculation task of the model to be tested is split into a plurality of task blocks;

[0032] C2, based on the plurality of task blocks, the inter-layer communication edge and the intra-layer communication edge are constructed, and the inter-Tile communication graph is generated.

[0033] Further, the communication network mapping module calculates the Hamilton distance between the mapped physical Tiles according to the Tile communication in the inter-Tile communication graph, and determines the communication delay between the Tiles according to the link delay, loads all the communication delays to the edges of the inter-Tile communication graph, and generates a task block communication graph.

[0034] Further, the Tile model interface splits the internal block cache into a plurality of cache blocks according to the task block communication graph, wherein the types of the cache blocks include data dependent cache, data replication cache, data synchronization cache, and data redundancy cache.

[0035] Further, the cache capacity iteration module generates an on-chip data flow graph according to the inter-cache communication graph, sets a starting cache node, produces a data as an iteration step size, traverses all nodes in the on-chip data flow graph, and completes the iteration solution.

[0036] The beneficial effects of the present application are:

[0037] (1) The peak demand simulation of the cache type according to the demand source division of the present application is convenient for users to customize optimization scheme according to the cache type;

[0038] (2) The present application abstracts the specific Tile implementation and only provides the Tile design principle and template, allowing users to flexibly adjust according to their own architecture without changing the entire accelerator;

[0039] (3) The present application relies on the producer-consumer model, only simulates data flow and transparently accelerates the solution process of data calculation and other processes. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 It is a structural schematic diagram of a cache capacity solver for a non-volatile storage and computing integrated architecture;

[0041] Figure 2 It is a schematic diagram of a router interconnecting multiple Tiles;

[0042] Figure 3 It is a Tile design specification diagram;

[0043] Figure 4 It is a Tile data flow model diagram;

[0044] Figure 5 It is an abstract Tile data flow model diagram constructed by a user according to a template;

[0045] Figure 6 It is a Tile model input interface that parses user Tile modeling and splits the cache graph according to functions;

[0046] Figure 7 It is a schematic diagram of operator graph parsing and weight splitting mapping;

[0047] Figure 8 It is a simulation iteration process. DETAILED DESCRIPTION

[0048] The embodiments of the present application will be further described below in conjunction with the accompanying drawings.

[0049] As shown in Figure 1 , the present application provides a cache capacity solver for a non-volatile storage and computing integrated architecture, comprising a configuration port, a CNN model loading interface, an operator analysis and fusion module, a weight splitting and mapping module, a communication network mapping module, a Tile model interface and a cache capacity iteration module;

[0050] The configuration port is used to control the configuration process;

[0051] The CNN model loading interface is used to generate the dependency relationship between operators after the configuration process is completed.

[0052] The operator analysis and fusion module is used to analyze the dependency relationship between operators and generate a fusion operator.

[0053] The weight splitting and mapping module is used to generate a Tile inter-communication graph according to the fusion operator.

[0054] The communication network mapping module is used to generate a task block communication graph according to the Tile inter-communication graph.

[0055] The Tile model interface is used to generate an inter-cache communication graph according to the task block communication graph.

[0056] The cache capacity iteration module is used to generate an on-chip data flow graph according to the inter-cache communication graph and perform iterative solving.

[0057] In the embodiment of the application, the configuration port control configuration process comprises the following steps:

[0058] A1. According to the hardware parameters configured by the user, a key-value pair is generated.

[0059] A2. The configuration items and specific values of the key-value pair are detected for legality, and after the legality detection, A3 is entered.

[0060] A3. The configuration port is used to determine whether all the necessary parameters for running the cache capacity solver are configured as valid values, and if so, the configuration process is completed, otherwise the configuration process is interrupted.

[0061] The configuration port allows the user to configure the Tile memory algorithm array specification, the hardware communication topology type, the mapping scheme and the communication bandwidth and other hardware-related characteristics, so as to further refine the hardware adaptation of the solver.

[0062] In A1 in the embodiment of the application, the expression of the key-value pair is as follows:

[0063]

[0064] In the formula, represents a first configuration item of hardware, represents a specific value of the first configuration item of hardware, represents a second configuration item of hardware, represents a specific value of the second configuration item of hardware, represents an nth configuration item of hardware, represents a specific value of the nth configuration item of hardware.

[0065] ​​​This indicates hardware configuration items, such as Tile memory array specifications and hardware communication topology type. This indicates the specific value or option for the corresponding item, such as an 8×8 Tile array, Mesh topology, 128×128 xbar size, and information such as the number of Xbars contained within a Tile.

[0066] Key-value pairs of configuration information can be saved by the user as an .xml file for easy loading. The configuration port will be determined based on the key-value pairs. Check if the emulator has a configuration parameter with that name, and check its corresponding... Check if the value is valid and supported. If the configuration key-value pair is not supported, the interface will automatically skip the key-value pair entered by the user. If the value is invalid, the configuration process will be interrupted and an error message will be displayed to the user. We need to retrieve values ​​from [A, B, C…], but the current result is abnormal. An exception will occur if the value is "...". After all key-value pairs in the configuration information have been loaded, the configuration information interface will check whether all necessary parameters for running the solver have been configured with valid values. If all are configured, the subsequent process will start; otherwise, the subsequent workflow will be interrupted and an exception will be thrown to the user. An "Not configured" exception occurred.

[0067] In this embodiment of the invention, the CNN model loading interface determines a directed graph based on the model format of the model to be tested and generates the dependencies between operators. The set of nodes in the directed graph represents the set of operators of the model to be tested, and the set of edges in the directed graph represents the dependencies between operators of the model to be tested.

[0068] The parameters of the operator corresponding to each node in the node set of a directed graph. The expression is:

[0069] ;

[0070] In the formula, Indicates the size of the input feature map. Indicates the size of the output feature map. Indicates the calculation mode. Indicates window size. Indicates the step size.

[0071] The CNN model loading interface provides the function of batch importing the to-be-tested model from mainstream deep learning frameworks, and is responsible for analyzing the types and topologies of operators thereof; specifically, the interface judges the format of the input model, such as pth and onnx, and if the input format is not consistent, the current process will be interrupted and an exception of “unsupported model format” will be thrown. If the input format is within the optional range, the interface will first parse the model according to the form in which the corresponding format saves the model (for example, the structure and weight of the model saved in the form of protobuf by Onnx), at this time, the weight part of the model is ignored, the model structure is extracted and a directed graph is obtained, and the node set represents the set of operators of the model, and the edge set represents the dependency relationship between the operators. Each node stores the parameters of the corresponding operator . If the calculation mode generated by parsing the operator is not in the set, the process will be terminated and an exception of “unresolvable operator type” will be thrown to the user. The operator that can be normally parsed is 1 when the calculation mode is not Conv or Pool , is 1, otherwise the parameter of the corresponding operator. The edge represents the dependency relationship between the operators and , that is, the calculation of depends on the calculation state of satisfying , wherein is a dependency condition function, is an expression related to the architecture data flow and the algorithm itself, and here only an empty is created for each node, and the function will be filled in the operator parsing and fusion module.

[0072] In the embodiment of the application, the operator parsing and fusion module generates a fused operator, including the following steps:

[0073] B1, constructing an operator optimization template library;

[0074] B2, constructing a fused node with the node and its corresponding successor node , judging whether the calculation mode of the fused node belongs to the operator optimization template library, if so, replacing the node with the fused node , and generating an edge between the node and the successor node ;

[0075] B3, repeating B2 until all nodes in the directed graph are replaced to generate a fused operator.

[0076] The operator parsing and fusion module analyzes the operator dependencies of the model and reconstructs fusion operators with complete in-memory computation semantics for parts that can be optimized (such as the fusion of convolution and BatchNorm).

[0077] For a node If its computation mode is Conv or Pool, it has a single data dependency node. ,calculate middle The data at that location requires its predecessor dependent nodes. Compute the output satisfying the given data stream. as well as Take all the points with values ​​and record the dependencies in the graph. middle.

[0078] If node If the computation mode is of type Add, then it has multiple predecessor data dependency nodes. , …and it can only be calculated when multiple dependency conditions are met simultaneously.

[0079] Building upon this, this module also defines a series of operator optimization templates conforming to the in-store computation format of Tile, forming a template library. The entire operator graph generated by the above process is traversed using graph search, and for each node... Check the node and its successor nodes. The fusion nodes constituted Calculation mode If it exists in the LA set, then it will be merged. Replace the original Nodes and records and To merge nodes while maintaining the original dependency between the two nodes, further modifications are made to all nodes. for Integrating the original The dependencies between nodes, ultimately from Delete Each node completes one operator fusion and then checks whether the fused node can be merged with its successor nodes. Construct a fusion operator that conforms to the template. If If none of its neighboring nodes can form a fusion operator that satisfies the template library LA, then the pairing ends. The search began with successor node The same search and detection are performed starting from this point.

[0080] In the embodiment of the present application, in B1, the expression of the operator optimization template library is

[0081]

[0082] In the formula, represents that the convolution and activation operations are completed in a Tile in the order of convolution first and then activation, represents that the convolution, activation, and pooling operations are completed in a Tile in the order of convolution first, then activation, and then pooling, represents that the convolution, activation, and residual addition operations are completed in a Tile in this order. Users can construct a template library according to their own Tile functions. If a Tile only contains a single computing function, the template library creation can be skipped.

[0083] In the embodiment of the present application, the weight splitting and mapping module generates a Tile intercommunication graph including the following steps:

[0084] C1, based on the fusion operator, splitting the computing task of the to-be-tested model into a plurality of task blocks;

[0085] C2, based on the plurality of task blocks, constructing adjacent layer communication edges and intra-layer communication edges to generate a Tile intercommunication graph.

[0086] The adjacent layer communication edge / cross-layer communication edge is: wherein, represents that there is an adjacent layer communication edge / cross-layer communication between the pth task block and the qth task block, represents the Tile corresponding to the (i, j) weight block of the xth operator node, represents the Tile corresponding to the (p, q) weight block of the yth operator node, represents the Tile set split by the operator node numbered x, represents the Tile set split by the operator node numbered y, the operator node numbered y should be a predecessor of the operator node numbered x, represents the input channel of the (i, j) weight block of the xth operator node, represents the output channel of the (k, l) weight block of the yth operator node. That is, if the input channel of the current Tile and the output channel of a Tile in the predecessor node have a coincident part, a data dependency edge is constructed and the dependency relationship of the previous two operator nodes is inherited, until all the Tile of the current operator node and all the predecessor node Tile are traversed, at which time the adjacent layer communication edge / cross-layer communication edge is constructed.​​​​

[0087] The checking of the intra-layer communication edge is similar to that, specifically: , , wherein, represents the output channel of the (k, l) weight block of the x operator node, wherein (k, l) is not equal to (i, j). That is, the current operator node Tile and the rest of the current operator node Tiles are traversed, and if the output channel of the current Tile has a coincident part with the output channel of a certain Tile in the operator node, a data dependency edge is formed and a dependency relationship of synchronously corresponding position data is created (that is, when the intra-layer fusion communication buffers of the two nodes are both non-empty, fusion can be performed) until the interrelation between all Tiles in the operator node is judged, and the intra-layer fusion communication edge is created.

[0088] In the embodiment of the application, the communication network mapping module calculates the Hamilton distance between the mapped physical Tiles according to the Tile communication condition in the Tile communication graph, and determines the communication delay between the Tiles according to the link delay, loads all the communication delays to the edges of the Tile communication graph, and generates a task block communication graph.

[0089] As shown in Figure 2 , the Tile generated in the previous module is a logical Tile, which needs to be one-to-one bound with the Tile in the actual physical position of the chip. The module can map the Tile to the physical architecture interconnected by the on-chip communication network according to a certain user-specified mapping algorithm, calculate the Hamilton distance between the mapped physical Tiles to be communicated according to the Tile communication condition in the Tile communication graph generated by the previous module, and obtain the communication delay between the Tiles according to the link delay given by the user configuration information. And load each communication delay to the edge of the Tile communication graph to form a task block communication graph.

[0090] In the embodiment of the application, the Tile model interface splits the internal blocking cache into a plurality of cache blocks according to the task block communication graph, wherein the types of the cache blocks include data dependency cache, data replication cache, data synchronization cache and data redundancy cache.

[0091] To adapt to different hardware tile schemes, the Tile model interface provides a customized tile modeling template, allowing users to highlight cache locations and release conditions on a specified template based on a predefined data flow scheme within a tile. This interface parses the user-input tile model to ensure it conforms to the template specifications (specifically, it checks the number of caches defined in the user model, whether all caches have input / output connections and are not isolated, whether all three types of tile input / output interfaces are connected to caches, whether each computational component has consumption and production conditions, and whether each computational component has inputs and outputs). It also checks for circular dependencies (circular dependencies are those where the output of cache A is the input of cache B, and the input of cache B is the output of cache A; this is checked by identifying the node in a directed graph within the template for each type of cache). To check for circular dependencies, the system is first determined by whether it is a directed acyclic graph (DAG). Specific detection algorithms can include Kahn's algorithm or Depth-First Search (DFS). Once verified, the internal block cache is broken down into cache blocks based on different demand sources. The cache demands within the in-memory compute tile are categorized into four types: 1. Data-dependent cache, caused by the data reuse distance of a specified data stream; 2. Data replication cache, caused by multiple tasks sharing input during task partitioning; 3. Data synchronization cache, caused by a computation task requiring data from multiple different sources with varying generation times; 4. Redundant cache, introduced to ensure system flexibility and physical feasibility. By default, all cache blocks are split into these four types. If users have specific functionalities for certain caches during programming, they can reduce the number of splits by marking the corresponding cache blocks. Communication latency between cache nodes after splitting the same cache block is zero, ultimately forming a cache communication graph differentiated by demand type.

[0092] In this embodiment of the invention, the cache capacity iteration module generates an intra-chip data flow graph based on the inter-cache communication graph, sets a starting cache node, uses the data generated by the starting cache node once as the iteration step size, traverses all nodes in the intra-chip data flow graph, and completes the iterative solution.

[0093] In embodiments of the present invention, such as Figure 3 As shown, custom tile modeling must meet the following requirements:

[0094] 1) The interconnection relationship and transmission / computation latency of the internal buffer area are explicitly indicated in the form of a weighted and directed graph within the Tile (the computation latency of the stored computation macro and other computation units are also directly saved as the latency on the corresponding path in the weighted and directed graph). The computation and communication components within the Tile are represented as data consumption conditions and data production conditions (and corresponding computation components) related to operator dependencies, and each component will bring a certain latency.

[0095] 2) The Tile model should include three types of input and output interfaces: adjacent layer data input, intra-layer partial data input, cross-layer data input, intra-layer partial data output, cross-layer data output, and adjacent layer data output. The connection relationship between the subgraph and the interface must be explicitly shown to ensure that the input data can be correctly loaded into the corresponding cache.

[0096] 3) The tile does not need to have actual functions; it only needs to reflect the data flow relationship. The data input and output ports in the iteration process do not transmit actual data, but rather the amount of data generated in one iteration.

[0097] Taking a complete running process as an example. First, the user needs to analyze the Tile data flow in the in-memory computing architecture to be simulated, such as... Figure 4 As shown, this tile needs to receive cross-layer data (residual connections), neighboring layer data (output of the previous convolutional layer), and intra-layer partial sum data (computation results of the corresponding tiles for other weight blocks in the same layer) from other tiles. Intra-layer partial sum data entering this tile only needs to be added sequentially to the computation results of the in-tile computation macro; therefore, both are stored in an aggregation synchronization cache for data synchronization. Neighboring and cross-layer data, however, need to be stored to meet the computational requirements of convolution and residual operators, and are therefore stored in a data dependency cache. If these data need to undergo pooling operations after completing their own computations, they also need to be stored in the data dependency cache first, until the data dependency requirements for pooling operations are met. This analysis clarifies the data exchange requirements between the functional modules in the tile, facilitating subsequent modeling.

[0098] like Figure 5 As shown, users can model the tile based on the tile template.

[0099] After the model is input into the system, the system parses the model, and some cached parts are broken down as follows: Figure 6 As shown, the internal functionality of a typical Tile cache may cover... Figure 4 The diagram shows several cache types. Therefore, based on the modeling of the Tile, the complete cache in the actual Tile is decomposed into different types of caches with zero communication latency for easier analysis, such as... Figure 6 In this context, the different types of caches in cache block 1 represent caches with different functions but the same physical carrier, therefore the latency of each type of cache in cache block 1 is 0. Cache block 1 and cache block 2 represent two different caches, and the communication latency between them depends on the link latency and the latency of the interconnected functional units.

[0100] like Figure 7 As shown, the user provides the Tile specification through the configuration information interface and passes in the CNN model to realize the operator parsing and weight splitting mapping of the model.

[0101] As shown in Figure 8 communication delay between each Tile, and load the customized Tile model into the Tile communication graph with the communication delay. Then iterate according to the user-set data injection rate. Finally, record the runtime size of each type of cache in each Tile during the system running process.

[0102] Finally, store the data amount in each type of cache in each Tile at each time as a csv file. The user can also convert the output into other formats. The numerical value can be used by the designer as a reference for setting the cache capacity and formulating the corresponding optimization strategy.

[0103] Those skilled in the art will understand that the embodiments described herein are for the purpose of helping the reader understand the principles of the present application and should be understood as not limiting the scope of protection of the present application to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations according to the technical inspiration disclosed in the present application without departing from the essence of the present application, and these modifications and combinations are still within the scope of protection of the present application.

Claims

1. A cache capacity solver for a non-volatile memory-compute integrated architecture, the cache capacity solver comprising: The configuration port, the CNN model loading interface, the operator analysis and fusion module, the weight splitting and mapping module, the communication network mapping module, the Tile model interface, and the cache capacity iteration module are included. The configuration port is configured to control the configuration process. The CNN model loading interface is configured to generate the dependency relationship between the operators after the configuration process is completed. The operator analysis and fusion module is configured to analyze the dependency relationship between the operators and generate the fused operators. The weight splitting and mapping module is configured to generate the inter-Tile communication graph according to the fused operators. The communication network mapping module is configured to generate the task block communication graph according to the inter-Tile communication graph. The Tile model interface is configured to generate the inter-cache communication graph according to the task block communication graph. The cache capacity iteration module is configured to generate the intra-Tile data flow graph according to the inter-cache communication graph and perform iterative solving. The operator analysis and fusion module generates the fused operators, including the following steps: B1. Construct an operator optimization template library. B2, Node and its corresponding successor node Constituting a fusion node Determine whether the computation mode of the fusion node belongs to the operator optimization template library; if so, then merge the node. Replace with merge node and generate nodes With successor nodes The edge between ; B3. Repeat B2 until all nodes in the directed graph are replaced to generate the fused operators. In the B1, the operator optimization template library The expression is: ； wherein denotes that the convolution and activation operations are done in a Tile in the order of convolution first and activation second, denotes that the convolution, activation, and pooling operations are done in a Tile in the order of convolution first, activation second, and pooling third, denotes that the convolution, activation, and residual addition operations are done in a Tile in this order; The weight splitting and mapping module generates the inter-Tile communication graph, including the following steps: C1. Based on the fused operators, split the calculation task of the model to be tested into a plurality of task blocks. C2. Based on the plurality of task blocks, construct the inter-layer communication edges and the intra-layer communication edges to generate the inter-Tile communication graph. The communication network mapping module calculates the Hamilton distance between the mapped physical Tiles according to the Tile communication condition in the inter-Tile communication graph, determines the communication delay between the Tiles according to the link delay, loads all the communication delays to the edges of the inter-Tile communication graph, and generates the task block communication graph. The Tile model interface splits the internal block cache into a plurality of cache blocks according to the task block communication graph, wherein the types of the cache blocks include data dependency cache, data replication cache, data synchronization cache, and data redundancy cache. The cache capacity iteration module generates the intra-Tile data flow graph according to the inter-cache communication graph, sets a starting cache node, produces one data of the starting cache node as an iteration step, traverses all the nodes in the intra-Tile data flow graph, and completes the iterative solving.

2. The cache capacity solver for non-volatile memory-compute integrated architecture according to claim 1, wherein, The configuration port controls the configuration process, including the following steps: A1. Generate a key-value pair according to the hardware parameters configured by the user. A2. Legally detect the configuration items and specific values of the key-value pair, and enter A3 after the legal detection. A3. Determine whether all the necessary parameters for running the cache capacity solver are configured as valid values using the configuration port, and if so, complete the configuration process, otherwise interrupt the configuration process.

3. The cache capacity solver for non-volatile memory-compute integrated architecture according to claim 2, wherein, In the A1, the expression of the key-value pair is: ； In the formula, This indicates the first configuration item of the hardware. This indicates the specific value of the first configuration item of the hardware. This indicates the second configuration item for the hardware. This indicates the specific value of the second configuration item for the hardware. The first part represents the hardware. Configuration items, The first part represents the hardware. The specific value of the configuration item.

4. The cache capacity solver for non-volatile memory compute integrated architecture according to claim 1, wherein, The CNN model loading interface determines the directed graph according to the model format of the model to be tested to generate the dependency relationship between the operators, wherein the node set of the directed graph represents the operator set of the model to be tested, and the edge set of the directed graph represents the dependency relationship between the operators of the model to be tested. each node in the set of nodes of the directed graph corresponds to a parameter of an operator The expression for the operator is: ； In the formula, represents the input feature map size, represents the output feature map size, represents the calculation mode, represents the window size, represents the step.

Images