Processing device, system and method for implementing high performance cache based on single port RAM

Abstract

The application provides a processing device, a system and a data read-write method for realizing high-performance cache based on a single-port RAM. The processing device comprises: an array module for dividing a large-capacity RAM into n single-port RAM arrays; a bank equalization scheduling module for realizing bank equalization scheduling of read-write operations in the same shot through a bank equalization scheduling and conflict avoidance mechanism; a free_addr_ctrl module and a next_point module for realizing dynamic address management through bidirectional list management of data addresses. The processing device, the system and the data read-write method in the technical scheme of the application can ensure high performance, significantly reduce area and power consumption, simplify timing design, and are suitable for high-bandwidth data processing scenarios.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of memory, and particularly relates to a processing device, a system and a data read-write method for realizing high-performance cache based on a single-port RAM (Random Access Memory). BACKGROUND

[0002] With the continuous increase of network data bandwidth, the demand for cache of data processing systems is also increasing. In a high-bandwidth environment, data cache needs to support higher throughput, and usually requires processing capacity of one or two packets per beat. This puts higher requirements on the design of the memory, especially in scenarios that support read and write operations at the same time. In related memory technologies, single-port RAM (1p11), pseudo-dual-port RAM (2p11) and true dual-port RAM (2p22) are common choices. Single-port RAM is suitable for scenarios where read and write operations are not required to be performed at the same time, but its limitation is that it cannot meet the demand of high-throughput data processing. Pseudo-dual-port RAM and true dual-port RAM are suitable for scenarios that require read and write operations to be performed at the same time, especially in high-bandwidth data processing, but their high area and power consumption limit their application in resource-constrained scenarios. SUMMARY

[0003] The application aims to provide a processing device, a system and a data read-write method for realizing high-performance cache based on a single-port RAM. It aims to solve the problems of large area, high power consumption, timing convergence difficulty and inability to realize continuous read and write in the related art.

[0004] According to a first aspect of the application, a processing device for realizing high-performance cache based on a single-port RAM is provided, which specifically comprises:

[0005] A Mem_array module configured to divide a large-capacity RAM into n single-port RAMs to form a mem_array, wherein n is a natural number greater than 2;

[0006] A free addr ctrl module configured to store the free addresses of each single-port RAM in an independent address management FIFO (a common data structure for managing address queues), for data write operation, and to prefetch a number of addresses to speed up address allocation;

[0007] A bank equalization scheduling module configured to balance the load among the banks to ensure that the amount of cache data of each bank is basically consistent, so as to reduce bank conflicts during reading;

[0008] The VL_PKT_Q module is configured to divide different virtual channels VL according to service requirements, create a bidirectional linked list according to address information and related data in the corresponding virtual channel, and connect corresponding write data addresses by means of a sub-chain.

[0009] The next_point module is configured to update address information of the bidirectional linked list.

[0010] The application splits a large-capacity RAM into multiple single-port RAMs, reduces the area and timing convergence difficulty of a single RAM, dynamically allocates read and write operations to different banks through the bank balancing scheduling module, avoids read and write conflicts, and realizes read and write operations in the same beat. In addition, the application increases the flexibility of timing modification through the VL_PKT_Q module, adapts to the requirements of different service scenarios. Through the free_addr_ctrl module and the next_point module, the address allocation and data read and write efficiency are optimized.

[0011] In an optional embodiment, the apparatus further comprises:

[0012] The MUX module (Multiplexer) is configured to determine a virtual channel VL of a packet according to packet information.

[0013] This embodiment improves the parallelism and flexibility of data processing through virtual channel division.

[0014] In an optional embodiment, the bank balancing scheduling module is configured to realize read and write operations in the same beat through a bank balancing scheduling and conflict avoidance mechanism. If a read bank and a write bank conflict, the scheduling selects other idle banks for write operation. This embodiment realizes read and write operations in the same beat through an intelligent scheduling mechanism, and effectively improves the data bandwidth.

[0015] In an optional embodiment, the VL_PKT_Q module is configured to have a number of sub-chains greater than or equal to a mem (Memory) read delay.

[0016] This embodiment sets the number of sub-chains to be greater than or equal to the mem read delay, increases the flexibility of timing modification, and adapts to the requirements of different service scenarios.

[0017] According to a second aspect of the application, a system for realizing high-performance cache based on a single-port RAM is provided, comprising: the processing apparatus for realizing high-performance cache based on a single-port RAM according to the first aspect.

[0018] According to a third aspect of the present application, a data read-write method for realizing high-performance cache based on single-port RAM is provided, comprising:

[0019] A data initialization step: write the free addresses of each bank into the corresponding bankn_addr_fifo, and after initialization, the bank equalization scheduling module schedules the addresses from the corresponding fifo for subsequent data processing;

[0020] A data write step: when external data is written, according to the header information, the data is distributed to the corresponding virtual channel VL through the MUX module, and a bidirectional linked list is created in the VL according to the scheduled address information and data;

[0021] A data storage step: while creating the linked list, the address provided by the corresponding data is written into the mem_array;

[0022] A linked list information caching step: cache the next_point information of the linked list for subsequent data reading.

[0023] In an optional implementation, the step of creating a bidirectional linked list in the VL according to the scheduled address information and data specifically comprises:

[0024] The first beat of data is written into the head pointer of the first sub-chain;

[0025] The second beat of data is written into the head pointer of the second sub-chain;

[0026] Similarly, a total of four sub-chains are used to cover the read delay of the mem, ensuring continuous data;

[0027] When the fifth beat of data arrives, the data is written into the mem_array, and the next_point and tail_point of the first sub-chain are updated;

[0028] When the sixth beat of data arrives, the next_point and tail_point of the second sub-chain are updated,

[0029] Similarly, the creation and updating of the linked list are completed.

[0030] In an optional implementation, the method further comprises:

[0031] A data read step: if the sending condition is met, an external read request is generated, and data needs to be read from the cache,

[0032] The address of the data is obtained from the head information of the first sub-chain table, and the data is read,

[0033] According to the next_point indication, read the address information buffered in the next_point, update to the head,

[0034] The next beat reads the head information of the second sub-chain, and also reads the address information corresponding to the next_point, and updates to the head of the second sub-chain,

[0035] By analogy, the data reading and linked list updating are completed;

[0036] The data output step reads the data buffered in the mem_array according to the address in the linked list and sends it to the outside;

[0037] The address recycling step reads the data address and sends it to the free_addr_ctrl module for subsequent scheduling.

[0038] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the application. The objects and other advantages of the present application can be realized and achieved by the structure and processes as described in the specification and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the embodiment or related art description. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0040] Figure 1 It is a structure schematic diagram of the device for realizing high-performance cache based on single-port RAM according to the exemplary embodiments of the present application.

[0041] Figure 2 It is a structure block diagram of the system for realizing high-performance cache based on single-port RAM according to the exemplary embodiments of the present application.

[0042] Figure 3 It is a flow block diagram of the data reading and writing method for realizing high-performance cache based on single-port RAM according to the exemplary embodiments of the present application.

[0043] Figure 4 It is a flow schematic diagram of the data reading and writing method for realizing high-performance cache based on single-port RAM according to the exemplary embodiments of the present application. DETAILED DESCRIPTION

[0044] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall into the scope of the present application.

[0045] In a high-bandwidth environment, data caching needs to support higher throughput, usually requiring the processing capacity of one or two packets per beat. This puts higher requirements on the design of the memory, especially in scenarios that support read and write operations simultaneously. In the related art, single-port RAM and pseudo-dual-port RAM have significant differences in area, power consumption and performance, and need to be weighed according to specific application scenarios.

[0046] Single-port RAM can only perform read or write operations in the same clock cycle and cannot perform read and write operations simultaneously. Its characteristics are high working frequency (1715N3 135MHz) and relatively small area and power consumption. For example, in the S12 process, the area of a single-port RAM (sram_w48_d256_1pl1) with a capacity of 12,288 bits is 3562.6721*2=7,125.344. Single-port RAM is suitable for scenarios where read and write operations are not required to be performed simultaneously, but its limitation is that it cannot meet the demand of high-throughput data processing.

[0047] Pseudo-dual-port RAM can perform read and write operations in the same clock cycle, but read and write operations cannot access the same address simultaneously. Its working frequency is relatively low (810-1484MHz), and the area and power consumption are large. For example, in the S12 process, the area of a pseudo-dual-port RAM (sram_w48_d256_2p11) with a capacity of 12,288 bits is 4297.7526*2=8,595.5052, which is 1.2 times that of single-port RAM. As the memory capacity increases, the gap in area and power consumption will further widen. Pseudo-dual-port RAM is suitable for scenarios that require read and write operations to be performed simultaneously, especially in high-bandwidth data processing, but its high area and power consumption limit its application in resource-constrained scenarios.

[0048] As can be seen, pseudo-dual-port RAM can perform read and write operations in the same clock cycle and is suitable for high-throughput data processing scenarios. However, directly using dual-port RAM can meet the high-throughput demand, but the area is large, the power consumption is high, and the timing convergence is difficult.

[0049] In order to reduce the area and power consumption, the patent document CN103594109A proposes a scheme of using single-port RAM to realize the pseudo dual-port function. The scheme realizes the read-write operation on a single single-port RAM through time division multiplexing. Although the scheme reduces the area and power consumption, it cannot realize continuous read-write and the data bandwidth is limited.

[0050] Based on the above analysis, referring to the structural schematic diagram of Figure 1 , the application exemplarily proposes a processing device for realizing high-performance cache based on single-port RAM, specifically comprising:

[0051] The Mem_array module is configured to divide the large-capacity RAM into n single-port RAMs to form a mem_array, wherein n is a natural number greater than 2;

[0052] The free addr ctrl module is configured to store the free addresses of each single-port RAM in an independent address management FIFO, for data write operation, and to prefetch a number of addresses to speed up address allocation;

[0053] The bank equalization scheduling module is configured to balance the load among the banks to ensure that the cache data amount of each bank is basically consistent, so as to reduce the bank conflict during reading;

[0054] The VL_PKT_Q module is configured to divide different virtual channels VL according to service requirements, to create a bidirectional linked list according to address information and related data in the corresponding virtual channel, and to connect the corresponding write data addresses through a sub-chain manner;

[0055] The next_point module is configured to update the address information of the bidirectional linked list.

[0056] Exemplarily, the Mem array module of the application divides the large-capacity RAM into n banks, each bank being implemented by a single-port RAM. Each bank can independently perform read and write operations. n is a natural number greater than 2, and the specific value is obtained by comprehensively considering the area, timing, and access conflict probability indicators in the UVM simulation platform. For example, for a 40k depth (40,960 entries), the simulation results show that when n = 10, the conflict probability approaches 0, and the control logic area is controllable. The bank division method is to evenly divide the total depth of 40k (40,960 entries) into 10 banks, and each bank has a capacity of 4K. By using the uniform division method, read and write requests are dispersed to 10 banks, and the conflict probability is about 10%. After simulation verification by balanced scheduling, it is further reduced to close to 0%, effectively avoiding read and write conflicts; under the S12 process, the total area of 10 1p11 is 35,626.7, which is significantly lower than 42,977.5 of the pseudo dual-port RAM, significantly reducing the area; in addition, the single bank operating frequency can reach 3135MHz, and the scheduling logic only needs to switch between 10 banks, the critical path delay is controllable, and the timing convergence is flexible.

[0057] Exemplarily, the free_addr_ctrl module of the application prewrites all free addresses of each single-port RAM into the corresponding fifo in the initialization stage. In the running stage, a plurality of addresses (for example, 2-4) are prefetched from the fifo and cached in the register for fast allocation. By pre-fetching the addresses, the delay of address allocation is reduced, and the data write throughput is improved.

[0058] The application reduces the area and timing convergence difficulty of a single RAM by splitting the large-capacity RAM into multiple single-port RAMs; avoids read and write conflicts and realizes read and write operations in the same beat by dynamically allocating read and write operations to different banks through the bank balanced scheduling module; in addition, the application increases the flexibility of timing modification through the VL_PKT_Q module to adapt to the needs of different service scenarios. The free_addr_ctrl module and the next_point module optimize the address allocation and data read and write efficiency.

[0059] In some optional embodiments, the apparatus further comprises:

[0060] The MUX module is configured to determine the virtual channel VL of the packet according to the packet information.

[0061] Exemplarily, as described above, the embodiment improves the parallelism and flexibility of data processing by dividing the virtual channel.

[0062] In an optional embodiment, the VL_PKT_Q module is configured to have a number of sub-chains greater than or equal to a mem read latency. This embodiment sets the number of sub-chains to be greater than or equal to the mem read latency, so that the flexibility of timing modification is increased to adapt to the requirements of different service scenarios.

[0063] In some optional embodiments, the bank balance scheduling module is configured to implement read and write operations in the same beat through a bank balance scheduling and conflict avoidance mechanism. If a read bank and a write bank conflict, the scheduling selects other free banks for write operations. This embodiment implements read and write operations in the same beat through an intelligent scheduling mechanism, effectively improving data bandwidth.

[0064] Correspondingly, as shown in Figure 2 illustrated, the present application exemplarily provides a system for implementing high-performance caching based on a single-port RAM, comprising: a processing device for implementing high-performance caching based on a single-port RAM as shown in Figure 1 illustrated.

[0065] In some optional embodiments, the device further comprises:

[0066] A MUX module configured to determine a virtual lane VL of a packet according to packet information.

[0067] Exemplarily, as described above, this embodiment improves the parallelism and flexibility of data processing through virtual lane division.

[0068] In an optional embodiment, the VL_PKT_Q module is configured to have a number of sub-chains greater than or equal to a mem read latency. This embodiment sets the number of sub-chains to be greater than or equal to the mem read latency, so that the flexibility of timing modification is increased to adapt to the requirements of different service scenarios.

[0069] In some optional embodiments, the bank balance scheduling module is configured to implement read and write operations in the same beat through a bank balance scheduling and conflict avoidance mechanism. If a read bank and a write bank conflict, the scheduling selects other free banks for write operations. This embodiment implements read and write operations in the same beat through an intelligent scheduling mechanism, effectively improving data bandwidth.

[0070] The device described above is completely consistent with the processing device for implementing high-performance caching based on a single-port RAM provided by the above embodiments, and specific details can be referred to the description of the device in the above embodiments, which will not be repeated here.

[0071] Correspondingly, as shown in Figure 3 illustrated, the present application exemplarily provides a data read-write method for implementing high-performance caching based on a single-port RAM, comprising:

[0072] Data initialization step: write the free address of each bank into the corresponding bankn_addr_fifo, and after initialization, the bank equalization scheduling module schedules the address from the corresponding fifo for subsequent data processing;

[0073] Data write step: when external data is written, according to the header information, the data is distributed to the corresponding virtual channel VL through the MUX module, and a bidirectional linked list is created in VL according to the scheduled address information and data;

[0074] Data storage step: while creating the linked list, write the address provided by the corresponding data into the mem_array;

[0075] Linked list information caching step: cache the next_point information of the linked list for subsequent data reading.

[0076] In some optional embodiments, a bidirectional linked list is created in VL according to the scheduled address information and data, which specifically includes:

[0077] The first beat of data is written to the head pointer of the first sub-chain;

[0078] The second beat of data is written to the head pointer of the second sub-chain;

[0079] By analogy, a total of four sub-chains are used to cover the read delay of the mem, ensuring continuous data;

[0080] When the fifth beat of data arrives, the data is written to the mem_array, and the next_point and tail_point of the first sub-chain are updated;

[0081] When the sixth beat of data arrives, the next_point and tail_point of the second sub-chain are updated,

[0082] By analogy, the creation and update of the linked list are completed,

[0083] Data output step: read the data cached in the mem_array according to the address in the linked list and send it to the outside;

[0084] The address recycling step reads the data address and sends it to the free_addr_ctrl module for subsequent scheduling. The number of sub-chains needs to be greater than or equal to the read delay of the mem, so that the address can be obtained from the sub-chain to directly read the data address, without waiting for the data at the next point to be read from the mem, thereby increasing the flexibility of timing modification. When the RAM read delay is equal to the number of sub-chains, the address storage positions of different write cycles do not overlap, thereby avoiding data conflicts. Taking four sub-chains as an example when the read delay is four beats, the first beat writes sub-chain 1 and the fifth beat reads sub-chain 1; the second beat writes sub-chain 2 and the sixth beat reads sub-chain 2; and so on. The read-write operation is completely decoupled in time and space, avoiding read-write conflicts and ensuring the continuity of reading data.

[0085] Correspondingly, as shown in Figure 4 The present application exemplarily provides a data read-write method for realizing high-performance cache based on a single-port RAM, and the specific steps are as follows:

[0086] Step S401: Data initialization: write all the free addresses of each bank into the corresponding bankn_addr_fifo, and after initialization, the bank equalization scheduling module schedules the addresses from the corresponding fifo for subsequent data processing;

[0087] Step S402: Data writing: when external data is written, according to the header information, the data is distributed to the corresponding virtual channel VL through the MUX module, and a bidirectional linked list is created in the VL according to the scheduled address information and data;

[0088] Step S403: Data storage: while creating the linked list, the address provided by the corresponding data is written into the mem_array;

[0089] Step S404: Linked list information caching: cache the next_point information of the linked list for subsequent data reading.

[0090] The present application realizes a processing device, system and method with high throughput, low area and low power consumption by using a single-port RAM and a linked list management mechanism, and the specific advantages are at least as follows:

[0091] 1. Reduced area: for a large-capacity cache, using a single-port RAM can significantly reduce the area. Generally, the area of a dual-port RAM is 20% to 50% larger than that of a single-port RAM. By splitting a large-capacity RAM into multiple single-port RAMs and using a linked list management mechanism, the area utilization is further optimized.

[0092] 2. Cost savings: the cost of a single-port RAM is lower than that of a dual-port RAM. By using a single-port RAM instead of a dual-port RAM, the hardware cost can be reduced.

[0093] 3. Timing is easy to converge. The working frequency of single-port RAM is usually higher than that of dual-port RAM. At high clock speed, single-port RAM can better meet the timing requirements and improve the overall performance of the system.

[0094] 4. Reduce power consumption. The power consumption of single-port RAM is significantly lower than that of dual-port RAM. By using single-port RAM, the power consumption of the system can be reduced, prolonging the endurance time of the device or reducing the cooling requirement.

[0095] 5. Cache management is easy to expand. The cache management is carried out by using a linked list, which has high flexibility and scalability. By increasing the number of corresponding queue linked lists, the cache management can be expanded to multiple queue data cache management, adapting to different business requirements.

[0096] It can be understood that the memory circuit structure, module name and element described in the above embodiments are only examples. Those skilled in the art can also easily think of combining and adjusting the structural features of the above multiple embodiments according to the use needs, and the concept of the present application should not be limited to the specific details of the above examples.

[0097] Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A processing device for implementing a high performance cache based on a single port RAM, characterized in that, The device comprises: a Mem_array module configured to divide a large-capacity RAM into n single-port RAMs to form a mem_array, wherein n is a natural number greater than 2; free _ addr _ a control module configured to store free addresses of each single-port RAM in an independent address management FIFO for data write operation and prefetch a number of addresses to speed up address allocation; a bank balancing scheduling module configured to balance the load among the banks to ensure that the amount of cached data in each bank is substantially consistent, thereby reducing bank conflicts during reading; a VL_PKT_Q module configured to divide different virtual lanes VL according to service requirements, create a double-linked list according to address information and related data in the corresponding virtual lane, and connect the corresponding write data addresses by means of sub-chains; a next_point module configured to update the address information of the double-linked list.

2. The processing device for implementing high performance cache based on single port RAM according to claim 1, wherein, The device further comprises: a MUX module configured to determine the virtual lane VL to which a packet is directed according to packet information.

3. The processing device for implementing high-performance cache based on single-port RAM according to claim 1, wherein the bank balancing scheduling module is configured to implement read and write operations in the same beat through a bank balancing scheduling and conflict avoidance mechanism, and if a read bank and a write bank conflict, the scheduling selects other idle banks for write operation.

4. The processing device for implementing high-performance cache based on single-port RAM according to claim 1, wherein the number of sub-chains of the VL_PKT_Q module is greater than or equal to the read delay of the mem.

5. The processing device for implementing high performance cache based on single port RAM according to claim 2, wherein, The device divides the data into a plurality of data packets by the VL _ PKT _ The Q module and the MUX module implement virtual lane division, improving parallelism and flexibility of data processing.

6. The processing device for implementing high performance cache based on single port RAM according to claim 2, wherein, The device is free _ addr _ The dynamic address management is realized by the ctrl module and the next_point module, and the address allocation and data read-write efficiency are optimized.

7. A system for implementing a high performance cache based on a single port RAM, characterized in that, The system comprises the processing device for implementing high-performance cache based on single-port RAM according to any one of claims 1-6.

8. A data read-write method for implementing a high-performance cache based on a single-port RAM, characterized in that, The method comprises: Data initialization step: write all the free addresses of each bank into the corresponding bankn _ addr _ In the fifo, after initialization, the bank equalization scheduling module schedules the addresses from the corresponding fifo for subsequent data processing; a data writing step: when external data is written, the data is allocated to the corresponding virtual lane VL through the MUX module according to the header information, and a double-linked list is created according to the address information and data scheduled in the VL; a data storage step: while the list is created, the address corresponding to the data is written into the mem_array; a list information caching step: the next_point information of the list is cached for subsequent data reading.

9. The data read / write method of claim 8, wherein, The double-linked list created according to the address information and data scheduled in the VL specifically comprises: first beat data is written into the head pointer of the first sub-chain; second beat data is written into the head pointer of the second sub-chain; and so on, a total of four sub-chains are used to cover the read delay of the mem to ensure data continuity; when fifth beat data arrives, the data is written into the mem_array, and the next_point and tail_point of the first sub-chain are updated; when sixth beat data arrives, the next_point and tail_point of the second sub-chain are updated, and so on, the creation and update of the list are completed.

10. The data read / write method of claim 9, wherein, The method further comprises: a data reading step: if a sending condition is met, an external read request is generated, and data needs to be read from the cache, the address of the data is obtained from the head information of the first sub-chain table, and the data is read, the address information cached in the next_point is read according to the next_point indication, and is updated into the head, and so on. The next beat reads the head information of the second sub-chain, reads the address information corresponding to the next_point, and updates the head of the second sub-chain, By analogy, the reading of data and the updating of the chain table are completed; In the data output step, the data cached in the mem_array is read according to the address in the chain table and sent to the outside. Address recycling step, reading data address while giving free _ addr _ Ctrl module for subsequent scheduling.

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