Inter-nuclear communication method and system, medium and product

Abstract

The invention provides an inter-core communication method and system, a medium and a product. The method is applied to a multi-core processor system, and a mailbox module of the multi-core processor system comprises a data channel. The method comprises the following steps: a first sending core determines a corresponding first data channel according to a first receiving core corresponding to data to be sent, and writes the data to be sent into the first data channel; wherein each sending core corresponds to a plurality of simplex data channels, and the receiving cores corresponding to the plurality of data channels are a plurality of cores except the sending core; and the first receiving core receives the data to be sent. The method provided by the invention is used for reducing competition of inter-core communication resources and improving data transmission efficiency.

Description

Technical Field

[0001] This application relates to computer technology, and in particular, to an inter-core communication method, system, medium, and product. Background Art

[0002] A multi-core processor refers to a processor that integrates two or more complete independent processing cores (kernels) in one processor, aiming to improve the overall performance of the processor and accelerate calculations by executing multiple tasks in parallel. Inter-core communication is crucial in a multi-core processor system and is used to ensure data exchange and collaboration between multiple processing cores.

[0003] In the prior art, inter-core communication is often achieved through shared memory. Two or more cores can access the same shared memory space and exchange information and status by reading and writing data in this space. However, the competition among multiple cores for the shared memory is relatively large, which will affect the system performance. Summary of the Invention

[0004] This application provides an inter-core communication method, system, medium, and product to reduce the competition for inter-core communication resources and improve data transmission efficiency.

[0005] On the one hand, this application provides an inter-core communication method applied to a multi-core processor system. The mailbox module of the multi-core processor system includes a data channel. The method includes:

[0006] The first sending core determines a corresponding first data channel according to the first receiving core corresponding to the data to be sent, and writes the data to be sent into the first data channel. Each sending core corresponds to multiple simplex data channels, and the receiving cores corresponding to these multiple data channels are respectively multiple cores except this sending core.

[0007] The first receiving core receives the data to be sent.

[0008] In a possible implementation, writing the data to be sent into the first data channel includes:

[0009] The first sending core writes the data to be sent and a first transaction variable corresponding to the data to be sent into the first data channel. The transaction variable is used to identify the kernel task corresponding to the data to be sent.

[0010] After the first receiving core receives the data to be sent, it further includes:

[0011] The first receiving core determines a first kernel task corresponding to the data to be sent according to the first transaction variable, and transfers the data to be sent to the first kernel task.

[0012] In one possible implementation, the first receiving core receives the data to be sent, including:

[0013] The first receiving core competes for the first read atomic lock corresponding to the first data channel, where each data channel corresponds to a read atomic lock;

[0014] If the competition is successful, it receives the data to be sent, writes the data to be sent into the cache of the first receiving core, and releases the first read atomic lock;

[0015] If the competition fails, it waits to compete for the first read atomic lock again.

[0016] In one possible implementation, the transmission of the data to be sent to the first kernel task includes:

[0017] Return the data to be sent to the first call function corresponding to the first kernel task; where each kernel task corresponds to a call function.

[0018] In one possible implementation, the competition for the first read atomic lock corresponding to the first data channel includes:

[0019] Swap in variable 1 to the first read atomic lock, where the initial value of the first read atomic lock is 0;

[0020] If variable 0 is swapped back, it indicates that the competition is successful; if variable 1 is swapped back, it indicates that the competition fails;

[0021] The release of the first read atomic lock includes:

[0022] Swap in variable 0 to the first read atomic lock.

[0023] In one possible implementation, the mailbox module further includes a notification register; after writing the data to be sent into the first data channel, it further includes:

[0024] The first sending core sets the first notification register corresponding to the first data channel to the interrupt state; where each data channel corresponds to a first notification register;

[0025] Before the first receiving core receives the data to be sent, it further includes:

[0026] The first receiving core triggers an interrupt according to the interrupt state of the first notification register.

[0027] In one possible implementation, the transmission of the data to be sent to the first kernel task includes:

[0028] Obtain a transaction table, where the transaction table includes transaction items corresponding to each data channel, each data channel corresponds to at least one transaction item, and each transaction item includes a transaction variable and a callback function corresponding to the transaction variable;

[0029] According to the transaction table, determine the first callback function corresponding to the first transaction variable, and transmit the data to be sent to the first callback function.

[0030] In a possible implementation, the mailbox module further includes a status register; the step of writing the data to be sent into the first data channel includes:

[0031] The first sending core queries the status of the first status register corresponding to the first data channel. When the first status register is in an idle state, write the data to be sent into the first data channel, and set the first status register corresponding to the receiving core to a busy state; wherein, each data channel corresponds to a status register;

[0032] The step that the first receiving core receives the data to be sent includes:

[0033] The first receiving core receives the data to be sent, writes the data to be sent into the cache of the first receiving core, and sets the first status register to an idle state.

[0034] In a possible implementation, before writing the data to be sent into the first data channel, it further includes:

[0035] The first sending core contends for the first write atomic lock corresponding to the first data channel, wherein each data channel corresponds to a write atomic lock;

[0036] If the contention is successful, write the data to be sent into the first data channel, and release the first write atomic lock after the writing is completed;

[0037] If the contention fails, wait to contend for the first write atomic lock again.

[0038] In a possible implementation, the step that the first sending core contends for the first write atomic lock corresponding to the first data channel includes:

[0039] Swap in variable 1 to the first write atomic lock, wherein the initial value of the write atomic lock is 0;

[0040] If variable 0 is swapped back, it indicates that the contention is successful; if variable 1 is swapped back, it indicates that the contention fails;

[0041] The step of releasing the first write atomic lock includes:

[0042] Swap in variable 0 to the first write atomic lock.

[0043] In a possible implementation, writing the data to be sent into the first data channel includes:

[0044] The first sending core defines a first array in the cache and initializes the first array to 0;

[0045] Write the data to be sent into the first array; and write the first array into the first data channel.

[0046] On the other hand, the present application provides a multi-core processor system. The mailbox module of the multi-core processor system includes a data channel; wherein,

[0047] The first sending core determines a corresponding first data channel according to the first receiving core corresponding to the data to be sent, and writes the data to be sent into the first data channel; wherein each sending core corresponds to multiple simplex data channels, and the receiving cores corresponding to the multiple data channels are respectively multiple cores except the sending core;

[0048] The first receiving core receives the data to be sent.

[0049] In a possible implementation, the first sending core is specifically configured to:

[0050] Write the data to be sent and a first transaction variable corresponding to the data to be sent into the first data channel, where the transaction variable is used to identify the kernel task corresponding to the data to be sent;

[0051] The first receiving core is further configured to:

[0052] Determine a first kernel task corresponding to the data to be sent according to the first transaction variable, and transmit the data to be sent to the first kernel task.

[0053] In a possible implementation, the first receiving core is specifically configured to:

[0054] Compete for a first read atomic lock corresponding to the first data channel, where each data channel corresponds to a read atomic lock;

[0055] If the competition is successful, receive the data to be sent, write the data to be sent into the cache of the first receiving core, and release the first read atomic lock;

[0056] If the competition fails, wait to compete for the first read atomic lock again.

[0057] In a possible implementation, the first receiving core is further specifically configured to:

[0058] Return the data to be sent to the first call function corresponding to the first kernel task; each kernel task corresponds to a call function.

[0059] In a possible implementation, the first receiving core is further specifically configured to:

[0060] Swap in variable 1 to the first read atomic lock, where the initial value of the first read atomic lock is 0;

[0061] If variable 0 is swapped back, it indicates successful acquisition; if variable 1 is swapped back, it indicates failed acquisition;

[0062] Releasing the first read atomic lock includes:

[0063] Swap in variable 0 to the first read atomic lock.

[0064] In a possible implementation, the mailbox module further includes a notification register; the first sending core is further configured to:

[0065] Set the first notification register corresponding to the first data channel to the interrupt state; each data channel corresponds to a first notification register;

[0066] The first receiving core is further configured to:

[0067] The first receiving core triggers an interrupt according to the interrupt state of the first notification register.

[0068] In a possible implementation, the first receiving core is further specifically configured to:

[0069] Obtain a transaction table, where the transaction table includes transaction items corresponding to each data channel, each data channel corresponds to at least one transaction item, and each transaction item includes a transaction variable and a callback function corresponding to the transaction variable;

[0070] According to the transaction table, determine the first callback function corresponding to the first transaction variable, and transmit the data to be sent to the first callback function.

[0071] In a possible implementation, the mailbox module further includes a status register; the first sending core is further configured to:

[0072] Query the status of the first status register corresponding to the first data channel. When the first status register is in the idle state, write the data to be sent to the first data channel, and set the first status register corresponding to the receiving core to the busy state; each data channel corresponds to a status register;

[0073] The first receiving core is further configured to:

[0074] Receive the data to be sent, write the data to be sent into the cache of the first receiving core, and set the first status register to the idle state.

[0075] In a possible implementation, the first sending core is further configured to:

[0076] The first sending core competes for the first write atomic lock corresponding to the first data channel, where each data channel corresponds to a write atomic lock;

[0077] If the competition is successful, write the data to be sent into the first data channel, and release the first write atomic lock after the writing is completed;

[0078] If the competition fails, wait to compete for the first write atomic lock again.

[0079] In a possible implementation, the first sending core is further configured to:

[0080] Swap variable 1 into the first write atomic lock, where the initial value of the write atomic lock is 0;

[0081] If variable 0 is swapped back, it indicates that the competition is successful; if variable 1 is swapped back, it indicates that the competition fails;

[0082] The releasing of the first write atomic lock includes:

[0083] Swap variable 0 into the first write atomic lock.

[0084] In a possible implementation, the first sending core is further configured to:

[0085] The first sending core defines a first array in the cache and initializes the first array to 0;

[0086] Write the data to be sent into the first array; and write the first array into the first data channel.

[0087] In another aspect, the present application provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, they are used to implement the method described above.

[0088] In another aspect, the present application provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the method described above.

[0089] In the inter-core communication method, system, medium and product provided by this application, by setting multiple data channels, each data channel uniquely corresponds to a group of sending cores and receiving cores, and the sending cores transmit the data to be sent to the receiving cores through this data channel, realizing multi-channel point-to-point communication, reducing the coupling degree of inter-core communication, greatly reducing the competition of the cores for channel resources, and improving the competition efficiency; in addition, the data channels are set in the mailbox module of the system, without occupying the general memory of the system, so that it can support an increase in the data transmission volume and improve the data transmission efficiency. Therefore, the embodiments of this application can effectively improve the inter-core communication efficiency and further improve the overall system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0090] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0091] Figure 1 FIG. shows a schematic structural diagram of a multi-core processor system provided by an embodiment of this application;

[0092] Figure 2 FIG. shows a schematic structural diagram of a data channel unit provided by an embodiment of this application.

[0093] Figure 3 FIG. shows a schematic flowchart of an inter-core communication method provided by an embodiment of this application;

[0094] Figure 4 FIG. shows a schematic structural diagram of a mailbox module provided by an embodiment of this application;

[0095] Figure 5 FIG. shows a schematic flowchart of another inter-core communication method provided by an embodiment of this application;

[0096] Figure 6 FIG. shows a schematic flowchart of a synchronous inter-core communication method provided by an embodiment of this application;

[0097] Figure 7 FIG. shows a schematic flowchart of an asynchronous inter-core communication method provided by an embodiment of this application.

[0098] Through the above accompanying drawings, specific embodiments of this application have been shown, and there will be more detailed descriptions hereinafter. These drawings and text descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0099] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0100] The modules in the present application refer to functional modules or logical modules. It can be in software form and its functions are realized by a processor executing program code; it can also be in hardware form. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0101] A multi-core processor refers to a processor that integrates two or more complete independent processing cores (kernels) in one processor, aiming to improve the overall performance of the processor and accelerate calculations by executing multiple tasks in parallel. Inter-core communication is crucial in a multi-core processor system and is used to ensure data exchange and cooperation between multiple processing cores.

[0102] In the prior art, inter-core communication is often achieved through shared memory. Two or more cores can access the same shared memory space and exchange information and status by reading and writing the data in this space. However, the competition among multiple cores for the shared memory is relatively large, which will affect the system performance.

[0103] To solve the above technical problems, the embodiments of the present application set up multiple data channels, and each data channel uniquely corresponds to a group of sending cores and receiving cores, thereby realizing multi-channel point-to-point communication. The inter-core communication between different groups is independent, reducing the coupling degree of inter-core communication, and thus improving the competition efficiency of communication resources.

[0104] The technical solutions of the present application will be illustrated by specific embodiments below. These several specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0105] First, in combination with Figure 1 , the structure of the multi-core processor system provided by the embodiments of the present application will be described.

[0106] Figure 1 is a schematic structural diagram of the multi-core processor system provided by the present application. As Figure 1As shown in the figure, the multi-core processor system 10 includes a multi-core processor 11 and a mailbox module 12. The multi-core processor 11 and the mailbox module 12 can communicate with each other through a bus 13. The multi-core processor 11 includes multiple cores 111, which can communicate with each other. Each core 111 can be used as a sending core for sending data or a receiving core for receiving data; the mailbox module 12 includes a data channel unit 121 and a control unit 122.

[0107] Among them, the data channel unit 121 includes multiple data channels, and these multiple data channels are simplex data channels. Assuming that the number of cores 111 is n, when each core is used as a sending core, it corresponds to (n - 1) data channels. The receiving cores corresponding to these (n - 1) data channels are respectively (n - 1) cores 111 among the n cores 111 except this sending core. The data channel unit 121 altogether includes n*(n - 1) data channels. Figure 2 It is a schematic structural diagram of the data channel unit provided by this application. As Figure 2 shown, taking the multi-core processor 11 including 4 cores 111, namely processor core 1, processor core 2, processor core 3, and processor core 4 as an example, the data channel unit 121 includes 12 data channels. Among them, the sending core corresponding to data channel 1 is processor core 1, and the receiving core corresponding to data channel 1 is processor core 2; the sending core corresponding to data channel 2 is processor core 1, and the receiving core corresponding to data channel 2 is processor core 3; the sending core corresponding to data channel 3 is processor core 1, and the receiving core corresponding to data channel 3 is processor core 4, and so on, which will not be elaborated here.

[0108] Figure 3 It is a schematic flow diagram of the inter-core communication method provided by an embodiment of this application. The execution subject of this method is Figure 1 the multi-core processor system shown in the figure. As Figure 3 shown, the inter-core communication method provided by this embodiment may include:

[0109] S301. The first sending core determines a corresponding first data channel according to the first receiving core corresponding to the data to be sent, and writes the data to be sent into the first data channel; wherein, each sending core corresponds to multiple simplex data channels, and the receiving cores corresponding to these multiple data channels are respectively multiple cores except this sending core;

[0110] S302. The first receiving core receives the data to be sent.

[0111] In a specific implementation, each data channel uniquely corresponds to a set of a sending core and a receiving core. When the first sending core performs inter-core communication, it can first determine the multiple data channels corresponding to the first sending core, and among the multiple data channels, a first data channel, and the receiving core corresponding to the first data channel is the first receiving core. Combining Figure 2 As shown in the figure, assuming that the first sending core is processor core 2 and the first receiving core is processor core 3, it can be determined that the data channels corresponding to processor core 2 are data channel 4, data channel 5, and data channel 6, and the receiving cores corresponding to data channel 4, data channel 5, and data channel 6 are processor core 1, processor core 3, and processor core 4 respectively. Therefore, it can be determined that data channel 5 is the first data channel. The first sending core writes the data to be sent to the address of the first data channel, so that the first receiving core can read the data to be sent according to the address of the first data channel, and realize the reception of the data to be sent.

[0112] Exemplarily, the memory size of the data channel can be configured to be word-aligned, such as 16 words.

[0113] It can be understood that the data channel also needs to occupy memory space. However, different from the prior art, in the prior art, the shared memory needs to occupy the general memory of the multi-core processor system. To avoid affecting the system performance, the size of the shared memory is limited, resulting in a small amount of data for inter-core communication and low data transmission efficiency. In the embodiment of the present application, the data channel is located in the mailbox module and only occupies the memory of the existing mailbox module, which will not affect the system performance. Therefore, it can support a large memory occupancy of the data channel, effectively increase the data transmission volume, and improve the data transmission efficiency. Further, the multi-core competition for the shared memory has a high coupling degree, resulting in relatively low competition efficiency. The embodiment of the present application adopts multi-channel point-to-point communication, effectively reducing the inter-core communication coupling, thereby improving the competition efficiency.

[0114] In a possible implementation manner, before writing the data to be sent into the first data channel, it further includes:

[0115] The first sending core competes for the first write atomic lock corresponding to the first data channel, where each data channel corresponds to a write atomic lock;

[0116] If the competition is successful, the data to be sent is written into the first data channel, and the first write atomic lock is released after the writing is completed;

[0117] If the competition fails, wait to compete for the first write atomic lock again.

[0118] In a specific implementation, to ensure the atomicity of data writing, a write atomic lock can be set for each data channel. When data is transmitted through the first data channel, the first sender core contends for the first write atomic lock corresponding to the first data channel. If the contention is successful, the first write atomic lock is not locked, and the data to be sent can be written into the first data channel. After the writing is completed, the first write atomic lock is released, so that the next data writing can be performed. If the contention fails, the first write atomic lock is locked, and the previous data transmission is not completed, and it is necessary to wait to contend for the first write atomic lock again.

[0119] Exemplarily, the first sender core contending for the first write atomic lock corresponding to the first data channel includes:

[0120] Swap variable 1 into the first write atomic lock, where the initial value of the write atomic lock is 0;

[0121] If variable 0 is swapped back, it indicates that the contention is successful; if variable 1 is swapped back, it indicates that the contention fails;

[0122] Releasing the first write atomic lock includes:

[0123] Swap variable 0 into the first write atomic lock.

[0124] In a specific implementation, the first sender core can use an atomic exchange instruction to swap variables into the first write atomic lock to achieve the contention and release of the write atomic lock. The initial value of each write atomic lock is 0. Before writing the data to be sent into the first data channel, the first sender core first swaps variable 1 into the first write atomic lock. If variable 0 is swapped back, it indicates that the contention is successful, and the data to be sent is written into the first data channel. If variable 1 is swapped back, it indicates that the contention fails, and wait to contend again. After the data writing is completed, variable 0 is swapped into the first write atomic lock. The above operations only need to use atomic exchange instructions. Therefore, the multi-core processor only needs to support atomic exchange instructions and does not need to implement all atomic instructions, which helps to simplify the chip hardware design and reduce the production cost of tape-out, and effectively reduces the implementation cost of inter-core communication.

[0125] Based on the above embodiments, to further ensure the atomicity of the first receiver core reading data, the reading status of the data channel can be identified through a status register. Figure 4 This is a schematic structural diagram of the mailbox module provided by the embodiment of the present application. As Figure 4 shown, in a possible implementation, the control unit 122 of the mailbox module 12 includes a status register 1221; writing the data to be sent into the first data channel includes:

[0126] The first sending core queries the status of the first status register corresponding to the first data channel. When the first status register is in the idle state, it writes the data to be sent into the first data channel and sets the first status register corresponding to the receiving core to the busy state; each data channel corresponds to a status register.

[0127] The first receiving core receives the data to be sent, including:

[0128] The first receiving core receives the data to be sent, writes the data to be sent into the cache of the first receiving core, and sets the first status register to the idle state.

[0129] In a specific implementation, a corresponding status register can be set for each data channel. The first sending core queries the status of the first status register corresponding to the first data channel. When the first status register is in the idle state, it writes the data to be sent into the first data channel and sets the first status register corresponding to the receiving core to the busy state, indicating that the first data channel has been occupied; when the first status register is in the busy state, the first sending core will not overwrite the data in the current first data channel. The first receiving core receives the data to be sent, and after writing the data to be sent into the cache of the first receiving core, it completes the reception and storage of the data to be sent, and sets the first status register to the idle state, so that the first sending core can write data again. The atomicity of data transmission can be effectively guaranteed through the status register.

[0130] In a possible implementation manner, writing the data to be sent into the first data channel includes:

[0131] The first sending core defines a first array in the cache and initializes the first array to 0;

[0132] Write the data to be sent into the first array; and write the first array into the first data channel.

[0133] In a specific implementation, the first sending core can allocate a sending data buffer area in the cache of the first sending core for caching the data written into the first data channel. The memory size of the sending data buffer area can be the same as the size of the first data channel. Each time the data to be sent is obtained, a first array is defined in the sending data buffer area, and the first array is directly initialized to 0 when the first array is declared. Copy the data to be sent into the first array. In this way, only by writing the first array into the first data channel can the data to be sent be written into the first data channel. By caching the data to be sent first and then writing it into the first data channel, the clearing operation of the data channel can be reduced, and the data transmission efficiency can be effectively improved. It can be understood that for multiple data channels corresponding to the first sending core, there can be multiple sending data buffer areas.

[0134] In the embodiments of the present application, by setting multiple data channels, each data channel uniquely corresponds to a set of sending cores and receiving cores. The sending cores transmit the data to be sent to the receiving cores through the data channels, realizing multi-channel point-to-point communication, reducing the coupling degree of inter-core communication, greatly reducing the competition of the cores for channel resources, and improving the competition efficiency. Moreover, the data channels are set in the mailbox module of the system, without occupying the general memory of the system, so that it can support an increase in the data transmission volume and improve the data transmission efficiency. Therefore, the embodiments of the present application can effectively improve the inter-core communication efficiency and further improve the overall system performance.

[0135] Based on the above embodiments, the kernel tasks corresponding to the data to be written can be identified, so as to realize the transmission of multi-tasks to multi-tasks among multiple cores. Figure 5 It is a schematic flowchart of another inter-core communication method provided by the embodiments of the present application. The execution subject of this method is a multi-core processor system. As Figure 5 shown, this method may include:

[0136] S501. The first sending core determines the corresponding first data channel according to the first receiving core corresponding to the data to be sent;

[0137] S502. The first sending core writes the data to be sent and the first transaction variable corresponding to the data to be sent into the first data channel, and the transaction variable is used to identify the kernel task corresponding to the data to be sent;

[0138] S503. The first receiving core receives the data to be sent and the first transaction variable;

[0139] S504. The first receiving core determines the first kernel task corresponding to the data to be sent according to the first transaction variable, and transmits the data to be sent to the first kernel task.

[0140] In specific implementation, each processor core can execute multiple tasks concurrently or in parallel. For the data to be sent corresponding to the first kernel task, when the first sending core writes the data to be sent into the first data channel, it can also write the first transaction variable corresponding to the data to be sent into the first data channel. Thus, after the first receiving core receives the data to be sent and the first transaction variable, it can determine the first kernel task corresponding to the data to be sent according to the first transaction variable, so as to accurately transmit the data to be sent to the first kernel task, realizing multi-task communication and effectively improving the flexibility of inter-core communication.

[0141] In practical applications, the first receiving core can synchronously or asynchronously transmit the data to be sent to the first kernel task. Figure 6 It is a schematic flowchart of the synchronous inter-core communication method provided by the embodiments of the present application. The execution subject of this method is a multi-core processor system. As Figure 6 shown, this method may include:

[0142] S601. The first sending core determines a corresponding first data channel according to the first receiving core corresponding to the data to be sent.

[0143] S602. The first sending core attempts to acquire the first write atomic lock corresponding to the first data channel.

[0144] In a specific implementation, the write atomic lock can be set in the shared memory of the mailbox module. When the sending core executes an atomic exchange instruction, a signal is generated and transmitted through the bus for the mailbox module to identify. When multiple cores execute atomic exchange instructions simultaneously, the bus can ensure that the requests of multiple cores are executed through a queuing response method.

[0145] S603. If the first sending core successfully acquires the lock, when the first status register is in an idle state, it writes the data to be sent and the corresponding first transaction variable of the data to be sent into the first data channel; if the acquisition fails, it waits to acquire the first write atomic lock again.

[0146] Exemplarily, the first sending core can allocate a sending data buffer in the cache of the first sending core, and the memory size of the sending data buffer can be the same as the size of the first data channel. Among them, in order to improve the convenience of data transmission, the size of the first data channel and the data length of the first transaction variable can be aligned with the read and write of the bus. Taking the Advanced High-performance Bus (AHB) as an example, the read and write behaviors of the AHB bus have a word length. Therefore, the size of the first data channel and the data length of the first transaction variable can be aligned with the word. For example, the size of the first data channel is 16 words, the size of the sending data buffer is 16 words, and the data length of the first transaction variable is 1 word. Excluding the first transaction variable, the maximum length of the data to be sent that can be copied in the sending data buffer is 15 words. Each arbitration of the AHB bus takes 1 clock cycle, requesting the address of the first data channel takes 1 clock cycle, and writing 1 word to the address of the first data channel takes 1 clock cycle. Therefore, writing the data in the 16Words sending data buffer into the first data channel requires a total of (1 + 1 + 1) * 16 = 48 clock cycles.

[0147] In practical applications, the first transaction variable can be an integer data or a variable of other data types, and there is no restriction on this here.

[0148] S604. The first sending core sets the first status register corresponding to the receiving core to the busy state.

[0149] S605. The first sending core releases the first write atomic lock.

[0150] S606. The first receiving core attempts to acquire the first read atomic lock corresponding to the first data channel, where each data channel corresponds to a read atomic lock.

[0151] S607. If the first receiving core successfully acquires the lock, it receives the data to be sent and writes the data to be sent and the first transaction variable into the cache of the first receiving core. If the acquisition fails, it waits to acquire the first read atomic lock again.

[0152] In a specific implementation, the first receiving core can also allocate a receiving data buffer for caching the data to be sent and the first transaction variable received. The first receiving core defines a first array in the receiving data buffer and initializes the first array to 0 directly when declaring it. After reading data from the first data channel, the data to be sent and the first transaction variable are written into the first array. To improve the convenience of data transmission, the size of the first receiving core can also be the same as that of the memory of the first data channel. The number of clock cycles spent by the first receiving core to copy data to the receiving data buffer is the same as the number of clock cycles spent by the first sending core to copy cached data to the first data channel.

[0153] Exemplarily, acquiring the first read atomic lock corresponding to the first data channel includes:

[0154] Swapping in variable 1 to the first read atomic lock, where the initial value of the first read atomic lock is 0;

[0155] If variable 0 is swapped back, it indicates successful acquisition; if variable 1 is swapped back, it indicates failed acquisition;

[0156] Releasing the first read atomic lock includes:

[0157] Swapping in variable 0 to the first read atomic lock.

[0158] In a specific implementation, the read atomic lock can be set in the shared memory of the mailbox module. When the receiving core executes the atomic exchange instruction, a signal is generated and transmitted through the bus for the mailbox module to identify. When multiple cores execute the atomic exchange instruction simultaneously, the bus can ensure that the requests of multiple cores are executed through a queuing response method.

[0159] It can be understood that the principle of the read atomic lock is similar to that of the write atomic lock, which will not be elaborated here.

[0160] S608. The first receiving core returns the data to be sent to the first call function corresponding to the first kernel task; where each kernel task corresponds to a call function.

[0161] In a specific implementation, the first receiving core may determine a first calling function corresponding to a first kernel task according to a first transaction variable, and return the cached data to be sent and the first transaction variable to the first calling function, so as to transmit the data to be sent to the first kernel task. Wherein, the first receiving core may also return a part of the data to be sent according to the data length to be read by the first calling function, and no limitation is imposed thereon herein.

[0162] S609. The first receiving core sets the first status register to the idle state.

[0163] It should be noted that in practical applications, the execution order of step S508 and step 509 may be interchanged.

[0164] S610. The first receiving core releases the first read atomic lock.

[0165] In a specific implementation, the first receiving core may release the read atomic lock by swapping in variable 0 through an atomic exchange instruction, indicating that the data reading this time has been completed. The read atomic lock can ensure mutually exclusive access of kernel multitasks during channel reading, so as to achieve unique access of kernel multitasks to the hardware channel.

[0166] In the embodiment of the present application, the atomicity of the data received by the first receiving core is ensured through the read atomic lock, and the first receiving core returns the received data to the first calling function corresponding to the first kernel task, realizing synchronous transmission of the data to be sent.

[0167] As Figure 4 shown, the control unit 122 may further include a notification register 1222. Figure 7 It is a schematic flowchart of an asynchronous inter-core communication method provided by an embodiment of the present application. The execution subject of this method is a multi-core processor system. As Figure 7 shown, this method may include:

[0168] S701. The first sending core determines a corresponding first data channel according to the first receiving core corresponding to the data to be sent.

[0169] S702. The first sending core contends for the first write atomic lock corresponding to the first data channel.

[0170] In a specific implementation, the write atomic lock may be set in the shared memory of the mailbox module. When the sending core executes an atomic exchange instruction, a signal is generated and transmitted through the bus for the mailbox module to identify. When multiple cores execute atomic exchange instructions simultaneously, the bus can ensure that the requests of multiple cores are executed through a queuing response method.

[0171] If the first sending core successfully acquires the lock, when the first status register is in the idle state, it writes the data to be sent and the first transaction variable corresponding to the data to be sent into the first data channel; if the acquisition fails, it waits to acquire the first write atomic lock again.

[0172] In specific implementation, to facilitate the first receiving core to read the first transaction variable, the first transaction variable can be written to the head of the first data channel. For example, assuming the first data channel includes 16 words, the first transaction variable can be written to the first word of the first data channel.

[0173] S704. The first sending core sets the first status register corresponding to the receiving core to the busy state.

[0174] S705. The first sending core sets the first notification register corresponding to the first data channel to the interrupt state; each data channel corresponds to a first notification register.

[0175] In specific implementation, the first receiving core can trigger an interrupt of the first receiving core through the first notification register, so that the first receiving core starts to receive the data sent by the first sending core. For example, the first sending core sets the first notification register to 1, thus setting the first notification register to the interrupt state.

[0176] S706. The first sending core releases the first write atomic lock.

[0177] S707. The first receiving core triggers an interrupt according to the interrupt state of the first notification register.

[0178] In specific implementation, for the first data channel, the first receiving core has pre-registered an interrupt handling function in the interrupt vector table. After the first notification register becomes the interrupt state, the interrupt handling function jumps to the position of the interrupt vector table to execute the interrupt handling function, thus triggering the interrupt.

[0179] It should be noted that in practical applications, the execution order of steps S706 and S707 can be exchanged.

[0180] S708. The first receiving core receives the data to be sent and writes the data to be sent and the first transaction variable into the cache of the first receiving core.

[0181] S709. The first receiving core obtains the transaction table. The transaction table includes transaction items corresponding to each data channel. Each data channel corresponds to at least one transaction item. Each transaction item includes a transaction variable and a callback function corresponding to the transaction variable; and, according to the transaction table, determines the first callback function corresponding to the first transaction variable.

[0182] In a specific implementation, a multi-core processor separately allocates a shared memory space to maintain a transaction table, which includes transaction items corresponding to each data channel, and each core can access the transaction table. Among them, each data channel corresponds to at least one transaction item, and each transaction item includes a transaction variable, a callback function corresponding to the transaction variable, callback function parameters, and a transaction registration status. The transaction variables in different transaction items are different, and each transaction variable uniquely corresponds to a core task. Exemplarily, the transaction registration status may include registered and unregistered. Therefore, the first receiving core can index the first callback function corresponding to the first transaction variable according to the transaction table.

[0183] S710. The first receiving core transfers the data to be sent to the first callback function.

[0184] In a specific implementation, the first receiving core calls a read function in the first callback function to read the cached data in the received data buffer, so as to transfer the data to be sent to the first callback function. When the first callback function is called by the first core task, the data to be sent is transferred to the first core task.

[0185] S711. The first receiving core sets the first status register to the idle state.

[0186] It should be noted that in practical applications, step S711 can be executed before step S710 or step S709.

[0187] S712. The first receiving core exits the interrupt state of the first notification register to end the interrupt.

[0188] In a specific implementation, after the first receiving core completes the reception and transmission of data, it can exit the interrupt and resume task execution. For example, the first sending core sets the first notification register to 0, so that the first notification register exits the interrupt state.

[0189] As Figure 1 、 Figure 2 and Figure 4 shown, an embodiment of the present application further provides a multi-core processor system, and the mailbox module of the multi-core processor system includes a data channel; among them,

[0190] The first sending core determines a corresponding first data channel according to the first receiving core corresponding to the data to be sent, and writes the data to be sent into the first data channel; among them, each sending core corresponds to multiple simplex data channels, and the receiving cores corresponding to the multiple data channels are respectively multiple cores except the sending core;

[0191] The first receiving core receives the data to be sent.

[0192] In a possible implementation manner, the first sending core is specifically used for:

[0193] Write the data to be sent and the first transaction variable corresponding to the data to be sent into the first data channel, where the transaction variable is used to identify the kernel task corresponding to the data to be sent;

[0194] The first receiving core is further configured to:

[0195] Determine the first kernel task corresponding to the data to be sent according to the first transaction variable, and transmit the data to be sent to the first kernel task.

[0196] In a possible implementation, the first receiving core is specifically configured to:

[0197] Contend for the first read atomic lock corresponding to the first data channel, where each data channel corresponds to a read atomic lock;

[0198] If the contention is successful, receive the data to be sent, write the data to be sent into the cache of the first receiving core, and release the first read atomic lock;

[0199] If the contention fails, wait to contend for the first read atomic lock again.

[0200] In a possible implementation, the first receiving core is further specifically configured to:

[0201] Return the data to be sent to the first call function corresponding to the first kernel task; where each kernel task corresponds to a call function.

[0202] In a possible implementation, the first receiving core is further specifically configured to:

[0203] Swap in variable 1 to the first read atomic lock, where the initial value of the first read atomic lock is 0;

[0204] If variable 0 is swapped back, it indicates that the contention is successful; if variable 1 is swapped back, it indicates that the contention fails;

[0205] The releasing of the first read atomic lock includes:

[0206] Swap in variable 0 to the first read atomic lock.

[0207] In a possible implementation, the mailbox module further includes a notification register; the first sending core is further configured to:

[0208] Set the first notification register corresponding to the first data channel to the interrupt state; where each data channel corresponds to a first notification register;

[0209] The first receiving core is further configured to:

[0210] The first receiving core triggers an interrupt according to the interrupt status of the first notification register.

[0211] In a possible implementation, the first receiving core is further specifically configured to:

[0212] Obtain a transaction table, where the transaction table includes transaction items corresponding to each data channel, each data channel corresponds to at least one transaction item, and each transaction item includes a transaction variable and a callback function corresponding to the transaction variable;

[0213] Determine a first callback function corresponding to the first transaction variable according to the transaction table, and transmit the data to be sent to the first callback function.

[0214] In a possible implementation, the mailbox module further includes a status register; the first sending core is further configured to:

[0215] Query the status of the first status register corresponding to the first data channel. When the first status register is in an idle state, write the data to be sent into the first data channel, and set the first status register corresponding to the receiving core to a busy state; where each data channel corresponds to a status register;

[0216] The first receiving core is further configured to:

[0217] Receive the data to be sent, write the data to be sent into the cache of the first receiving core, and set the first status register to an idle state.

[0218] In a possible implementation, the first sending core is further configured to:

[0219] The first sending core contends for a first write atomic lock corresponding to the first data channel, where each data channel corresponds to a write atomic lock;

[0220] If the contention is successful, write the data to be sent into the first data channel, and release the first write atomic lock after the writing is completed;

[0221] If the contention fails, wait to contend for the first write atomic lock again.

[0222] In a possible implementation, the first sending core is further configured to:

[0223] Swap in variable 1 to the first write atomic lock, where the initial value of the write atomic lock is 0;

[0224] If variable 0 is swapped back, it indicates that the contention is successful; if variable 1 is swapped back, it indicates that the contention fails;

[0225] Releasing the first write atomic lock includes:

[0226] Swapping variable 0 into the first write atomic lock.

[0227] In a possible implementation, the first sending core is further configured to:

[0228] Define a first array in the cache in the first sending core and initialize the first array to 0;

[0229] Write the data to be sent into the first array; and write the first array into the first data channel.

[0230] In a specific implementation, the multi-core processor system may further include a memory. The multi-core processor and the memory can communicate with each other through a bus. The communication interface can be used for information transmission. The multi-core processor can call the logical instructions in the memory to execute the methods in the above embodiments.

[0231] In addition, when the logical instructions in the above memory are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.

[0232] As a computer-readable storage medium, the memory can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the methods in the embodiments of the present disclosure. The multi-core processor executes functional applications and data processing by running the software programs, instructions, and modules stored in the memory, that is, implements the methods in the above method embodiments.

[0233] The memory may include a program storage area and a data storage area. Among them, the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory may include high-speed random access memory and may also include non-volatile memory.

[0234] It should be noted that the multi-core processor system provided in the embodiments of the present application is used to execute the inter-core communication method as described above, which will not be elaborated here.

[0235] The embodiments of the present application also provide a non-temporary computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method as described in the foregoing embodiments.

[0236] The embodiments of the present application also provide a computer program product, including a computer program. When the computer program is executed by a processor, it implements the method as described in the foregoing embodiments.

[0237] Other embodiments of the present application will be readily apparent to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0238] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A method for inter-core communication, characterized in that: Applied to a multi-core processor system, the mailbox module of the multi-core processor system includes a data channel; the method includes: The first sending core determines the corresponding first data channel according to the first receiving core corresponding to the data to be sent, and writes the data to be sent into the first data channel; wherein each sending core corresponds to a plurality of simplex data channels, and the receiving cores corresponding to the plurality of data channels are respectively a plurality of cores other than the sending core; The first receiving core receives the data to be sent.

2. The method according to claim 1, characterized in that The step of writing the to-be-sent data into the first data channel comprises: The first sending core writes the data to be sent and a first transaction variable corresponding to the data to be sent into the first data channel, wherein the transaction variable is used to identify the kernel task corresponding to the data to be sent; After the first receiving core receives the data to be sent, the method further includes: The first receiving core determines a first kernel task corresponding to the data to be sent according to the first transaction variable, and transmits the data to be sent to the first kernel task.

3. The method according to claim 2, characterized in that The first receiving core receives the data to be sent, including: The first receiving core strives for a first read atomic lock corresponding to the first data channel, wherein each data channel corresponds to a read atomic lock; If the acquisition succeeds, the data to be sent is received, the data to be sent is written into the cache of the first receiving core, and the first read atomic lock is released; If the acquisition fails, wait for acquiring the first read atomic lock again.

4. The method according to claim 3, characterized in that The task of transmitting the to-be-sent data to the first kernel includes: The data to be sent is returned to a first calling function corresponding to the first kernel task; wherein each kernel task corresponds to a calling function.

5. The method according to claim 3, characterized in that: The obtaining of the first read atomic lock corresponding to the first data channel includes: Swapping variable 1 into the first read atomic lock, wherein the initial value of the first read atomic lock is 0; If the variable is changed back to 0, it means the fight is successful; if the variable is changed back to 1, it means the fight is unsuccessful; The releasing the first read atomic lock comprises: The variable 0 is swapped into the first read atomic lock.

6. The method according to claim 2, characterized in that The mailbox module further includes a notification register; after the data to be sent is written into the first data channel, the module further includes: The first sending core sets the first notification register corresponding to the first data channel to an interrupt state; wherein each data channel corresponds to a first notification register; Before the first receiving core receives the data to be sent, the method further includes: The first receiving core triggers an interrupt according to an interrupt status of the first notification register.

7. The method according to claim 6, characterized in that The task of transmitting the to-be-sent data to the first kernel includes: Obtain a transaction table, where the transaction table includes transaction items corresponding to each data channel, each data channel corresponds to at least one transaction item, and each transaction item includes a transaction variable and a callback function corresponding to the transaction variable; According to the transaction table, a first callback function corresponding to the first transaction variable is determined, and the data to be sent is transmitted to the first callback function.

8. The method according to claim 1, characterized in that The mailbox module also includes a status register; and writing the data to be sent into the first data channel includes: The first sending core queries the state of the first status register corresponding to the first data channel, and when the first status register is in an idle state, writes the data to be sent into the first data channel, and sets the first status register corresponding to the receiving core to a busy state; wherein each data channel corresponds to a status register; The first receiving core receives the data to be sent, including: The first receiving core receives the data to be sent, writes the data to be sent into a cache of the first receiving core, and sets the first status register to an idle state.

9. The method according to claim 1, characterized in that: Before writing the data to be sent into the first data channel, the method further includes: The first sending core strives for a first write atomic lock corresponding to the first data channel, wherein each data channel corresponds to one write atomic lock; If the acquisition is successful, the data to be sent is written into the first data channel, and the first write atomic lock is released after the writing is completed; If the acquisition fails, wait for acquiring the first write atomic lock again.

10. The method according to claim 9, characterized in that The first sending core strives for a first write atomic lock corresponding to the first data channel, including: Swapping variable 1 into the first write atomic lock, wherein the initial value of the write atomic lock is 0; If the variable is changed back to 0, it means the fight is successful; if the variable is changed back to 1, it means the fight is unsuccessful; The releasing the first write atomic lock comprises: The variable 0 is swapped into the first write atomic lock.

11. The method according to any one of claims 1 to 10, characterized in that: The step of writing the to-be-sent data into the first data channel comprises: The first sending core defines a first array in a cache and initializes the first array to 0; writing the data to be sent into the first array; and writing the first array into the first data channel.

12. A multi-core processor system, wherein a mailbox module of the multi-core processor system includes a data channel; wherein: The first sending core determines the corresponding first data channel according to the first receiving core corresponding to the data to be sent, and writes the data to be sent into the first data channel; wherein each sending core corresponds to a plurality of simplex data channels, and the receiving cores corresponding to the plurality of data channels are respectively a plurality of cores other than the sending core; The first receiving core receives the data to be sent.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 11 when executed by a processor.

14. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 11 when being executed by a processor.

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