Method for running DSP program based on FPGA single-port RAM space

Abstract

The invention relates to a method for running a DSP (Digital Signal Processor) program based on a single-port RAM (Random Access Memory) space of an FPGA (Field Programmable Gate Array), an IP (Internet Protocol) core generator in the FPGA is used for generating a 256KB RAM space, and a DSP is connected with the RAM block through an external interface EMIF (External Memory Interface) bus and is used for storing and reading DSP program data. And in the DSP program, the specified DSP program is stored in the external storage space of the DSP through the # P CODESECTION pseudo instruction, and the specified data is stored in the external storage space of the DSP through the # P DATASECTION pseudo instruction, for example, the storage space is defined as an FPGA RAM (Field Programmable Gate Array Random Access Memory). And meanwhile, a storage area MEMORY section and a space mapping SECTION section are modified in a linker configuration CMD file of DSP software engineering, so that a defined FPGA RAM space can be mapped into an FPGA RAM entity, and data required by a program operated by the DSP is stored in a 256KB RAMZ defined by the FPGA.

Description

Technical Field

[0001] The present invention belongs to the technical field of data processing, and particularly relates to a method for running a DSP program based on the space of a single-port RAM of an FPGA. Background Art

[0002] Currently, the hardware architectures for system calculation in most strapdown inertial navigation devices are based on DSP plus FPGA. The FPGA is mainly used for data synchronous acquisition. The DSP reads the data collected by the FPGA and uses various algorithmic schemes to implement the calculation of inertial navigation quantities. With the development of inertial navigation devices, in order to achieve higher-precision navigation calculation, the calculation scheme algorithms are becoming increasingly complex, the parameters to be defined are increasing, and the external interface protocols are becoming increasingly rich, resulting in an increasing memory space occupied by the DSP program. Usually, the solution is to expand a piece of SDRAM or DDR outside the DSP as the running space of the DSP, which requires changing the original hardware design and increasing the additional design cost. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art and propose a method for running a DSP program based on the space of a single-port RAM of an FPGA, which can effectively solve the problem of insufficient memory space of the DSP program due to complex algorithms, excessive parameters, and complicated interface protocols, and can be applied to various FPGA plus DSP strapdown inertial navigation calculation hardware architecture schemes.

[0004] The present invention solves its technical problems by adopting the following technical solutions:

[0005] A method for running a DSP program based on the space of a single-port RAM of an FPGA includes the following steps:

[0006] Step 1: Generate a single-port RAM soft core through the IP core generator of the FPGA;

[0007] Step 2: The DSP is hardware-connected to the RAM core generated by the FPGA through the external bus interface and uses the DSP EMIF bus, and the DSP EMIF bus is defined;

[0008] Step 3: Macro-definition is performed on the functions and data in the DSP program to implement the running of the DSP program in the RAM space.

[0009] Moreover, in Step 1, the clk clock of the single-port RAM soft core is set to 100Mhz, reaching the working clock frequency of a general SDRAM. The data input datain and output dataout are 16 bits, the address bit addra is 17 bits, and the space size of the RAM core is 256K bytes.

[0010] Moreover, in the step 2, the DSP EMIF bus includes an em_cs0 signal line, em_add[16:0] signal lines, an ema_awe signal line, em_data[15:0] signal lines, and an em_aoe signal line.

[0011] Moreover, the em_cs0 signal line is connected to the cea signal of the RAM core after being inverted inside the FPGA; the write enable ema_awe signal line of the DSP EMIF bus is connected to the wea signal of the RAM core after taking the falling edge inside the FPGA; the 17 address lines em_add[16:0] of the DSP EMIF are directly connected to the addra[16:0] of the RAM core; the 16-bit data lines em_data[15:0] of the DSP EMIF are input into the datain[15:0] of the RAM core at the moment of the falling edge of the write enable ema_awe; at the moment of the em_aoe read enable of the DSP, the data of the dataout[15:0] of the RAM core is placed on the data lines em_data[15:0] for the DSP to read the data.

[0012] Moreover, the step 3 includes the following steps:

[0013] Step 1: After defining functions in the DSP program, use the DSP instruction #program CODE_SECTION to specify these functions to a specific section.

[0014] Step 2: After defining data or arrays in the DSP program, use the DSP instruction #program DATA_SECTION to specify these data to a specific section.

[0015] Step 3: In the MEMORY section of the storage area in the linker configuration CMD file of the DSP software engineering, add a space corresponding to the FPGA RAM for the address space allocation. The starting address is 0X80000000, the address corresponds to the em_cs0 space of the DSP, and the length is 0X40000 (256KB).

[0016] Step 4: In the SECTION section of the space mapping in the linker configuration CMD file of the DSP software engineering, map the specified sections FPGA_RAM_FUN and FPGA_RAM_DATA sections to the address space of the FPGA_RAM.

[0017] Step 5: In the power-on working state of the DSP, through the DSP emulator and the Memory Browser tool of the development software, the data with a starting address of 0X80000000 and a length of 256KB in the DSP can be read out and saved as a data file.

[0018] Step 6: Use the data file read in Step 5 above to initialize the RAM through the FPGA RAM core generator. When the FPGA is powered on and starts up, a data file for the DSP to run in the RAM will be generated in the FPGA RAM.

[0019] The advantages and positive effects of the present invention are:

[0020] The present invention uses the IP core generator in the FPGA to generate a RAM space of 256KB in size. The DSP is connected to this RAM block through the external interface EMIF bus for storing and reading DSP program data. In the DSP program, the specified DSP program is placed in the external storage space of the DSP through the #pragma CODE_SECTION pseudo-instruction, and the specified data is placed in the external storage space of the DSP through the #pragma DATA_SECTION pseudo-instruction, such as defining this storage space as FPGA_RAM. At the same time, in the linker configuration CMD file of the DSP software engineering, the storage area MEMORY segment and the space mapping SECTION segment are modified so that the defined FPGA_RAM space can be mapped to the FPGARAM entity, thereby storing the data required for the DSP running program into the 256KB RAMZ defined by the FPGA. The present invention can effectively solve the problem of insufficient memory space of the DSP program due to complex algorithms, excessive parameters, and complex interface protocols, and can be applied to various FPGA plus DSP strapdown inertial navigation solution hardware architecture schemes. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a block diagram of the hardware connection between the DSP EMIF bus and the FPGARAM of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] The present invention will be further described in detail below with reference to the accompanying drawings.

[0023] A method for running a DSP program based on the single-port RAM space of an FPGA includes the following steps:

[0024] Step 1: Generate a single-port RAM soft core through the IP core generator of the FPGA.

[0025] Generate a single-port RAM soft core as shown in Figure 1 through the IP core generator of the FPGA. Its interface definition is shown in Table 1. The clk clock of the single-port RAM soft core is set to 100Mhz, reaching the working clock frequency of a general SDRAM. The data input datain and output dataout are 16 bits, the address bit addra is 17 bits, and the space size of the RAM core is 256K bytes.

[0026] Table 1 FPGA RAM Soft Core Interface Definition

[0027]

[0028] Step 2: The DSP makes a hardware connection with the RAM core generated by the FPGA through the external bus interface and uses the DSP EMIF bus, and defines the DSP EMIF bus.

[0029] The DSP makes a hardware connection with the RAM core generated by the FPGA through the external bus interface (EMIF bus). The definition of the EMIF bus is shown in Table 2.

[0030] Table 2 Definition of DSP EMIF Bus Interface

[0031]

[0032] The em_cs0 signal line of the DSP is connected to the cea signal of the RAM core after being inverted inside the FPGA.

[0033] The write enable ema_awe signal of the DSP is connected to the wea signal of the RAM core after taking the falling edge inside the FPGA.

[0034] The 17 address lines em_add[16:0] of the DSP are directly connected to the addra[16:0] of the RAM core.

[0035] The 16-bit data line em_data[15:0] of the DSP is input into the datain[15:0] of the RAM core at the moment of the falling edge of the write enable ema_awe; at the moment of the em_aoe read enable of the DSP, the data of the dataout[15:0] of the RAM core is placed on the data line em_data[15:0] for the DSP to read the data.

[0036] Step 3: Macro-defines the functions and data in the DSP program to implement running the DSP program in the RAM space.

[0037] Step 1: After defining functions in the DSP program, use the DSP instruction #program CODE_SECTION to specify these functions to a specific section.

[0038] void function1(void); void function2(void);...............(1)

[0039] #program CODE_SECTION(function1,".FPGA_RAM_FUN")...........(2)

[0040] #program CODE_SECTION(function2,".FPGA_RAM_FUN")...........(3)

[0041] Expression 1 defines two functions, function1 and function2. Expressions 2 and 3 use the #program CODE_SECTION directive to assign these two functions to the FPGA_RAM_FUN section.

[0042] Step 2: After defining data or arrays in the DSP program, use the DSP directive #program DATA_SECTION to assign this data to a specific section.

[0043] double data1

[100] ; double data2

[100] ;........................(4)

[0044] #program DATA_SECTION(data1,".FPGA_RAM_DATA")...........(5)

[0045] #program DATA_SECTION(data2,".FPGA_RAM_DATA")...........(6)

[0046] Expression 4 defines an array of type double, data1 and data2. Expressions 5 and 6 use the #program CODE_DATA directive to assign the arrays and data to the section defined by FPGA_RAM_DATA.

[0047] Step 3: In the MEMORY section of the linker configuration CMD file in the DSP software engineering, add a space corresponding to the FPGA RAM for the address space allocation. The starting address is 0X80000000, the address corresponds to the em_cs0 space of the DSP, and the length is 0X40000 (256KB).

[0048] MEMORY

[0049] { ................................

[0051] FPGA_RAM o = 0x80000000 l = 40000h..............................(7)

[0052] }

[0053] Step 4. In the space mapping SECTION segment of the linker configuration CMD file for the DSP software engineering, map the specified segments FPGA_RAM_FUN and FPGA_RAM_DATA to the address space of FPGA_RAM.

[0054] SECTION

[0055] { ................................

[0057] .FPGA_RAM_FUN > FPGA_RAM..............................(8)

[0058] .FPGA_RAM_DATA > FPGA_RAM..............................(9)

[0059] }

[0060] After the above settings, connect the target DSP chip with a DSP emulator and run the modified DSP program. The DSP chip can normally read the data collected by the FPGA and perform system calculations. The two defined functions function1 and function2 and the arrays data1 and data2 function properly. At the same time, through the Memory Browser tool of the DSP development software, it can be seen that the external memory space with the starting address of 0x800000000 for the DSP is defined as the function segment of FPGA_RAM_FUN, and the data segment corresponding to FPGA_RAM_DATA is after the function segment. Read out the data with the starting address of 0x800000000 and a length of 256KB from the DSP storage space, and at the same time read out 256KB of data from the RAM space of the FPGA. Compare the two data files, and it can be seen that the two data files are consistent. This shows that the specific functions function1 and function2 defined by the DSP, as well as the defined data data1 and data2, run in the RAM space of the FPGA.

[0061] Step 5. Through the FPGA RAM core generator, initialize the RAM with the read data file starting from the DSP starting address 0X80000000 and with a length of 256KB. When the FPGA is powered on and starts up, a data file for the DSP to run in the RAM will be generated in the FPGA RAM.

[0062] If the DSP uses a dedicated SDRAM or DDR as the program running memory, the boot program needs to copy the startup data solidified in the external FLASH to the DSP's own memory and SDRAM or DDR at the same time when the DSP starts running. This requires more modifications to the boot program, such as initializing SDRAM in the boot program and copying data from the specified location of FLASH to SDRAM or DDR. By initializing the FPGA RAM, there is no need to modify the DSP's boot program, and there is no need to save the initialized RAM data to the external FLASH, which simplifies the modification of DSP files and reduces the difficulty of program transplantation.

[0063] According to the above method of running DSP program based on FPGA single-port RAM space, the main solving functions and interface functions of DSP in the solving board of inertial navigation equipment are defined in FPGA RAM according to the above method for running. After long-term high and low temperature and dynamic test assessment, the system solving can run normally and the output accuracy is not reduced. Therefore, it is confirmed that this solution is stable and reliable, and can effectively solve the problem of insufficient memory space of DSP program due to complex algorithms, too many parameters and complicated interface protocols.

[0064] It should be emphasized that the embodiments described in the present invention are illustrative rather than restrictive. Therefore, the present invention includes but is not limited to the embodiments described in the specific implementation manner. Any other implementation manners derived by those skilled in the art based on the technical solution of the present invention also fall within the scope of protection of the present invention.

Claims

1. A method for running a DSP program based on a single-port RAM space of an FPGA, characterized in that: The following steps are involved: Step 1: Generate a single-port RAM soft core through the FPGA IP core generator; Step 2, the DSP uses the DSP EMIF bus to establish a hardware connection with the RAM core generated by the FPGA through the external bus interface, and defines the DSP EMIF bus; Step 3: Define macros for functions and data in the DSP program to run the DSP program in RAM space.

2. The method for running a DSP program based on a FPGA single-port RAM space according to claim 1, characterized in that: In the step 1, the clk clock of the single-port RAM soft core is set to 100Mhz, reaching the working clock frequency of the general SDRAM, the data input datain and the output dataout are 16 bits, the address bit addra is 17 bits, and the space size of the RAM core is 256K bytes.

3. The method for running a DSP program based on a FPGA single-port RAM space according to claim 1, characterized in that: In the step 2, the DSP EMIF bus includes an em_cs0 signal line, an em_add[16:0] signal line, an ema_awe signal line, an em_data[15:0] signal line and an em_aoe signal line.

4. The method for running a DSP program based on a FPGA single-port RAM space according to claim 3, characterized in that: The em_cs0 signal line is connected to the cea signal of the RAM core after being inverted inside the FPGA; the write enable ema_awe signal line of the DSP EMIF bus is connected to the wea signal of the RAM core after taking the falling edge inside the FPGA; the 17 address lines em_add[16:0] of the DSP EMIF are directly connected to the addra[16:0] of the RAM core; the 16-bit data line em_data[15:0] of the DSP EMIF is input into the datain[15:0] of the RAM core at the falling edge of the write enable ema_awe; at the DSP's em_aoe read enable moment, the dataout[15:0] of the RAM core is placed on the data line em_data[15:0] to allow the DSP to read the data.

5. The method for running a DSP program based on a FPGA single-port RAM space according to claim 1, characterized in that: The step 3 comprises the following steps: Step 1. After defining the functions in the DSP program, use the DSP instruction #program CODE_SECTION to assign these functions to specific segments; Step 2: After defining data or arrays in the DSP program, use the DSP instruction #program DATA_SECTION to assign these data to a specific segment; Step 3. In the storage area MEMORY segment in the linker configuration CMD file of the DSP software project, add a space corresponding to the FPGA RAM for address space allocation, with a starting address of 0X80000000, an address corresponding to the DSP's em_cs0 space, and a length of 0X40000 (256KB); Step 4: In the space mapping SECTION section of the linker configuration CMD file of the DSP software project, map the specified sections FPGA_RAM_FUN and FPGA_RAM_DATA to the address space of FPGA_RAM; Step 5, when the DSP is powered on, read out the data with a starting address of 0X80000000 and a length of 256KB in the DSP through the DSP simulator and the Memory Browser tool of the development software, and save it as a data file; Step 6: Initialize the RAM using the data file read out in step 5 through the FPGA RAM core generator. When the FPGA is powered on, a data file for the DSP to run in the RAM will be generated in the FPGA RAM.

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