A Memristive In-Memory Logic Synthesis Method and System Driven by a Multi-Logic Function Set

Abstract

The present invention discloses a memristor-based in-memory logic synthesis method and system driven by multiple logic function sets. The present invention includes converting the input original complex computing function into a synthesized netlist composed of simple logic functions; introducing composite logic functions to combine the mergeable simple logic functions in the synthesized netlist into composite logic functions; mapping the new netlist containing composite logic functions; statistically analyzing the performance indicators in the synthesis mapping process, and by comparing the performance indicators of the netlist results obtained by using different state logic function sets for the same complex computing function, selecting the netlist result with the optimal corresponding performance indicator according to the application scenario requirements as the finally output netlist result. The purpose of the present invention is to synthesize different structures of netlists using multiple simple logic function sets, optimize and improve the in-memory computing efficiency by merging the logic functions in the synthesized netlist, and obtain mapping results adapted to different scenario requirements by different selections of the results.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital circuits, and particularly relates to a memristive in-memory logic synthesis method and system driven by multiple logic function sets. Background Art

[0002] In the post-Moore era, traditional processor chips are constrained by the problems of insufficient computing power and energy efficiency, which is particularly evident when executing data-intensive tasks. This is because the traditional von Neumann architecture separates storage from computing, with the storage unit and the computing unit being independent of each other. The continuous data transfer between the storage unit and the computing unit has become the main bottleneck for improving computer performance. The in-memory computing architecture, by bringing the computing unit and the storage unit as close as possible, is a technology that is expected to break through the "memory wall" and "power wall" in traditional von Neumann systems and can support data-intensive and edge computing applications that require high energy efficiency.

[0003] As a non-volatile storage medium, the memristor provides fine-grained support for the implementation of the in-memory computing architecture with its inherent logic-storage fusion characteristics. The state logic gate composed of memristors can map logic 0 and 1 to the high-resistance state and low-resistance state of the memristor and realize in-situ logical calculation of stored data by relying on the conditional switching of the device resistance state. By combining non-volatility and conditional transition characteristics, the memristor-based state logic circuit (where both logical inputs and outputs are represented by non-volatile resistance states) supports true in-memory computing at the architecture level.

[0004] Figure 1 Shows an example of a state logic circuit that adopts a PMR structure ("parallel memristor + series resistor"), which consists of three parallel bipolar memristors (A, B, and C) and a series resistor (R S ). By applying an appropriate voltage to the non-common end of the memristor, the circuit can be triggered to perform the expected logical operation.

[0005] Table 1 shows the truth table of the NOR logic, which is Figure 1 one of the logical functions that the circuit can implement. If the high-resistance state (HRS) and the low-resistance state (LRS) are respectively mapped to logic "0" and logic "1", as long as the initial resistance of C is set to HRS ("0"), the logical function is the mapping between the final resistance of C and the resistances of the two memristors A and B.

[0006] Table 1: Figure 1 Truth table of the NOR logic of the shown state logic circuit

[0007] .

[0008] In fact, if the initial resistance of C is regarded as a third logic input instead of a fixed 0 (HRS), this circuit can also implement the compound logic function ONOR (~(A + B)+C), as shown in Table 2. For convenience, the circuit that implements the NOR function is called a simple gate (where the logic input and output are in different devices), and the circuit that implements the ONOR function is called a compound gate (where the logic output is in the same device as one of the logic inputs).

[0009] Table 2: Figure 1 Compound logic functions implemented by the state logic circuit shown

[0010]

[0011] In Table 2, A, B, and C are inputs, and C’ is the output of the compound logic function ONOR (~(A + B)+C).

[0012] However, a single state logic gate can only perform simple single-step logic calculations. To perform complex calculations in a memristor based crossbar array (MCBA), multiple state logic gates need to be configured, as shown in (a) of Figure 2 For example, the simple state logic gate Gate1 needs to configure a state logic gate with two inputs and one output in the MCBA. V R1 represents the control voltage applied to the input device configured for the simple state logic gate Gate1, and V W1 represents the control voltage applied to the output device configured for the simple state logic gate Gate1; the compound state logic gate Gate2 needs to configure a state logic gate with two inputs and one input / output in the MCBA. V R2 represents the control voltage applied to the input device configured for the compound state logic gate Gate2, and V W2 represents the control voltage applied to the output device configured for the compound state logic gate Gate2; WL is the word line. At the same time, the state logic gates need to be logically cascaded so that the calculation results can be continuously passed backward, as shown in (b) of Figure 2 where a - c are the state logic gates configured for the simple state logic gate Gate1 in the MCBA, and d and e are the state logic gates configured for the compound state logic gate Gate2 in the MCBA. Therefore, before the state logic calculation system performs a specific operation, the sequence of state logic gates to be executed must first be determined. This requires the support of the state logic synthesis process.

[0013] In recent years, a variety of state logic synthesis processes have been developed to automatically find an optimized cascading sequence of state logic gates to implement complex logic functions in MCBA. With CMOS-oriented logic synthesis tools, complex logic functions can be decomposed into logic functions represented by state logic gates without considering the constraints of MCBA. Then, a mapping process is developed to determine the final execution sequence and location of state logic gates in MCBA while considering optimization objectives and array constraints. Under this framework, a variety of state logic synthesis works related to different mapping modes and constraints have been developed, such as {SIMPLE SAID} (targeting the entire array with the goal of delay optimization), CONTRA (targeting the entire array with the goals of delay and area optimization), and {SIMPLER, X-MAGIC, LOSSS} (targeting a single row / column in the array with the goals of delay and area optimization).

[0014] The state logic computing system eliminates data movement during the computing process, but the spatio-temporal cascading of state logic gates makes it difficult for the state logic circuit itself to outperform the spatially cascaded CMOS combinational logic circuit in terms of execution time, thus weakening the benefits brought by in-memory computing. Although it has been verified that this weakness can be compensated by parallelly executing multiple computing processes in MCBA, reducing the cascading steps of state logic gates for implementing a single computing instance is very important for improving the overall system performance and worthy of in-depth study.

[0015] There are two common drawbacks in the current state logic synthesis processes: 1) Most synthesis processes only use a single set of functionally complete state logic gates, which contains a few simple gates (such as {NOR, NOT} or {IMP, NOT}), while compound gates and gates with other logic functions are not fully utilized. Although the two works of X-MAGIC and LOSSS utilize compound gates, the types of their logic functions are still limited to a small range. Introducing more state logic gate functions is expected to further reduce the number of gates and thus reduce the cascading steps. 2) The capabilities of CMOS-oriented logic synthesis tools have not been fully utilized. In most current CMOS-oriented logic synthesis tools (such as Design Compiler and ABC, etc.), the default optimization objective is the delay of the critical path, which is different from the desired high-timeliness (equivalent to reducing the number of gates) optimization objective in state logic synthesis. In addition, the core optimization algorithms of these CMOS-oriented logic synthesis tools are all heuristic and usually cannot obtain the global optimal solution. Therefore, finding some strategies to better utilize CMOS-oriented synthesis tools to provide better results for the functional decomposition of state logic is of great significance for improving time efficiency. Summary of the Invention

[0016] Technical problems to be solved by the present invention: Aiming at the above problems of the prior art, a memristor in-memory logic synthesis method and system driven by multiple logic function sets are provided. The present invention aims to synthesize netlists with different structures by using multiple simple logic function sets, optimize and improve the in-memory computing efficiency by merging the logic functions in the synthesized netlist, and obtain mapping results adapted to different scenario requirements by different selections of the results.

[0017] To solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0018] A memristor in-memory logic synthesis method driven by multiple logic function sets includes the following steps:

[0019] S101. For the input complex computing function, construct multiple logic function sets by changing the number of simple logic functions used, use different simple logic function sets as the synthesis unit library, set their areas to the same value, and use the synthesis tool to transform the input original complex computing function into a synthesized netlist composed of simple logic functions with the minimum area as the goal.

[0020] S102. Introduce the COPY logic function and the composite logic function, find the combinable simple logic function combinations in the synthesized netlist and merge them into the corresponding composite logic functions, and adjust the netlist to make its logic function correct to obtain a new netlist containing composite logic functions; all the logic functions of the new netlist are the logic functions abstracted from the simple state logic gates and composite state logic gates verified on the given memristor storage array model, and the composite state logic gate is equivalent to the function combination of multiple simple state logic gates in terms of logic function.

[0021] S103. Map the new netlist containing composite logic functions, and continuously reduce the array scale of the memristor storage array during the mapping process until the mapping tool cannot be used to map the new netlist, so as to obtain the state logic gate execution sequence under the minimum array width; for the mapping results obtained from each logic function set, select the maximum value of the minimum array width to remap the complex computing function.

[0022] S104. Statistically analyze the performance indicators in the comprehensive mapping process, and select the corresponding netlist result with the optimal performance indicator as the finally output netlist result by comparing the performance indicators of the netlist results obtained by using different state logic function sets for the same complex computing function according to the application scenario requirements.

[0023] Optionally, step S101 includes:

[0024] S201. For the input complex computing function, under the condition of meeting the comprehensive tool limitations, construct multiple logical function sets by changing the number of simple logical functions used.

[0025] S202. Set the standard cell library of the comprehensive tool to each simple logical function set in turn, and set the area attribute value of each simple logical function to the same value, and set the maximum load capacitance to a preset extremely large value.

[0026] S203. Convert the cell library files containing different simple logical function sets into cell library files that can be used by the comprehensive tool, and add the cell library files that can be used by the comprehensive tool to the target library list and link library list to be used during the synthesis of the comprehensive tool through the configuration file.

[0027] S204. For each cell library containing different simple logical function sets, set the maximum delay in the synthesis constraints to a preset extremely large value, set the maximum area to 0, set the synthesis process to optimize for area, and start the iterative synthesis process of the comprehensive tool, so as to convert the input original complex computing function into a synthesized netlist composed of simple logical functions.

[0028] Optionally, step S102 includes:

[0029] S301. Obtain the merging situation of each simple logical function combination in the synthesized netlist. If the acquisition is successful, jump to step S302; otherwise, jump to step S303.

[0030] S302. Perform the following processing for the obtained merging situation: Search for simple logical function combinations that meet the preset merging conditions in the synthesized netlist. If the search is successful, merge the simple logical function combinations that meet the preset merging conditions into simple logical functions or composite logical functions with the same function, and adjust the netlist structure to ensure the correctness of the netlist function; If a circular dependency problem occurs during the merging process, record the position of the state logic gate with the circular dependency problem and determine whether it can be merged. If it is determined that it can be merged, record the position where the COPY gate is inserted. If it is determined that it cannot be merged, this merging will not be performed and the search will continue; If the input and output ports of the original netlist are about to be overwritten during the merging process, this merging will not be performed; Jump to step S301; The circular dependency problem refers to that the composite state logic gate obtained after merging needs to be the parent node that the overwritten gate executes last. When the execution of other parent nodes of the overwritten logic gate except the composite state logic gate requires the execution result of the composite state logic gate, an irreconcilable contradiction will occur, and no matter how it is executed, it will affect the correctness of the result.

[0031] S303. For the cyclic dependency problem existing in the merged netlist, according to the positions of the state logic gates with cyclic dependency problems recorded, a copy gate COPY is added between the covered gates and the composite state logic gates generated by the merging to back up the data of the gates that would originally be covered to avoid conflicts.

[0032] Optionally, before step S102, it also includes verifying the correctness of the logic functions of the state logic gates based on the given memristor storage array model: for the two types of state logic gates, namely simple state logic gates and composite state logic gates that need to be functionally verified, based on the given memristor simulation model, using circuit simulation tools, the external voltage of the state logic gate circuit is determined through theoretical analysis and experimental verification, and the correctness of the state logic gate function is verified. If the correctness verification of the state logic gate function passes, it means it can participate in the merging process and is stored for use in the subsequent synthesis process.

[0033] Optionally, step S103 includes:

[0034] S401. Set the array width of the memristor storage array, use a single row of the memristor storage array for mapping, divide the memristor cells in a row of the memristor storage array into two parts. One part of the memristor cells is the original input and does not need to be initialized, and the other memristor cells are intermediate nodes and outputs. The memristor cells are initialized to 0 and 1 respectively according to the ratio of the set gates to the reset gates in the simple state logic gates of the netlist: the ratio of the cells initialized to 1 is the result obtained by dividing the number of reset gates that need to be initialized to 1 in the post-processed netlist by the total number of simple state logic gates in the post-processed netlist. The number of cells initialized to 1 is the product of the ratio of the cells initialized to 1 and the total number of cells that need to be initialized. The number of cells initialized to 0 is the result of subtracting the number of cells initialized to 1 from the total number of cells that need to be initialized.

[0035] S402. Perform memristor cell mapping for state logic gates in a manner similar to topological sorting: All logical inputs are pre-given and already allocated memristor cells, serving as all leaf nodes of a directed acyclic graph. Use a traversal method to allocate memristor cells. Start allocating cells for nodes from the leaf nodes of the directed acyclic graph. In each round of traversal, the current node can only be allocated when all its child nodes have been allocated. In the next round of traversal, set the nodes allocated in this round as allocated nodes; if the current node is a set gate, allocate a memristor cell initialized to 0. If the current node is a reset gate, allocate a memristor cell initialized to 1. If there are not enough memristor cells of a certain type, re-initialize the cells. For memristor cells that are no longer needed for information, those originally initialized to 0 remain initialized to 0, and those initialized to 1 remain initialized to 1, and are added to the allocatable queue; if the current node is a composite state logic gate, it needs to be processed separately. It must be ensured that all parent nodes of the covered node have been allocated before this composite state logic gate node can be allocated to ensure that the composite state logic gate is the last one to execute among all parent nodes of the covered node. At the same time, the composite state logic gate can directly occupy the covered child nodes during mapping without allocating other memristor cells; continue traversing until all nodes are allocated. If the current array width can allocate all nodes, it is determined that the execution sequence of state logic gates under the minimum array width has been obtained, output the execution sequence of state logic gates within a single row of the memristor storage array, and jump to step S403; if the current array width cannot allocate all nodes, print a prompt for mapping errors, and end and exit.

[0036] S403. For the mapping results obtained for each state logic function set, select the maximum value of the minimum array width to re-map the complex calculation function.

[0037] Optionally, when counting the performance metrics in the comprehensive mapping process in step S104, the performance metrics in the comprehensive mapping process include counting the minimum array width, the number of operations, the delay at the minimum array width, and the delay after unifying the array width for each simple logic function set as a cell library.

[0038] Optionally, in step S104, by comparing the performance metrics of the netlist results obtained for the same complex calculation function using different logic function sets, and selecting the netlist result with the optimal performance metrics according to the application scenario requirements as the final output netlist result, including:

[0039] S501. Obtain the mapping result with the minimum delay, minimum area, and longest service life by comparing the performance metrics of the netlist results obtained using different logic function sets for the same complex computing function: When obtaining the mapping result with the minimum delay, keep the row width at a preset smaller value, compare the number of cycles required for mapping at the same array width to find the minimum value. If the results of multiple function sets are the same at this time, then compare the cycle results obtained by mapping at the minimum row width. If the minimum value is compared at this time, select the result of this set as the final result. If the minimum value still cannot be found, select the results with the same number of cycles as the final result; When obtaining the mapping result with the minimum area, directly compare the results of the minimum row width required for each netlist mapping, and select the one with the minimum row width as the final result. If there are multiple, then these multiple results are all optional; When obtaining the mapping result with the longest service life, represent the service life by the number of operations of the device, and select the result with the minimum number of required operations as the final result of the longest device life. Directly compare the number of operations required for each netlist mapping after merging processing, and select the one with the minimum number of required operations as the final result. If there are multiple, then these multiple results are all optional;

[0040] S502. According to the application scenario requirements, select the netlist result corresponding to this application scenario from the mapping results with the minimum delay, minimum area, and longest service life as the final output netlist result.

[0041] In addition, the present invention also provides a multi-logic-function-set-driven memristive in-memory logic synthesis system, including a microprocessor and a memory connected to each other, and the microprocessor is programmed or configured to execute the multi-logic-function-set-driven memristive in-memory logic synthesis method.

[0042] In addition, the present invention also provides a computer-readable storage medium, in which a computer program or instruction is stored, and the computer program or instruction is programmed or configured to execute the multi-logic-function-set-driven memristive in-memory logic synthesis method through a processor.

[0043] In addition, the present invention also provides a computer program product, including a computer program or instruction, and the computer program or instruction is programmed or configured to execute the multi-logic-function-set-driven memristive in-memory logic synthesis method through a processor.

[0044] Compared with the prior art, the present invention can mainly achieve the following beneficial effects: By constructing multiple state logic function sets, different types of simple function combinations are used for synthesis to obtain netlists with different structures. Utilizing the corresponding relationship between the logic functions of simple functions and composite functions, multiple simple state logic function combinations are merged into composite logic functions, and the problem of netlist correctness in the synthesis mapping process is solved, optimizing and improving the in-memory computing efficiency. At the same time, by selecting different results, mapping results adaptable to different scenario requirements can be obtained. Description of the Drawings

[0045] Figure 1 It is an example of a state logic circuit in the prior art.

[0046] Figure 2 It is a schematic diagram of the configuration and logic cascade of different state logic gates in the prior art MCBA.

[0047] Figure 3 It is a comprehensive mapping flowchart of the method in the embodiment of the present invention.

[0048] Figure 4 It is an example of the state logic gate circuit structure in the embodiment of the present invention. Among them, (a) is the circuit diagram of the COPY gate, NOT gate, ANOT gate, and IMP gate; (b) is the circuit diagram of the NOR gate, AND gate, OR gate, ONOR gate, three-input AND gate AND3, AOR gate, and ANOR gate.

[0049] Figure 5 It is the first part of the verification result of the state logic gate circuit structure in the embodiment of the present invention.

[0050] Figure 6 It is the second part of the verification result of the state logic gate circuit structure in the embodiment of the present invention.

[0051] Figure 7 It is a schematic diagram of all preset merging operations in the embodiment of the present invention. Among them, (a) to (f) are circuit examples of six preset merging operations respectively.

[0052] Figure 8 It is a schematic diagram of the constraint conditions for the merging operation in the embodiment of the present invention. Among them, (a) and (b) are circuit examples of two constraint conditions for the merging operation. Detailed Embodiment

[0053] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0054] As Figure 3As shown in the figure, the method for synthesizing memristive in-memory logic driven by multiple logic function sets in this embodiment includes the following steps:

[0055] S101. For the input complex computing function, construct multiple logic function sets by changing the number of simple logic functions used, and use different simple logic function sets as the synthesis unit library ( Figure 3 denoted as.lib unit library in the figure), and set their areas to the same value. Use the synthesis tool to target the minimum area and convert the input original complex computing function (denoted as test set.v in the figure) into a synthesized netlist composed of simple logic functions;

[0056] S102. Introduce the COPY logic function and the composite logic function, find the combinable simple logic function combinations in the synthesized netlist and merge them into the corresponding composite logic functions, and adjust the netlist to make its logic function correct to obtain a new netlist (.v file) containing composite logic functions; all the logic functions of the new netlist are the logic functions abstracted from the simple state logic gates and composite state logic gates verified on the given memristive storage array model, and the composite state logic gate is equivalent to the function combination of multiple simple state logic gates in terms of logic function; among them, the simple logic function can also be described as the basic logic function, which is the smallest unit of the logic function; the composite state logic gate is obtained by combining multiple basic logic functions;

[0057] S103. Map the new netlist containing composite logic functions, and continuously reduce the array scale of the memristive storage array during the mapping process until the mapping tool can no longer map the new netlist, so as to obtain the state logic gate execution sequence under the minimum array width; for the mapping result (.json file) obtained for each logic function set, select the maximum value of the minimum array width to remap the complex computing function;

[0058] S104. Statistically analyze the performance indicators in the synthesis mapping process, and by comparing the performance indicators of the netlist results obtained by using different logic function sets for the same complex computing function ( Figure 3 denoted as result comparison in the figure), select the netlist result with the optimal corresponding performance indicator as the finally output netlist result according to the application scenario requirements.

[0059] In this embodiment, step S101 includes:

[0060] S201. For the input complex calculation function, under the condition of meeting the constraints of the synthesis tool, construct multiple sets of logic functions by changing the number of simple logic functions used. As an alternative implementation, the synthesis tool in this embodiment is Design Compiler, but the synthesis tool is not limited to this, and can be specifically selected according to actual needs. As the synthesis tool, the function that must be used during synthesis is the NOT function, and it is not allowed to combine the NOT function alone with the OR function or the AND function. Therefore, there are 5 types of state logic function sets constructed using four simple logic functions, which are: First, the NOT function, the NOR function, and the AND function; Second, the NOT function, the NOR function, the AND function, and the OR function; Third, the NOT function, the AND function, and the OR function; Fourth, the NOT function and the NOR function; Fifth, the NOT function, the NOR function, and the OR function.

[0061] S202. Set the standard cell library of the synthesis tool to each set of simple logic functions in turn, and set the area attribute values of each simple logic function to the same value, and set the maximum load capacitance to a preset maximum value. For example, use the first one mentioned above, including the NOT function, the NOR function, and the AND function, etc. Add all the functions in the set of simple logic functions (the simple state logic gates of different functions to be used during the synthesis stage) to the unit library file (.lib file) of the synthesis tool, and set the area attribute of each simple state logic gate to the same value, and set the maximum load capacitance to a maximum value so that the load size does not affect the construction of the circuit. The specific values of these two can be set according to needs. For example, in this embodiment, the area attribute of each simple state logic gate is set to 20.00, and the maximum load capacitance is set to 1000.00.

[0062] S203. Convert the unit library file containing different sets of simple logic functions into a unit library file that can be used by the synthesis tool, and add the unit library file that can be used by the synthesis tool to the target library list and the link library list used during the synthesis of the synthesis tool through the configuration file. For example, specifically in this embodiment, use the read_lib and write_lib commands of the Library Compiler tool to convert the.lib unit library file into a.db unit library file that can be used by the synthesis tool, and add the available unit library file (.db file) to the target_library and link_library lists used during the synthesis of the synthesis tool as the configuration file.

[0063] S204. For each unit library containing different sets of simple logic functions, set the maximum delay in the synthesis constraints to a preset maximum value, set the maximum area to 0, set the synthesis process to optimize for area, and start the iterative synthesis process of the synthesis tool, so as to transform the input original complex computing function into a synthesized netlist composed of simple logic functions. For example, in this embodiment, for each unit library containing different sets of simple logic functions, set the maximum delay in the synthesis constraints to the preset maximum value of 1000, set the maximum area to 0, set the synthesis process to optimize for area, and start the compilation optimization process of the synthesis tool, so as to transform the input original complex computing function into a synthesized netlist composed of simple logic functions. In this embodiment, the compilation optimization is performed twice. The first time, the synthesis target is set to optimize for area for the overall compilation optimization of the logic function. The second time, the synthesis target is set to optimize for area for the incremental compilation of the logic function. At this time, the synthesis tool only performs gate-level optimization.

[0064] In this embodiment, step S102 includes:

[0065] S301. Obtain the merging situation of each simple logic function combination in the synthesized netlist. If the obtaining is successful, jump to step S302; otherwise, jump to step S303.

[0066] S302. Perform the following processing for the obtained merging situation: Search for simple logic function combinations that meet the preset merging conditions in the synthesized netlist. If the search is successful, merge the simple logic function combinations that meet the preset merging conditions into simple logic functions or composite logic functions with the same function, and adjust the netlist structure to ensure the correctness of the netlist function. If a cyclic dependency problem occurs during the merging process, record the position of the state logic gate with the cyclic dependency problem and determine whether it can be merged. If it is determined that it can be merged, record the position where the COPY gate is inserted. If it is determined that it cannot be merged, this merging will not be performed and the search will continue. If the input and output ports of the original netlist are about to be overwritten during the merging process, this merging will not be performed. Jump to step S301. The cyclic dependency problem refers to that the composite state logic gate obtained after merging needs to be the parent node that the overwritten gate executes last. When the execution of other parent nodes of the overwritten logic gate except the composite state logic gate requires the execution result of the composite state logic gate, an irreconcilable contradiction will occur, and no matter how it is executed, it will affect the correctness of the result.

[0067] S303. For the cyclic dependency problem existing in the merged netlist, according to the recorded position of the state logic gate with the cyclic dependency problem, add a copy gate COPY between the overwritten gate and the composite state logic gate generated by the merging to back up the data of the gate that would originally be overwritten to avoid conflicts.

[0068] Iteratively process each merging case through steps S301 and S302. After one merging case search is completed, automatically start searching for the next merging case until all cases have been searched. Repeat the search and merging operations for each merging case until no new combinable combinations appear in a new round, and then execute step S303.

[0069] In steps S301 and S302, the merging cases of simple logic function combinations are predefined and can be defined as needed. For example, as an optional implementation, the merging cases of simple logic function combinations in this embodiment include:

[0070] NOR(NOT)+OR, whose corresponding composite logic function is ONOR(IMP), where ONOR is a NOR-OR logic gate and IMP is an implication logic gate. As shown in (a) of Figure 7 , it can be expressed as:

[0071] NOR(NOT)+OR → ONOR(IMP),

[0072] Because OR(NOR(a, b), c) == ONOR(a, b, c) and OR(NOT(a), b) == IMP(a, b), the logic functions before and after the merging operation are the same. Here, a, b, and c are the inputs of the logic gates. At the same time, in ONOR, c is the logic output, and in IMP, b is the logic output.

[0073] NOR(NOT)+NOR, whose corresponding composite logic function is ONOR(IMP)+NOT, as shown in (b) of Figure 7 , it can be expressed as:

[0074] NOR(NOT)+NOR → ONOR(IMP)+NOT,

[0075] Because the NOR gate can be regarded as a combination of OR and NOT, similar to point 1, the logic functions before and after the merging operation are the same, and it is set as a preset merging operation.

[0076] NOR(NOT / AND / OR)+AND, whose corresponding composite logic function is ANOR(ANOT / AND3 / AOR), where ANOR is a NOR-AND logic gate, ANOT is a NAND logic gate, AND3 is a three-input AND logic gate, and AOR is an OR-AND logic gate. As shown in (c) of Figure 7 , it can be expressed as:

[0077] NOR(NOT / AND / OR)+AND → ANOR(ANOT / AND3 / AOR),

[0078] Since AND(NOR(a, b), c) == ANOR(a, b, c), AND(NOT(a), b) == ANOT(a, b), AND(AND(a, b), c) == AND3(a, b, c), AND(OR(a, b), c) == AOR(a, b, c), the logical functions before and after the merging operation are the same. Here, a, b, and c are the inputs of the logic gates. At the same time, in ANOR, AND3, and AOR, c is the logical output, and in ANOT, b is the logical output.

[0079] NOR(OR)+NOT, and its corresponding merged logical function is OR(NOR), as Figure 7 shown in (d) of

[0080] NOR(OR)+NOT → OR(NOR),

[0081] Since NOT(OR(a, b)) == NOR(a, b), the logical functions before and after the merging operation are the same. Here, a and b are the inputs of the logic gates, and there is a unit outside a and b as the output of the logic gate.

[0082] NOT+NOT, and its corresponding merged logical function is NOT, as Figure 7 shown in (e) of

[0083] NOT+NOT → NOT,

[0084] Since NOT(NOT(a)) == a, the signal remains unchanged after passing through two consecutive NOT gates. Then, the latter NOT gate can be deleted, and the circuit behind it can be connected to the input terminal of the first NOT gate.

[0085] NOR(NOT)+NOR+NOT, and its corresponding composite logical function is ONOR(IMP)+NOT, as Figure 7 shown in (f) of

[0086] NOR(NOT)+NOR+NOT → ONOR(IMP)+NOT,

[0087] Since NOT(NOR(NOR(a, b), c)) == NOT(NOT(ONOR(a, b, c))), where a, b, and c are logical inputs and c is the logical output, and NOT(NOR(NOT(a), b)) == NOT(NOT(IMP(a, b))), where a and b are logical inputs and b is the logical output. After the above merging, it can be found that there are two consecutive NOT gates connected. The NOT+NOT merging operation can be considered to further simplify the netlist. This merging situation actually includes two merging cases: NOR(NOT)+NOR and NOT+NOT. The reason for considering this merging situation is that the cyclic dependency problem in the separate NOR(NOT)+NOR merging operation will introduce COPY gates, thus increasing the number of logical gates after merging. However, if this merging situation is satisfied, the cyclic dependency problem can also be merged because the merging operation will not increase the number of logical gates. In this embodiment, the execution order of the merging operation for the above merging situation is as follows:

[0088] (1)NOR(OR)+NOT → OR(NOR);

[0089] (2)NOR(NOT)+OR → ONOR(IMP);

[0090] (3)NOR(NOT / AND / OR)+AND → ANOR(ANOT / AND3 / AOR);

[0091] (4)NOR(NOT)+NOR → ONOR(IMP)+NOT;

[0092] (5)NOR(NOT)+NOR+NOT → ONOR(IMP)+NOT;

[0093] (6)NOT+NOT → NOT。

[0094] In this embodiment, when combining simple logic function combinations that meet the preset merging situation into a composite logic function, the following constraint conditions need to be satisfied: (1): The output of the previous simple state logic gate in the replaced simple logic function combination cannot drive other state logic gates except the latter simple state logic gate in the same combination, as shown in (a) of Figure 8 ; (2): The other input of the latter simple state logic gate in the replaced simple logic function combination will become the covered input after replacement and cannot be used as the covered input of other composite state logic gates, as shown in Figure 8as shown in (a) of Figure 8 ; (3): When performing two consecutive NOT merges, if the inputs of the latter NOT gate and the former NOT gate are both covered inputs, they cannot be merged because a logic gate cannot be a covered input for two composite state logic gates, which will lead to logical errors; in other cases, the latter NOT gate can be deleted, and the circuit connected to the latter NOT can be connected to the input terminal of the former NOT, as shown in Figure 8 In the figure, a, b, and c are all inputs, and "xxx" represents any logic gate.

[0095] In this embodiment, before step S102, it also includes verifying the correctness of the logic function of the state logic gate based on the given memristor storage array model: for the two types of state logic gates, namely the simple state logic gate and the composite state logic gate that need to be verified for their functions, based on the given memristor simulation model, using a circuit simulation tool to determine the applied voltage of the state logic gate circuit and verify the correctness of the state logic gate function through theoretical analysis and experimental verification. If the correctness verification of the state logic gate function passes, it means that it can participate in the merge process and is stored for use in the subsequent synthesis process. Among them, the two types of state logic gates, the simple state logic gate and the composite state logic gate, for which the function is verified, can be selected as needed. For example, it includes but is not limited to: copy gate COPY ( 's logic function), not-and logic gate ANOT ( 's logic function, which includes the NOT function ), implication logic gate IMP ( 's logic function, which includes the NOT function), or-nor logic gate ONOR ( 's logic function, which includes the NOR function ), or-and logic gate AOR ( 's logic function, which includes the OR function ), three-input and logic gate AND3 ( 's logic function, which includes the AND function ), and not-or-and logic gate ANOR ( The logic functions, including the NOR function, etc. The circuit structures of the COPY gate, NOT gate, ANOT gate, and IMP gate are as shown in Figure 4 (a) in it, and the circuit structures of the NOR gate, AND gate, OR gate, ONOR gate, three-input AND gate AND3, AOR gate, and ANOR gate are as shown in Figure 4 (b) in it. The given memristor simulation model can be selected according to actual needs. For example, as an optional implementation, the given memristor simulation model in this embodiment is Stanford RRAM Model v1.0.0, and the circuit simulation tool HSPICE (but not limited to this) is used to verify the correctness of the functions of the state logic gates.

[0096] Figure 5 This is the verification result of the first part of the state logic gate circuit structure in this embodiment. Figure 6 This is the verification result of the second part of the state logic gate circuit structure in this embodiment. Figure 5 and Figure 6 In, V R represents the control voltage applied to the input device, V W represents the control voltage applied to the output device, in1 represents the information on the first logic input device, in2 represents the second logic input information, and out represents the logic output information. The first row shows the applied pulse voltage, and then shows the gap changes (reflecting the resistance change) of the input and output devices during the execution of each logic gate. The gap value reflects the resistance of the device. 1.7 nm represents the high resistance state (HRS, logic 0), and 0.2 nm represents the low resistance state (LRS, logic 1). Figure 5 and Figure 6 In, ①, ②, ⑧, and respectively represent the verification results of the COPY gate, NOT gate, OR gate, AND gate, and NOR gate of the reset type. The logic output is LRS before execution, and the logic function is based on the conditional reset transition of the output device. ④ and ⑥ respectively represent the verification results of the NOT gate and NOR gate of the set type. The logic output is HRS before execution, and the logic function is based on the conditional reset transition of the output device. Based on the simulation of expanding the logic output to the opposite value of the original on the basis of the simple gate, the simulation results of the composite gates can be obtained. ③, ⑤, ⑦, ⑨, and respectively represent the simulation results of six composite gates, namely the ANOT gate, IMP gate, ONOR gate, AOR gate, AND3 gate, and ANOR gate. The above simulation results show that all 13 logic gates can successfully implement the logic functions.

[0097] In this embodiment, step S103 includes:

[0098] S401, set the array width of the memristor memory array, use a single row of the memristor memory array for mapping, divide the memristor cells in a row of the memristor memory array into two parts. One part of the memristor cells, as the original input, does not need to be initialized, and the other memristor cells are used as intermediate nodes and outputs. Initialize the memristor cells to 0 and 1 respectively according to the ratio of the set gate and the reset gate in the simple state logic gates of the netlist: The ratio of the cells initialized to 1 is the result obtained by dividing the number of reset gates that need to be initialized to 1 in the post-processed netlist by the total number of simple state logic gates in the post-processed netlist. The number of cells initialized to 1 is the product of the ratio of the cells initialized to 1 and the total number of cells that need to be initialized. The number of cells initialized to 0 is the result of subtracting the number of cells initialized to 1 from the total number of cells that need to be initialized, which can be expressed as:

[0099] Ratio of cells initialized to 1 = Number of reset gates that need to be initialized to 1 in the netlist / Total number of simple gates in the post-processed netlist;

[0100] Number of cells initialized to 1 = Ratio of cells initialized to 1 Total number of cells that need to be initialized;

[0101] Number of cells initialized to 0 = Total number of cells that need to be initialized - Number of cells initialized to 1;

[0102] S402. Perform the mapping of memristive cells for state logic gates in a manner similar to topological sorting: All logical inputs are pre-given and already allocated memristive cells, serving as all leaf nodes of a directed acyclic graph. Use a traversal method to allocate memristive cells. Start allocating cells for nodes from the leaf nodes of the directed acyclic graph. In each round of traversal, the current node can only be allocated when all its child nodes have been allocated. In the next round of traversal, set the nodes allocated in this round as allocated nodes. If the current node is a set gate, allocate a memristive cell initialized to 0. If the current node is a reset gate, allocate a memristive cell initialized to 1. If there are not enough memristive cells of a certain type, re-initialize the cells. For memristive cells no longer needed for information, the memristive cells originally initialized to 0 remain initialized to 0, and those initialized to 1 remain initialized to 1, and are added to the allocable queue. If the current node is a composite state logic gate, it needs to be processed separately. It must be ensured that all parent nodes of the covered node have been allocated before this composite state logic gate node can be allocated to ensure that the composite state logic gate is the last one to be executed among all parent nodes of the covered node. At the same time, the composite state logic gate can directly occupy the covered child nodes during mapping without allocating other memristive cells. Keep traversing until all nodes are allocated. If the current array width can allocate all nodes, it is determined that the execution sequence of state logic gates under the minimum array width has been obtained, output the execution sequence of state logic gates within a single row of the memristor storage array, and jump to step S403. If the current array width cannot allocate all nodes, print a prompt for mapping errors, end, and exit.

[0103] S403. For the mapping results obtained for each state logic function set, select the maximum value of the minimum array width to re-map the complex computing functions. For example, in this embodiment, compare the minimum array widths required for the netlist mappings corresponding to five standard cell libraries, and obtain the maximum value among them. Set the array widths of the netlist mappings corresponding to the five standard cell libraries to this maximum value and perform re-mapping to obtain the mapping results under this same array width condition.

[0104] The mapping process in step S103 of this embodiment is based on LOSSS, and the improved parts include: 1. More composite state logic gates are introduced in the mapping process, and it must be ensured that the composite state logic gate is the last logic gate to be mapped and executed among all the parent logic gates of the covered logic gate; 2. The ratio of initializing memristive units to 0 and 1 is changed. When initializing the units other than the input, the ratio of the units initialized to 0 and 1 is determined by the ratio of the set-type simple gates to the reset-type simple gates in the netlist after merging processing; 3. The mapping method of the state logic gate is changed. The original mapping method using a recursive strategy is changed to a method similar to topological sorting in this example. Relying on the already allocated nodes to find the allocable nodes, continuously traversing and searching until all nodes are allocated. The reason for not using the original method is that the recursive method uses a stack to store the previous states, and an overly complex netlist may lead to a stack overflow problem.

[0105] In this embodiment, when counting the performance metrics in the comprehensive mapping process in step S104, the performance metrics in the comprehensive mapping process include counting the minimum array width, the number of operations, the delay at the minimum array width, and the delay after unifying the array width for each set of simple logic functions as the cell library.

[0106] After counting the minimum array width, the number of operations, the delay at the minimum array width, and the delay information after unifying the array width for each set of simple logic functions as the cell library, then the mapping results suitable for the current scenario requirements are selected through data comparison as the final result. In this embodiment, in step S104, by comparing the performance metrics of the netlist results obtained by using different sets of logic functions for the same complex computing function, the netlist result with the optimal corresponding performance metric is selected as the final output netlist result according to the application scenario requirements, including:

[0107] S501. Obtain the mapping result with the minimum latency (number of selection mapping cycles), minimum area, and longest service life by comparing the performance metrics of the netlist results obtained using different logic function sets for the same complex calculation function: When obtaining the mapping result with the minimum latency, keep the row width at a preset small value, compare the number of cycles required for mapping at the same array width (specifically, the maximum of five minimum array widths in this embodiment) to find the minimum value. If the results of multiple function sets are the same at this time, then compare the cycle results obtained by mapping at the minimum row width. If the minimum value is compared at this time, select the result of this set as the final result. If the minimum value still cannot be found, select the results with the same number of cycles as the final result. When obtaining the mapping result with the minimum area, directly compare the results of the minimum row width required for each netlist mapping, and select the one with the minimum row width as the final result. If there are multiple, then these multiple results are all optional. When obtaining the mapping result with the longest service life, represent the service life by the number of operations of the device, and select the result with the minimum number of required operations as the final result of the longest device life. Directly compare the number of operations required for each netlist mapping after merging processing, and select the one with the minimum number of required operations as the final result. If there are multiple, then these multiple results are all optional.

[0108] S502. According to the requirements of the application scenario, select the netlist result corresponding to this application scenario from the mapping results with the minimum latency, minimum area, and longest service life as the finally output netlist result. For example, if comprehensive mapping needs to be performed on the smallest area currently, then the result with the minimum required array width can be selected.

[0109] In summary, the purpose of the memristive in-memory logic synthesis method driven by multiple logic function sets in this embodiment is to complete a high-efficiency synthesis mapping from complex combinatorial logic functions to the execution sequence of state logic gates, use multiple simple logic function sets for synthesis to obtain netlists with different structures, and optimize and improve the in-memory computing efficiency by merging the logic functions in the synthesized netlists.The process of the whole method includes: (1) Using the same memristor model to build a state logic gate circuit, and verifying that this circuit can implement the state logic gates used to ensure the compatibility of these state logic gates in the same memristor storage array. The verified state logic gates include, but are not limited to, simple state logic gates with five logical functions of NOR, NOT, OR, AND, and COPY (where the COPY gate is only used to solve the cyclic dependency problem) and composite state logic gates with six logical functions of ANOT, IMP, ONOR, AOR, AND3, and ANOR; (2) Using four simple logical functions to construct five state logic function sets (NOT function, NOR function, AND function; NOT function, NOR function, AND function, OR function; NOT function, AND function, OR function; NOT function, NOR function; NOT function, NOR function, OR function). Let each set be used as a synthesis tool to synthesize the unit library and set the area value of each function to the same value. Using the synthesis tool, compile and optimize the original complex calculation function with the goal of minimizing the area into a synthesized netlist composed of logical functions within the state logic function set; (3) Adopting a specially developed merging process to merge and adjust the logical functions of the synthesized netlist, including merging the NOR(NOT)+OR function that meets the merging condition into the ONOR(IMP) function, merging the NOR(NOT)+NOR function that meets the merging condition into the ONOR(IMP)+NOT function, merging the NOR(NOT / AND / OR)+AND function that meets the merging condition into the ANOR(ANOT / AND3 / AOR) function, merging the NOR(OR)+NOT function that meets the merging condition into the OR(NOR) function, merging the NOR(NOT)+NOR+NOT function that meets the merging condition into the ONOR(IMP)+NOT function, deleting the forward connection of the latter NOT gate and the logic circuit after deleting two consecutive NOT gates that meet the merging condition, and introducing the COPY gate to handle the cyclic dependency problem; (4) Adopting a mapping method improved based on LOSSS to complete the mapping process from the logical netlist after the merging operation to the in-memory state logic gates within a single row of the memristor storage array, determining the minimum array width required to complete the mapping and the execution sequence of the in-memory state logic gates at this time; (5) For the mapping results obtained for each state logic function set, select the maximum value of the minimum array width to remap the complex calculation function; (6) Statistically analyze data such as the minimum array width, delay, number of operations, and delay at the same array width during the synthesis and mapping process. By comparing the netlist results of the same complex calculation function using different state logic function sets, select the execution result with the optimal corresponding index as the final result according to the application scenario requirements.In this embodiment, by combining and merging multiple simple logic functions, the computing efficiency is significantly improved and the service life of the array is extended. The method of this embodiment can obtain netlists with different structures by performing logic synthesis on different sets of simple logic functions. After merging processing and mapping, different mapping results can be obtained. For different mapping objectives (such as area, delay, or lifespan, etc.), mapping results for different application scenarios can be obtained.

[0110] In addition, this embodiment also provides a multi-logic-function-set-driven memristive in-memory logic synthesis system, including a microprocessor and a memory connected to each other. The microprocessor is programmed or configured to execute the multi-logic-function-set-driven memristive in-memory logic synthesis method.

[0111] In addition, this embodiment also provides a computer-readable storage medium, in which a computer program or instruction is stored. The computer program or instruction is programmed or configured to execute the multi-logic-function-set-driven memristive in-memory logic synthesis method through a processor.

[0112] In addition, this embodiment also provides a computer program product, including a computer program or instruction. The computer program or instruction is programmed or configured to execute the multi-logic-function-set-driven memristive in-memory logic synthesis method through a processor.

[0113] Those skilled in the art should understand that the technical solution provided by the present invention can be in the form of a method, a system, or a computer program product. Therefore, the present invention can be implemented in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can be implemented in the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes. The present invention is described with reference to the flowcharts and / or block diagrams of the method, device (system), and computer program product according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate for realizing in the process Figure 1 each process or multiple processes and / or blocks Figure 1Apparatus for functions specified in one or more boxes. These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufactured article including an instruction apparatus that implements the functions specified in the process Figure 1 One process or more processes and / or boxes Figure 1 Apparatus for functions specified in one or more boxes. These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in the process Figure 1 One process or more processes and / or boxes Figure 1 Apparatus for functions specified in one or more boxes.

[0114] The above are only the preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the concept of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, several improvements and refinements made without departing from the principle of the present invention should also be regarded as within the protection scope of the present invention.

Claims

1. A memristive in-memory logic synthesis method driven by a multi-logic function set, characterized in that It includes the following steps: S101. For the input complex calculation function, construct multiple logical function sets by changing the number of simple logical functions used, use different simple logical function sets as the synthesis unit library, set their areas to the same value, and use the synthesis tool to transform the original complex calculation function with the goal of minimizing the area into a synthesized netlist composed of simple logical functions; S102. Introduce the COPY logical function and the composite logical function, find the combinable simple logical function combinations in the synthesized netlist and merge them into the corresponding composite logical functions, and adjust the netlist to make its logical function correct to obtain a new netlist containing composite logical functions; all the logical functions of the new netlist are logical functions abstracted from the simple state logic gates and composite state logic gates verified on the given memristor storage array model, and the composite state logic gate is equivalent to the function combination of multiple simple state logic gates in terms of logical function; S103. Map the new netlist containing composite logical functions, and continuously reduce the array scale of the memristor storage array during the mapping process until the mapping tool can no longer map the new netlist, so as to obtain the state logic gate execution sequence under the minimum array width; for the mapping results obtained for each logical function set, select the maximum value of the minimum array width to remap the complex calculation function; S104. Statistically analyze the performance indicators in the comprehensive mapping process, compare the performance indicators of the netlist results obtained by using different state logical function sets for the same complex calculation function, and select the netlist result with the optimal corresponding performance indicator as the finally output netlist result according to the application scenario requirements; Step S103 includes: S401. Set the array width of the memristor storage array, use a single row of the memristor storage array for mapping, divide the memristor cells in a row of the memristor storage array into two parts, one part of the memristor cells is used as the original input and does not need to be initialized, and the other memristor cells are used as intermediate nodes and outputs, and initialize the memristor cells to 0 and 1 respectively according to the ratio of the set gate to the reset gate in the simple state logic gates of the netlist: the ratio of the cells initialized to 1 is the result obtained by dividing the number of reset gates that need to be initialized to 1 in the post-processed netlist by the total number of simple state logic gates in the post-processed netlist, the number of cells initialized to 1 is the product of the ratio of the cells initialized to 1 and the total number of cells that need to be initialized, and the number of cells initialized to 0 is the result of subtracting the number of cells initialized to 1 from the total number of cells that need to be initialized; S402. Perform memristor cell mapping for state logic gates in a way similar to topological sorting: All logical inputs are pre-given and already allocated memristor cells, serving as all leaf nodes of a directed acyclic graph. Use a traversal method to allocate memristor cells. Start allocating cells for nodes from the leaf nodes of the directed acyclic graph. In each round of traversal, the current node can only be allocated when all its child nodes have been allocated. In the next round of traversal, set the nodes allocated in this round as allocated nodes. If the current node is a set gate, allocate a memristor cell initialized to 0. If the current node is a reset gate, allocate a memristor cell initialized to 1. If there are not enough memristor cells of a certain type, re-initialize the cells. For memristor cells no longer needed for information, those originally initialized to 0 remain initialized to 0, and those initialized to 1 remain initialized to 1, and add them to the allocable queue. If the current node is a composite state logic gate, it needs to be processed separately. It must be ensured that all parent nodes of the covered node have been allocated before this composite state logic gate node can be allocated to ensure that the composite state logic gate is the last one to execute among all parent nodes of the covered node. At the same time, the composite state logic gate can directly occupy the covered child nodes during mapping without allocating other memristor cells. Keep traversing until all nodes are allocated. If the current array width can allocate all nodes, it is determined that the execution sequence of state logic gates under the minimum array width has been obtained, output the execution sequence of state logic gates within a single row of the memristor storage array, and jump to step S403. If the current array width cannot allocate all nodes, print a prompt for mapping errors, end, and exit. S403. For the mapping results obtained for each state logic function set, select the maximum value of the minimum array width to remap the complex calculation function.

2. The multi-logic-function-set-driven memristive in-memory logic synthesis method according to claim 1, wherein Step S101 includes: S201. For the input complex calculation function, construct multiple logic function sets by changing the number of simple logic functions used under the condition of meeting the restrictions of the synthesis tool. S202. Set the standard cell library of the synthesis tool to each simple logic function set in turn, and set the area attribute value of each simple logic function to the same value, and set the maximum load capacitance to a preset extremely large value. S203. Convert the cell library files containing different simple logic function sets into cell library files that can be used by the synthesis tool, and add the cell library files that can be used by the synthesis tool to the target library list and link library list used during the synthesis of the synthesis tool through a configuration file. S204. For each cell library containing different simple logic function sets, set the maximum delay in the synthesis constraints to a preset extremely large value, set the maximum area to 0, set the synthesis process to optimize for area, and start the iterative synthesis process of the synthesis tool, so as to convert the input original complex calculation function into a synthesized netlist composed of simple logic functions.

3. The multi-logic-function-set-driven memristive in-memory logic synthesis method according to claim 1, wherein Step S102 includes: S301. Obtain the merging situation of each simple logic function combination in the synthesized netlist. If the obtaining is successful, jump to step S302; otherwise, jump to step S303. S302. Perform the following processing on the obtained merging situation: Search for simple logic function combinations that meet the preset merging conditions in the synthesized netlist. If the search is successful, merge the simple logic function combinations that meet the preset merging conditions into simple logic functions or composite logic functions with the same function, and adjust the netlist structure to ensure the correctness of the netlist function. If a circular dependency problem occurs during the merging process, record the position of the state logic gate with the circular dependency problem and determine whether it can be merged. If it is determined that it can be merged, record the position where the COPY gate is inserted. If it is determined that it cannot be merged, this merging will not be performed and continue the search. If the input and output ports of the original netlist are about to be overwritten during the merging process, this merging will not be performed. Jump to step S301. The circular dependency problem refers to that the composite state logic gate obtained after merging needs to be the parent node that the overwritten gate executes last. When the execution of other parent nodes of the overwritten logic gate except the composite state logic gate requires the execution result of the composite state logic gate, an irreconcilable contradiction will occur, and no matter how it is executed, it will affect the correctness of the result. S303. For the circular dependency problem existing in the merged netlist, according to the recorded position of the state logic gate with the circular dependency problem, add a copy gate COPY between the overwritten gate and the composite state logic gate generated by the merging to back up the data of the gate that would originally be overwritten to avoid conflicts.

4. The multi-logic-function-set-driven memristive in-memory logic synthesis method according to claim 1, wherein Before step S102, it also includes verifying the correctness of the logic function of the state logic gate based on the given memristor storage array model: For the two types of state logic gates, namely simple state logic gates and composite state logic gates that need to be functionally verified, based on the given memristor simulation model, use circuit simulation tools to determine the external voltage of the state logic gate circuit and verify the correctness of the state logic gate function through theoretical analysis and experimental verification. If the correctness verification of the state logic gate function passes, it means that it can participate in the merging process and store it for use in the subsequent synthesis process.

5. The multi-logic function set-driven memristive in-memory logic synthesis method according to claim 1, wherein When counting the performance metrics in step S104 during the synthesis mapping process, the performance metrics in the synthesis mapping process include counting the minimum array width, the number of operations, the delay at the minimum array width, and the delay after unifying the array width for each simple logic function set as the cell library.

6. The multi-logic function set-driven memristive in-memory logic synthesis method according to claim 5, wherein In step S104, by comparing the performance metrics of the netlist results obtained by using different logic function sets for the same complex calculation function, selecting the netlist result with the optimal corresponding performance metric as the final output netlist result according to the application scenario requirements includes: S501. Obtain the mapping result with the minimum delay, minimum area, and longest service life by comparing the performance metrics of the netlist results obtained by using different logic function sets for the same complex computing function: When obtaining the mapping result with the minimum delay, keep the row width as a preset smaller value, compare the number of cycles required for mapping at the same array width to find the minimum value. If the results of multiple function sets are the same at this time, then compare the cycle results obtained by mapping at the minimum row width. If the minimum value is compared at this time, then select the result of this set as the final result. If the minimum value still cannot be found, then select the results with the same number of cycles as the final result; When obtaining the mapping result with the minimum area, directly compare the results of the minimum row width required for each netlist mapping, and select the one with the minimum row width as the final result. If there are multiple, then these multiple results are all optional; When obtaining the mapping result with the longest service life, represent the service life by the number of operations of the device, and select the result with the minimum number of required operations as the final result of the longest device life. Directly compare the number of operations required for each netlist mapping after merging processing, and select the one with the minimum number of required operations as the final result. If there are multiple, then these multiple results are all optional; S502. According to the requirements of the application scenario, select the netlist result corresponding to this application scenario from the mapping results with the minimum delay, minimum area, and longest service life as the finally output netlist result.

7. A memristive in-memory logic synthesis system driven by a multi-logic function set, comprising a microprocessor and a memory connected to each other, characterized in that, The microprocessor is programmed or configured to execute the multi-logic-function-set-driven memristive in-memory logic synthesis method according to any one of claims 1 to 6.

8. A computer-readable storage medium storing a computer program or instructions, characterized in that, The computer program or instruction is programmed or configured to execute the multi-logic-function-set-driven memristive in-memory logic synthesis method according to any one of claims 1 to 6 through a processor.

9. A computer program product comprising a computer program or instructions, characterized in that, The computer program or instruction is programmed or configured to execute the multi-logic-function-set-driven memristive in-memory logic synthesis method according to any one of claims 1 to 6 through a processor.

Images