AI technique for determining maximum thermal performance of system-on-chip layout planning

Abstract

Systems, devices, and methods may provide techniques for determining a plurality of transient thermal responses for a corresponding plurality of power source locations on a semiconductor die, obtaining a corner block list (CBL) representation associated with a plurality of candidate layout plans, and performing an artificial intelligence (AI)-based search on the CBL representation, wherein the output of the AI-based search is one or more suggested layout plans having a transient thermal response below a thermal threshold.

Description

BACKGROUND OF THE INVENTION

[0001] In the design of semiconductor packages, buried power rails (BPR) and backside power delivery (BSPD) techniques have been adopted for further scaling implementations. Using BPR and BSPD techniques, a system-on-chip (SoC) can be coupled to the front side of a substrate, and a power delivery network can be coupled to the back side of the substrate, where the power rails are buried in the substrate. Such an approach frees up routing resources for the power / ground supply network ("nets") in both standard cell and block designs. Additionally, BPR has a direct power supply from package interconnects (e.g., bump contacts) and has lower resistance compared to conventional back-end-of-line (BEOL) rails in older technologies. Such an approach can significantly improve current resistance (IR) drop and provide better power, performance, and area (PPA) results.

[0002] However, a challenge with BPR is thermal performance management. In older technologies, a heat sink could be directly connected to the body of the silicon substrate, which provided an efficient transfer of heat generated by the transistors to the heat sink. However, for BPR technology, the silicon substrate is sandwiched between front and back metal stacks. Since the substrate is moved further away from the heat sink, a negative impact on thermal performance may be encountered. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The various advantages of the embodiments will become apparent to those skilled in the art by reading the following specification and the appended claims, and by referring to the following drawings, in which:

[0004] Figure 1A is a comparative illustration of an example of an enhanced layout planning heat map and a conventional layout planning heat map according to an embodiment;

[0005] Figure 1B is an illustration of an example of an enhanced layout planning heat map according to another embodiment;

[0006] Figure 2 is an illustration of an example of a superposition source simulation according to an embodiment;

[0007] Figure 3 is an illustration of an example of an enhanced layout planning heat map with dummy blocks according to an embodiment;

[0008] Figure 4 is a block diagram of an example of a process flow for handling physical connectivity constraints according to an embodiment;

[0009] Figure 5 is a block diagram of an example of a process flow involving the use of a thermal response tool according to an embodiment;

[0010] Figure 6is a flowchart of an example of a method for generating a system-on-chip (SoC) layout plan according to an embodiment;

[0011] Figure 7 is a flowchart of an example of a method for managing a corner block list (CBL) representation according to an embodiment;

[0012] Figure 8 is a block diagram of an example of a performance-enhanced computing system according to an embodiment;

[0013] Figure 9 is an illustration of an example of a semiconductor packaging device according to an embodiment;

[0014] Figure 10 is a block diagram of an example of a processor according to an embodiment; and

[0015] Figure 11 is a block diagram of an example of a multi-processor-based computing system according to an embodiment. DETAILED DESCRIPTION

[0016] Managing the temperature of a processor chip can affect both the performance and reliability of the chip. A system thermal architect may typically spend weeks obtaining the lowest maximum temperature by considering different system-on-chip (SoC) layout plans. Since there is no commercial software that can automate this thermal performance optimization process, the thermal architect may manually study all known combinations. Additionally, it is often unclear whether an even lower temperature (e.g., and thus better performance) is even achievable for a given layout plan.

[0017] Figure 1A Shows a thermal map of a conventional SoC layout plan 20. In the example shown, there are thirty-one functional blocks, including six high-performance cores (e.g., closely spaced cores "R0" to "R5", where R2 is designated as the "mesh" for detailed analysis), two efficient cores (e.g., cores "M0" and "M1"), eight last-level caches (LLCs), two secondary (L2) caches, nine digital linear voltage regulators (DLVRs), and eight CBOs (cache boxes, e.g., cache coherence and LLC controllers in a convergence coherence fabric / CCF). The thermal map of layout plan 20 produces a predicted maximum temperature of 103.485 degrees Celsius (°C) during operation.

[0018] Traditional SoC layout planning 20 represents traditional manual placement, where various functional (e.g., intellectual property / IP) blocks are arranged in a very organized / balanced manner. Although balanced placement can facilitate manual verification of various signal timing and routing constraints between IP blocks, such an approach results in clustering of duplicate copies of the same block (e.g., central processing unit / CPU core) together. Since these blocks typically consume higher power, traditional SoC layout planning 20 relatively generates a high operating temperature due to the proximity of the cores to each other. The power concentration caused by clustering leads to poor thermal conductivity of the system cooling solution and ultimately reduces the total power that the SoC can dissipate.

[0019] In contrast, enhanced SoC layout planning 22 demonstrates that the techniques described herein can optimize the thermal performance of traditional SoC layout planning 20. More specifically, by optimizing the functional block layout and the power map within each block, it is possible to reduce the maximum temperature, which improves chip performance and reliability. In the example shown, enhanced SoC layout planning 22 is unbalanced, and without considering any physical connectivity constraints between the blocks, the predicted maximum temperature during operation is reduced from an initial 103.485 °C to 99.3775 °C.

[0020] Figure 1B A thermal map is shown for another enhanced SoC layout planning 24, for which physical connectivity constraints between functional blocks (e.g., DLVR attached to R, L2 cache attached to M) are considered. In the example shown, the predicted maximum temperature during operation is reduced to 98.8043 °C. For this particular layout planning 24 with one workload, the techniques described herein achieve a temperature drop of approximately 4 - 5 °C. In most instances, a 3 °C drop is sufficient to change the design decision. For all test cases, the embodiments can also be used to achieve a temperature drop greater than 3 °C. In fact, layout planning 24 can be selected from multiple layout plans, all of which provide improved thermal performance due to the techniques described herein. Additionally, the total execution time of the techniques described herein is significantly faster (e.g., approximately 4 hours) than the manual approach associated with traditional SoC layout planning 20 ( Figure 1A )

[0021] With the end of Dennard scaling (e.g., stating that as transistor sizes decrease, their power density remains constant), but with the continued pursuit of advanced lithography nodes, semiconductor temperature response and local heat propagation have become more relevant and more of a priority in chip design. Some computing products can include performance cores (e.g., the highest power density blocks) placed near the center of the die. Such a layout still results in some clustering of similar IP blocks (e.g., computing cores), but the cores are located near the center of the die (e.g., where non-computing IP such as input / output (IO), system agents, and register blocks surround the cores). These low-power regions can enable the heat from the cores to dissipate and propagate with a lower temperature gradient.

[0022] Other computing products resulting from a manual layout process result in an aspect ratio across the chip based on a linear progression of functional block placement, and the layout has strict uniformity. In a direct comparison with other layouts, the cores are not only clustered together but are placed along the edges of the die, where the IO, system agents, and register blocks are located on the far side of the die. In such a configuration, the central CPU core tends to be the thermal limiter because the heat generated by the central CPU core is confined within the floorplan. Such a configuration has cores on both sides of the substrate, which also generates heat, and the edges of the die prevent heat conduction in that direction.

[0023] Enhanced SoC floorplans 22, 24 ( Figure 1A , Figure 1B ) can be achieved through AI-based methods for more efficient SoC floorplanning and improved thermal performance. Several optimization processes from computational intelligence techniques (a subset of artificial intelligence) are adapted and customized for this thermal SoC floorplanning optimization problem. Additionally, the tools and / or techniques described herein can generate many floorplans with acceptable thermal performance for the user to select during optimization. Embodiments can be used at different length scales (from SoC core layout to system IP blocks).

[0024] Advantages of the techniques described herein include faster thermal response evaluation for any floorplan, simultaneous optimization of the entire SoC floorplan and the power map in each block, the ability to provide lower bounds on SoC thermal performance and more floorplan options, and increased engineering efficiency (e.g., time reduced from weeks to hours).

[0025] The techniques described herein prevent the CPU cores from clustering with strict uniformity (e.g., enhancing performance). In fact, incorporating thermal performance (e.g., not just power performance) into SoC design is a significant advancement over traditional methods.

[0026] System thermal architects can use the techniques described herein to understand the maximum thermal performance of any SoC floorplan. Such an approach can ensure that manual optimization ends when a sufficiently low temperature is reached, while taking into account all physical design constraints. Embodiments can accelerate the optimization of an SoC floorplan for thermal performance from weeks to within a day, while providing an optimal thermal solution. With a better thermal SoC, the chip product has better performance and is more reliable. The automated techniques described herein enable more complex floorplan options to be considered and accelerate the design process of complex SOCs by inherently incorporating accurate thermal considerations into the process.

[0027] As already mentioned, the AI-based techniques described herein rapidly evaluate thermal responses and identify the lowest temperature bounds with or without any constraints in an SoC floorplan. Thus, the thermal architect can determine the maximum achievable thermal performance and stop the optimization effort when a sufficiently low temperature is reached, while taking into account all physical design constraints. Such an approach accelerates the development of an SoC floorplan for thermal performance, thus saving time and resources.

[0028] Embodiments include using a rapid thermal response evaluation tool (e.g., INTEL SUPERGRID). The thermal response tool helps to evaluate a higher volume of floorplans and workloads. The thermal response tool builds a physics-based machine learning model for thermal analysis. Since the materials are the same, the SoC thermal performance is typically linear and does not change over time. Thus, the superposition principle (e.g., stating that for all linear systems, the net response caused by two or more stimuli is the sum of the responses that would have been caused by each stimulus alone) holds. However, due to numerical issues regarding many sources of superposition, it may be difficult to implement using the superposition principle under traditional methods.

[0029] In one example, a thermal analysis tool (such as, for example, the INTEL DOCEA tool) can be utilized to examine the applicability of superposition. Such an analysis tool has demonstrated that the numerical issues have been resolved and that the superposition method can be effectively used for the use cases of interest. The acceleration of the analysis time is significant (e.g., more than 50,000 times faster), which enables the relevant analysis processes. Additionally, this reduction in latency is achieved without any loss of accuracy and without approximations.

[0030] Now turning to Figure 2, the thermal response tool divides the die area 30 into a grid with superimposed sources 32, 34, 36. Although three superimposed sources 32, 34, 36 are shown, the total number of superimposed sources 32, 34, 36 is the same as the number of grid cells. This approach not only aids in the application of the superposition principle but also helps in creating any possible layout plan suitable for the die area 30 of the chip. More specifically, the thermal response tool creates a grid of superimposed sources 32, 34, 36 for the die of interest and runs a thermal step response for each cell in the grid with any non-grid sources (e.g., applying 1 watt (W) and measuring the thermal response across the die over X time steps). Then, the thermal response tool applies the superposition principle to find the transient thermal response for any possible layout plan and power map. As Figure 2 shown, the determination of the transient thermal response can be repeated for any additional layout plan and power map. In the example shown, for an 8 millimeter (mm) by 9 mm die that is meshed at 100 micrometers (μm) by 100 μm, only the first three of 7200 source cells are shown.

[0031] The rapid evaluation of the thermal response from the thermal response tool significantly enhances the optimization of the SoC layout plan for thermal performance. Then, an AI-based methodology can be used to find the best layout plan and power map rotation with the minimum thermal temperature. In an embodiment, the methodology involves two-level optimization:

[0032] - Using an optimization process with a CBL (Corner Block List) representation to find a new layout plan adapted to the SoC area.

[0033] - Using a genetic process to optimize the power map of each functional block to determine the minimum temperature. The corner block list is a mathematical representation of the layout plan and is an effective method in the field of very large scale integration (VLSI) design. Different AI-based searches (such as simulated annealing, reinforcement learning, etc.) can be used to identify the layout plan based on the CBL representation. These processes are also applicable to finding the global optimum. For example, the simulated annealing operation performs a heuristic search method of artificial intelligence and accepts a worse solution with a certain probability to introduce randomness. This method helps to avoid local minima. In the reinforcement learning operation, the agent can use an exploration strategy that introduces randomness (e.g., "epsilon-greedy") to encourage the exploration of different actions. Additionally, the CBL can be customized with two new advancements for thermal analysis.

[0034] Now turning to Figure 3, The first improvement is to insert additional "dummy" blocks into the CBL representation to create additional space. The additional space separates the hotspots between the cores, which in turn reduces the maximum temperature. More specifically, a heat map of the floorplan 40 is shown, where dummy blocks ("Dummy 1" to "Dummy 10") are inserted into the CBL representation. The solution shown exploits the fact that splitting core hotspots will generally result in better chip thermal performance. For example, hotspots R1 and R0 are further separated by Dummy Block 2. The size and number of dummy blocks can be determined by how much blank space is available for each SoC design.

[0035] Now turning to Figure 4 , The second improvement is to handle the physical connectivity constraints of the functional blocks within the CBL framework. Typically, the hierarchical design process begins by identifying multiple blocks 50, 52 with physical connectivity constraints and combining / merging the multiple blocks 50, 52 into a group 54. For example, the first block 50 may include a DLVR that is to be placed connected / adjacent to a second block 52 that includes a R1 core. Thus, the multiple blocks 50, 52 are merged into a larger block called the "R1 group". After an AI-based search of the CBL representation (e.g., including simulated annealing, reinforcement learning operations, and / or rotation analysis) generates a feasible floorplan, the group 54 is split back into the original blocks 50, 52 for thermal performance calculation. As will be discussed in more detail, the thermal performance calculation may include symmetry analysis. The example shown demonstrates symmetry analysis, which examines the thermal effects of repositioning the blocks 50, 52 around the horizontal axis of the previous group 54 (e.g., while maintaining physical connectivity / proximity).

[0036] Now turning to Figure 5 , A process flow 60 is shown, where a thermal response tool is used for fast thermal response during optimization. The first operation 62 prepares the blocks adapted to the chip area by adding dummy blocks and grouping the blocks with connectivity constraints. The size and number of dummy blocks are determined by the remaining blank space of the designed die. The dummy blocks can have an area similar to the median size of all available blocks on the SoC. If no space remains, the addition of dummy blocks can be bypassed. When proximity design constraints (e.g., a DLVR block attached to its corresponding core block) are available in the SoC design, groups are formed for the blocks. This approach facilitates realistic design requirements. The second operation 64 uses an optimization process with CBL to generate a new feasible floorplan to fit the die area. In one example, simulated annealing is used as the optimization process for CBL. In another example, reinforcement learning is used to generate a feasible floorplan. For each new floorplan, the third operation 66 splits the grouped blocks into the original blocks for a fourth operation 68 involving power map optimization (e.g., based on symmetry analysis).

[0037] Since the dummy blocks have zero power consumption, they are not used in the thermal performance calculations. A genetic process is used to optimize the power map such that the maximum temperature can potentially be reduced below the current best solution. There are eight degrees of freedom for the power map optimization of each block - four from rotation and four from symmetry. Thus, the total optimization solution space for the genetic algorithm is N 8 , where N is the number of blocks in each SoC floorplan. For the example of 31 blocks of the conventional SoC floorplan 20( Figure 1A ), this solution space is 8.5×10 11 . A programmable maximum number of iterations (e.g., default of 30,000) can be set for the genetic process. When the number of iterations of the genetic process exceeds the user-defined number, the optimization loop can be exited. The techniques described herein output the final floorplan with the best possible thermal performance within the user-defined maximum iterations for the user to review. Also, several solutions may be output during the optimization process for the user to select and be enlightened by.

[0038] As already mentioned, embodiments can be used at different length scales (from core blocks to SoC IP blocks and to system IP blocks). Each IP block in the SoC can generally be considered an immutable object. However, the same type of analysis can be performed on the core layout itself to improve the core blocks individually. Such an approach provides further opportunities to improve the thermal performance of the SoC.

[0039] In one example, the process flow 60 represents the SUPERGRID for a fast thermal response solution. The SUPERGRID uses a superposition method where a set of simulations are performed to "characterize" the SoC, from which any layout map / workload can be quickly solved. More specifically, the SoC can be divided into a grid of N sources, where an initial characterization simulation is run by exciting each source with 1W and recording the thermal response across the entire response region. Then, the thermal response can be simply calculated by summing the new power (P s ) of each source and scaling by the superposition coefficient (C s ). This operation can be repeated for all x, y positions at each time step (t).

[0040] Figure 6A method 70 for generating a SoC layout plan is shown. The method 70 can be implemented as a set of logic instructions (e.g., executable program instructions) stored in a machine or computer-readable storage medium such as random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in hardware, or any combination thereof, in one or more modules. For example, a hardware implementation can include configurable logic, fixed-functional logic, or any combination thereof. Examples of configurable logic (e.g., configurable hardware) include a properly configured programmable logic array (PLA), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), and a general-purpose microprocessor. Examples of fixed-functional logic (e.g., fixed-functional hardware) include a properly configured application-specific integrated circuit (ASIC), combinational logic circuits, and sequential logic circuits. The configurable or fixed-functional logic can be implemented using complementary metal-oxide semiconductor (CMOS) logic circuits, transistor-transistor logic (TTL) logic circuits, or other circuits.

[0041] The computer program code for performing the operations shown in the method 70 can be written in any combination of one or more programming languages, including object-oriented programming languages (such as JAVA, SMALLTALK, MATLAB, C++, etc.) and traditional procedural programming languages (such as the "C" programming language or similar programming languages). In addition, the logic instructions can include assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, status-setting data, configuration data of integrated circuit modules, and status information for personalizing other structural components native to electronic circuit modules and / or hardware (e.g., host processors, central processing units / CPUs, microcontrollers, etc.).

[0042] The processing block 72 shown determines multiple transient thermal responses for corresponding multiple power source locations on a semiconductor die. In an embodiment, the processing block 72 uses a thermal response tool to determine the multiple transient thermal responses (e.g., by applying 1W of power and measuring the thermal response across the die over X time steps). The processing block 74 obtains a CBL representation associated with multiple candidate layout plans. Generally, the CBL representation is generated from a two-dimensional (2D) layout plan. In one example, the CBL is a data structure containing three-valued tuples (S, L, T): block name, orientation, and binary string, which is used for an efficient topological representation of the layout plan. The processing block 76 performs an AI-based search on the CBL representation, where the output of the AI-based search is one or more proposed layout plans having a transient thermal response below a thermal threshold (e.g., 100 °C). The AI-based search can include one or more simulated annealing operations, one or more reinforcement learning operations, etc., or any combination thereof. Thus, the method 70 enhances performance at least to the extent that the AI-based search enables thermal performance to be considered during the SoC design phase (e.g., as opposed to after the SoC design is completed). Additionally, performing the AI-based search on the CBL representation accelerates the optimization of the SoC layout plan, improves the reliability of the selected layout plan, and enables more complex layout plan options to be considered.

[0043] Figure 7 A method 80 for managing a CBL representation is shown. The method 80 can generally be incorporated into the method 70 that has been discussed ( Figure 6 ). More specifically, the method 80 can be implemented as a set of logic instructions stored in a machine or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., in hardware, or any combination thereof, in one or more modules.

[0044] The processing block 82 shown inserts one or more dummy blocks (e.g., dummy functional blocks) into the CBL representation based on blank space data associated with the semiconductor die. The processing block 84 identifies multiple blocks (e.g., functional blocks) having physical connectivity constraints (e.g., the blocks will be placed adjacent to each other). The processing block 86 combines the multiple blocks into groups. In one example, the processing blocks 84 and 86 are repeated for multiple groups. In an embodiment, the processing block 88 performs a rotation analysis of the groups based on one or more of the multiple transient thermal responses. For example, the processing block 88 can use a genetic process (e.g., simulated annealing, reinforcement learning, etc.) to rotate each functional block and / or group according to four degrees of freedom (e.g., 0° rotation, 90° rotation, 180° rotation, 270° rotation) and evaluate the thermal response at each rotation angle. The rotation analysis can also include placement analysis (e.g., moving each functional block and / or group around the semiconductor die and evaluating the thermal response at each location).

[0045] After the rotation analysis, processing block 90 divides each group into a plurality of original functional blocks, where processing block 92 performs a symmetry analysis of the plurality of functional blocks based on one or more of the plurality of transient thermal responses. In one example, the symmetry analysis is performed according to a genetic process (e.g., simulated annealing, reinforcement learning, etc.) and four degrees of freedom, where the functional blocks are placed on both sides of the horizontal axis and both sides of the vertical axis, and the thermal response is evaluated for each placement. Thus, method 80 further enhances performance at least to the extent that the group, rotation analysis, and / or symmetry analysis improve the reliability of the (one or more) proposed layout plans.

[0046] Turning now to Figure 8 , a performance-enhanced computing system 280 is shown. System 280 can generally be part of an electronic device / platform having computing functionality (e.g., personal digital assistant / PDA, laptop computer, tablet computer, deformable tablet computer, edge node, server, cloud computing infrastructure), communication functionality (e.g., smart phone), imaging functionality (e.g., camera, video camera), media playback functionality (e.g., smart TV / TV), wearable functionality (e.g., watch, glasses, headgear, footwear, jewelry), vehicle functionality (e.g., car, truck, motorcycle), robotic functionality (e.g., autonomous robot), Internet of Things (IoT) functionality, drone functionality, or any combination thereof.

[0047] In the example shown, system 280 includes a host processor 282 (e.g., central processing unit / CPU) having an integrated memory controller (IMC) 284 coupled to a system memory 286 (e.g., dual in-line memory module / DIMM including multiple DRAMs). In an embodiment, an IO (input / output) module 288 is coupled to the host processor 282. The illustrated IO module 288 communicates with, for example, a display 290 (e.g., touch screen, liquid crystal display / LCD, light emitting diode / LED display), a mass storage device 302 (e.g., hard disk drive / HDD, optical disk, solid state drive / SSD), and a network controller 292 (e.g., wired and / or wireless). The host processor 282 can be combined with the IO module 288, a graphics processor 294, and an artificial intelligence (AI) accelerator 296 (e.g., a dedicated processor) into a system-on-chip (SoC) 298.

[0048] The host processor 282 and / or the AI accelerator 296 retrieve one or more executable program instructions 300 from the system memory 286 and / or the mass storage device 302 and execute the instructions 300 to perform the methods 70 ( Figure 6 ) and / or method 80 ( Figure 7) aspects of one or more. Thus, the execution of instruction 300 causes the host processor 282, the AI accelerator 296, and / or the computing system 280 to determine a plurality of thermal responses (e.g., transient thermal responses) corresponding to a plurality of power source locations on the semiconductor die (e.g., including buried power rails (BPR) and / or backside power delivery (BSPD) techniques), obtain a CBL representation associated with a plurality of candidate layout plans, and perform an AI-based search on the CBL representation, wherein the output of the AI-based search is one or more proposed layout plans having a transient thermal response below a thermal threshold.

[0049] Thus, the computing system 280 is considered performance-enhanced at least to the extent that the AI-based search enables thermal performance to be considered during the SoC design phase (e.g., as opposed to after the SoC design is complete). Additionally, performing the AI-based search on the CBL representation accelerates the optimization of the SoC layout plan, improves the reliability of the selected layout plan, and enables more complex layout plan options to be considered. Instruction 300 further enhances performance to the extent that group, rotation analysis, and / or symmetry analysis improve the reliability of the one or more proposed layout plans.

[0050] Figure 9 Illustrates a semiconductor device 350 (e.g., a chip, die, package). The illustrated device 350 includes one or more substrates 352 (e.g., silicon, sapphire, gallium arsenide) and logic 354 (e.g., a transistor array and other integrated circuit / IC components) coupled to the one or more substrates 352. In an embodiment, the logic 354 implements one or more aspects of the methods 70 ( Figure 6 ) and / or method 80 ( Figure 7 ). Thus, the logic 354 determines a plurality of thermal responses (e.g., transient thermal responses) corresponding to a plurality of power source locations on the semiconductor die, obtains a CBL representation associated with a plurality of candidate layout plans, and performs an AI-based search on the CBL representation, wherein the output of the AI-based search is one or more proposed layout plans having a transient thermal response below a thermal threshold.

[0051] The logic 354 may be implemented at least partially in configurable or fixed-functional hardware. In one example, the logic 354 includes transistor channel regions located (e.g., embedded) within the one or more substrates 352. Thus, the interface between the logic 354 and the one or more substrates 352 may not be a abrupt junction. The logic 354 may also be considered to include an epitaxial layer grown on an initial wafer of the one or more substrates 352.

[0052] Figure 10FIG. 0 shows a processor core 400 according to one embodiment. The processor core 400 may be a core of any type of processor (such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, or other device for executing code). Although only one processor core 400 is shown in Figure 10 , the processing elements may alternatively include more than one Figure 10 processor core 400 as shown. The processor core 400 may be a single-threaded core, or for at least one embodiment, the processor core 400 may be multi-threaded, as it may include more than one hardware thread context (or “logical processor”) per core.

[0053] Figure 10 Also shown is a memory 470 coupled to the processor core 400. The memory 470 may be any of a variety of memories (including the various levels of a memory hierarchy) known to those of ordinary skill in the art or otherwise available. The memory 470 may include one or more code 413 instructions to be executed by the processor core 400, where the code 413 may implement the methods 70 ( Figure 6 ) and / or method 80 ( Figure 7 ) that have been discussed. The processor core 400 follows a program sequence of instructions indicated by the code 413. Each instruction may enter a front-end portion 410 and be processed by one or more decoders 420. The decoder 420 may generate micro-operations (such as fixed-width micro-operations in a predefined format) as its output, or may generate other instructions, micro-instructions, or control signals that reflect the original code instruction. The illustrated front-end portion 410 also includes register renaming logic 425 and scheduling logic 430, which generally allocate resources and queue the operations corresponding to the translated instructions for execution.

[0054] The processor core 400 is shown as including execution logic 450 having a set of execution units 455-1 to 455-N. Some embodiments may include multiple execution units dedicated to a particular function or set of functions. Other embodiments may include only one execution unit or one execution unit that can perform a particular function. The illustrated execution logic 450 performs the operations specified by the code instructions.

[0055] After completion of execution of the operations specified by the code instructions, the backend logic 460 retires the instructions of the code 413. In one embodiment, the processor core 400 allows out-of-order execution, but requires in-order retirement of instructions. The retirement logic 465 can take various forms known to those skilled in the art (e.g., reorder buffer, etc.). In this manner, the processor core 400 is transformed during execution of the code 413 in terms of at least the output generated by the decoder, the hardware registers and tables utilized by the register renaming logic 425, and any registers (not shown) modified by the execution logic 450.

[0056] Although Figure 10 not shown in, the processing element may include other elements on the chip having the processor core 400. For example, the processing element may include memory control logic together with the processor core 400. The processing element may include I / O control logic and / or may include I / O control logic integrated with the memory control logic. The processing element may also include one or more caches.

[0057] Now referring to Figure 11 , shown is a block diagram of an embodiment of a computing system 1000 according to an embodiment. Figure 11 Shown in is a multiprocessor system 1000, which includes a first processing element 1070 and a second processing element 1080. Although two processing elements 1070 and 1080 are shown, it is to be understood that embodiments of the system 1000 may also include only one such processing element.

[0058] System 1000 is shown as a point-to-point interconnect system, in which the first processing element 1070 and the second processing element 1080 are coupled via a point-to-point interconnect 1050. It should be understood that Figure 11 any or all of the interconnects shown in may be implemented as a multi-drop bus instead of a point-to-point interconnect.

[0059] As Figure 11 shown in, each of the processing elements 1070 and 1080 may be a multi-core processor, including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b). Such cores 1074a, 1074b, 1084a, 1084b may be configured to execute instruction code in a manner similar to that discussed above in connection with Figure 10 discussion.

[0060] Each processing element 1070, 1080 may include at least one shared cache 1896a, 1896b. The shared caches 1896a, 1896b may store data (e.g., instructions) utilized by one or more components of the processor, such as cores 1074a, 1074b and 1084a, 1084b, respectively. For example, the shared caches 1896a, 1896b may locally cache data stored in memories 1032, 1034 for faster access by components of the processor. In one or more embodiments, the shared caches 1896a, 1896b may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4) or other levels of cache, last-level cache (LLC), and / or combinations thereof.

[0061] Although only two processing elements 1070, 1080 are shown, it is to be understood that the scope of the embodiments is not limited thereto. In other embodiments, one or more additional processing elements may be present in a given processor. Alternatively, one or more of the processing elements 1070, 1080 may be elements other than a processor, such as an accelerator or a field programmable gate array. For example, the additional processing element(s) may include one or more additional processors that are the same as the first processor 1070, one or more additional processors that are heterogeneous or asymmetric with respect to the first processor 1070, accelerators (such as, for example, a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array, or any other processing element. There may be various differences between the processing elements 1070, 1080 in terms of a range of quality metrics including architecture, microarchitecture, thermal, power consumption characteristics, etc. These differences themselves may effectively manifest as asymmetry and heterogeneity between the processing elements 1070, 1080. For at least one embodiment, the various processing elements 1070, 1080 may reside in the same die package.

[0062] The first processing element 1070 may further include memory controller logic (MC) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, the second processing element 1080 may include MC 1082 and P-P interfaces 1086 and 1088. As Figure 11 shown, MCs 1072 and 1082 couple the processors to the respective memories, i.e., memory 1032 and memory 1034, which may be part of the main memory locally attached to the respective processors. Although MCs 1072 and 1082 are shown as integrated into the processing elements 1070, 1080, for alternative embodiments, the MC logic may be discrete logic external to the processing elements 1070, 1080 rather than integrated therein.

[0063] The first processing element 1070 and the second processing element 1080 can be coupled to the I / O subsystem 1090 via P-P interconnections 1076 and 1086, respectively. As Figure 11 shown, the I / O subsystem 1090 includes P-P interfaces 1094 and 1098. In addition, the I / O subsystem 1090 includes an interface 1092 for coupling the I / O subsystem 1090 to the high-performance graphics engine 1038. In one embodiment, the bus 1049 can be used to couple the graphics engine 1038 to the I / O subsystem 1090. Alternatively, point-to-point interconnections can couple these components.

[0064] Furthermore, the I / O subsystem 1090 can be coupled to the first bus 1016 via an interface 1096. In one embodiment, the first bus 1016 can be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third-generation I / O interconnect bus, although the scope of the embodiments is not limited thereto.

[0065] As Figure 11 shown, various I / O devices 1014 (e.g., a biometric scanner, a speaker, a camera, a sensor) can be coupled to the first bus 1016, along with a bus bridge 1018 that can couple the first bus 1016 to the second bus 1020. In one embodiment, the second bus 1020 can be a Low Pin Count (LPC) bus. In one embodiment, various devices can be coupled to the second bus 1020, including, for example, a keyboard / mouse 1012, one or more communication devices 1026, and a data storage unit 1019, such as a disk drive or other mass storage device that can include code 1030. The code 1030 shown can implement the methods 70 ( Figure 6 ) and / or method 80 ( Figure 7 ). In addition, audio I / O 1024 can be coupled to the second bus 1020, and the battery 1010 can supply power to the computing system 1000.

[0066] Note that other embodiments are also contemplated. For example, instead of Figure 11 the point-to-point architecture, the system can implement a multi-drop bus or another such communication topology. In addition, Figure 11 the components of Figure 11 can alternatively be partitioned using more or fewer integrated chips than shown in

[0067] Additional Notes and Examples:

[0068] Example 1 includes a performance-enhanced computing system, including a network controller, a processor coupled to the network controller, and a memory coupled to the processor, wherein the memory includes one or more executable program instructions that, when executed by the processor, cause the processor to determine a plurality of transient thermal responses at corresponding plurality of power source locations on a semiconductor die, obtain a corner block list (CBL) representation associated with a plurality of candidate layout plans, and perform an artificial intelligence (AI)-based search on the CBL representation, wherein the output of the AI-based search is one or more proposed layout plans having transient thermal responses below a thermal threshold.

[0069] Example 2 includes the computing system of Example 1, wherein the one or more executable program instructions, when executed, further cause the processor to identify a plurality of blocks having physical connectivity constraints and combine the plurality of blocks into groups.

[0070] Example 3 includes the computing system of Example 2, wherein the one or more executable instructions, when executed, further cause the processor to perform a rotation analysis on the groups based on one or more of the plurality of transient thermal responses.

[0071] Example 4 includes the computing system of Example 3, wherein the one or more executable instructions, when executed, further cause the processor to, after the rotation analysis, split the groups into the plurality of blocks and perform a symmetry analysis on the plurality of blocks based on one or more of the plurality of transient thermal responses.

[0072] Example 5 includes the computing system of any one of Examples 1 to 4, wherein the one or more executable instructions, when executed, further cause the processor to insert one or more dummy blocks into the CBL representation based on blank space data associated with the semiconductor die.

[0073] Example 6 includes at least one computer-readable storage medium including one or more executable program instructions that, when executed by a computing system, cause the computing system to determine a plurality of transient thermal responses at corresponding plurality of power source locations on a semiconductor die, obtain a corner block list (CBL) representation associated with a plurality of candidate layout plans, and perform an artificial intelligence (AI)-based search on the CBL representation, wherein the output of the AI-based search is one or more proposed layout plans having transient thermal responses below a thermal threshold.

[0074] Example 7 includes at least one computer-readable storage medium as described in Example 6, wherein when the one or more executable program instructions are executed, the computing system is further caused to identify a plurality of blocks having physical connectivity constraints and to combine the plurality of blocks into groups.

[0075] Example 8 includes at least one computer-readable storage medium as described in Example 7, wherein when the one or more executable instructions are executed, the computing system is further caused to perform a rotation analysis on the group based on one or more of the plurality of transient thermal responses.

[0076] Example 9 includes at least one computer-readable storage medium as described in Example 8, wherein when the one or more executable instructions are executed, the computing system is further caused to, after the rotation analysis, split the group into the plurality of blocks and to perform a symmetry analysis on the plurality of blocks based on one or more of the plurality of transient thermal responses.

[0077] Example 10 includes at least one computer-readable storage medium as described in Example 6, wherein when the one or more executable instructions are executed, the computing system is further caused to insert one or more dummy blocks into the CBL representation based on blank space data associated with the semiconductor die.

[0078] Example 11 includes at least one computer-readable storage medium as described in any one of Examples 6 to 10, wherein the AI-based search includes one or more simulated annealing operations.

[0079] Example 12 includes at least one computer-readable storage medium as described in any one of Examples 6 to 10, wherein the AI-based search includes one or more reinforcement learning operations.

[0080] Example 13 includes a semiconductor device including one or more substrates and logic coupled to the one or more substrates, wherein the logic is at least partially implemented in one or more of configurable or fixed functionality hardware, the logic for determining a plurality of transient thermal responses at corresponding plurality of power source locations on a semiconductor die, obtaining a corner block list (CBL) representation associated with a plurality of candidate floorplans, and performing an artificial intelligence (AI)-based search on the CBL representation, wherein the output of the AI-based search is one or more proposed floorplans having transient thermal responses below a thermal threshold.

[0081] Example 14 includes the semiconductor device as described in Example 13, wherein the logic is further for identifying a plurality of blocks having physical connectivity constraints and for combining the plurality of blocks into groups.

[0082] Example 15 includes the semiconductor device described in Example 14, wherein the logic is further configured to perform a rotation analysis on the group based on one or more of the plurality of transient thermal responses.

[0083] Example 16 includes the semiconductor device described in Example 15, wherein the logic is further configured to, after the rotation analysis, split the group into the plurality of blocks and perform a symmetry analysis on the plurality of blocks based on one or more of the plurality of transient thermal responses.

[0084] Example 17 includes the semiconductor device described in Example 13, wherein the logic is further configured to insert one or more dummy blocks into the CBL representation based on blank space data associated with the semiconductor die.

[0085] Example 18 includes the semiconductor device described in any one of Examples 13 to 17, wherein the AI-based search includes one or more simulated annealing operations.

[0086] Example 19 includes the semiconductor device described in any one of Examples 13 to 17, wherein the AI-based search includes one or more reinforcement learning operations.

[0087] Example 20 includes the semiconductor device described in any one of Examples 13 to 19, wherein the logic coupled to the one or more substrates includes transistor channel regions located within the one or more substrates.

[0088] Example 21 includes a method of operating a computationally enhanced system, the method including determining a plurality of transient thermal responses corresponding to a plurality of power source locations on a semiconductor die, obtaining a corner block list (CBL) representation associated with a plurality of candidate floorplans, and performing an artificial intelligence (AI)-based search on the CBL representation, wherein an output of the AI-based search is one or more proposed floorplans having a transient thermal response below a thermal threshold.

[0089] Example 22 includes an apparatus including components for performing the method described in Example 21.

[0090] An embodiment can be implemented in one or more modules as a set of logical instructions stored in a machine or computer-readable storage medium such as random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in hardware, or any combination thereof. For example, a hardware implementation can include configurable logic, fixed-functional logic, or any combination thereof. Examples of configurable logic (e.g., configurable hardware) include a properly configured programmable logic array (PLA), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), and a general-purpose microprocessor. Examples of fixed-functional logic (e.g., fixed-functional hardware) include a properly configured application-specific integrated circuit (ASIC), combinational logic circuits, and sequential logic circuits. The configurable or fixed-functional logic can be implemented using complementary metal-oxide semiconductor (CMOS) logic circuits, transistor-transistor logic (TTL) logic circuits, or other circuits.

[0091] Example sizes / models / values / ranges may have been given, but the embodiments are not limited thereto. As manufacturing technologies (e.g., lithography) mature over time, it is expected that devices of smaller sizes can be manufactured. Additionally, for the sake of simplicity of illustration and discussion, and in order not to obscure certain aspects of the embodiments, well-known power / ground connections to the IC chip and other components may or may not be shown in the figures. Further, the arrangements may be shown in block diagram form in order not to obscure the embodiments, and also in view of the fact that details regarding the implementation of such block diagram arrangements highly depend on the computing system in which the embodiments will be implemented, i.e., such details should be entirely within the purview of those skilled in the art. In cases where specific details (e.g., circuits) are set forth in order to describe example embodiments, those skilled in the art should appreciate that the embodiments can be practiced without these specific details or with variations of these specific details. Accordingly, the description is to be regarded as illustrative rather than restrictive.

[0092] The term "coupled" can be used herein to refer to any type of direct or indirect relationship between the components being discussed, and can apply to electrical, mechanical, fluidic, optical, electromagnetic, electromechanical, or other connections. Additionally, unless otherwise indicated, the terms "first", "second", etc. may be used herein solely for convenience of discussion and do not carry a particular temporal or chronological significance.

[0093] As used in this application and in the claims, a list of items joined by the term "one or more" can represent any combination of the listed terms. For example, the phrase "one or more of A, B, or C" can represent A; B; C; A and B; A and C; B and C; or A, B, and C.

[0094] Those skilled in the art will appreciate from the foregoing description that the broad techniques of the embodiments can be implemented in various forms. Accordingly, while the embodiments have been described in connection with their specific examples, the true scope of the embodiments should not be so limited, as other modifications will become apparent to those skilled in the art upon study of the drawings, the specification, and the appended claims.

Claims

1. A computing system comprising: Network controller; a processor coupled to the network controller; as well as a memory coupled to the processor, wherein the memory includes one or more executable program instructions that, when executed by the processor, cause the processor to: determining a plurality of transient thermal responses corresponding to a plurality of power source locations on the semiconductor die, obtaining a corner block list (CBL) representation associated with a plurality of candidate floorplans, and An artificial intelligence (AI) based search is performed on the CBL representation, wherein an output of the AI ​​based search is one or more suggested floorplans having a transient thermal response below a thermal threshold.

2. The computing system of claim 1, wherein: The one or more executable program instructions, when executed, further cause the processor to: Identify multiple blocks with physical connectivity constraints, and The plurality of blocks are combined into groups.

3. The computing system of claim 2, wherein: The one or more executable instructions, when executed, further cause the processor to perform a rotational analysis on the group based on one or more of the plurality of transient thermal responses.

4. The computing system of claim 3, wherein: The one or more executable instructions, when executed, further cause the processor to: After the rotation analysis, splitting the group into the plurality of blocks; and A symmetry analysis is performed on the plurality of blocks based on one or more of the plurality of transient thermal responses.

5. The computing system according to any one of claims 1 to 4, wherein: The one or more executable instructions, when executed, further cause the processor to insert one or more dummy blocks into the CBL representation based on white space data associated with the semiconductor die.

6. At least one computer-readable storage medium comprising one or more executable program instructions, which, when executed by a computing system, cause the computing system to: determining a plurality of transient thermal responses corresponding to a plurality of power source locations on the semiconductor die; obtaining a corner block list (CBL) representation associated with a plurality of candidate floorplans; and An artificial intelligence (AI) based search is performed on the CBL representation, wherein: The output of the AI-based search is one or more suggested floorplans having a transient thermal response below a thermal threshold.

7. The at least one computer-readable storage medium of claim 6, wherein: The one or more executable program instructions, when executed, further cause the computing system to: identifying a plurality of blocks having physical connectivity constraints; and The plurality of blocks are combined into groups.

8. The at least one computer-readable storage medium of claim 7, wherein: The one or more executable instructions, when executed, further cause the computing system to perform a rotational analysis on the group based on one or more of the plurality of transient thermal responses.

9. The at least one computer-readable storage medium of claim 8, wherein: The one or more executable instructions, when executed, further cause the computing system to: After the rotation analysis, splitting the group into the plurality of blocks; and A symmetry analysis is performed on the plurality of blocks based on one or more of the plurality of transient thermal responses.

10. The at least one computer-readable storage medium of claim 6, wherein: The one or more executable instructions, when executed, further cause the computing system to insert one or more dummy blocks into the CBL representation based on white space data associated with the semiconductor die.

11. At least one computer-readable storage medium according to any one of claims 6 to 10, wherein: The AI-based search includes one or more simulated annealing operations.

12. At least one computer-readable storage medium according to any one of claims 6 to 10, wherein: The AI-based search includes one or more reinforcement learning operations.

13. A semiconductor device comprising: one or more substrates; as well as Logic coupled to the one or more substrates, wherein the logic is implemented at least in part in one or more of configurable or fixed functionality hardware, the logic to: determining a plurality of transient thermal responses corresponding to a plurality of power source locations on the semiconductor die; obtaining a corner block list (CBL) representation associated with a plurality of candidate floorplans; and An artificial intelligence (AI) based search is performed on the CBL representation, wherein an output of the AI ​​based search is one or more suggested floorplans having a transient thermal response below a thermal threshold.

14. The semiconductor device according to claim 13, wherein: The logic is also used to: identifying a plurality of blocks having physical connectivity constraints; and The plurality of blocks are combined into groups.

15. The semiconductor device according to claim 14, wherein: The logic is further configured to perform a rotational analysis on the group based on one or more of the plurality of transient thermal responses.

16. The semiconductor device according to claim 15, wherein: The logic is also used to: After the rotation analysis, splitting the group into the plurality of blocks; and A symmetry analysis is performed on the plurality of blocks based on one or more of the plurality of transient thermal responses.

17. The semiconductor device according to claim 13, wherein: The logic is also for inserting one or more dummy blocks into the CBL representation based on white space data associated with the semiconductor die.

18. The semiconductor device according to any one of claims 13 to 17, wherein: The AI-based search includes one or more simulated annealing operations.

19. The semiconductor device according to any one of claims 13 to 17, wherein: The AI-based search includes one or more reinforcement learning operations.

20. The semiconductor device according to any one of claims 13 to 17, wherein: The logic coupled to the one or more substrates includes a transistor channel region within the one or more substrates.

21. A method of operating a computing system with enhanced performance, the method comprising: determining a plurality of transient thermal responses corresponding to a plurality of power source locations on the semiconductor die, obtaining a corner block list (CBL) representation associated with a plurality of candidate floorplans, and An artificial intelligence (AI) based search is performed on the CBL representation, wherein an output of the AI ​​based search is one or more suggested floorplans having a transient thermal response below a thermal threshold.

22. The method according to claim 21, further comprising: identifying a plurality of blocks having physical connectivity constraints; as well as The plurality of blocks are combined into groups.

23. The method of claim 22, further comprising performing a rotational analysis on the group based on one or more of the plurality of transient thermal responses.

24. The method according to claim 23, further comprising: After the rotation analysis, splitting the group into the plurality of blocks; as well as A symmetry analysis is performed on the plurality of blocks based on one or more of the plurality of transient thermal responses.

25. The method of any of claims 21-24, further comprising inserting one or more dummy blocks into the CBL representation based on white space data associated with the semiconductor die.

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