Edge-end-oriented low-power-consumption infrared intelligent sensing chip and image processing method

Abstract

The invention discloses a low-power-consumption infrared intelligent sensing chip facing an edge end and an image processing method, and the chip comprises a transconductance amplifier circuit which converts a light current generated by an infrared detector into a voltage signal, and comprises a switchable reset mode and an integral mode; the binary neural network analog calculation circuit is connected with the output end of the transconductance amplifier circuit to realize analog domain multiply-accumulate operation; the weight storage circuit is directly in hard connection with the binary neural network analog calculation circuit by adopting a nonvolatile memory unit, and supports weight real-time loading of a neural network calculation phase; and the comparator linear activation circuit is used for executing a time sequence control module for dynamically coordinating the phase switching of each circuit at the activation output phase, so that the photocurrent integration, the neural network calculation and the activation output three-phase sequence are executed to reduce the time overlapping rate. The infrared intelligent sensing chip and the image processing method provided by the invention are higher in intelligence, higher in integration level and lower in power consumption.

Description

Technical Field

[0001] The present invention belongs to the field of infrared image processing methods, and particularly relates to a low-power infrared intelligent sensing chip and an image processing method for the edge side. Background Art

[0002] With the rapid development of infrared technology and artificial intelligence, intelligent infrared technology is highly demanded. Among them, low-power intelligent infrared chips that can be deployed on the edge side are one of the important development directions. However, the existing infrared intelligent sensing systems have problems such as high power consumption, low frame rate, and slow processing speed. Research shows that directly performing on-chip preprocessing on the image information after the infrared sensor on the chip obtains the image data avoids the use of a high-performance processing chip in the subsequent process, significantly reducing the overall system power consumption and improving the processing speed at the same time. This on-chip preprocessing infrared intelligent vision sensing architecture provides a new idea for deploying infrared intelligent chips on the edge side in the future.

[0003] The implementation of an infrared intelligent chip requires preprocessing of infrared image information. In 2016, Glauco et al. from New Mexico State University designed and published an infrared image region vision enhancement chip in the TCAS-I journal, which visually enhanced the infrared image region by changing the bias of the readout circuit. In 2016, Sechang Oh et al. from Michigan State University designed and published a low-power infrared motion detection chip in the VLSI conference. This chip used a wake-up trigger technology to process the infrared motion image information and achieved low-power detection. In 2024, Yanwen Su et al. from Huazhong University of Science and Technology designed and published a perception chip based on infrared vision drive in the TCAS-II journal. Due to the characteristics of its vision drive circuit, the processing speed of this chip can be extremely high, reaching thousands of frames.

[0004] Although the above-mentioned infrared intelligent chips with preprocessing functions are expected to be deployed in the infrared intelligent sensing system on the edge side. However, the existing chip architectures still have a large room for improvement in terms of power consumption, frame rate processing speed, intelligence, etc., and cannot reach a relatively high level simultaneously: 1) There are problems with power consumption and frame rate: Although existing work can reach a relatively high level in one of the aspects of power consumption and speed, the two indicators still cannot be at a relatively high level simultaneously. The problems with power consumption and frame rate are described separately below.

[0005] a) A large amount of static current bias circuits are introduced due to readout and intelligent processing, which makes the chip power consumption large, resulting in problems that the infrared intelligent chip deployed on the edge side still cannot work for a long time, and it is frequent and difficult to replace the battery.

[0006] b) Since the existing chip architectures often convert analog image information into digital information through ADC and input it into the DSP module for processing, the processing time is wasted in the process of information conversion and transmission, which results in a relatively slow infrared sensing speed and a low frame rate.

[0007] 2) Intelligence problem: The definition of intelligence is whether more information can be extracted after obtaining information. The amount of information obtained by the existing work is relatively small.

[0008] a) The visual enhancement of the infrared image processing chip only processes the image information without obtaining new information, so the intelligence is insufficient.

[0009] b) The infrared motion detection chip can obtain information about whether there is an object in motion and uses the wake-up technology to make the overall power consumption relatively low, achieving great progress in power consumption. However, the amount of information obtained is small, and only two types of information, "motion" and "non-motion", are obtained, so the intelligence is still insufficient.

[0010] c) The infrared sensing chip based on infrared vision drive uses an adaptive threshold voltage generation circuit and performs infrared intelligent sensing through event drive. Similar to the motion detection chip, since it is event-driven, only two types of information, whether there is an event or not, are obtained, so the intelligence is insufficient. Summary of the Invention

[0011] The first object of the present invention is to provide a low-power infrared intelligent sensing chip for the edge side in view of the problems in the prior art.

[0012] To achieve the above object, the present invention adopts the following technical solutions: The low-power infrared intelligent sensing chip for the edge side includes: A transconductance amplifier circuit that converts the photocurrent generated by the infrared detector into a voltage signal and includes a switchable reset mode and integration mode; A binary neural network analog computing circuit connected to the output end of the transconductance amplifier circuit to implement analog domain multiply-accumulate operations: Reset phase: Clearing the charge of the computing capacitor array through M8 / M9 transistors; Multiply-accumulate phase: Alternately turning on M1 / M2 transistors to complete double sampling, and synchronously introducing binary weights by driving M3-M6 transistors by the weight storage circuit; Fully connected phase: Closing the charge averaging switch to complete charge sharing and perform full connection; A weight storage circuit that uses non-volatile memory cells and is directly connected to the binary neural network analog computing circuit to support real-time acquisition of weights during the neural network computing phase; A comparator linear activation circuit that quantifies the multiply-accumulate result: Pre - charge: Charge the load capacitance to VDD; Compare and quantize: Output binary classification and quantization results through a dynamic comparator; A timing control module controls the phase switching of the circuit, enabling the three - phase sequence execution of photocurrent integration, neural network calculation, and activation output to reduce the time overlap rate.

[0013] While adopting the above - mentioned technical solutions, the present invention can also adopt or combine the following technical solutions: As a preferred technical solution of the present invention: The transconductance amplifier circuit includes: A programmable integration capacitor array with a capacitance value configuration range of 50fF - 200fF; A reset switch that clears the charge of the integration capacitor during the reset phase; A dynamic bias circuit that self - adjusts the transconductance gain according to the input photocurrent intensity.

[0014] As a preferred technical solution of the present invention: The binary neural network analog computing circuit includes: A dual - sampling switch array that eliminates the threshold voltage mismatch of MOS transistors; A weight control switch array directly driven by a weight storage circuit; A configurable computing capacitor array that supports processing of pixel scales from 4×4 to 32×32; A charge averaging switch network that realizes fully - connected operations in the analog domain.

[0015] As a preferred technical solution of the present invention: In the multiply - accumulate phase, the binary neural network analog computing circuit realizes dual - sampling operations by alternately turning on M1 / M2 transistors: When M1 transistor is turned on, the positive phase of the input voltage signal is sampled and temporarily stored in the first sampling capacitor, and when M2 transistor is turned on, the negative phase signal is sampled into the second sampling capacitor to eliminate the error introduced by the threshold voltage mismatch of MOS transistors; Synchronously, the weight storage circuit dynamically drives the conduction combination of M3 - M6 transistors according to the pre - trained binary weights (+1 / -1) - when the weight is +1, M3 / M6 transistors are turned on to inject the sampled charge positively into the computing capacitor array, and when the weight is -1, M4 / M5 transistors are turned on to achieve reverse charge injection, thus directly completing the multiply - accumulate operation of "voltage sampling × binary weight" in the analog domain. Through hard - wired connection, the weight can be loaded with zero delay <1ns, and the charge injection amount is strictly matched with the weight polarity. Finally, an analog voltage signal equivalent to the neural network multiply - accumulate operation is formed on the computing capacitor array.

[0016] As a preferred technical solution of the present invention: the comparator linear activation circuit adopts three-phase timing control to achieve efficient non-linear activation: in the enable phase, the power switch completely cuts off the circuit power supply to achieve zero static power consumption; after entering the pre-charge phase, the control charging network charges the load capacitor to the VDD reference level and stabilizes the common-mode operating point through the differential pair transistors; finally, in the linear activation phase, the positive feedback comparator with an adjustable hysteresis window performs non-linear transformation on the input signal, and its cross-coupled transistor pair M17-M18 generates a voltage conversion characteristic similar to the Sigmoid function. At the same time, the output stage push-pull structure ensures that the rail-to-rail swing is completed within 20 ns. Through the capacitance coupling and positive feedback cooperation mechanism, while realizing the neural network activation function, the dynamic energy consumption is reduced to 0.05 pJ per activation.

[0017] As a preferred technical solution of the present invention: the comparator linear activation circuit described above: The adjustable range of the activation threshold voltage is ±200 mV; The response time < 20 ns @ 0.5 pF load.

[0018] The second object of the present invention is to provide an infrared image processing method for solving the problems in the prior art.

[0019] To achieve this, the above object of the present invention is realized through the following technical solutions: An infrared image processing method, which is realized based on a low-power infrared intelligent sensing chip at the edge end, includes the steps: S1. Photoelectric conversion stage: Integrate the photocurrent into a voltage signal through a transconductance amplifier; S2. Feature extraction stage: Complete the multiply-accumulate operation of the binary neural network in the analog domain; S3. Linear activation stage: Use a dynamic comparator to output the classification result.

[0020] While adopting the above technical solutions, the present invention can also adopt or combine the following technical solutions: As a preferred technical solution of the present invention: in the photoelectric conversion stage, the photocurrent generated by the infrared detector is integrated by a dynamic bias transconductance amplifier and converted into a voltage signal in the range of 0.3 - 0.7VDD, where the value of the integration capacitor is programmable to adapt to different lighting conditions.

[0021] As a preferred technical solution of the present invention: in the feature extraction stage, use the analog domain binary neural network for processing, eliminate the device mismatch error through the double sampling of M1 / M2 transistors, and cooperate with the M3-M6 transistor array directly driven by the weight storage circuit to realize the analog multiply-accumulate operation on the computing capacitor.

[0022] As a preferred technical solution of the present invention: in the decision output stage, after the dynamic comparator is precharged to the VDD reference, the positive feedback comparator with an adjustable hysteresis window is used to complete the non-linear activation, and the binary classification result is output.

[0023] Compared with the prior art, the low-power infrared intelligent sensing chip and image processing method for edge devices of the present invention have the following beneficial effects: through the innovative chip architecture and collaborative algorithm, the present invention successfully solves the problems of high power consumption restricting the battery life, large data processing delay, and insufficient intelligence of the traditional infrared sensing architecture in the edge deployment of the infrared intelligent sensing system, and achieves a breakthrough innovation in the field of infrared intelligent sensing edge computing: First, the innovation of improved intelligence: The programmable binary neural network (BNN) analog computing unit is integrated in a single infrared sensing chip for the first time to realize the integrated design of sensing and computing. This architecture supports parallel processing of 32×32 pixels, and realizes the fully connected operation in the analog domain through the innovative charge sharing technology, solves the problem that the existing infrared intelligent chips cannot extract new information or extract less information from infrared images, and can realize the recognition of infrared handwritten digits. The calculation delay is low, and the energy consumption per single calculation is low within the same calculation time; Second, the technical breakthrough in power consumption optimization: The dynamic biasing technology of the transconductance amplifier circuit is used to solve the problem of excessive power consumption in the photoelectric conversion link of the traditional infrared sensing system. By adopting the switchable reset / integration dual-phase working mode, the integration phase is only started when the photocurrent is input, avoiding the waste of continuous bias current; The charge domain operation of the binary neural network analog computing circuit is used to solve the problem of low energy efficiency of digital domain MAC operations: the M1 / M2 transistor double sampling is used to eliminate the static power consumption, and the multiply-accumulate operation is directly completed in the analog domain. The weight direct connection architecture eliminates the storage access overhead, realizing high operation energy efficiency; The precise phase management of the timing control module is used to solve the problem of system-level static power consumption accumulation: by enabling the comparator circuit to be powered only in the activation stage, and strictly isolating the integration-computation-activation three phases in time sequence, the reduction of both static power consumption and dynamic power consumption is realized; Through the above-mentioned synergistic effects, the total power consumption of single-pin processing is reduced, the energy efficiency ratio is greatly improved, and the breakthrough low-power effect is achieved.

[0024] The present invention innovatively proposes an all-analog-domain infrared intelligent sensing chip architecture, which realizes a revolutionary innovation in edge computing through three major core technology breakthroughs: First, a sensing-computing integrated design that directly couples a transconductance amplifier with a binary neural network analog computing circuit is adopted, completely avoiding the analog-to-digital conversion link, reducing the power consumption of photocurrent processing by several orders of magnitude; Second, a multiplexed dual-sampling multiply-accumulate circuit (M1-M6 transistor array) realizes binary fully-connected neural network computing in the analog domain, achieving a multiple-fold improvement in computing energy efficiency; Finally, a dynamic power management is realized through a timing control module with ns-level accuracy, making the static power consumption lower than 10 μW, providing a low-power infrared intelligent sensing chip and an image processing method for edge devices with higher intelligence, higher integration, and lower power consumption, which has great application prospects in technical fields such as industry and consumer electronics. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic structural diagram of the architecture of the low-power infrared intelligent sensing chip for edge devices of the present invention; Figure 2 It is a schematic diagram of the binary neural network analog computing circuit of the present invention; Figure 3 It is a schematic diagram of the weight storage circuit of the present invention; Figure 4 It is a schematic diagram of the comparator linear activation circuit of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] The present invention will be further described in detail with reference to the accompanying drawings and specific embodiments.

[0027] The low-power infrared intelligent sensing chip for edge devices of the present invention includes: A transconductance amplifier circuit that converts the photocurrent generated by an infrared detector into a voltage signal, including a switchable reset mode and integration mode; A binary neural network analog computing circuit connected to the output end of the transconductance amplifier circuit to realize analog-domain multiply-accumulate operations: Reset phase: Clearing the charge of the computing capacitor array through M8 / M9 transistors; Multiply-accumulate phase: Alternately turning on M1 / M2 transistors to complete dual sampling, and synchronously introducing binary weights by M3-M6 transistors driven by the weight storage circuit; Fully-connected phase: Closing the charge averaging switch to complete charge sharing and perform full connection; A weight storage circuit that uses non-volatile memory cells directly connected to the binary neural network analog computing circuit to support real-time acquisition of weights during the neural network computing phase; A comparator linear activation circuit that quantifies the multiply-accumulate result: Pre-charging: Charging the load capacitor to VDD; Comparison quantization: Output binary classification and quantize the result through a dynamic comparator. A timing control module controls the phase switching of the circuit, enabling the three-phase sequential execution of photocurrent integration, neural network calculation, and activation output to reduce the time overlap rate.

[0028] The transconductance amplifier circuit includes: A programmable integration capacitor array with a capacitance value configuration range of 50fF - 200fF; A reset switch that clears the charge of the integration capacitor during the reset phase; A dynamic bias circuit that self-adjusts the transconductance gain according to the input photocurrent intensity.

[0029] The binary neural network analog computing circuit includes: A dual-sampling switch array that eliminates the MOS transistor threshold voltage mismatch; A weight control switch array directly driven by the weight storage circuit; A configurable computing capacitor array that supports processing of pixel scales from 4×4 to 32×32; A charge averaging switch network that realizes fully connected operations in the analog domain.

[0030] In the multiply-accumulate phase, the binary neural network analog computing circuit realizes dual-sampling operations by alternately turning on the M1 / M2 transistors: when the M1 transistor is turned on, the positive phase of the input voltage signal is sampled and temporarily stored in the first sampling capacitor, and when the M2 transistor is turned on, the negative phase signal is sampled into the second sampling capacitor to eliminate the error introduced by the MOS transistor threshold voltage mismatch; synchronously, the weight storage circuit dynamically drives the conduction combination of the M3 - M6 transistors according to the pre-trained binary weights (+1 / -1) - when the weight is +1, the M3 / M6 transistors are turned on to inject the sampling charge positively into the computing capacitor array, and when the weight is -1, the M4 / M5 transistors are turned on to achieve reverse charge injection, thus directly completing the multiply-accumulate operation of "voltage sampling × binary weight" in the analog domain. The weight is loaded with zero delay <1ns through hard-wired connection, and the charge injection amount strictly matches the weight polarity, finally forming an analog voltage signal equivalent to the neural network multiply-accumulate operation on the computing capacitor array.

[0031] The comparator linear activation circuit adopts three-phase timing control to achieve efficient non-linear activation: in the enable phase, the power switch tube completely cuts off the circuit power supply to achieve zero static power consumption; after entering the pre-charge phase, the control charging network charges the load capacitor to the VDD / 2 reference level and stabilizes the common-mode operating point through the differential pair transistors; finally, in the linear activation phase, the positive feedback comparator with an adjustable hysteresis window performs non-linear transformation on the input signal. Its cross-coupled transistor pair M17-M18 generates a voltage conversion characteristic similar to the Sigmoid function. At the same time, the output stage push-pull structure ensures that the rail-to-rail swing is completed within 20 ns. Through the capacitive coupling and positive feedback cooperation mechanism, while realizing the neural network activation function, the dynamic energy consumption is reduced to 0.05 pJ per activation.

[0032] As a preferred technical solution of the present invention: the comparator linear activation circuit: The adjustable range of the activation threshold voltage is ±200 mV; The response time < 20 ns @ 0.5 pF load.

[0033] An infrared image processing method provided by the present invention is implemented based on a low-power infrared intelligent sensing chip at the edge end, including the steps: S1. Photoelectric conversion stage: Integrate the photocurrent into a voltage signal through a transconductance amplifier; S2. Feature extraction stage: Complete the multiply-accumulate operation of the binary neural network in the analog domain; S3. Linear activation stage: Use a dynamic comparator to output the classification result.

[0034] In the photoelectric conversion stage, the photocurrent generated by the infrared detector is integrally processed by a dynamic bias transconductance amplifier and converted into a voltage signal in the range of 0.3 - 0.7VDD. The value of the integration capacitor is programmable to adapt to different lighting conditions.

[0035] In the feature extraction stage, analog domain binary neural network processing is adopted. The device mismatch error is eliminated by double sampling of M1 / M2 transistors, and the M3 - M6 transistor array directly driven by the weight storage circuit is used to realize the analog multiply-accumulate operation on the computing capacitor.

[0036] In the decision output stage, after the dynamic comparator is pre-charged to the VDD / 2 reference, the positive feedback comparator with an adjustable hysteresis window is used to complete non-linear activation and output the binary classification result.

[0037] The low-power infrared intelligent perception chip and image processing method for the edge side of the present invention significantly improve the intelligence of the infrared intelligent system and reduce the power consumption, which is more conducive to being deployed in devices and scenarios at the edge side. Through simulation on EDA simulation software platforms such as Cadence Virtuoso, the chip architecture can implement the calculation of a one-layer binary fully-connected neural network, and the calculation result can be used as the output result of the first layer of infrared image classification. The power consumption is 2-3 orders of magnitude lower than that of other infrared perception systems. Compared with other infrared chips and systems, it has higher intelligence, higher integration, and lower power consumption: 1. The new architecture of the fully analog-domain infrared intelligent perception chip: Avoiding the use of analog-to-digital converters effectively reduces the overall power consumption. At the same time, it also avoids the conversion time and improves the processing speed and frame rate.

[0038] 2. By designing a reused dual-sampled multiply-accumulate fully-connected neural network calculation unit circuit, the on-chip infrared image recognition is realized.

[0039] Embodiment 1 In order to better deploy the intelligent infrared vision perception chip at the edge side, the present invention first proposes a low-power infrared intelligent perception chip for the edge side, providing a low-power infrared intelligent perception chip architecture, as shown in Figure 1 shown. This architecture includes a transconductance amplifier circuit, a binary neural network analog calculation circuit, a weight storage circuit, and a comparator linear activation circuit. The working mode of this architecture is as follows: The infrared detector detects the infrared image information and converts the radiation information into photocurrent through the photoelectric effect, and then inputs the photocurrent into the infrared vision intelligent perception chip. First, it passes through the transconductance amplifier circuit. The transconductance amplifier has two working phases. When no photocurrent is input, the reset phase switch is closed. When the photocurrent is input, the transconductance amplifier enters the integration phase, and the photocurrent will be integrated on the integration capacitor to linearly convert the current signal into a voltage signal. The voltage signal is input into the binary neural network analog calculation circuit, as shown in Figure 2 shown. This circuit has three working phases, namely: the reset phase, the multiply-accumulate calculation phase, and the fully-connected phase. Reset phase: Before starting the calculation, first perform the reset phase. Transistors M8 and M9 are turned on to empty and reset the charge of the calculation capacitor array. Multiply-accumulate calculation phase: The read voltage signal is input into the calculation circuit. Transistors M1 and M2 will be turned on in sequence to perform dual sampling on the voltage signal. At the same time, the weight storage unit, as shown in Figure 3As shown, the weight signals of the entire network will be directly connected to the binary neural network analog computing circuit to save the time and power consumption of read / write transmission. The weight signals will turn on transistors M3, M4, M5, and M6 according to the trained network weights, and import their double-sampled signals into the computing capacitor array respectively. Since the double-sampling operation and the binary neural network are similar in mathematical form. Therefore, this step realizes the first layer of multiply-accumulate operation of the binary neural network. Fully connected phase: After the signals of all pixels are input into the computing capacitor array through the sampling switch, the charge averaging switch will be closed for full connection to average the charges. After the calculation is completed, the calculation result will be output to the comparator linear activation circuit, as Figure 4 shown. This circuit has three working phases, namely: enable phase, pre-charge phase, and linear activation phase. Enable phase: When the calculation is not completed, the enable signal will turn off this module to save power. Pre-charge phase: When the calculation is about to be completed, this circuit will be charged to prepare for subsequent comparison and linear activation. Linear activation phase: Linearly activate the calculation result, pulling larger values to high level and smaller values to low level. Finally, the calculation and activation result will be output for off-chip processing.

[0040] The present invention significantly improves the intelligence of the infrared intelligent system and reduces the power consumption, which is more conducive to being deployed in edge devices and scenarios. Through simulation on EDA simulation software platforms such as Cadence Virtuoso, this chip architecture can implement the calculation of a layer of binary fully connected neural network, and this calculation result can be used as the output result of the first layer of infrared image classification, with the power consumption being 2-3 orders of magnitude lower than that of other infrared sensing systems. Compared with other infrared chips and systems, it has higher intelligence, higher integration, and lower power consumption: 1. The new architecture of the fully analog-domain infrared intelligent sensing chip: Avoiding the use of analog-to-digital converters effectively reduces the overall power consumption. At the same time, it also avoids the conversion time and improves the processing speed and frame rate.

[0041] 2. By designing a reusable double-sampled multiply-accumulate fully connected neural network computing unit circuit, the on-chip recognition of infrared images is realized.

[0042] The above specific embodiments are used to explain the present invention, which are only the preferred embodiments of the present invention, rather than limiting the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and scope of the claims of the present invention fall within the protection scope of the present invention.

Claims

1. Low-power infrared intelligent sensing chip for edge end, characterized by: include: A transconductance amplifier circuit converts the photocurrent generated by the infrared detector into a voltage signal, including a switchable reset mode and an integration mode; The binary neural network simulation calculation circuit is connected to the output end of the transconductance amplifier circuit to realize analog domain multiplication and accumulation operations: Reset phase: clear the charge of the computing capacitor array through M8 / M9 tubes; Multiplication and accumulation phase: alternately turn on the M1 / M2 tubes to complete double sampling, and synchronously drive the M3-M6 tubes driven by the weight storage circuit to import binary weights; Full connection phase: close the charge averaging switch to complete charge sharing and perform full connection; The weight storage circuit uses a non-volatile memory unit to directly connect to the binary neural network simulation calculation circuit, supporting the real-time acquisition of the weight of the neural network calculation phase; Comparator linear activation circuit to quantize the multiplication and accumulation results: Precharge: Charge the load capacitor to VDD; Comparative quantification: Binarized classification is output through dynamic comparator to quantify the results; The timing control module controls the circuit phase switching so that the three phases of photocurrent integration, neural network calculation and activation output are executed sequentially to reduce the time overlap rate.

2. The low-power infrared intelligent sensing chip for edge terminals according to claim 1 is characterized in that: The transconductance amplifier circuit comprises: Programmable integrating capacitor array, the capacitance value configuration range is 50fF-200fF; Reset switch, clearing the charge of the integration capacitor in the reset phase; Dynamic bias circuit, self-adjusting transconductance gain according to input photocurrent intensity.

3. The low-power infrared intelligent sensing chip for edge terminals according to claim 1, characterized in that: The binary neural network simulation calculation circuit comprises: Double sampling switch array to eliminate MOS tube threshold voltage mismatch; The weight control switch array is driven directly by the weight storage circuit; Configurable computational capacitor array, supporting 4×4 to 32×32 pixel scale processing; Charge averaging switch network to achieve fully connected operation in the analog domain.

4. The low-power infrared intelligent sensing chip for edge terminals according to claim 1, characterized in that: In the multiplication-accumulation phase, the binary neural network analog calculation circuit realizes double sampling operation by alternately turning on M1 / M2 tubes: when M1 tube is turned on, the positive phase of the input voltage signal is sampled and temporarily stored in the first sampling capacitor, and when M2 tube is turned on, the negative phase signal is sampled in the second sampling capacitor to eliminate the error introduced by the threshold voltage mismatch of the MOS tube; synchronously, the weight storage circuit dynamically drives the conduction combination of M3-M6 tubes according to the pre-trained binary weight (+1 / -1) - when the weight is +1, M3 / M6 tubes are turned on to inject the sampled charge forward into the calculation capacitor array, and when the weight is -1, M4 / M5 tubes are turned on to realize reverse charge injection, thereby directly completing the multiplication-accumulation operation of "voltage sampling×binary weight" in the analog domain, realizing weight zero delay loading <1ns through hard wiring connection, and the charge injection amount is strictly matched with the weight polarity, and finally forming an analog voltage signal equivalent to the neural network multiplication-accumulation operation on the calculation capacitor array.

5. The low-power infrared intelligent sensing chip for edge terminals according to claim 1, characterized in that: The comparator linear activation circuit adopts three-phase timing control to achieve efficient nonlinear activation: in the enabling phase, the power switch tube completely cuts off the circuit power supply to achieve zero static power consumption; After entering the pre-charging phase, the charging network is controlled to charge the load capacitor to the VDD / 2 reference level, and the common-mode operating point is stabilized through the differential pair tube; finally, in the linear activation phase, the positive feedback comparator with an adjustable hysteresis window performs a nonlinear transformation on the input signal, and its cross-coupled transistor pair M17-M18 produces a Sigmoid function-like voltage conversion characteristic. At the same time, the output stage push-pull structure ensures that the rail-to-rail swing is completed within 20ns. Through the capacitor coupling and positive feedback synergy mechanism, while realizing the neural network activation function, the dynamic energy consumption is reduced to 0.05pJ / activation.

6. The low-power infrared intelligent sensing chip for edge terminals according to claim 5, characterized in that: The comparator linear activation circuit: The activation threshold voltage is adjustable within the range of ±200mV; Response time <20ns@0.5pF load.

7. An infrared image processing method, based on any one of claims 1 to 6, implemented on a low-power infrared intelligent sensing chip at the edge, comprising the steps of: S1. Photoelectric conversion stage: the photocurrent is integrated into a voltage signal through a transconductance amplifier; S2. Feature extraction stage: complete the multiplication and accumulation operation of binary neural network in the simulation domain; S3. Linear activation stage: dynamic comparator is used to output the classification result.

8. The infrared image processing method according to claim 7, characterized in that: In the photoelectric conversion stage, the photocurrent generated by the infrared detector is integrated by a dynamic bias transconductance amplifier and converted into a voltage signal in the range of 0.3-0.7VDD, where the integration capacitor value can be programmed to adapt to different lighting conditions.

9. The infrared image processing method according to claim 7, characterized in that: In the feature extraction stage, analog domain binary neural network processing is adopted to eliminate device mismatch errors through double sampling of M1 / M2 tubes, and the M3-M6 tube array directly driven by the weight storage circuit is used to realize analog multiplication and accumulation operations on the calculation capacitor.

10. The infrared image processing method according to claim 7, characterized in that: In the decision output stage, the dynamic comparator is pre-charged to the VDD reference, and then uses a positive feedback comparator with an adjustable hysteresis window to complete nonlinear activation and output a binary classification result.

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