Display device and method of driving same

Abstract

The present disclosure provides a display device and a method of driving the same. The display device includes: a display panel including sub-pixels connected to data lines and reference lines; a driving circuit connected to the data line; a sensing circuit including a first voltage circuit connected to the reference line and configured to apply a first reference voltage to initialize a sensing node of the sub-pixel, and a sampling circuit configured to perform a sampling operation to sense the sensing node of the sub-pixel; and a timing controller configured to control at least one of the driving circuit or the sensing circuit, in which the timing controller generates a first reference voltage control signal for changing a level of the first reference voltage based on a driving frequency of the display panel.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2023-0180899, filed on December 13, 2023, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0002] The present disclosure relates to a display device and a method of driving the display device. Background Art

[0003] With the development of information technology, the market for display devices as a medium for communication between users and information is continuously growing. Accordingly, display devices such as light-emitting diode (LED) devices, quantum dot display (QDD) devices, and liquid crystal display (LCD) devices are increasingly used.

[0004] The above-described display device includes: a display panel including sub-pixels, a driver that outputs a driving signal for driving the display panel, and a power supply that generates power to be supplied to the display panel or the driver.

[0005] In such a display device, when driving signals such as a scan signal and a data signal are supplied to sub-pixels formed in the display panel, the selected sub-pixels transmit light or emit light directly, thereby displaying an image. Summary of the Invention

[0006] Accordingly, the present disclosure relates to a display device and a method of driving the display device that substantially avoid one or more problems caused by the limitations and disadvantages of the related art.

[0007] An object of the present disclosure is to solve the shortage of sensing time by reducing the sensing time so that deterioration of elements included in a display panel of a high-resolution or high-frequency model can be sensed and compensated, and to improve compensation performance by ensuring time required for compensation.

[0008] Additional advantages, objects, and features of the present disclosure will be partially described in the following description, and will be partially apparent to those of ordinary skill in the art upon examination of the following, or may be learned from practice of the present disclosure. The objects and other advantages of the present disclosure may be realized and obtained by the structures particularly pointed out in the written description and claims and the drawings.

[0009] To achieve these objects and other advantages, and in accordance with the purpose of the present disclosure as embodied and broadly described herein, a display device includes: a display panel including sub-pixels connected to data lines and reference lines; a driving circuit connected to the data lines; a sensing circuit including a first voltage circuit connected to the reference lines and configured to apply a first reference voltage to initialize a sensing node of the sub-pixels, and a sampling circuit configured to perform a sampling operation to sense the sensing node of the sub-pixels; and a timing controller configured to control at least one of the driving circuit or the sensing circuit, wherein the timing controller generates a first reference voltage control signal for changing the level of the first reference voltage based on a driving frequency of the display panel.

[0010] The first reference voltage may change to a higher level as the driving frequency of the display panel increases.

[0011] The first reference voltage may be increased from 0V to 1.x V (x is an integer equal to or greater than 0) under the control of the timing controller.

[0012] The display device may further include a power supply configured to supply the first reference voltage to the first voltage circuit, wherein the power supply may increase the level of the first reference voltage in response to a first reference voltage control signal output from the timing controller.

[0013] The timing controller and the power supply may perform data transmission and reception through an I2C communication method to transmit and receive signals, and the first reference voltage control signal may be included in the data signal transmitted through the I2C communication method.

[0014] The display device may further include a digital-to-analog converter configured to supply the first reference voltage to the first voltage circuit, wherein the digital-to-analog converter may increase the level of the first reference voltage in response to a first reference voltage control signal output from the timing controller.

[0015] The timing controller and the digital-to-analog converter may perform data transmission and reception through an EPI communication method to transmit and receive signals, and the first reference voltage control signal may be included in the data signal transmitted through the EPI communication method.

[0016] The driving circuit and the sensing circuit may be included in a data driver, and the first reference voltage may be output from a digital-to-analog converter included in the driving circuit.

[0017] In another aspect of the present disclosure, a method of driving a display device includes: applying a first reference voltage to a reference line by driving a first voltage circuit to initialize a sensing node of a sub-pixel; performing a sampling operation on the reference line by driving a sensing circuit to sense the sensing node of the sub-pixel; and compensating for deterioration of elements included in the display panel based on a sensed voltage obtained by performing the sampling operation on the reference line, wherein a level of the first reference voltage varies in response to a driving frequency of the display panel.

[0018] The first reference voltage may change to a higher level as the driving frequency of the display panel increases.

[0019] The first reference voltage may be increased from 0 V to 1.x V (x is an integer equal to or greater than 0) under the control of a timing controller.

[0020] Applying the first reference voltage and performing the sampling operation are performed during a blank period of a vertical synchronization signal to drive the display panel.

[0021] It should be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the claimed present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0023] Figure 1 schematically shows a block diagram of a light-emitting display device, Figure 2 schematically shows Figure 1 a configuration diagram of a sub-pixel shown in Figure 3 and is a diagram showing a pixel composed of sub-pixels.

[0024] Figure 4 and Figure 5 is a diagram showing a configuration of an in-panel gate-type gate driver, and Figure 6 is a diagram showing an example of an arrangement of an in-panel gate-type gate driver;

[0025] Figure 7 schematically shows a sub-pixel and a data driver according to a first example of an embodiment, Figure 8 schematically shows a sub-pixel and a data driver according to a second example of an embodiment, and Figure 9 is a waveform diagram showing a sensing period and a display period according to an embodiment;

[0026] Figure 10FIG. is a diagram showing in more detail some of the components included in a data driver according to an embodiment, and Figure 11 and Figure 12 FIG. is a diagram showing a method of sensing a display panel according to an embodiment;

[0027] Figure 13 FIG. is a driving waveform diagram for describing a sensing operation of a light-emitting display device according to an embodiment, and Figure 14 and Figure 15 FIG. is a diagram showing some operation states of a device of a driving waveform according to Figure 13 ;

[0028] Figure 16 FIG. is a diagram showing the relationship between a sensing time and a driving frequency (or resolution), Figure 17 FIG. is a diagram showing a change in a sensing time according to a first reference voltage raising method according to an embodiment, and Figure 18 FIG. is a diagram showing advantages of a first reference voltage raising method according to an embodiment;

[0029] Figure 19 and Figure 20 FIG. is a diagram for briefly describing some components of a light-emitting display device according to a first embodiment and an example of changing a first reference voltage, and Figure 21 and Figure 22 FIG. is a diagram for briefly describing an example of transmitting a first reference voltage control signal for changing a first reference voltage according to a first communication method according to a first embodiment;

[0030] Figure 23 and Figure 24 FIG. is a diagram showing a configuration of each block of a data driver according to a first embodiment;

[0031] Figure 25 and Figure 26 FIG. is a diagram for briefly describing some components of a light-emitting display device according to a second embodiment and an example of changing a first reference voltage, and Figure 27 FIG. is a diagram showing an example of transmitting a first reference voltage control signal for changing a first reference voltage according to a second communication method according to a second embodiment; and

[0032] Figure 28 and Figure 29 FIG. is a diagram showing a configuration of each block of a data driver according to a second embodiment. DETAILED DESCRIPTION

[0033] The display device according to the present disclosure can be implemented as a television system, an image player, a personal computer (PC), a home theater, an automotive electrical device, a smart phone, etc., but is not limited thereto. The display device according to the present disclosure can be implemented as a light-emitting display (LED) device, a quantum dot display (QDD) device, a liquid crystal display (LCD) device, etc. However, for ease of description, as an example, a light-emitting display device that directly emits light based on an inorganic light-emitting diode or an organic light-emitting diode will be described below.

[0034] Figure 1 is a block diagram schematically showing a light-emitting display device, Figure 2 is schematically showing Figure 1 the configuration diagram of the sub-pixels shown in, and Figure 3 is a diagram showing a pixel composed of sub-pixels.

[0035] As Figure 1 , Figure 2 and Figure 3 shown, the light-emitting display device may include an image provider 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, a power supply 180, etc.

[0036] The image provider 110 (device or host system) can output various driving signals and an image data signal supplied externally or an image data signal stored in an internal memory. The image provider 110 can supply a data signal and various driving signals to the timing controller 120.

[0037] The timing controller 120 can output a gate timing control signal GDC for controlling the operation timing of the gate driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, and various synchronization signals. The timing controller 120 can supply the data signal DATA supplied from the image provider 110 to the data driver 140 together with the data timing control signal DDC. The timing controller 120 can be implemented in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

[0038] The gate driver 130 can output a gate signal (or gate voltage) in response to the gate timing control signal GDC supplied from the timing controller 120. The gate driver 130 can supply a gate signal to the sub-pixels included in the display panel 150 through gate lines GL1 to GLm. The gate driver 130 can be implemented in the form of an IC, or directly formed on the display panel 150 in an in-panel gate structure, but is not limited thereto.

[0039] The data driver 140 may sample and latch the data signal DATA in response to a data timing control signal DDC supplied from the timing controller 120, convert the digital data signal into an analog data voltage based on a gamma reference voltage, and output the analog data voltage. The data driver 140 may supply the data voltage to sub-pixels included in the display panel 150 through data lines DL1 to DLn. The data driver 140 may be implemented in the form of an integrated circuit (IC) and mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

[0040] The power supply 180 may generate a high-level first power and a low-level second power based on an externally supplied external input voltage. The power supply 180 may output the first power through a first power line EVDD and output the second power through a second power line EVSS. The power supply 180 may generate and output voltages required to drive the gate driver 130 (e.g., a scan high voltage and a scan low voltage) and voltages required to drive the data driver 140 (e.g., a drain voltage and a semi-drain voltage), as well as the first power and the second power.

[0041] The display panel 150 may display an image in response to a driving signal including a scan signal and a data voltage, the first power, and the second power. Sub-pixels of the display panel 150 may emit light directly. The display panel 150 may be manufactured based on a substrate having rigidity or flexibility such as, for example, glass, silicon, polyimide, etc. For example, one sub-pixel SP may be connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS, and may include a pixel circuit including a switching transistor, a driving transistor, a capacitor, an organic light-emitting diode, etc.

[0042] The sub-pixel SP used in the light-emitting display device emits light directly, and thus its circuit configuration is complex. In addition, there are various compensation circuits that not only compensate for the deterioration of the light-emitting organic light-emitting diode but also compensate for the deterioration of the driving transistor that supplies the driving current required to drive the organic light-emitting diode. Therefore, the sub-pixel SP is simply shown in the form of a block.

[0043] The light-emitting sub-pixels may include red, green, and blue pixels or may include red, green, blue, and white pixels. For example, a pixel P may include a red sub-pixel SPR connected to a first data line DL1, a white sub-pixel SPW connected to a second data line DL2, a green sub-pixel SPG connected to a third data line DL3, and a blue sub-pixel SPB connected to a fourth data line DL4. Additionally, the red sub-pixel SPR, the white sub-pixel SPW, the green sub-pixel SPG, and the blue sub-pixel SPB may be commonly connected to a first reference line VREF1. The first reference line VREF1 may be used to sense the degradation of an element included in one of the red sub-pixel SPR, the white sub-pixel SPW, the green sub-pixel SPG, and the blue sub-pixel SPB, which will be described hereinafter.

[0044] Above, the timing controller 120, the gate driver 130, and the data driver 140 have been described as separate components. However, depending on the implementation of the light-emitting display device, one or more of the timing controller 120, the gate driver 130, and the data driver 140 may be integrated into a single IC. In addition, the timing controller 120, the gate driver 130, the data driver 140, the power supply 180, and the display panel 150 are components for displaying an image and may be defined as a display module.

[0045] In addition, as an example, a pixel P in which the red sub-pixel SPR, the white sub-pixel SPW, the green sub-pixel SPG, and the blue sub-pixel SPB are arranged in sequence is shown. However, the arrangement order and direction of the sub-pixels may vary depending on the implementation of the light-emitting display device.

[0046] Figure 4 and Figure 5 is a diagram showing the configuration of an in-panel gate type gate driver, and Figure 6 is a diagram showing an example of the arrangement of an in-panel gate type gate driver.

[0047] As Figure 4 shown, the in-panel gate type gate driver may include a shift register 131 and a level shifter 135. The level shifter 135 may generate a driving clock signal Clks and a start signal Vst based on signals and voltages output from the timing controller 120 and the power supply 180.

[0048] The shift register 131 operates based on the signals Clks and Vst output from the level shifter 135 and may output gate signals Gate[1] to Gate[m] for turning on or off transistors formed in the display panel. The shift register 131 may be in the form of a thin film on the display panel with an in-panel gate structure.

[0049] As Figure 4and Figure 5 As shown, unlike the shift register 131, the level shifter 135 may be independently formed in the form of an IC or may be included in the power supply 180. However, this is merely an example and is not limited thereto.

[0050] As Figure 6 shown, in an in-panel gate type gate driver, the shift registers 131a and 131b that output gate signals may be disposed in the non-display area NA of the display panel 150. As an example, the shift registers 131a and 131b are disposed in the left non-display area NA and the right non-display area NA of the display panel 150, but the shift registers 131a and 131b may also be disposed in the upper non-display area NA and the lower non-display area NA of the display panel 150, or may be disposed within the display area AA of the display panel 150.

[0051] Figure 7 is a diagram schematically showing a sub-pixel and a data driver according to a first example of an embodiment, Figure 8 is a diagram schematically showing a sub-pixel and a data driver according to a second example of an embodiment, and Figure 9 is a waveform diagram showing a sensing period and a display period.

[0052] As Figure 7 shown, according to the first example, one sub-pixel SP may include a switching transistor SW, a driving transistor DT, a sensing transistor ST, a capacitor CST, and an organic light emitting diode OLED.

[0053] The driving transistor DT may include a gate electrode connected to the first electrode of the capacitor CST, a first electrode connected to the first power line EVDD, and a second electrode connected to the anode of the organic light emitting diode OLED. The capacitor CST may have a first electrode connected to the gate electrode of the driving transistor DT and a second electrode connected to the anode electrode of the organic light emitting diode OLED. The organic light emitting diode OLED may have an anode connected to the second electrode of the driving transistor DT and a cathode connected to the second power line EVSS.

[0054] The switching transistor SW may include: a gate electrode connected to the first scan line Gate1 included in the first gate line GL1, a first electrode connected to the first data line DL1, and a second electrode connected to the gate electrode of the driving transistor DT. The sensing transistor ST may include: a gate electrode connected to the second scan line Gate2 included in the first gate line GL1, a first electrode connected to the first reference line VREF1, and a second electrode connected to the anode of the organic light emitting diode OLED.

[0055] The sensing transistor ST is a compensation circuit added to compensate for the degradation (in terms of threshold voltage, mobility, etc.) of the driving transistor DT or the organic light-emitting diode OLED. The sensing transistor ST can implement physical threshold voltage sensing based on the source follower operation of the driving transistor DT. The sensing transistor ST can operate through a sensing node defined between the driving transistor DT and the organic light-emitting diode OLED to obtain a sensing voltage.

[0056] According to an embodiment, the data driver 140 may include a driving circuit 141 for driving the sub-pixel SP and a sensing circuit 145 for sensing the sub-pixel SP. The driving circuit 141 may be connected to the first data line DL1 through the first data channel DCH1. The driving circuit 141 may output a data voltage Vdata for driving the sub-pixel SP through the first data channel DCH1.

[0057] The sensing circuit 145 may be connected to the first reference line VREF1 through the first sensing channel SCH1. The sensing circuit 145 may obtain a sensing voltage Vsen sensed from the sub-pixel SP through the first sensing channel SCH1. The sensing circuit 145 may obtain the sensing voltage Vsen based on a current sensing or voltage sensing method.

[0058] As Figure 8 shown, according to a second example, the first gate line GL1 may be integrated into one. That is, different from the first example, the first gate line GL1 may not be divided into a first scan line and a second scan line. In this case, the switching transistor SW and the sensing transistor ST are commonly connected to the first gate line GL1, and thus can be turned on or off simultaneously.

[0059] As Figure 9 shown, when operating to drive the display panel, the light-emitting display device according to an embodiment may adopt driving modes corresponding to a first operation period PWR_ON, a second operation period DISPLAY, and a third operation period PWR_OFF, respectively.

[0060] The first operation period PWR_ON may correspond to a driving start period for applying power to the display panel, the second operation period DISPLAY may correspond to a panel driving period for performing operations such as displaying an image after applying power to the display panel, and the third operation period PWR_OFF may correspond to a driving end period for cutting off the power applied to the display panel. At the same time, the third operation period PWR_OFF is a period for driving the display panel for a certain period while displaying black so that the sensing operation of the display panel can be performed. That is, it should be noted that during the third operation period PWR_OFF, the power applied to the display panel etc. is not completely cut off.

[0061] The light-emitting display device according to the embodiment may sense the display panel in at least one of a first operation period PWR_ON, a second operation period DISPLAY, and a third operation period PWR_OFF. As an example, in the second operation period DISPLAY, a blank period BLK included in the vertical synchronization signal Vsync may be defined as a sensing period PSP, and an active period ACT included in the vertical synchronization signal Vsync may be defined as a display period DSP. The light-emitting display device according to the embodiment may sense, in real time during the second operation period DISPLAY, the degradation of elements included in sub-pixels of the display panel.

[0062] Figure 10 is a diagram showing in more detail some of the components included in the data driver according to the embodiment, and Figure 11 and Figure 12 is a diagram showing a method of sensing a display panel according to the embodiment. Hereinafter, as an example, Figure 7 the structure of the sub-pixel SP shown in

[0063] As in the Figure 10 embodiment shown in, the driving circuit 141 may include a digital-to-analog converter DAC to output a sensing data voltage, a black data voltage, or a display data voltage through a first data line DL1. The sensing circuit 145 may include a first voltage circuit SPRE, a second voltage circuit RPRE, a sampling circuit SAM, and an analog-to-digital converter ADC to output and sense a voltage through a first reference line VREF1.

[0064] The first voltage circuit SPRE and the second voltage circuit RPRE may perform a voltage output operation to initialize or charge to a specific voltage level a node or a circuit included in the sub-pixel SP. The first voltage circuit SPRE and the second voltage circuit RPRE may include a first reference voltage source VPRES and a second reference voltage source VPRER, respectively. The first voltage circuit SPRE may output a first reference voltage based on the first reference voltage source VPRES, and the second voltage circuit RPRE may output a second reference voltage based on the second reference voltage source VPRER. The first reference voltage may be set to a voltage lower than the second reference voltage.

[0065] The sampling circuit SAM may perform a sampling operation to obtain a sensing voltage through the first reference line VREF1. For example, the sampling circuit SAM may obtain a sensing voltage from the sensing capacitor PCAP based on the sensing capacitor PCAP formed on the first reference line VREF1.

[0066] The analog-to-digital converter ADC can convert the analog sensed voltage obtained by the sampling circuit SAM into a digital sensed voltage and output the digital sensed voltage. For example, the analog-to-digital converter ADC can convert the analog sensed voltage charged into the sensing capacitor PCAP into a digital sensed voltage and output the digital sensed voltage.

[0067] The timing controller 120 can receive the sensed voltage (sensed data value) from the sensing circuit 145. The timing controller 120 can determine whether the driving transistor DT or the organic light-emitting diode OLED included in the sub-pixel SP has deteriorated based on the sensed voltage, and perform an operation to compensate for the deterioration. Additionally, the timing controller 120 can determine the presence or absence of a defect in the light-emitting display device based on the sensed voltage, and perform an operation to notify or remove the defect.

[0068] As Figure 11 shown, according to the first example, the light-emitting display device can perform a sequential sensing method in which sensing is performed from the first gate line GL1 to the M-th gate line GLm of the display panel 150. Although Figure 11 an example of performing sensing sequentially starting from the first gate line GL1 at the top of the display panel 150 is shown, the sensing can start from the M-th gate line GLm at the bottom of the display panel 150.

[0069] As Figure 12 shown, according to the second example, the light-emitting display device can perform a random sensing method in which only the I-th gate line GLi of the display panel 150 is sensed. Although Figure 12 an example of sensing only the I-th gate line GLi as one of the specific gate lines is shown, the sensing target can be two or more gate lines.

[0070] Figure 13 is a driving waveform diagram for describing the sensing operation of the light-emitting display device according to an embodiment, and Figure 14 and Figure 15 is a diagram showing some operation states of the device of the driving waveform according to Figure 13 .

[0071] As Figure 13 shown, the light-emitting display device according to an embodiment can perform operations in a first period P1, a second period P2, and a third period P3 to sense the deterioration of elements included in the sub-pixel SP.

[0072] As Figure 13 and Figure 14As shown, the scan signal Scan and the sense signal Sense can be applied as a turn-on voltage (high voltage) during a first period P1 and a second period P2, and as a turn-off voltage (low voltage) during a third period P3. The switching transistor SW and the sensing transistor ST included in the sub-pixel SP can be turned on by the scan signal Scan and the sense signal Sense of the turn-on voltage applied during the first period P1 and the second period P2.

[0073] The first voltage circuit control signal Spre can be applied as a turn-on voltage (high voltage) during the first period P1, and as a turn-off voltage (low voltage) during the second period P2 and the third period P3. The first voltage circuit SPRE can be turned on by the first voltage circuit control signal Spre of the turn-on voltage applied during the first period P1 to output a first reference voltage Vpres. The first reference voltage Vpres applied during the first period P1 can be applied to the sense node through the first reference line VREF1 of the sub-pixel SP and the turned-on sensing transistor ST. The source electrode (i.e., the second electrode) of the driving transistor DT and the second electrode of the capacitor CST are connected to the sense node. The sense node can be initialized by the first reference voltage Vpres applied during the first period P1.

[0074] The sense data voltage Sdata can be applied during the first period P1, and not applied during the second period P2 and the third period P3. The sense data voltage Sdata applied during the first period P1 can be applied to the gate node through the turned-on switching transistor SW. The gate electrode of the driving transistor DT and the first electrode of the capacitor CST are connected to the gate node.

[0075] As Figure 13 shown, the switching transistor SW and the sensing transistor ST can be turned on during the second period P2. The driving transistor DT can operate as a constant current source by charging the sense data voltage Sdata into the capacitor CST.

[0076] As the driving transistor DT operates as a constant current source, the sense voltage Vsen that can be obtained from the sense node can increase. Here, the change in the sense voltage Vsen that can be obtained from the sense node can be proportional to the current of the driving transistor DT. Therefore, the sense voltage Vsen that can be obtained from the sense node can rise to a level close to the threshold voltage of the driving transistor DT and then saturate. The sense voltage Vsen can also be charged into the sense capacitor PCAP formed on the first reference line VREF1 of the sub-pixel SP.

[0077] As Figure 13 and Figure 15As shown, a sampling control signal Sam can be applied as a turn-on voltage during a third period P3. The sampling circuit SAM can be turned on by the sampling control signal Sam of the turn-on voltage applied during the third period P3. On the other hand, the switching transistor SW and the sensing transistor ST included in the sub-pixel SP can be turned off during the third period P3.

[0078] According to the sampling operation of the sampling circuit SAM, the sensing voltage Vsen charged into the sensing capacitor PCAP of the first reference line VREF1 (or the sensing voltage charged into the sensing node) can be charged into the sampling capacitor SCAP of the sampling circuit SAM.

[0079] Figure 16 is a graph showing the relationship between the sensing time and the driving frequency (or resolution), Figure 17 is a graph showing the change in the sensing time according to the first reference voltage raising method according to an embodiment, and Figure 18 is a graph showing the advantages of the first reference voltage raising method according to an embodiment.

[0080] As Figure 16 shown, the sensing voltage Vsen obtained through the sampling operation during the third period P3 can be defined as a voltage that rises from the reference voltage Vref and reaches a level close to the threshold voltage of the driving transistor.

[0081] The sensing voltage Vsen can be obtained as a first sensing voltage Vsen1 having a first slope or as a second sensing voltage Vsen2 having a second slope. As can be determined by the reference voltage difference expression ΔV = (I * Δt) / C, the factor that has the greatest influence on the sensing voltage Vsen is the sensing time Δt, where I is the current of the driving transistor DT, Δt is the sensing time, and C is the capacitance of the capacitor CST. That is, even when sensing the same sub-pixel, if there are conditions (such as driving frequency or resolution) that may cause differences in the sensing time Δt, the level of the sensing voltage Vsen may change.

[0082] As Figure 17 shown, compared with the previous level, the sensing method according to an embodiment raises the level of the first reference voltage that is the standard of the sensing voltage Vsen compared with the previous level. In other words, the level of the first reference voltage for initialization is raised compared with the previous level.

[0083] Figure 17 The first sample Vsena and the first sample group Vsenag in Figure 17The second sample Vsenb and the second sample group Vsenbg in [description] are examples showing the change in the slope of the sensed voltage when the level of the first reference voltage is set to 1.x V (x is an integer greater than or equal to 0).

[0084] As can be determined from the example of [[reference]] Figure 17 if the level of the first reference voltage used for initialization is increased, the same slope as that at the second sensing time Samt2 can be obtained even at the first sensing time Samt1 earlier than the second sensing time Samt2. In other words, according to the embodiment, by increasing the level of the first reference voltage used for initialization to at least 1.0 V, the sensing time can be advanced to a first time earlier than the second time earlier

[0085] As Figure 18 shown, the degradation sensing method according to the embodiment can be performed during the blank period BLK included in the vertical synchronization signal Vsync. The blank period BLK can be shortened or lengthened depending on the conditions for determining the driving frequency, such as the vertical synchronization signal Vsync.

[0086] For example, the blank period BLK of the vertical synchronization signal Vsync generated based on a driving frequency of 60 Hz is longer than the blank period BLK of the vertical synchronization signal Vsync generated based on a driving frequency of 240 Hz. Therefore, when the driving frequency of the light-emitting display device is 240 Hz, the time required to obtain the sensed voltage is shorter than the time required to obtain the sensed voltage when the driving frequency is 60 Hz. This problem may also occur when the driving frequency increases and the display panel is implemented as a high-resolution and high pixels per inch (PPI) model.

[0087] Therefore, as in the embodiment, when the driving frequency increases from the first frequency to the second frequency or the method is applied to a model with high resolution (e.g., high frequency, high resolution, and high PPI), the sensing voltage acquisition method of increasing the level of the first reference voltage used for initialization is advantageous.

[0088] In addition, the degradation sensing method according to the embodiment can control related components such that when at least one of the frequency, resolution, or PPI increases, the first reference voltage increases in response thereto. Additionally, the degradation sensing method according to the embodiment can use a look-up table to provide a preferred first reference voltage in response to at least one of the frequency, resolution, or PPI.

[0089] Figure 19 and Figure 20 are diagrams for briefly describing some components of the light-emitting display device according to the first embodiment and an example of changing the first reference voltage, and Figure 21 andFigure 22 This is a diagram for briefly describing an example of transmitting a first reference voltage control signal for changing a first reference voltage based on a first communication method according to a first embodiment.

[0090] As Figure 19 and Figure 20 shown, according to the first embodiment, a first voltage circuit SPRE included in the sensing circuit 145 may be connected to one of the output terminals of the power supply 180. The first voltage circuit SPRE may use the voltage output from one of the output terminals of the power supply 180 as a first reference voltage Vpres for initializing the sensing node. When at least one of the frequency, resolution, or PPI increases, in response, the first reference voltage Vpres may be output as 1.x V (x is an integer equal to or greater than 0) higher than 0V. That is, when at least one of the frequency, resolution, or PPI increases, in response, the power supply 180 may change the level of the first reference voltage Vpres to 1.x higher than 0V and output this level.

[0091] As Figure 21 and Figure 22 shown, according to the first embodiment, the power supply 180 may change the level of the first reference voltage Vpres under the control of the timing controller 120 and output this level. The power supply 180 and the timing controller 120 may perform data transmission and reception through the first communication method to transmit and receive signals.

[0092] The timing controller 120 may include a first interface 121 and a controller 125. The power supply 180 may include a second interface 181 and a first reference voltage generator 183.

[0093] A clock line SCL and a data line SDA may be provided between the first interface 121 of the timing controller 120 and the second interface 181 of the power supply 180 to transmit and receive signals using an I2C communication method corresponding to an example of the first communication method. A clock signal Scl for implementing the start and stop of signal transmission between the first interface 121 and the second interface 181 may be transmitted through the clock line SCL. A data signal Sda for implementing data transmission between the first interface 121 and the second interface 181 may be transmitted through the data line SDA.

[0094] The controller 125 of the timing controller 120 may generate a first reference voltage control signal Vpresc for controlling the first reference voltage and control the first interface 121 such that the first reference voltage control signal Vpresc is transmitted to the first reference voltage generator 183 included in the power supply 180. As Figure 22As shown, the first reference voltage control signal Vpresc can be transmitted by being included in the data signal I2C DATA transmitted through the I2C communication method.

[0095] The power supply 180 can extract the first reference voltage control signal Vpresc from the signal received through the second interface 181 and transmit it to the first reference voltage generator 183. The first reference voltage generator 183 can change the level of the first reference voltage Vpres in response to the data value included in the first reference voltage control signal Vpresc.

[0096] Meanwhile, when the driving frequency changes from the first frequency (e.g., 60 Hz) to the second frequency (120 Hz, 240 Hz or higher), the controller 125 can generate the first reference voltage control signal Vpresc. In addition, the controller 125 can change the data value included in the first reference voltage control signal Vpresc into a form that can change the level of the first reference voltage Vpres in response to the driving frequency.

[0097] Figure 23 and Figure 24 are diagrams showing the configuration of each block of the data driver according to the first embodiment.

[0098] As Figure 23 and Figure 24 shown, according to the first embodiment, the data driver 140 includes a driving circuit 141 for driving the sub-pixel SP and a sensing circuit 145 for sensing the sub-pixel SP.

[0099] The driving circuit 141 can include a data reception and recovery unit RX&CDR, a first data processing and logic unit S2P&PLOG, a shift register SRES, a first latch LAT1, a second latch LAT2, a digital-to-analog converter DAC, and an output circuit COC.

[0100] The data reception and recovery unit RX&CDR can be used to receive and process the packet data sent from the timing controller and recover the error in the reception of the data signal or clock signal included in the packet data in case an error has occurred.

[0101] The first data processing and logic unit S2P&PLOG can be used to convert the serial signal output from the data reception and recovery unit RX&CDR into a parallel signal and output the control signal to be applied to the controller TCL and the data signal to be applied to the first latch LAT1 respectively.

[0102] The shift register SRES can be used to generate a signal such that the data signal applied to the first latch LAT1 or the second latch LAT2 is sampled and latched for one row.

[0103] The first latch LAT1 and the second latch LAT2 can be used to sample, latch, and output the data signals output from the first data processing and logic unit S2P&PLOG for a row. Here, the second latch LAT2 can output the data signal based on the source output enable signal output from the first data processing and logic unit S2P&PLOG.

[0104] The digital-to-analog converter DAC can be used to convert the digital data signal output from the second latch LAT2 into an analog data voltage based on the gamma reference voltage and output the analog data voltage.

[0105] The output circuit COC can be used to perform additional modulation, such as amplifying the data voltage output from the digital-to-analog converter DAC, and then output the data voltage through the data channel.

[0106] The sensing circuit 145 can include a controller TCL, a sensing processor CIA, a multiplexer MUX, a sampling and downscaling unit SAM&DS, a gain amplifier GA, an analog-to-digital converter ADC, a second data processor P2S, and a data transmitter TX.

[0107] The controller TCL can be used to control the operation timing of the components included in the sensing circuit 145 based on the control signal output from the first data processing and logic unit S2P&PLOG.

[0108] The sensing processor CIA can be used to obtain a sensing voltage through a sensing channel connected to a reference line, process the sensing voltage, and output the processed sensing voltage. The sensing processor CIA can be configured according to the sensing method of the sensing circuit 145. For example, the sensing processor CIA can be configured as a current integration circuit or a voltage sensing circuit.

[0109] The multiplexer MUX can be used to selectively output the first reference voltage Vpres and the second reference voltage Vprer applied from the outside. The multiplexer MUX can include a first voltage circuit that outputs the first reference voltage Vpres and a second voltage circuit that outputs the second reference voltage Vprer. The first voltage circuit can receive the first reference voltage Vpres through the first reference voltage input terminal VPRESCH, and the second voltage circuit can receive the second reference voltage through the second reference voltage input terminal VPRERCH.

[0110] The sampling and downscaling unit SAM&DS can be used to sample the sensing voltage obtained by the sensing processor CIA and downscale the sensing voltage. As Figure 24As shown, the sampling and downscaling unit SAM&DS can sample the sensed voltage in the form of an analog signal output from the sensing processor CIA into a sampled analog signal, and downscale the sampled analog signal to output an analog signal identical to the sampled and downscaled analog signal.

[0111] The gain amplifier GA can be used to control the gain of the sensed voltage output from the sampling and downscaling unit SAM&DS. The analog-to-digital converter ADC can be used to convert the analog sensed voltage output from the gain amplifier GA into a digital sensed voltage (sensed data value) and output the digital sensed voltage.

[0112] The second data processor P2S can be used to process the parallel digital sensed voltage output from the analog-to-digital converter ADC into a serial digital sensed voltage. The data transmitter TX can be used to transmit the serial digital sensed voltage output from the second data processor P2S to the timing controller.

[0113] Figure 25 and Figure 26 are diagrams for briefly describing some components of the light-emitting display device according to the second embodiment and an example of changing the first reference voltage, and Figure 27 is a diagram showing an example of transmitting a first reference voltage control signal for changing the first reference voltage based on the second communication method according to the second embodiment.

[0114] As Figure 25 , Figure 26 and Figure 27 shown, according to the second embodiment, the first voltage circuit SPRE included in the sensing circuit 145 can be connected to one of the output terminals of the second digital-to-analog converter DAC2. The first voltage circuit SPRE can use the voltage output from one of the output terminals of the second digital-to-analog converter DAC2 as the first reference voltage Vpres for initializing the sensing node. The first reference voltage Vpres can be changed by the second digital-to-analog converter DAC2 and output as 1.x V (x is an integer greater than or equal to 0) higher than 0V.

[0115] The second digital-to-analog converter DAC2 can generate the first reference voltage Vpres based on the voltage output from the power supply 180. The second digital-to-analog converter DAC2 can change the level of the first reference voltage Vpres under the control of the timing controller 120 and output the level.

[0116] The sensing circuit 145 and the timing controller 120 may perform data transmission and reception through a second communication method to transmit and receive signals. The sensing circuit 145 and the timing controller 120 may use an Embedded Clock Point-Point Interface (EPI), which is an example of a second communication method, to transmit and receive signals. The EPI communication method may be used to transmit data signals, control signals, and clock signals in the form of differential signals through a pair of lines.

[0117] The timing controller 120 may generate a first reference voltage control signal Vpresc for controlling a first reference voltage and transmit it to the sensing circuit 145. As Figure 27 shown, the first reference voltage control signal Vpresc may be transmitted by being included in the data signal EPI DATA transmitted through the EPI communication method. CTR indicates a control signal used when transmitting data through the EPI communication method.

[0118] The second digital-to-analog converter DAC2 may change the level of the first reference voltage Vpres in response to the data value included in the first reference voltage control signal Vpresc. Meanwhile, an example has been described above in which the driving circuit 141 includes a first digital-to-analog converter DAC1, the sensing circuit 145 includes a second digital-to-analog converter DAC2, and the driving circuit 141 and the sensing circuit 145 are different from each other. However, the sensing circuit 145 may use the first digital-to-analog converter DAC1 included in the driving circuit 141 instead of including the second digital-to-analog converter DAC2, which will be described below.

[0119] Figure 28 and Figure 29 are diagrams showing the configuration of each block of the data driver according to the second embodiment.

[0120] As Figure 28 and Figure 29 shown, according to the second embodiment, the data driver 140 may include a driving circuit 141 for driving the sub-pixel SP and a sensing circuit 145 for sensing the sub-pixel SP.

[0121] The driving circuit 141 may include a data reception and recovery unit RX&CDR, a first data processing and logic unit S2P&PLOG, a shift register SRES, a first latch LAT1, a second latch LAT2, a digital-to-analog converter DAC, and an output circuit COC.

[0122] The sensing circuit 145 may include a controller TCL, a sensing processor CIA, a multiplexer MUX, a sampling and downscaling unit SAM&DS, a gain amplifier GA, an analog-to-digital converter ADC, a second data processor P2S, and a data transmitter TX.

[0123] According to the second embodiment, the sensing circuit 145 may use a voltage output from one of the output terminals of the analog-to-digital converter ADC included in the driving circuit 141 as the first reference voltage Vpres. That is, the first reference voltage Vpres may be output from one of the output terminals of the analog-to-digital converter ADC included in the driving circuit 141.

[0124] Therefore, different from the first embodiment, the data driver 140 according to the second embodiment may receive only the second reference voltage Vprer separately from the outside. In other words, although the multiplexer MUX includes a first voltage circuit that outputs the first reference voltage Vpres and a second voltage circuit that outputs the second reference voltage Vprer, since the first reference voltage Vpres is generated in the data driver 140, only the second reference voltage Vprer is applied separately from the outside. Therefore, the data driver 140 may include only a second reference voltage input terminal VPRERCH through which the second reference voltage is input, and may not include (may omit or remove) a first reference voltage input terminal through which the first reference voltage is input.

[0125] As described above, the present disclosure has the effect of reducing the sensing time such that deterioration of elements included in a display panel of a high-resolution or high-frequency model can be sensed and compensated. In addition, the present disclosure has the effect of solving insufficient sensing time that may occur in a display panel of a high-resolution or high-frequency model and improving compensation performance by ensuring the time required for compensation.

[0126] It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: a display panel including sub-pixels connected to data lines and reference lines; a driving circuit connected to the data line; a sensing circuit, the sensing circuit comprising a first voltage circuit and a sampling circuit, the first voltage circuit being connected to the reference line and configured to apply a first reference voltage to initialize a sensing node of the sub-pixel, the sampling circuit being configured to perform a sampling operation to sense the sensing node of the sub-pixel; as well as a timing controller configured to control at least one of the driving circuit or the sensing circuit, The timing controller generates a first reference voltage control signal for changing a level of the first reference voltage based on a driving frequency of the display panel.

2. The display device according to claim 1, wherein: The first reference voltage changes to a higher level as the driving frequency of the display panel increases.

3. The display device according to claim 1, wherein: The first reference voltage is increased from 0 V to 1.x V under the control of the timing controller, where x is an integer of 0 or greater.

4. The display device according to claim 1, further comprising a power supply configured to provide the first reference voltage to the first voltage circuit, in, The power supply increases a level of the first reference voltage in response to the first reference voltage control signal output from the timing controller.

5. The display device according to claim 4, wherein: The timing controller and the power supply perform data transmission and reception through an I2C communication method to transmit and receive a signal, and the first reference voltage control signal is included in the data signal transmitted through the I2C communication method.

6. The display device according to claim 1, further comprising a digital-to-analog converter configured to provide the first reference voltage to the first voltage circuit. in, The digital-to-analog converter changes a level of the first reference voltage in response to the first reference voltage control signal output from the timing controller.

7. The display device according to claim 6, wherein: The timing controller and the digital-to-analog converter perform data transmission and reception through an EPI communication method to transmit and receive a signal, and the first reference voltage control signal is included in a data signal transmitted through the EPI communication method.

8. The display device according to claim 1, wherein: The driving circuit and the sensing circuit are included in a data driver, and the first reference voltage is output from a digital-to-analog converter included in the driving circuit.

9. The display device according to claim 1, wherein: The first voltage circuit is configured to perform applying the first reference voltage during a blank period of a vertical synchronization signal, and the sampling circuit is configured to perform the sampling operation during the blank period.

10. A method for driving the display device according to claim 1, comprising: applying the first reference voltage to the reference line by driving the first voltage circuit to initialize the sensing node of the sub-pixel; performing a sampling operation on the reference line by driving the sensing circuit to sense the sensing node of the sub-pixel; as well as compensating for degradation of an element included in the display panel based on a sensing voltage acquired by the sampling operation performed on the reference line, The level of the first reference voltage varies in response to a driving frequency of the display panel.

11. The method according to claim 10, wherein: The first reference voltage changes to a higher level as the driving frequency of the display panel increases.

12. The method according to claim 10, wherein: The first reference voltage is increased from 0 V to 1.x V under the control of the timing controller, where x is an integer of 0 or greater.

13. The method according to claim 10, wherein: Applying the first reference voltage and performing a sampling operation are performed during a blank period of a vertical synchronization signal to drive the display panel.

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