Pixel driving circuit, driving method thereof and display panel

Abstract

The invention provides a pixel driving circuit, a driving method thereof and a display panel, and relates to the technical field of display. The pixel driving circuit comprises a driving transistor, a threshold compensation sub-circuit, a storage sub-circuit and a data write-in sub-circuit. The driving transistor can output driving current under the control of the control electrode voltage; the threshold compensation sub-circuit can compensate the threshold voltage of the driving transistor; the data writing sub-circuit can write a data signal into the pixel driving circuit; the storage sub-circuit can store a threshold voltage and a data signal of the driving transistor; the pixel driving circuit can work in any one of a first working mode and a second working mode: in the first working mode, the pixel driving circuit firstly performs threshold compensation and then performs data writing; and in the second working mode, the pixel driving circuit performs threshold compensation and data writing at the same time. The compatibility of the pixel driving circuit can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and more particularly, to a pixel driving circuit, a driving method thereof, and a display panel. Background Art

[0002] Pixel driving circuits are classified into discrete pixel driving circuits and non-discrete pixel driving circuits according to the threshold compensation method. Since the threshold compensation and data writing are separated in the discrete pixel driving circuit, the threshold compensation is not limited by the data writing time, and the compensation is more sufficient. Since the threshold compensation and data writing are in the same stage in the non-discrete pixel driving circuit, the design of the circuit structure can be simplified and the cost can be reduced.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] The present disclosure provides a pixel driving circuit, a driving method thereof, and a display panel, which can improve the compatibility of the pixel driving circuit.

[0005] According to a first aspect of the present disclosure, a pixel driving circuit is provided. The pixel driving circuit includes a driving transistor, a threshold compensation sub-circuit, a storage sub-circuit, and a data writing sub-circuit; the driving transistor can output a driving current under the control of a control gate voltage;

[0006] The threshold compensation sub-circuit can compensate the threshold voltage of the driving transistor;

[0007] The data writing sub-circuit can write a data signal into the pixel driving circuit;

[0008] The storage sub-circuit can store the threshold voltage of the driving transistor and the data signal;

[0009] The pixel driving circuit can operate in any one of a first operating mode and a second operating mode:

[0010] In the first operating mode, the pixel driving circuit first performs threshold compensation and then performs data writing;

[0011] In the second operating mode, the pixel driving circuit performs threshold compensation and data writing simultaneously.

[0012] In an embodiment of the present disclosure, the threshold compensation sub-circuit includes a threshold compensation transistor;

[0013] The first pole of the threshold compensation transistor, the first pole of the driving transistor, and the first node are electrically connected to each other. The second pole of the threshold compensation transistor, the control pole of the driving transistor, and the second node are electrically connected to each other. The control pole of the threshold compensation transistor is used to load the first reset signal. The threshold compensation transistor is used to conduct in response to the selected on-level of the first reset signal;

[0014] The storage sub-circuit includes a first capacitor and a second capacitor;

[0015] The first end of the first capacitor, the first end of the second capacitor, and the fifth node are electrically connected to each other. The second end of the first capacitor is electrically connected to the second node. The second end of the second capacitor, the second pole of the driving transistor, and the third node are electrically connected to each other;

[0016] The data writing sub-circuit includes a data writing transistor;

[0017] The first pole of the data writing transistor is used to load the data signal. The second pole of the data writing transistor is electrically connected to the third node. The control pole of the data writing transistor is used to load the second scan signal. The data writing transistor is used to conduct in response to the selected on-level of the second scan signal.

[0018] In an embodiment of the present disclosure, the pixel driving circuit further includes a first reset sub-circuit, a second reset sub-circuit, and a third reset sub-circuit;

[0019] Wherein, the first end of the first reset sub-circuit is used to load a first initialization voltage. The second end of the first reset sub-circuit is electrically connected to the fifth node. The control end of the first reset sub-circuit is used to load a second reset signal. The first reset sub-circuit is used to load the first initialization voltage to the fifth node in response to the selected on-level of the second reset signal;

[0020] The first end of the second reset sub-circuit is used to load a second initialization voltage. The second end of the second reset sub-circuit, the pixel electrode, and the fourth node are electrically connected to each other. The control end of the second reset sub-circuit is used to load a third scan signal. The second reset sub-circuit is used to load the second initialization voltage to the fourth node in response to the selected on-level of the third scan signal;

[0021] The first end of the third reset sub-circuit is used to load a reference voltage. The second end of the third reset sub-circuit is electrically connected to the first node. The control end of the third reset sub-circuit is used to load a first scan signal. The third reset sub-circuit is used to load the reference voltage to the first node in response to the selected on-level of the first scan signal.

[0022] In one embodiment of the present disclosure, the first reset sub-circuit includes a first reset transistor;

[0023] A first pole of the first reset transistor is used to load the first initialization voltage, a second pole of the first reset transistor is electrically connected to the fifth node, and a control pole of the first reset transistor is used to load the second reset signal; the first reset transistor is used to conduct in response to an electrified level of the second reset signal;

[0024] The second reset sub-circuit includes a second reset transistor;

[0025] A first pole of the second reset transistor is used to load the second initialization voltage, a second pole of the second reset transistor is electrically connected to the fourth node, and a control pole of the second reset transistor is used to load the third scan signal; the second reset transistor is used to conduct in response to an electrified level of the third scan signal;

[0026] The third reset sub-circuit includes a third reset transistor;

[0027] A first pole of the third reset transistor is used to load the reference voltage, a second pole of the third reset transistor is electrically connected to the first node, and a control pole of the third reset transistor is used to load the first scan signal; the third reset transistor is used to conduct in response to an electrified level of the first scan signal.

[0028] In one embodiment of the present disclosure, the pixel driving circuit further includes a fourth reset sub-circuit; the storage sub-circuit only includes a first capacitor;

[0029] Wherein, a first end of the first capacitor, a first end of the fourth reset sub-circuit, and the fifth node are electrically connected to each other, a second end of the fourth reset sub-circuit is electrically connected to the third node, and a control end of the fourth reset sub-circuit is used to load a fourth reset signal; the fourth reset sub-circuit is used to connect the third node and the fifth node in response to an electrified level of the fourth reset signal;

[0030] A control end of the first reset sub-circuit is used to load a third reset signal; the first reset sub-circuit is used to load the first initialization voltage to the fifth node in response to an electrified level of the third reset signal.

[0031] In one embodiment of the present disclosure, the first reset sub-circuit includes a first reset transistor;

[0032] The first pole of the first reset transistor is used to load the first initialization voltage, the second pole of the first reset transistor is electrically connected to the fifth node, and the control pole of the first reset transistor is used to load the third reset signal; the first reset transistor is used to conduct in response to the selected conduction level of the third reset signal;

[0033] The fourth reset sub - circuit includes a fourth reset transistor. The first pole of the fourth reset transistor is electrically connected to the fifth node, the second pole of the fourth reset transistor is electrically connected to the third node, and the control pole of the fourth reset transistor is used to load a fourth reset signal; the fourth reset transistor is used to conduct in response to the selected conduction level of the fourth reset signal.

[0034] In an embodiment of the present disclosure, the pixel driving circuit further includes a third capacitor. The first end of the third capacitor is used to load a driving power supply voltage, and the second end of the third capacitor is electrically connected to the third node.

[0035] In an embodiment of the present disclosure, the pixel driving circuit further includes a first light - emitting control sub - circuit and a second light - emitting control sub - circuit;

[0036] Among them, the first end of the first light - emitting control sub - circuit is used to load a driving power supply voltage, the second end of the first light - emitting control sub - circuit is electrically connected to the first node, and the control end of the first light - emitting control sub - circuit is used to load a first light - emitting control signal; the first light - emitting control sub - circuit is used to load the driving power supply voltage to the first node in response to the selected conduction level of the first light - emitting control signal;

[0037] The first end of the second light - emitting control sub - circuit is electrically connected to the third node, the second end of the second light - emitting control sub - circuit is electrically connected to the fourth node, and the control end of the second light - emitting control sub - circuit is used to load the second light - emitting control signal; the second light - emitting control sub - circuit is used to connect the third node and the fourth node in response to the selected conduction level of the second light - emitting control signal.

[0038] In an embodiment of the present disclosure, the first light - emitting control sub - circuit includes a first light - emitting control transistor. The first pole of the first light - emitting control transistor is used to load a driving power supply voltage, the second pole of the first light - emitting control transistor is electrically connected to the first node, and the control pole of the first light - emitting control transistor is used to load the first light - emitting control signal; the first light - emitting control transistor is used to conduct in response to the selected conduction level of the first light - emitting control signal;

[0039] The second light-emitting control sub-circuit includes a second light-emitting control transistor. A first pole of the second light-emitting control transistor is electrically connected to the third node. A second pole of the second light-emitting control transistor is electrically connected to the fourth node. A control pole of the second light-emitting control transistor is used to load the second light-emitting control signal. The second light-emitting control transistor is used to conduct in response to an on-level of the second light-emitting control signal.

[0040] In an implementation manner of the present disclosure, at least a channel region of the driving transistor among each transistor is a metal oxide semiconductor material. The driving transistor has a top gate and a bottom gate. The bottom gate of the driving transistor is electrically connected to the third node. The top gate of the driving transistor is electrically connected to the second node.

[0041] According to a second aspect of the present disclosure, there is provided a driving method for a pixel driving circuit, which is applied to the pixel driving circuit described in any of the above implementation manners. Wherein, the driving method of the pixel driving circuit includes:

[0042] In a first working mode, the pixel driving circuit is first subjected to threshold compensation, and then data is written into the pixel driving circuit.

[0043] In a second working mode, threshold compensation and data writing are simultaneously performed on the pixel driving circuit.

[0044] In an implementation manner of the present disclosure, the pixel driving circuit further includes a first light-emitting control transistor and a second light-emitting control transistor. A first pole of the first light-emitting control transistor is used to load a driving power supply voltage. A second pole of the first light-emitting control transistor is electrically connected to the first node. A control pole of the first light-emitting control transistor is used to load a first light-emitting control signal. The first light-emitting control transistor is used to conduct in response to an on-level of the first light-emitting control signal.

[0045] A first pole of the second light-emitting control transistor is electrically connected to the third node. A second pole of the second light-emitting control transistor is electrically connected to the fourth node. A control pole of the second light-emitting control transistor is used to load a second light-emitting control signal. The second light-emitting control transistor is used to conduct in response to an on-level of the second light-emitting control signal.

[0046] The driving method of the pixel driving circuit includes:

[0047] In the first working mode:

[0048] In a reset stage, on-levels of the first reset signal, the second reset signal, the first scan signal, and the third scan signal are loaded to the pixel driving circuit.

[0049] In the writing stage, the selected conduction level of the second scan signal is loaded to the pixel driving circuit;

[0050] In the light emitting stage, the selected conduction levels of the second reset signal, the first light emission control signal, and the second light emission control signal are loaded to the pixel driving circuit.

[0051] In an embodiment of the present disclosure, the driving method of the pixel driving circuit includes:

[0052] In the second working mode:

[0053] In the reset stage, the selected conduction levels of the first reset signal, the second reset signal, the first scan signal, and the third scan signal are loaded to the pixel driving circuit;

[0054] In the writing stage, the selected conduction levels of the first reset signal, the second reset signal, and the second scan signal are loaded to the pixel driving circuit;

[0055] In the light emitting stage, the selected conduction levels of the second reset signal, the first light emission control signal, and the second light emission control signal are loaded to the pixel driving circuit.

[0056] In an embodiment of the present disclosure, the pixel driving circuit further includes a first light emission control transistor and a second light emission control transistor. The first pole of the first light emission control transistor is used to load a driving power supply voltage. The second pole of the first light emission control transistor is electrically connected to the first node. The control pole of the first light emission control transistor is used to load the first light emission control signal; the first light emission control transistor is used to conduct in response to the selected conduction level of the first light emission control signal;

[0057] The first pole of the second light emission control transistor is electrically connected to the third node. The second pole of the second light emission control transistor is electrically connected to the fourth node. The control pole of the second light emission control transistor is used to load the second light emission control signal; the second light emission control transistor is used to conduct in response to the selected conduction level of the second light emission control signal;

[0058] The driving method of the pixel driving circuit includes:

[0059] In the first working mode:

[0060] In the reset stage, the selected conduction levels of the first reset signal, the third reset signal, the first scan signal, and the third scan signal are loaded to the pixel driving circuit;

[0061] In the writing stage, the selected conduction levels of the fourth reset signal and the second scan signal are loaded to the pixel driving circuit;

[0062] During the light-emitting stage, the selected conduction levels of the first light-emitting control signal and the second light-emitting control signal are loaded to the pixel driving circuit.

[0063] In an embodiment of the present disclosure, the driving method of the pixel driving circuit includes:

[0064] In the second working mode:

[0065] During the reset stage, the selected conduction levels of the first reset signal, the third reset signal, the fourth reset signal, the first scan signal, and the third scan signal are loaded to the pixel driving circuit;

[0066] During the writing stage, the selected conduction levels of the first reset signal, the third reset signal, and the second scan signal are loaded to the pixel driving circuit;

[0067] During the light-emitting stage, the selected conduction levels of the first light-emitting control signal and the second light-emitting control signal are loaded to the pixel driving circuit.

[0068] According to the third aspect of the present disclosure, a display panel is provided, including the pixel driving circuit described in any of the above embodiments.

[0069] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0071] Figure 1 FIG. is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0072] Figure 2 FIG. is a schematic diagram of the film layers of a display panel in an embodiment of the present disclosure.

[0073] Figure 3 FIG. is an equivalent circuit diagram of a pixel driving circuit in an embodiment of the present disclosure.

[0074] Figure 4 FIG. is an equivalent circuit diagram of a pixel driving circuit in an embodiment of the present disclosure.

[0075] Figure 5 FIG. Figure 4 is the driving timing diagram of the pixel driving circuit in the first working mode.

[0076] Figure 6 For Figure 4 the driving timing diagram of the pixel driving circuit in the second working mode.

[0077] Figure 7 In an embodiment of the present disclosure, it is the equivalent circuit diagram of the pixel driving circuit.

[0078] Figure 8 In an embodiment of the present disclosure, it is the equivalent circuit diagram of the pixel driving circuit.

[0079] Figure 9 For Figure 8 the driving timing diagram of the pixel driving circuit in the first working mode.

[0080] Figure 10 For Figure 8 the driving timing diagram of the pixel driving circuit in the second working mode. Detailed Embodiments

[0081] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0082] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the direction of the examples described in the drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0083] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second" and "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0084] In an embodiment of the present disclosure, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. The channel region refers to the region where current mainly flows.

[0085] In an embodiment of the present disclosure, in the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and the "drain electrode" may be interchanged with each other. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other. In an embodiment of the present disclosure, for any transistor, one of the "source" and the "drain" is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor, and the gate is referred to as the control pole of the transistor. The first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In an embodiment of the present disclosure, at least some signals have a high level and a low level; one of the high level and the low level can be used as the selected conduction level of the signal, and the selected conduction level of the signal can make the controlled transistor conduct; the other of the high level and the low level can be used as the cut-off level of the signal, and the cut-off level of the signal can make the controlled transistor cut off. For example, for a signal that controls a P-type transistor (the signal can be applied to the control pole of the P-type transistor), its selected conduction level is the low level, and its cut-off level is the high level. For another example, for a signal that controls an N-type transistor (the signal can be applied to the control pole of the N-type transistor), its selected conduction level is the high level, and its cut-off level is the low level.

[0086] In an embodiment of the present disclosure, for a driving transistor that has both a top gate and a bottom gate at the same time, only the top gate is referred to as the control pole of the driving transistor, and the bottom gate is not used as the control pole of the driving transistor.

[0087] The structural layer X is located on the side of the structural layer Y away from the substrate. It can be understood that the structural layer X is formed on the side of the structural layer Y facing away from the substrate. When the structural layer Y is a patterned structure, some structures of the structural layer X can also be located at the same physical height as the structural layer Y or at a physical height lower than that of the structural layer Y, where the substrate is the height reference.

[0088] An embodiment of the present disclosure provides a display panel PNL. Refer to Figure 1, the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. The display area AA of the display panel PNL includes display units arranged in an array. The display unit includes a sub-pixel PIX and a pixel driving circuit PDC for driving the sub-pixel PIX. Among them, the display panel PNL has a plurality of scan lines GL arranged in the row direction DH in the display area AA, and each scan line GL is correspondingly arranged with each row of display units; the scan line GL is connected to each pixel driving circuit PDC of the corresponding row of display units. The display panel PNL has a plurality of data lines DL arranged in the column direction DV in the display area AA, and each data line DL is correspondingly arranged with each column of display units; the data line DL is connected to each pixel driving circuit PDC of the corresponding column of display units. In this way, the pixel driving circuit PDC of each display unit is connected to a scan line GL and a data line DL. When a gate signal is loaded on the scan line GL, the data voltage loaded on the data line DL can be loaded onto the pixel driving circuit PDC, so that the pixel driving circuit PDC can control the brightness of the sub-pixel PIX according to the written driving voltage.

[0089] Optionally, the sub-pixel PIX can be a current-driven self-luminous element, such as an organic light-emitting diode (OLED), a polymer light-emitting diode (PLED), a quantum dot light-emitting diode (QLED), a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), or any other such light-emitting element. In this embodiment, the sub-pixel PIX can include sub-pixels PIX of multiple different colors, such as a red sub-pixel for emitting red light, a green sub-pixel for emitting green light, and a blue sub-pixel for emitting blue light. It can be understood that in other embodiments of the present disclosure, the sub-pixels PIX in the display area AA can also have sub-pixels PIX of other colors (such as a yellow sub-pixel for emitting yellow light, a cyan sub-pixel for emitting cyan light, a white sub-pixel for emitting white light, etc.).

[0090] In one embodiment of the present disclosure, refer to Figure 2, the display panel PNL may include a substrate base BP, a driving layer DRL, and a pixel layer PIXL that are sequentially stacked. Sub-pixels PIX are provided in the pixel layer PIXL, and a pixel driving circuit PDC for driving the sub-pixels PIX is provided in the driving layer DRL; each sub-pixel PIX can emit light under the drive of the pixel driving circuit PDC to display an image. Further, the display panel PNL further includes a thin film encapsulation layer TFE on the side of the pixel layer PIXL away from the substrate base BP, and the thin film encapsulation layer TFE can encapsulate and protect the pixel layer PIXL.

[0091] Optionally, the substrate base BP can be a substrate base of inorganic material, or a substrate base of organic material; of course, it can also be a composite substrate formed by laminating a substrate base of inorganic material and a substrate base of organic material. For example, in some embodiments of the present disclosure, the material of the substrate base BP can be glass materials such as soda-lime glass, quartz glass, and sapphire glass. In some other embodiments of the present disclosure, the material of the substrate base BP can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate or a combination thereof. In some other embodiments of the present disclosure, the substrate base BP can also be a flexible substrate base, for example, the material of the substrate base BP can include polyimide.

[0092] Optionally, in the driving layer DRL, any one pixel driving circuit PDC can include a thin film transistor TFT and a storage capacitor. Further, the thin film transistor TFT can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a double-gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor materials; the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0093] It can be understood that among the transistors in the pixel driving circuit PDC, the types of any two transistors can be the same or different. Exemplarily, in some embodiments, in a pixel driving circuit PDC, some transistors can be N-type transistors and some transistors can be P-type transistors. Another example is that in some other embodiments, in a pixel driving circuit PDC, the material of the active layer of some transistors can be low-temperature polycrystalline silicon semiconductor material, and the material of the active layer of some transistors can be metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low-temperature polycrystalline silicon transistor. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polycrystalline silicon transistors and some thin film transistors are metal oxide transistors.

[0094] Optionally, the driving layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, a planarization layer PLN, etc., which are stacked between the substrate BP and the pixel layer PIXL. Each thin film transistor and storage capacitor may be located in film layers such as the semiconductor layer SCL, the gate insulating layer GI, the gate layer GT, the interlayer dielectric layer ILD, and the source-drain metal layer SD. Among them, the positional relationship of each film layer may be determined according to the film layer structure of the thin film transistor. Further, the semiconductor layer SCL may be used to form the channel region of the transistor, and in necessary cases, partial traces or conductive structures may also be formed by conductorization. The gate layer GT may be used to form one or more of the gate layer GT traces such as the write control trace, the reset control trace, and the light emission control trace, may also be used to form the gate of the transistor, and may also be used to form part or all of the electrode plates of the storage capacitor. The source-drain metal layer SD may be used to form source-drain metal layer traces such as data traces and driving power supply voltage traces, and may also be used to form part of the electrode plates of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL may also include other film layers according to needs, for example, may also include a light-shielding layer located between the semiconductor layer SCL and the substrate BP. According to needs, any one of the above film layers such as the semiconductor layer SCL, the gate layer GT, and the source-drain metal layer SD may also be a multi-layer. For example, the driving layer DRL may include two different semiconductor layers SCL, or include two or three source-drain metal layers SD, or include two or three gate layers GT; correspondingly, the insulating film layers (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) in the driving layer DRL may be adaptively increased or decreased, or new insulating film layers may be added according to needs.

[0095] Optionally, the driving layer DRL may further include a passivation layer, and the passivation layer may be disposed on the surface of the source-drain metal layer SD away from the substrate BP to protect the source-drain metal layer SD.

[0096] As an example, referring to Figure 2 , the driving layer DRL may include a buffer layer Buff, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, and a planarization layer PLN that are sequentially stacked, and the thin film transistor thus formed is a top-gate thin film transistor.

[0097] In one embodiment of the present disclosure, the sub-pixel PIX in the pixel layer PIXL is a thin film type light emitting element, which may include two electrodes stacked and a light emitting functional unit sandwiched between the two electrodes. For example, referring to Figure 2, the pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer EFL, and a common electrode layer COML that are sequentially stacked. Among them, the pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area of the display panel; the part of the light-emitting functional layer EFL connected to the pixel electrode PE serves as the light-emitting functional unit of the sub-pixel PIX, and the common electrode layer COML serves as a common electrode and is electrically connected to the light-emitting functional units of each sub-pixel PIX.

[0098] Furthermore, the pixel layer PIXL may further include a pixel definition layer PDL located between the pixel electrode layer PEL and the light-emitting functional layer EFL. The pixel definition layer PDL has a plurality of through pixel openings corresponding one-to-one to the plurality of pixel electrodes PE, and any one pixel opening exposes at least a partial area of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode PE and exposes at least a partial internal area of the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of the pixel electrode PE (the area directly connected to the light-emitting functional unit), and further define the light-emitting area and light-emitting area of the sub-pixel PIX. The light-emitting functional layer EFL covers at least the pixel electrode PE exposed by the pixel definition layer PDL. The common electrode layer COML may cover the light-emitting functional layer EFL in the display area. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EFL, so that the light-emitting functional layer EFL emits light. The part of the light-emitting functional layer EFL located between the pixel electrode layer PEL and the common electrode layer COML may serve as a light-emitting functional unit. The pixel electrode PE, the common electrode layer COML, and the light-emitting functional unit form a sub-pixel PIX. Among them, one of the pixel electrode PE and the common electrode layer COML serves as the anode of the sub-pixel PIX, and the other serves as the cathode of the sub-pixel PIX.

[0099] In one example, the pixel electrode PE serves as the anode of the sub-pixel PIX, and the common electrode layer COML serves as the cathode of the sub-pixel PIX.

[0100] It can be understood that the types of light-emitting elements are different, and the materials and film layers of the light-emitting functional units are different. For example, when the light-emitting element is an OLED, the light-emitting functional unit may include an organic electroluminescent material layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0101] See Figure 2, the thin film encapsulation layer TFE can be disposed on the surface of the pixel layer PIXL away from the substrate BP, and it can include an inorganic encapsulation layer and an organic encapsulation layer that are alternately stacked. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PIXL and causing the materials in the pixel layer PIXL to age. Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce the stress between the inorganic encapsulation layers. Among them, the edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2 that are sequentially stacked on the side of the pixel layer PIXL away from the substrate BP. The first inorganic encapsulation layer CVD1 covers the display area and extends to the outside of the barrier rib; the organic encapsulation layer covers the display area and extends to the inside of the barrier rib; the second inorganic encapsulation layer CVD2 covers the organic encapsulation layer IJP and extends to the outside of the barrier rib. On the outside of the barrier rib, the second inorganic encapsulation layer CVD2 contacts the first inorganic encapsulation layer CVD1. In this way, the organic encapsulation layer IJP is enclosed by the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2, and the stress between the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 is balanced. The first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 enclose the organic encapsulation layer IJP, isolating the organic encapsulation layer IJP from contact with water and oxygen.

[0102] In some embodiments of the present disclosure, referring to Figure 2 , the display panel PNL may further include a touch function layer TSL, and the touch function layer TSL can be disposed on the side of the thin film encapsulation layer TFE away from the driving backplane DBP, so that the display panel PNL has a touch function.

[0103] Optionally, the pixel driving circuit PDC includes at least a data writing transistor, a driving transistor, and a storage capacitor. The gate of the driving transistor can be electrically connected to one electrode plate of the storage capacitor. The source of the data writing transistor can be electrically connected to the data line DL, and the gate of the data writing transistor can be electrically connected to the scanning line GL. The pixel driving circuit PDC is configured such that when a scanning signal is loaded on the scanning line GL, the data writing transistor is turned on, and thus the driving voltage on the data line DL is written into the gate of the driving transistor and the storage capacitor. After the data writing transistor is turned off, the driving voltage can be held by the storage capacitor. The driving transistor can output a driving current under the control of the voltage on its gate to drive the sub-pixel PIX to emit light. It can be understood that the pixel driving circuit PDC according to the embodiments of the present disclosure may further include other transistors or capacitors to enable the pixel driving circuit PDC to have better driving performance. For example, the pixel driving circuit PDC may be a 7T1C (7 thin film transistors and 1 storage capacitor), an 8T1C (8 thin film transistors and 1 storage capacitor), or a pixel driving circuit with other architectures.

[0104] In the related art, pixel driving circuits are classified into a separate pixel driving circuit and a non-separate pixel driving circuit according to the threshold compensation method. Since the threshold compensation and data writing of the separate pixel driving circuit are separated, the threshold compensation is not limited by the data writing time, and the compensation is more sufficient. Since the threshold compensation and data writing of the non-separate pixel driving circuit are in the same stage, the design of the circuit structure can be simplified and the cost can be reduced. However, the separate pixel driving circuit can only be driven by a separate driving method, and the non-separate pixel driving circuit can only be driven by a non-separate driving method, which cannot cope with complex driving situations and reduces the compatibility of the pixel driving circuit.

[0105] To solve the above problems, the embodiments of the present disclosure provide a pixel driving circuit PDC applied to a display panel PNL. Refer to Figure 3 、 Figure 7 , the pixel driving circuit PDC includes a driving transistor T3, a threshold compensation sub-circuit SW2, a storage sub-circuit SW3, and a data writing sub-circuit SW4. Among them, the driving transistor T3 can output a driving current under the control of a control electrode voltage.

[0106] The first end of the threshold compensation sub-circuit SW2 is electrically connected to the first node N1. The second end of the threshold compensation sub-circuit SW2, the control electrode of the driving transistor T3, one end of the storage sub-circuit SW3, and the second node N2 are electrically connected to each other. The control end of the threshold compensation sub-circuit SW2 is used to load a first reset signal RST1. The threshold compensation sub-circuit SW2 is configured to connect the first node N1 and the second node N2 in response to the selected electrical level of the first reset signal RST1 to compensate for the threshold voltage of the driving transistor T3.

[0107] The first terminal of the data writing sub - circuit SW4 is used to load the data signal Data. The second terminal of the data writing sub - circuit SW4, the second terminal of the driving transistor T3, the other end of the storage sub - circuit SW3, and the third node N3 are electrically connected to each other. The control terminal of the data writing sub - circuit SW4 is used to load the second scan signal G2; the data writing sub - circuit SW4 is configured to load the data signal Data to the third node N3 in response to the selected - on level of the second scan signal G2, so as to be able to write the data signal Data to the pixel driving circuit PDC.

[0108] The storage sub - circuit SW3 can store the threshold voltage of the driving transistor T3 and the data signal Data.

[0109] The pixel driving circuit PDC can operate in any one of a first operating mode and a second operating mode:

[0110] In the first operating mode, the pixel driving circuit PDC first performs threshold compensation and then performs data writing.

[0111] In the second operating mode, the pixel driving circuit PDC performs threshold compensation and data writing simultaneously.

[0112] Thus, the pixel driving circuit PDC has a first operating mode and a second operating mode. In the first operating mode, the pixel driving circuit PDC can first write the threshold voltage of the driving transistor T3 to the control electrode (the second node N2) of the driving transistor T3 through the threshold compensation sub-circuit SW2, and then write the data signal Data to the third node N3 through the data writing sub-circuit SW4. Through the coupling effect of the storage sub-circuit SW3, the data signal Data is written to the control electrode of the driving transistor T3. The storage sub-circuit SW3 stores the threshold voltage of the driving transistor T3 and the data signal Data. During the light-emitting stage, the driving transistor T3 generates a driving current to drive the light-emitting element to emit light. This operating mode can be applied to the high-frequency refresh mode. In the second operating mode, the pixel driving circuit PDC can write the threshold voltage of the driving transistor T3 and the data signal Data to the control electrode of the driving transistor T3 through the threshold compensation sub-circuit SW2 and the data writing sub-circuit SW4 at the same time. The storage sub-circuit SW3 stores the threshold voltage of the driving transistor T3 and the data signal Data. During the light-emitting stage, the driving transistor T3 generates a driving current to drive the light-emitting element to emit light. This operating mode can be applied to the low-frequency refresh mode to reduce power consumption. By setting a pixel driving circuit PDC with two operating modes, compared with the pixel driving circuit PDC in the related art that can only operate in one operating mode, the pixel driving circuit PDC of the present disclosure embodiment can be applied to complex operating modes (such as high-frequency refresh mode and low-frequency refresh mode), improving the compatibility and flexibility of the pixel driving circuit PDC and optimizing the structural design of the pixel driving circuit PDC.

[0113] In an embodiment of the present disclosure, the pixel driving circuit PDC can select one of the first operating mode and the second operating mode to operate. In one example, the pixel driving circuit PDC can select the corresponding operating mode according to the requirements of the driving chip. For example, when the system needs to perform a high-frequency refresh mode, the driving chip can control the pixel driving circuit PDC to operate in the first operating mode. For another example, when the system needs to perform a low-frequency refresh mode, the driving chip can control the pixel driving circuit PDC to operate in the second operating mode. In another example, the user can manually control the operating mode of the pixel driving circuit PDC according to the usage requirements. For example, when the user needs the system to perform a high-frequency refresh mode, an instruction can be sent to the driving chip, and after receiving the instruction, the driving chip can control the pixel driving circuit PDC to operate in the first operating mode. For another example, when the user needs the system to perform a low-frequency refresh mode, an instruction can be sent to the driving chip, and after receiving the instruction, the driving chip can control the pixel driving circuit PDC to operate in the second operating mode.

[0114] In an embodiment of the present disclosure, refer to Figure 3 、Figure 7 The threshold compensation sub - circuit SW2 includes a threshold compensation transistor T2. The first pole of the threshold compensation transistor T2, the first pole of the driving transistor T3, and the first node N1 are electrically connected to each other. The second pole of the threshold compensation transistor T2, the control pole of the driving transistor T3, and the second node N2 are electrically connected to each other. The control pole of the threshold compensation transistor T2 is used to load the first reset signal RST1; the threshold compensation transistor T2 is used to conduct in response to the selected - on level of the first reset signal RST1. In some other embodiments of the present disclosure, the threshold compensation sub - circuit SW2 may include a plurality of threshold compensation transistors T2 connected in series or in parallel. Thus, by loading the selected - on level of the first reset signal RST1 on the control pole of the threshold compensation transistor T2, the threshold compensation transistor T2 is made to conduct, so as to connect the first node N1 and the second node N2, facilitating the writing of the threshold voltage of the driving transistor T3 into the second node N2.

[0115] In one embodiment of the present disclosure, referring to Figure 3 , Figure 7 the data writing sub - circuit SW4 includes a data writing transistor T4. The first pole of the data writing transistor T4 is used to load the data signal Data, the second pole of the data writing transistor T4 is electrically connected to the third node N3, and the control pole of the data writing transistor T4 is used to load the second scan signal G2; the data writing transistor T4 is used to conduct in response to the selected - on level of the second scan signal G2. In some other embodiments of the present disclosure, the data writing sub - circuit SW4 may include a plurality of data writing transistors T4 connected in series or in parallel. Thus, by loading the selected - on level of the second scan signal G2 on the control pole of the data writing transistor T4, the data writing transistor T4 is made to conduct, and the data signal Data can be loaded to the third node N3, facilitating the writing of the data signal Data into the second node N2.

[0116] In one embodiment of the present disclosure, referring to Figure 3 the storage sub - circuit SW3 includes a first capacitor C1 and a second capacitor C2. The first end of the first capacitor C1, the first end of the second capacitor C2, and the fifth node N5 are electrically connected to each other. The second end of the first capacitor C1 is electrically connected to the second node N2. The second end of the second capacitor C2, the second pole of the driving transistor T3, and the third node N3 are electrically connected to each other. Thus, in the first working mode, the data signal Data can be coupled from the third node N3 to the second node N2 through the first capacitor C1 and the second capacitor C2, which is beneficial to the writing of the data signal Data.

[0117] In one embodiment of the present disclosure, referring to Figure 3, the pixel driving circuit PDC further includes a first reset sub - circuit SW1, a second reset sub - circuit SW7, and a third reset sub - circuit SW8. Among them, the first end of the first reset sub - circuit SW1 is used to load a first initialization voltage Vinit1, the second end of the first reset sub - circuit SW1 is electrically connected to the fifth node N5, and the control end of the first reset sub - circuit SW1 is used to load a second reset signal RST2. The first reset sub - circuit SW1 is used to load the first initialization voltage Vinit1 to the fifth node N5 in response to the selected - on level of the second reset signal RST2. In this way, by turning on the first reset sub - circuit SW1, the first initialization voltage Vinit1 can be loaded to the fifth node N5 to reset and stabilize the voltage of the fifth node N5.

[0118] The first end of the second reset sub - circuit SW7 is used to load a second initialization voltage Vinit2, the second end of the second reset sub - circuit SW7, the pixel electrode, and the fourth node N4 are electrically connected to each other, and the control end of the second reset sub - circuit SW7 is used to load a third scan signal G3; the second reset sub - circuit SW7 is used to load the second initialization voltage Vinit2 to the fourth node N4 in response to the selected - on level of the third scan signal G3. In this way, by turning on the second reset sub - circuit SW7, the second initialization voltage Vinit2 can be loaded to the fourth node N4 to reset the pixel electrode of the light - emitting element.

[0119] The first end of the third reset sub - circuit SW8 is used to load a reference voltage Vref, the second end of the third reset sub - circuit SW8 is electrically connected to the first node N1, and the control end of the third reset sub - circuit SW8 is used to load a first scan signal G1; the third reset sub - circuit SW8 is used to load the reference voltage Vref to the first node N1 in response to the selected - on level of the first scan signal G1. In this way, by turning on the third reset sub - circuit SW8 and the threshold compensation sub - circuit SW2, the reference voltage Vref can be loaded to the first node N1 to facilitate the reset of the first node N1 and the second node N2.

[0120] In an embodiment of the present disclosure, refer to Figure 3, the first reset sub - circuit SW1 includes a first reset transistor T1. The first pole of the first reset transistor T1 is used to load a first initialization voltage Vinit1. The second pole of the first reset transistor T1 is electrically connected to the fifth node N5. The control pole of the first reset transistor T1 is used to load a second reset signal RST2; the first reset transistor T1 is used to conduct in response to the selected - on level of the second reset signal RST2. In some other embodiments of the present disclosure, the first reset sub - circuit SW1 may include a plurality of first reset transistors T1 connected in series or in parallel. Thus, by loading the selected - on level of the second reset signal RST2 to the control pole of the first reset transistor T1 to make the first reset transistor T1 conduct, the first initialization voltage Vinit1 can be loaded to the fifth node N5, facilitating the reset of the fifth node N5.

[0121] In one embodiment of the present disclosure, referring to Figure 3 , Figure 7 , the second reset sub - circuit SW7 includes a second reset transistor T7. The first pole of the second reset transistor T7 is used to load a second initialization voltage Vinit2. The second pole of the second reset transistor T7 is electrically connected to the fourth node N4. The control pole of the second reset transistor T7 is used to load a third scan signal G3; the second reset transistor T7 is used to conduct in response to the selected - on level of the third scan signal G3. In one embodiment of the present disclosure, the second reset sub - circuit SW7 may include a plurality of second reset transistors T7 connected in series or in parallel. Thus, by loading the selected - on level of the third scan signal G3 to the control pole of the second reset transistor T7 to make the second reset transistor T7 conduct, the second initialization voltage Vinit2 can be loaded to the fourth node N4, facilitating the reset of the fourth node N4.

[0122] In one embodiment of the present disclosure, referring to Figure 3 , Figure 7 , the third reset sub - circuit SW8 includes a third reset transistor T8. The first pole of the third reset transistor T8 is used to load a reference voltage Vref. The second pole of the third reset transistor T8 is electrically connected to the first node N1. The control pole of the third reset transistor T8 is used to load a first scan signal G1; the third reset transistor T8 is used to conduct in response to the selected - on level of the first scan signal G1. In some other embodiments of the present disclosure, the third reset sub - circuit SW8 may include a plurality of third reset transistors T8 connected in series or in parallel. Thus, by loading the selected - on level of the first scan signal G1 to the control pole of the third reset transistor T8 to make the third reset transistor T8 conduct, the reference voltage Vref can be loaded to the first node N1, facilitating the reset of the first node N1.

[0123] In one embodiment of the present disclosure, referring to Figure 7, the pixel driving circuit PDC further includes a fourth reset sub-circuit SW9; the storage sub-circuit SW3 only includes a first capacitor C1. Wherein, the first end of the first capacitor C1, the first end of the fourth reset sub-circuit SW9, and the fifth node N5 are electrically connected to each other, the second end of the fourth reset sub-circuit SW9 is electrically connected to the third node N3, and the control end of the fourth reset sub-circuit SW9 is used to load a fourth reset signal RST4; the fourth reset sub-circuit SW9 is used to connect the third node N3 and the fifth node N5 in response to the selected on-level of the fourth reset signal RST4; the control end of the first reset sub-circuit SW1 is used to load a third reset signal RST3; the first reset sub-circuit SW1 is used to load the first initialization voltage Vinit1 to the fifth node N5 in response to the selected on-level of the third reset signal RST3. Thus, by turning on the first reset sub-circuit SW1 and the fourth reset sub-circuit SW9, the third node N3 and the fifth node N5 can be connected, facilitating the loading of the first initialization voltage Vinit1 to the third node N3 and the fifth node N5 to reset the third node N3 and the fifth node N5.

[0124] In an embodiment of the present disclosure, refer to Figure 7 , the first reset sub-circuit SW1 includes a first reset transistor T1. The first pole of the first reset transistor T1 is used to load the first initialization voltage Vinit1, the second pole of the first reset transistor T1 is electrically connected to the fifth node N5, and the control pole of the first reset transistor T1 is used to load the third reset signal RST3; the first reset transistor T1 is used to conduct in response to the selected on-level of the third reset signal RST3. In some other embodiments of the present disclosure, the first reset sub-circuit SW1 may include a plurality of first reset transistors T1 connected in series or in parallel. Thus, by loading the selected on-level of the third reset signal RST3 to the control pole of the first reset transistor T1 to make the first reset transistor T1 conduct, the first initialization voltage Vinit1 can be loaded to the fifth node N5, facilitating the reset of the fifth node N5.

[0125] In an embodiment of the present disclosure, refer to Figure 7, the fourth reset sub - circuit SW9 includes a fourth reset transistor T9. The first pole of the fourth reset transistor T9 is electrically connected to the fifth node N5, the second pole of the fourth reset transistor T9 is electrically connected to the third node N3, and the control pole of the fourth reset transistor T9 is used to load a fourth reset signal RST4; the fourth reset transistor T9 is used to conduct in response to the selected - on level of the fourth reset signal RST4. In some other embodiments of the present disclosure, the fourth reset sub - circuit SW9 may include a plurality of fourth reset transistors T9 connected in series or in parallel. Thus, by loading the selected - on level of the fourth reset signal RST4 to the control pole of the fourth reset transistor T9 to make the fourth reset transistor T9 conduct, the first initialization voltage Vinit1 can be loaded to the third node N3, facilitating the reset of the third node N3.

[0126] In one embodiment of the present disclosure, referring to Figure 7 , the pixel driving circuit PDC further includes a third capacitor C3. The first end of the third capacitor C3 is used to load a driving power supply voltage VDD, and the second end of the third capacitor C3 is electrically connected to the third node N3. Thus, the third capacitor C3 can stabilize the voltage of the third node N3, improving the stability of the pixel driving circuit PDC.

[0127] In one embodiment of the present disclosure, referring to Figure 3 、 Figure 7 , the pixel driving circuit PDC further includes a first light - emitting control sub - circuit SW5 and a second light - emitting control sub - circuit SW6. Among them, the first end of the first light - emitting control sub - circuit SW5 is used to load a driving power supply voltage VDD, the second end of the first light - emitting control sub - circuit SW5 is electrically connected to the first node N1, and the control end of the first light - emitting control sub - circuit SW5 is used to load a first light - emitting control signal EM1; the first light - emitting control sub - circuit SW5 is used to make the driving power supply voltage VDD load to the first node N1 in response to the selected - on level of the first light - emitting control signal EM1.

[0128] The first end of the second light - emitting control sub - circuit SW6 is electrically connected to the third node N3, the second end of the second light - emitting control sub - circuit SW6 is electrically connected to the fourth node N4, and the control end of the second light - emitting control sub - circuit SW6 is used to load a second light - emitting control signal EM2; the second light - emitting control sub - circuit SW6 is used to connect the third node N3 and the fourth node N4 in response to the selected - on level of the second light - emitting control signal EM2. Thus, by turning on the first light - emitting control sub - circuit SW5 and the second light - emitting control sub - circuit SW6, the driving power supply voltage VDD can be loaded to the third node N3, so that the driving transistor T3 generates a driving current, and the driving current can flow through the second light - emitting control transistor T6 to reach the light - emitting element to realize the light - emission of the light - emitting element.

[0129] In one embodiment of the present disclosure, referring toFigure 3 , Figure 7 , the first light-emitting control sub-circuit SW5 includes a first light-emitting control transistor T5. The first pole of the first light-emitting control transistor T5 is used to load the driving power supply voltage VDD. The second pole of the first light-emitting control transistor T5 is electrically connected to the first node N1. The control pole of the first light-emitting control transistor T5 is used to load the first light-emitting control signal EM1. The first light-emitting control transistor T5 is used to turn on in response to the selected conduction level of the first light-emitting control signal EM1. In this way, by loading the selected conduction level of the first light-emitting control signal EM1 on the control pole of the first light-emitting control transistor T5 to turn on the first light-emitting control transistor T5, the driving power supply voltage VDD can be loaded to the third node N3, facilitating the driving transistor T3 to generate a driving current.

[0130] In an embodiment of the present disclosure, referring to Figure 3 , Figure 7 , the number of the first light-emitting control transistors T5 can be multiple. The multiple first light-emitting control transistors T5 are connected in series. The control poles of the multiple first light-emitting control transistors T5 are all used to load the first light-emitting control signal EM1. The first pole of one of the first light-emitting control transistors T5 is used to load the driving power supply voltage VDD. The second pole of one of the first light-emitting control transistors T5 is electrically connected to the first node N1. For example, the number of the first light-emitting control transistors T5 can be two, three, four, etc. In this way, the switching performance can be improved by multiple first light-emitting control transistors T5, preventing the driving power supply voltage VDD from leaking to the first node N1.

[0131] In an embodiment of the present disclosure, referring to Figure 3 , Figure 7 , the second light-emitting control sub-circuit SW6 includes a second light-emitting control transistor T6. The first pole of the second light-emitting control transistor T6 is electrically connected to the third node N3. The second pole of the second light-emitting control transistor T6 is electrically connected to the fourth node N4. The control pole of the second light-emitting control transistor T6 is used to load the second light-emitting control signal EM2. The second light-emitting control transistor T6 is used to turn on in response to the selected conduction level of the second light-emitting control signal EM2. In some other embodiments of the present disclosure, the second light-emitting control sub-circuit SW6 can include multiple second light-emitting control transistors T6 connected in series or in parallel. In this way, by loading the selected conduction level of the second light-emitting control signal EM2 on the control pole of the second light-emitting control transistor T6 to turn on the second light-emitting control transistor T6, the driving current generated by the driving transistor T3 can be loaded to the fourth node N4, facilitating the light-emitting element to emit light.

[0132] In an embodiment of the present disclosure, the channel regions of at least the driving transistor T3 among the transistors are made of metal oxide semiconductor material. The driving transistor T3 has a top gate and a bottom gate. The bottom gate of the driving transistor T3 is electrically connected to the third node N3, and the top gate of the driving transistor T3 is electrically connected to the second node N2. In this way, the bottom gate of the driving transistor T3 is connected to the third node N3, which can reduce the electron mobility of the driving transistor T3 and increase the subthreshold swing (SS) of the driving transistor T3, which is beneficial to improving the low gray-scale image quality of the display panel PNL.

[0133] In one example, referring to Figure 3 、 Figure 7 , the channel regions of the first reset transistor T1, the threshold compensation transistor T2, and the driving transistor T3 are made of metal oxide semiconductor material to reduce the leakage current of the first reset transistor T1 and the threshold compensation transistor T2, facilitate the normal light emission of the light-emitting element, and improve the display quality of the display panel PNL. In another example, the channel regions of all the transistors of the pixel driving circuit PDC are made of metal oxide semiconductor material.

[0134] In an embodiment of the present disclosure, referring to Figure 3 、 Figure 7 , both the first reset transistor T1 and the threshold compensation transistor T2 have a top gate and a bottom gate. The top gate and the bottom gate of the first reset transistor T1 are electrically connected to load the same signal; the top gate and the bottom gate of the threshold compensation transistor T2 are electrically connected to load the same signal. In some other embodiments of the present disclosure, one of the first reset transistor T1 and the threshold compensation transistor T2 has a top gate and a bottom gate. In this way, the stability of the first reset transistor T1 and the threshold compensation transistor T2 can be improved, and the influence of impurities in the organic material on the channel regions of the first reset transistor T1 and the threshold compensation transistor T2 can be reduced.

[0135] In an embodiment of the present disclosure, the first initialization voltage Vinit1 and the second initialization voltage Vinit2 can be the same signal. The first light emission control signal EM1 and the second light emission control signal EM2 can be the same signal. The first scan signal G1 and the third scan signal G3 can be the same signal. In this way, the number of gate driving circuits and traces can be reduced, which is beneficial to the narrow bezel of the display panel PNL and reduces the production cost.

[0136] The present disclosure embodiment also provides a driving method for a pixel driving circuit PDC, which is applied to the pixel driving circuit PDC described in any of the above embodiments. Among them, the driving method of the pixel driving circuit PDC includes:

[0137] In the first working mode, the pixel driving circuit PDC is first subjected to threshold compensation, and then data is written into the pixel driving circuit PDC.

[0138] In the second working mode, threshold compensation and data writing are simultaneously performed on the pixel driving circuit PDC.

[0139] In this way, the pixel driving circuit PDC can work in different working modes according to requirements, improving the compatibility and flexibility of the pixel driving circuit PDC and optimizing the structural design of the pixel driving circuit PDC.

[0140] The following further describes the pixel driving circuit PDC provided by the embodiments of the present disclosure in conjunction with specific equivalent circuit diagrams.

[0141] In the first example, refer to Figure 4, the pixel driving circuit PDC includes a first reset transistor T1 to a third reset transistor T8, a first capacitor C1, a second capacitor C2, and a light-emitting element. Among them, the first pole of the first reset transistor T1 is electrically connected to the first initialization voltage terminal, the second pole of the first reset transistor T1 is electrically connected to the fifth node N5, and the control pole of the first reset transistor T1 is electrically connected to the second reset signal terminal; the first reset transistor T1 is used to conduct in response to the selected conduction level of the second reset signal RST2. The first pole of the threshold compensation transistor T2 is electrically connected to the first node N1, the second pole of the threshold compensation transistor T2 is electrically connected to the second node N2, and the control pole of the threshold compensation transistor T2 is electrically connected to the first reset signal terminal; the threshold compensation transistor T2 is used to conduct in response to the selected conduction level of the first reset signal RST1. The first pole of the driving transistor T3 is electrically connected to the first node N1, the second pole of the driving transistor T3 is electrically connected to the third node N3, and the control pole of the driving transistor T3 is electrically connected to the second node N2; the driving transistor T3 is used to generate a driving current. The first pole of the data writing transistor T4 is electrically connected to the data signal terminal, the second pole of the data writing transistor T4 is electrically connected to the third node N3, and the control pole of the data writing transistor T4 is electrically connected to the second scan signal terminal; the data writing transistor T4 is used to conduct in response to the selected conduction level of the second scan signal G2. The first pole of the first light-emitting control transistor T5 is electrically connected to the driving power supply voltage terminal, the second pole of the first light-emitting control transistor T5 is electrically connected to the first node N1, and the control pole of the first light-emitting control transistor T5 is electrically connected to the first light-emitting control signal terminal; the first light-emitting control transistor T5 is used to conduct in response to the selected conduction level of the first light-emitting control signal EM1. The first pole of the second light-emitting control transistor T6 is electrically connected to the third node N3, the second pole of the second light-emitting control transistor T6 is electrically connected to the fourth node N4, and the control pole of the second light-emitting control transistor T6 is electrically connected to the second light-emitting control signal terminal; the second light-emitting control transistor T6 is used to conduct in response to the selected conduction level of the second light-emitting control signal EM2. The first pole of the second reset transistor T7 is electrically connected to the second initialization voltage terminal, the second pole of the second reset transistor T7 is electrically connected to the fourth node N4, and the control pole of the second reset transistor T7 is electrically connected to the third scan signal terminal; the second reset transistor T7 is used to conduct in response to the selected conduction level of the third scan signal G3. The first pole of the third reset transistor T8 is electrically connected to the reference voltage terminal, the second pole of the third reset transistor T8 is electrically connected to the first node N1, and the control pole of the third reset transistor T8 is electrically connected to the first scan signal terminal; the third reset transistor T8 is used to conduct in response to the selected conduction level of the first scan signal G1. The first end of the first capacitor C1 is electrically connected to the fifth node N5, and the second end of the first capacitor C1 is electrically connected to the second node N2. The first end of the second capacitor C2 is electrically connected to the fifth node N5, and the second end of the second capacitor C2 is electrically connected to the third node N3.The anode (pixel electrode) of the light-emitting element is electrically connected to the fourth node N4, and the cathode of the light-emitting element is used to load the reference power supply voltage VSS.

[0142] It should be noted that in this example, the first reset transistor T1, the threshold compensation transistor T2, and the driving transistor T3 are all N-type transistors, and the remaining transistors are P-type transistors. The first reset transistor T1, the threshold compensation transistor T2, and the driving transistor T3 all have a bottom gate and a top gate; the top gate and the bottom gate of the first reset transistor T1 are the control electrodes of the first reset transistor T1, the top gate and the bottom gate of the threshold compensation transistor T2 are the control electrodes of the threshold compensation transistor T2, the top gate of the driving transistor T3 is the control electrode of the driving transistor T3, and the bottom gate of the driving transistor T3 is electrically connected to the third node N3. The number of the first light-emitting control transistors T5 is two, and the two first light-emitting control transistors T5 are connected in series. The first pole of one first light-emitting control transistor T5 is electrically connected to the driving power supply voltage terminal, the second pole of the other first light-emitting control transistor T5 is electrically connected to the first node N1, and the control electrodes of the two first light-emitting control transistors T5 are both used to load the first light-emitting control signal EM1.

[0143] As follows, taking Figure 4 the pixel driving circuit PDC shown as an example, refer to Figure 5 the driving timing diagram of the pixel driving circuit PDC in the first operating mode, and an exemplary description of the driving method of the pixel driving circuit PDC in this example will be given.

[0144] At time P1 (reset stage), refer to Figure 4 and Figure 5 , the selected conduction levels of the first reset signal RST1, the second reset signal RST2, the first scan signal G1, and the third scan signal G3 are loaded to the pixel driving circuit PDC, so that the first reset transistor T1, the threshold compensation transistor T2, the second reset transistor T7, and the third reset transistor T8 are turned on; the cut-off levels of the first light-emitting control signal EM1, the second light-emitting control signal EM2, and the second scan signal G2 are loaded to the pixel driving circuit PDC, so that the data writing transistor T4, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are turned off. The reference voltage Vref is loaded to the first node N1 and the second node N2 to reset the first node N1 and the second node N2. The first initialization voltage Vinit1 is loaded to the fifth node N5, and the second initialization voltage Vinit2 is loaded to the fourth node N4 to reset the fourth node N4 and the fifth node N5. At this time, VN1 = VN2 = Vref, VN4 = Vinit2, VN5 = Vinit1; when VN3 = Vref - Vth, the driving transistor T3 is turned off to write the threshold voltage.

[0145] It should be noted that at time P1, after loading the cut-off levels of the first light emission control signal EM1 and the second light emission control signal EM2 to the pixel driving circuit PDC, the selected conduction level of the first reset signal RST1 is loaded to the pixel driving circuit PDC, and then the selected conduction levels of the first scan signal G1 and the third scan signal G3 are loaded to the pixel driving circuit PDC, so that after the first light emission control transistor T5 and the second light emission control transistor T6 are cut off, the threshold compensation transistor T2 is turned on, and finally the second reset transistor T7 and the third reset transistor T8 are turned on to reduce signal crosstalk.

[0146] At time P2 (writing stage), refer to Figure 4 、 Figure 5 , the selected conduction level of the second scan signal G2 is loaded to the pixel driving circuit PDC to turn on the data writing transistor T4. The cut-off levels of the first reset signal RST1, the second reset signal RST2, the first light emission control signal EM1, the second light emission control signal EM2, the first scan signal G1, and the third scan signal G3 are loaded to the pixel driving circuit PDC to turn off the first reset transistor T1, the threshold compensation transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, the second reset transistor T7, and the third reset transistor T8. At this time, the data signal Data is loaded to the third node N3, so that VN3 = Data; at this time, C1 and C2 are in series, and through the coupling effect of the second capacitor C2, VN5 = Vinit1 + (Data - Vref + Vth) * (C1 + C2) / C1; through the coupling effect of the first capacitor C1, VN2 = Vref + (Data - Vref + Vth) * (C1 + C2) / C1.

[0147] It should be noted that at time P2, after loading the cut-off level of the second reset signal RST2 to the pixel driving circuit PDC, the selected conduction level of the second scan signal G2 is loaded to the pixel driving circuit PDC, so that after the first reset transistor T1 is cut off, the data writing transistor T4 is turned on to facilitate writing the data signal to the second node N2.

[0148] At time P3 (light emission stage), refer to Figure 4 、 Figure 5, the select-on levels of the second reset signal RST2, the first emission control signal EM1, and the second emission control signal EM2 are loaded to the pixel driving circuit PDC, so that the first reset transistor T1, the driving transistor T3, the first emission control transistor T5, and the second emission control transistor T6 are turned on; the cut-off levels of the first reset signal RST1, the first scan signal G1, the second scan signal G2, and the third scan signal G3 are loaded to the pixel driving circuit PDC, so that the threshold compensation transistor T2, the data writing transistor T4, the second reset transistor T7, and the third reset transistor T8 are turned off. At this time, VN5 = Vinit1, C1 and C2 are in parallel. Through the coupling effect of the first capacitor C1, VN2 = Vref + (Data - Vref + Vth) * (C1 + C2) / C1 - (Data - Vref + Vth) = Vref + (Data - Vref + Vth) * C2 / C1; when the capacitance values of the first capacitor C1 and the second capacitor C2 are the same, VN2 = Data + Vth, VN3 = VDD, then Vgs = VN2 - VN3 = Data + Vth - VDD. The driving transistor T3 generates a driving current to cause the light-emitting element to emit light. The driving current where μ n ·C OX ·W / L is a constant related to the process and the driving design. For example, μ n is the carrier mobility, C OX is the gate oxide capacitance, and W / L is the transistor width-to-length ratio; the driving current in the above formula is independent of Vth, thus solving the problem of Vth drift of the driving transistor T3 and facilitating the improvement of the display quality of the display panel PNL.

[0149] It should be noted that at time P3, after loading the cut-off level of the second scan signal G2 to the pixel driving circuit PDC, the select-on level of the second reset signal RST2 is loaded to the pixel driving circuit PDC, and finally the select-on levels of the first emission control signal EM1 and the second emission control signal EM2 are loaded to the pixel driving circuit PDC, so that after the data writing transistor T4 is turned off, the first reset transistor T1 is turned on, and finally the first emission control transistor T5 and the second emission control transistor T6 are turned on, so as to load a driving current to the light-emitting element and drive the light-emitting element to emit light.

[0150] It should be noted that in this example, the selected conduction level of the first reset signal RST1 and the second reset signal RST2 is high level, and the cut-off level is low level; the selected conduction level of the first light emission control signal EM1, the second light emission control signal EM2, the first scan signal G1, the second scan signal G2, and the third scan signal G3 is low level, and the cut-off level is high level. The first light emission control signal EM1 and the second light emission control signal EM2 are the same signal, the first initialization voltage Vinit1 and the second initialization voltage Vinit2 are the same signal, and the first scan signal G1 and the third scan signal G3 are the same signal. The first scan signal G1 and the second scan signal G2 share a gate driving circuit, and the second scan signal G2 loaded to the pixel driving circuit of the nth row is the same as the first scan signal G1 loaded to the pixel driving circuit of the (n - x)th row; where n > x > 0, and both x and n are positive integers. For example, when x = 1 and n = 2, the second scan signal G2 loaded to the pixel driving circuit of the 2nd row is the same as the first scan signal G1 loaded to the pixel driving circuit of the 1st row. For another example, when x = 2 and n = 3, the second scan signal G2 loaded to the pixel driving circuit of the 3rd row is the same as the first scan signal G1 loaded to the pixel driving circuit of the 1st row. In this way, the number of gate driving circuits can be reduced, which is beneficial to the narrow bezel of the display panel PNL.

[0151] It should also be noted that in this example, VN1, VN2, VN3, VN4, and VN5 are the voltages of the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 respectively, Vgs is the gate-source voltage of the driving transistor T3, and Vth is the threshold voltage of the driving transistor T3.

[0152] As follows, taking Figure 4 the pixel driving circuit PDC shown as an example, refer to Figure 6 the driving timing diagram of the pixel driving circuit PDC in the second working mode shown, and an exemplary description of the driving method of the pixel driving circuit PDC in this example will be given.

[0153] At the moment P1 (reset stage), refer to Figure 4 、 Figure 6, the selection conduction levels of a first reset signal RST1, a second reset signal RST2, a first scan signal G1, and a third scan signal G3 are loaded to a pixel driving circuit PDC, so that a first reset transistor T1, a threshold compensation transistor T2, a second reset transistor T7, and a third reset transistor T8 are turned on; the cut-off levels of a first light emission control signal EM1, a second light emission control signal EM2, and a second scan signal G2 are loaded to the pixel driving circuit PDC, so that a data writing transistor T4, a first light emission control transistor T5, and a second light emission control transistor T6 are turned off. A reference voltage Vref is loaded to a first node N1 and a second node N2 to reset the first node N1 and the second node N2. A first initialization voltage Vinit1 is loaded to a fifth node N5, and a second initialization voltage Vinit2 is loaded to a fourth node N4 to reset the fourth node N4 and the fifth node N5. At this time, VN1 = VN2 = Vref, VN4 = Vinit2, and VN5 = Vinit1.

[0154] It should be noted that at time P1, after the cut-off levels of the first light emission control signal EM1 and the second light emission control signal EM2 are loaded to the pixel driving circuit PDC, the selection conduction level of the first reset signal RST1 is loaded to the pixel driving circuit PDC, then the selection conduction levels of the first scan signal G1 and the third scan signal G3 are loaded to the pixel driving circuit PDC, so that after the first light emission control transistor T5 and the second light emission control transistor T6 are turned off, the threshold compensation transistor T2 is turned on, and finally the second reset transistor T7 and the third reset transistor T8 are turned on to reduce signal crosstalk.

[0155] At time P2 (writing stage), refer to Figure 4 , Figure 6, the selection conduction levels of a first reset signal RST1, a second reset signal RST2, and a second scan signal G2 are loaded to a pixel driving circuit PDC, so that a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, and a data writing transistor T4 are turned on. The cut-off levels of a first light emission control signal EM1, a second light emission control signal EM2, a first scan signal G1, and a third scan signal G3 are loaded to the pixel driving circuit PDC, so that a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7, and a third reset transistor T8 are turned off. At this time, a data signal Data is loaded to a third node N3, so that VN3 = Data; a first initialization voltage Vinit1 is loaded to a fifth node N5, so that the data signal Data cannot be written to a second node N2 through the coupling action of a first capacitor C1 and a second capacitor C2. The data signal Data is written to the second node N2 sequentially through the driving transistor T3 and the threshold compensation transistor T2. When VN2 = Data + Vth, the driving transistor T3 is turned off to realize writing the data signal Data and Vth to the second node N2 at the same moment.

[0156] It should be noted that at time P2, after the selection conduction levels of the first reset signal RST1 and the second reset signal RST2 are loaded to the pixel driving circuit PDC, the selection conduction level of the second scan signal G2 is loaded to the pixel driving circuit PDC, so that the first reset transistor T1 and the threshold compensation transistor T2 are turned on and then the data writing transistor T4 is turned on, preventing the data signal from being written to the second node N2 by means of capacitive coupling and reducing the loss of the data signal.

[0157] At time P3 (light emission stage), refer to Figure 4 , Figure 6 , the selection conduction levels of the second reset signal RST2, the first light emission control signal EM1, and the second light emission control signal EM2 are loaded to the pixel driving circuit PDC, so that the first reset transistor T1, the driving transistor T3, the first light emission control transistor T5, and the second light emission control transistor T6 are turned on; the cut-off levels of the first reset signal RST1, the first scan signal G1, the second scan signal G2, and the third scan signal G3 are loaded to the pixel driving circuit PDC, so that the threshold compensation transistor T2, the data writing transistor T4, the second reset transistor T7, and the third reset transistor T8 are turned off. At this time, VN5 = Vinit1, VN3 = VDD, VN2 = Data + Vth; then Vgs = VN2 - VN3 = Data + Vth - VDD. The driving transistor T3 generates a driving current to make the light emitting element emit light. The driving current wherein, μ n ·C OX ·W / L is a constant related to the process and the driving design. For example, μ nis the carrier mobility, C OX is the gate oxide capacitance, and W / L is the transistor width-to-length ratio; in the above formula, the driving current is independent of Vth, thus solving the problem of Vth drift of the driving transistor T3 and facilitating the improvement of the display quality of the display panel PNL.

[0158] It should be noted that at time P3, after loading the cut-off level of the second scan signal G2 to the pixel driving circuit PDC, the cut-off level of the first reset signal RST1 is loaded to the pixel driving circuit PDC, and finally the selected conduction levels of the first light emission control signal EM1 and the second light emission control signal EM2 are loaded to the pixel driving circuit PDC, so that after the data writing transistor T4 is cut off, the threshold compensation transistor T2 is cut off, and finally the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, so as to load the driving current to the light emitting element and drive the light emitting element to emit light.

[0159] It should be noted that in this example, the selected conduction levels of the first reset signal RST1 and the second reset signal RST2 are high levels, and the cut-off levels are low levels; the selected conduction levels of the first light emission control signal EM1, the second light emission control signal EM2, the first scan signal G1, the second scan signal G2, and the third scan signal G3 are low levels, and the cut-off levels are high levels. The first light emission control signal EM1 and the second light emission control signal EM2 are the same signal, the first initialization voltage Vinit1 and the second initialization voltage Vinit2 are the same signal, and the first scan signal G1 and the third scan signal G3 are the same signal. The first scan signal G1 and the second scan signal G2 share a gate driving circuit, and the second scan signal G2 loaded to the pixel driving circuit of the nth row is the same as the first scan signal G1 loaded to the pixel driving circuit of the (n - x)th row; where n > x > 0, and both x and n are positive integers. For example, when x = 1 and n = 2, the second scan signal G2 loaded to the pixel driving circuit of the 2nd row is the same as the first scan signal G1 loaded to the pixel driving circuit of the 1st row. For another example, when x = 2 and n = 3, the second scan signal G2 loaded to the pixel driving circuit of the 3rd row is the same as the first scan signal G1 loaded to the pixel driving circuit of the 1st row. In this way, the number of gate driving circuits can be reduced, which is beneficial to the narrow bezel of the display panel PNL.

[0160] It should also be noted that in this example, VN1, VN2, VN3, VN4, and VN5 are the voltages of the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 respectively, Vgs is the gate-source voltage of the driving transistor T3, and Vth is the threshold voltage of the driving transistor T3.

[0161] In the second example, refer to Figure 8, the pixel driving circuit PDC includes a first reset transistor T1 to a fourth reset transistor T9, a first capacitor C1, a third capacitor C3, and a light-emitting element. Among them, the first pole of the first reset transistor T1 is electrically connected to the first initialization voltage terminal, the second pole of the first reset transistor T1 is electrically connected to the fifth node N5, and the control pole of the first reset transistor T1 is electrically connected to the third reset signal terminal; the first reset transistor T1 is used to conduct in response to the selected conduction level of the third reset signal RST3. The first pole of the threshold compensation transistor T2 is electrically connected to the first node N1, the second pole of the threshold compensation transistor T2 is electrically connected to the second node N2, and the control pole of the threshold compensation transistor T2 is electrically connected to the first reset signal terminal; the threshold compensation transistor T2 is used to conduct in response to the selected conduction level of the first reset signal RST1. The first pole of the driving transistor T3 is electrically connected to the first node N1, the second pole of the driving transistor T3 is electrically connected to the third node N3, and the control pole of the driving transistor T3 is electrically connected to the second node N2. The driving transistor T3 is used to generate a driving current. The first pole of the data writing transistor T4 is electrically connected to the data signal terminal, the second pole of the data writing transistor T4 is electrically connected to the third node N3, and the control pole of the data writing transistor T4 is electrically connected to the second scan signal terminal; the data writing transistor T4 is used to conduct in response to the selected conduction level of the second scan signal G2. The first pole of the first light-emitting control transistor T5 is electrically connected to the driving power supply voltage terminal, the second pole of the first light-emitting control transistor T5 is electrically connected to the first node N1, and the control pole of the first light-emitting control transistor T5 is electrically connected to the first light-emitting control signal terminal; the first light-emitting control transistor T5 is used to conduct in response to the selected conduction level of the first light-emitting control signal EM1. The first pole of the second light-emitting control transistor T6 is electrically connected to the third node N3, the second pole of the second light-emitting control transistor T6 is electrically connected to the fourth node N4, and the control pole of the second light-emitting control transistor T6 is electrically connected to the second light-emitting control signal terminal; the second light-emitting control transistor T6 is used to conduct in response to the selected conduction level of the second light-emitting control signal EM2. The first pole of the second reset transistor T7 is electrically connected to the second initialization voltage terminal, the second pole of the second reset transistor T7 is electrically connected to the fourth node N4, and the control pole of the second reset transistor T7 is electrically connected to the third scan signal terminal; the second reset transistor T7 is used to conduct in response to the selected conduction level of the third scan signal G3. The first pole of the third reset transistor T8 is electrically connected to the reference voltage terminal, the second pole of the third reset transistor T8 is electrically connected to the first node N1, and the control pole of the third reset transistor T8 is electrically connected to the first scan signal terminal; the third reset transistor T8 is used to conduct in response to the selected conduction level of the first scan signal G1. The first pole of the fourth reset transistor T9 is electrically connected to the fifth node N5, the second pole of the fourth reset transistor T9 is electrically connected to the third node N3, and the control pole of the fourth reset transistor T9 is electrically connected to the fourth reset signal terminal; the fourth reset transistor T9 is used to conduct in response to the selected conduction level of the fourth reset signal RST4.The first end of the first capacitor C1 is electrically connected to the fifth node N5, and the second end of the first capacitor C1 is electrically connected to the second node N2. The first end of the third capacitor C3 is electrically connected to the driving power supply voltage terminal, and the second end of the third capacitor C3 is electrically connected to the third node N3. The anode (pixel electrode) of the light-emitting element is electrically connected to the fourth node N4, and the cathode of the light-emitting element is used to load the reference power supply voltage VSS.

[0162] It should be noted that in this example, the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, and the fourth reset transistor T9 are all N-type transistors, and the remaining transistors are P-type transistors. The first reset transistor T1, the threshold compensation transistor T2, and the driving transistor T3 all have a bottom gate and a top gate; the top gate and the bottom gate of the first reset transistor T1 are the control electrodes of the first reset transistor T1, the top gate and the bottom gate of the threshold compensation transistor T2 are the control electrodes of the threshold compensation transistor T2, the top gate of the driving transistor T3 is the control electrode of the driving transistor T3, and the bottom gate of the driving transistor T3 is electrically connected to the third node N3. The number of the first light-emitting control transistors T5 is two, and the two first light-emitting control transistors T5 are connected in series. The first pole of one first light-emitting control transistor T5 is electrically connected to the driving power supply voltage terminal, the second pole of the other first light-emitting control transistor T5 is electrically connected to the first node N1, and the control electrodes of the two first light-emitting control transistors T5 are both used to load the first light-emitting control signal EM1.

[0163] As follows, taking Figure 8 the pixel driving circuit PDC shown as an example, refer to Figure 9 the driving timing diagram of the pixel driving circuit PDC shown in the first working mode, and an exemplary description of the driving method of the pixel driving circuit PDC in this example will be given.

[0164] At the moment P1 (reset stage), refer to Figure 8 and Figure 9, the selected conduction levels of the first reset signal RST1, the third reset signal RST3, the first scan signal G1, and the third scan signal G3 are loaded into the pixel driving circuit PDC, causing the first reset transistor T1, the threshold compensation transistor T2, the second reset transistor T7, and the third reset transistor T8 to conduct; the cut-off levels of the fourth reset signal RST4, the first light emission control signal EM1, the second light emission control signal EM2, and the second scan signal G2 are loaded into the pixel driving circuit PDC, causing the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the fourth reset transistor T9 to cut off. The reference voltage Vref is loaded onto the first node N1 and the second node N2 to reset the first node N1 and the second node N2. The first initialization voltage Vinit1 is loaded onto the fifth node N5, and the second initialization voltage Vinit2 is loaded onto the fourth node N4 to reset the fourth node N4 and the fifth node N5. At this time, VN1 = VN2 = Vref, VN4 = Vinit2, VN5 = Vinit1; when VN3 = Vref - Vth, the driving transistor T3 cuts off to achieve the writing of the threshold voltage.

[0165] It should be noted that at time P1, after loading the cut-off levels of the first light emission control signal EM1 and the second light emission control signal EM2 into the pixel driving circuit PDC, the selected conduction levels of the first reset signal RST1 and the third reset signal RST3 are loaded into the pixel driving circuit PDC, and then the selected conduction levels of the first scan signal G1 and the third scan signal G3 are loaded into the pixel driving circuit PDC, causing the first light emission control transistor T5 and the second light emission control transistor T6 to cut off and then conducting the threshold compensation transistor T2, and finally conducting the second reset transistor T7 and the third reset transistor T8 to reduce signal crosstalk.

[0166] At time P2 (writing stage), refer to Figure 8 , Figure 9 , the selected conduction levels of the fourth reset signal RST4 and the second scan signal G2 are loaded into the pixel driving circuit PDC, causing the data writing transistor T4 and the fourth reset transistor T9 to conduct. The cut-off levels of the first reset signal RST1, the third reset signal RST3, the first light emission control signal EM1, the second light emission control signal EM2, the first scan signal G1, and the third scan signal G3 are loaded into the pixel driving circuit PDC, causing the first reset transistor T1, the threshold compensation transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, the second reset transistor T7, and the third reset transistor T8 to cut off. At this time, the data signal Data is loaded onto the third node N3, making VN3 = Data; through the coupling effect of the first capacitor C1, VN2 = Vref + (Data - Vref + Vth) * C1 / (C1 + C3).

[0167] It should be noted that at time P2, after loading the selected on-level of the fourth reset signal RST4 to the pixel driving circuit PDC, the selected on-level of the second scan signal G2 is loaded to the pixel driving circuit PDC, so that after the fourth reset transistor T9 is turned on, the data writing transistor T4 is turned on, facilitating the writing of the data signal to the second node N2 and reducing crosstalk between signals.

[0168] At time P3 (the light-emitting stage), referring to Figure 8 、 Figure 9 , the selected on-levels of the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are loaded to the pixel driving circuit PDC, turning on the first light-emitting control transistor T5 and the second light-emitting control transistor T6; the cut-off levels of the first reset signal RST1, the third reset signal RST3, the fourth reset signal RST4, the first scan signal G1, the second scan signal G2, and the third scan signal G3 are loaded to the pixel driving circuit PDC, turning off the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, the second reset transistor T7, the third reset transistor T8, and the fourth reset transistor T9. At this time, VN3 = VDD. When the capacitance value of the first capacitor C1 is much larger than that of the third capacitor C3, VN2 = Data + Vth, then Vgs = VN2 - VN3 = Data + Vth - VDD. The driving transistor T3 generates a driving current, causing the light-emitting element to emit light. The driving current wherein, μ n ·C OX ·W / L is a constant related to the process and the driving design. For example, μ n is the carrier mobility, C OX is the gate oxide capacitance, and W / L is the transistor width-to-length ratio; the driving current in the above formula is independent of Vth, thus solving the problem of the Vth drift of the driving transistor T3 and facilitating the improvement of the display quality of the display panel PNL.

[0169] It should be noted that at time P3, after loading the cut-off level of the second scan signal G2 to the pixel driving circuit PDC, the cut-off level of the fourth reset signal RST4 is loaded to the pixel driving circuit PDC, and finally the selected on-levels of the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are loaded to the pixel driving circuit PDC, turning off the data writing transistor T4 and then the fourth reset transistor T9, and finally turning on the first light-emitting control transistor T5 and the second light-emitting control transistor T6, facilitating the loading of the driving current to the light-emitting element and driving the light-emitting element to emit light.

[0170] It should be noted that in this example, the selected conduction level of the first reset signal RST1, the third reset signal RST3, and the fourth reset signal RST4 is high level, and the cut-off level is low level; the selected conduction level of the first light emission control signal EM1, the second light emission control signal EM2, the first scan signal G1, the second scan signal G2, and the third scan signal G3 is low level, and the cut-off level is high level. The first light emission control signal EM1 and the second light emission control signal EM2 are the same signal, the first initialization voltage Vinit1 and the second initialization voltage Vinit2 are the same signal, the first reset signal RST1 and the third reset signal RST3 are the same signal, and the first scan signal G1 and the third scan signal G3 are the same signal. The first scan signal G1 and the second scan signal G2 share a gate driving circuit, and the second scan signal G2 loaded to the pixel driving circuit of the nth row is the same as the first scan signal G1 loaded to the pixel driving circuit of the (n - x)th row; where n > x > 0, and both x and n are positive integers. For example, when x = 1 and n = 2, the second scan signal G2 loaded to the pixel driving circuit of the 2nd row is the same as the first scan signal G1 loaded to the pixel driving circuit of the 1st row. For another example, when x = 2 and n = 3, the second scan signal G2 loaded to the pixel driving circuit of the 3rd row is the same as the first scan signal G1 loaded to the pixel driving circuit of the 1st row. In this way, the number of gate driving circuits can be reduced, which is beneficial to the narrow bezel of the display panel PNL.

[0171] It should also be noted that in this example, VN1, VN2, VN3, VN4, and VN5 are the voltages of the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 respectively, Vgs is the gate-source voltage of the driving transistor T3, and Vth is the threshold voltage of the driving transistor T3.

[0172] As follows, taking Figure 8 the schematic pixel driving circuit PDC shown as an example, refer to Figure 10 the driving timing diagram of the pixel driving circuit PDC in the second working mode shown, and an exemplary description of the driving method of the pixel driving circuit PDC in this example will be given.

[0173] At the moment P1 (reset stage), refer to Figure 8 、 Figure 10, the selection conduction levels of the first reset signal RST1, the third reset signal RST3, the fourth reset signal RST4, the first scan signal G1, and the third scan signal G3 are loaded to the pixel driving circuit PDC, so that the first reset transistor T1, the threshold compensation transistor T2, the second reset transistor T7, the third reset transistor T8, and the fourth reset transistor T9 are turned on; the cut-off levels of the first light emission control signal EM1, the second light emission control signal EM2, and the second scan signal G2 are loaded to the pixel driving circuit PDC, so that the data writing transistor T4, the first light emission control transistor T5, and the second light emission control transistor T6 are turned off. The reference voltage Vref is loaded to the first node N1 and the second node N2 to reset the first node N1 and the second node N2. The first initialization voltage Vinit1 is loaded to the fifth node N5 and the third node N3, and the second initialization voltage Vinit2 is loaded to the fourth node N4 to reset the fourth node N4 and the fifth node N5. At this time, VN1 = VN2 = Vref, VN4 = Vinit2, and VN3 = VN5 = Vinit1.

[0174] It should be noted that at time P1, after the cut-off levels of the first light emission control signal EM1 and the second light emission control signal EM2 are loaded to the pixel driving circuit PDC, the selection conduction levels of the first reset signal RST1 and the third reset signal RST3 are loaded to the pixel driving circuit PDC, and then the selection conduction levels of the first scan signal G1 and the third scan signal G3 are loaded to the pixel driving circuit PDC, so that after the first light emission control transistor T5 and the second light emission control transistor T6 are turned off, the first reset transistor T1 and the threshold compensation transistor T2 are turned on, and finally the second reset transistor T7 and the third reset transistor T8 are turned on to reduce signal crosstalk.

[0175] At time P2 (writing stage), refer to Figure 8 , Figure 10, the first reset signal RST1, the third reset signal RST3, and the selected on-level of the second scan signal G2 are loaded to the pixel driving circuit PDC, so that the first reset transistor T1, the threshold compensation transistor T2, and the data writing transistor T4 are turned on. The off-levels of the fourth reset signal RST4, the first emission control signal EM1, the second emission control signal EM2, the first scan signal G1, and the third scan signal G3 are loaded to the pixel driving circuit PDC, so that the first emission control transistor T5, the second emission control transistor T6, the second reset transistor T7, the third reset transistor T8, and the fourth reset transistor T9 are turned off. At this time, the first initialization voltage Vinit1 is loaded to the fifth node N5 for voltage stabilization, and the data signal Data is loaded to the third node N3. Since the driving transistor T3 is turned on, the data signal is sequentially written to the second node N2 through the driving transistor T3 and the threshold compensation transistor T2. When VN2 = Data + Vth, the driving transistor T3 is turned off to realize the simultaneous writing of the data signal Data and Vth to the second node N2.

[0176] It should be noted that at time P2, after loading the off-level of the fourth reset signal RST4 to the pixel driving circuit PDC, the selected on-levels of the first reset signal RST1 and the third reset signal RST3 are loaded to the pixel driving circuit PDC, and finally the selected on-level of the second scan signal G2 is loaded to the pixel driving circuit PDC, so that the fourth reset transistor T9 is turned off and then the first reset transistor T1 and the threshold compensation transistor T2 are turned on, facilitating the writing of the data signal and the threshold voltage to the second node N2 and reducing the crosstalk between signals.

[0177] At time P3 (emission stage), refer to Figure 8 , Figure 10 , the selected on-levels of the first emission control signal EM1 and the second emission control signal EM2 are loaded to the pixel driving circuit PDC, so that the first emission control transistor T5 and the second emission control transistor T6 are turned on; the off-levels of the first reset signal RST1, the third reset signal RST3, the fourth reset signal RST4, the first scan signal G1, the second scan signal G2, and the third scan signal G3 are loaded to the pixel driving circuit PDC, so that the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, the second reset transistor T7, the third reset transistor T8, and the fourth reset transistor T9 are turned off. At this time, VN3 = VDD, VN2 = Data + Vth, then Vgs = VN2 - VN3 = Data + Vth - VDD. The driving transistor T3 generates a driving current to make the light-emitting element emit light. The driving current where μ n ·C OX ·W / L is a constant related to the process and the driving design. For example, μ nis the carrier mobility, C OX is the gate oxide capacitance, and W / L is the transistor width-to-length ratio; in the above formula, the driving current is independent of Vth, thus solving the problem of Vth drift of the driving transistor T3 and facilitating the improvement of the display quality of the display panel PNL.

[0178] It should be noted that at time P3, after loading the cut-off level of the second scan signal G2 to the pixel driving circuit PDC, the cut-off levels of the first reset signal RST1 and the third reset signal RST3 are loaded to the pixel driving circuit PDC, and finally the selected conduction levels of the first light emission control signal EM1 and the second light emission control signal EM2 are loaded to the pixel driving circuit PDC, so that after the data writing transistor T4 is cut off, the first reset transistor T1 and the threshold compensation transistor T2 are cut off, and finally the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, so as to facilitate loading the driving current to the light emitting element and driving the light emitting element to emit light.

[0179] It should be noted that in this example, the selected conduction levels of the first reset signal RST1, the third reset signal RST3, and the fourth reset signal RST4 are high levels, and the cut-off levels are low levels; the selected conduction levels of the first light emission control signal EM1, the second light emission control signal EM2, the first scan signal G1, the second scan signal G2, and the third scan signal G3 are low levels, and the cut-off levels are high levels. The first light emission control signal EM1 and the second light emission control signal EM2 are the same signal, the first initialization voltage Vinit1 and the second initialization voltage Vinit2 are the same signal, the first reset signal RST1 and the third reset signal RST3 are the same signal, and the first scan signal G1 and the third scan signal G3 are the same signal. The first scan signal G1 and the second scan signal G2 share a gate driving circuit, and the second scan signal G2 loaded to the pixel driving circuit of the nth row is the same as the first scan signal G1 loaded to the pixel driving circuit of the (n - x)th row; where n > x > 0, and both x and n are positive integers. For example, when x = 1 and n = 2, the second scan signal G2 loaded to the pixel driving circuit of the 2nd row is the same as the first scan signal G1 loaded to the pixel driving circuit of the 1st row. For another example, when x = 2 and n = 3, the second scan signal G2 loaded to the pixel driving circuit of the 3rd row is the same as the first scan signal G1 loaded to the pixel driving circuit of the 1st row. In this way, the number of gate driving circuits can be reduced, which is beneficial to the narrow bezel of the display panel PNL.

[0180] It should also be noted that, in this example, VN1, VN2, VN3, VN4, and VN5 are respectively the voltages of the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5, Vgs is the gate-source voltage of the driving transistor T3, and Vth is the threshold voltage of the driving transistor T3.

[0181] It should be noted that although the steps of the driving method of the pixel driving circuit in the present disclosure are described in a specific order in the drawings, however, this does not require or imply that these steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

[0182] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only to be considered exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A pixel driving circuit, wherein: The pixel driving circuit includes a driving transistor, a threshold compensation subcircuit, a storage subcircuit, and a data writing subcircuit; the driving transistor can output a driving current under the control of a control electrode voltage; The threshold compensation subcircuit is capable of compensating the threshold voltage of the driving transistor; The data writing subcircuit is capable of writing a data signal to the pixel driving circuit; The storage subcircuit is capable of storing the threshold voltage of the driving transistor and the data signal; The pixel driving circuit can operate in any one of a first operating mode and a second operating mode: In the first working mode, the pixel driving circuit first performs threshold compensation and then writes data; In the second operation mode, the pixel driving circuit performs threshold compensation and data writing simultaneously.

2. The pixel driving circuit according to claim 1, wherein: The threshold compensation subcircuit includes a threshold compensation transistor; The first electrode of the threshold compensation transistor, the first electrode of the driving transistor, and the first node are electrically connected to each other, the second electrode of the threshold compensation transistor, the control electrode of the driving transistor, and the second node are electrically connected to each other, and the control electrode of the threshold compensation transistor is used to load a first reset signal; the threshold compensation transistor is used to be turned on in response to a gating level of the first reset signal; The storage subcircuit includes a first capacitor and a second capacitor; The first end of the first capacitor, the first end of the second capacitor, and the fifth node are electrically connected to each other, the second end of the first capacitor is electrically connected to the second node, and the second end of the second capacitor, the second electrode of the driving transistor, and the third node are electrically connected to each other; The data writing sub-circuit includes a data writing transistor; The first electrode of the data write transistor is used to load the data signal, the second electrode of the data write transistor is electrically connected to the third node, and the control electrode of the data write transistor is used to load the second scan signal; the data write transistor is used to be turned on in response to the selection level of the second scan signal.

3. The pixel driving circuit according to claim 2, wherein: The pixel driving circuit further includes a first reset subcircuit, a second reset subcircuit, and a third reset subcircuit; The first end of the first reset subcircuit is used to load a first initialization voltage, the second end of the first reset subcircuit is electrically connected to the fifth node, and the control end of the first reset subcircuit is used to load a second reset signal; the first reset subcircuit is used to respond to the gating level of the second reset signal so that the first initialization voltage is loaded to the fifth node; The first end of the second reset subcircuit is used to load the second initialization voltage, the second end of the second reset subcircuit, the pixel electrode, and the fourth node are electrically connected to each other, and the control end of the second reset subcircuit is used to load the third scanning signal; the second reset subcircuit is used to respond to the gating level of the third scanning signal so that the second initialization voltage is loaded to the fourth node; The first end of the third reset sub-circuit is used to load a reference voltage, the second end of the third reset sub-circuit is electrically connected to the first node, and the control end of the third reset sub-circuit is used to load a first scan signal; the third reset sub-circuit is used to respond to the selection level of the first scan signal so that the reference voltage is loaded to the first node.

4. The pixel driving circuit according to claim 3, wherein: The first reset subcircuit includes a first reset transistor; The first electrode of the first reset transistor is used to load the first initialization voltage, the second electrode of the first reset transistor is electrically connected to the fifth node, and the control electrode of the first reset transistor is used to load the second reset signal; the first reset transistor is used to be turned on in response to the gating level of the second reset signal; The second reset subcircuit includes a second reset transistor; The first electrode of the second reset transistor is used to load the second initialization voltage, the second electrode of the second reset transistor is electrically connected to the fourth node, and the control electrode of the second reset transistor is used to load the third scanning signal; the second reset transistor is used to be turned on in response to the gating level of the third scanning signal; The third reset subcircuit comprises a third reset transistor; The first electrode of the third reset transistor is used to load the reference voltage, the second electrode of the third reset transistor is electrically connected to the first node, and the control electrode of the third reset transistor is used to load the first scanning signal; the third reset transistor is used to be turned on in response to the selection level of the first scanning signal.

5. The pixel driving circuit according to claim 3, wherein: The pixel driving circuit further includes a fourth reset subcircuit; the storage subcircuit only includes a first capacitor; The first end of the first capacitor, the first end of the fourth reset subcircuit, and the fifth node are electrically connected to each other, the second end of the fourth reset subcircuit is electrically connected to the third node, and the control end of the fourth reset subcircuit is used to load a fourth reset signal; the fourth reset subcircuit is used to connect the third node and the fifth node in response to the gating level of the fourth reset signal; The control terminal of the first reset sub-circuit is used to load a third reset signal; the first reset sub-circuit is used to respond to the selection level of the third reset signal to load a first initialization voltage to the fifth node.

6. The pixel driving circuit according to claim 5, wherein: The first reset subcircuit includes a first reset transistor; The first electrode of the first reset transistor is used to load the first initialization voltage, the second electrode of the first reset transistor is electrically connected to the fifth node, and the control electrode of the first reset transistor is used to load the third reset signal; the first reset transistor is used to be turned on in response to the gating level of the third reset signal; The fourth reset subcircuit includes a fourth reset transistor, a first electrode of the fourth reset transistor is electrically connected to the fifth node, a second electrode of the fourth reset transistor is electrically connected to the third node, and a control electrode of the fourth reset transistor is used to load a fourth reset signal; the fourth reset transistor is used to be turned on in response to a selection level of the fourth reset signal.

7. The pixel driving circuit according to claim 5, wherein: The pixel driving circuit further includes a third capacitor, a first end of the third capacitor is used to load a driving power supply voltage, and a second end of the third capacitor is electrically connected to the third node.

8. The pixel driving circuit according to any one of claims 2 to 7, wherein: The pixel driving circuit further includes a first light emitting control subcircuit and a second light emitting control subcircuit; The first end of the first light-emitting control subcircuit is used to load a driving power supply voltage, the second end of the first light-emitting control subcircuit is electrically connected to the first node, and the control end of the first light-emitting control subcircuit is used to load a first light-emitting control signal; the first light-emitting control subcircuit is used to respond to the gating level of the first light-emitting control signal so that the driving power supply voltage is loaded to the first node; The first end of the second light-emitting control subcircuit is electrically connected to the third node, the second end of the second light-emitting control subcircuit is electrically connected to the fourth node, and the control end of the second light-emitting control subcircuit is used to load a second light-emitting control signal; the second light-emitting control subcircuit is used to respond to the selection level of the second light-emitting control signal to connect the third node with the fourth node.

9. The pixel driving circuit according to claim 8, wherein: The first light emission control subcircuit comprises a first light emission control transistor, a first electrode of the first light emission control transistor is used to load a driving power supply voltage, a second electrode of the first light emission control transistor is electrically connected to the first node, and a control electrode of the first light emission control transistor is used to load the first light emission control signal; the first light emission control transistor is used to be turned on in response to a gating level of the first light emission control signal; The second light-emitting control subcircuit includes a second light-emitting control transistor, a first electrode of the second light-emitting control transistor is electrically connected to the third node, a second electrode of the second light-emitting control transistor is electrically connected to the fourth node, and a control electrode of the second light-emitting control transistor is used to load the second light-emitting control signal; the second light-emitting control transistor is used to turn on in response to a selection level of the second light-emitting control signal.

10. The pixel driving circuit according to any one of claims 1 to 7, wherein: At least the channel region of the driving transistor in each transistor is made of metal oxide semiconductor material, the driving transistor has a top gate and a bottom gate, the bottom gate of the driving transistor is electrically connected to the third node, and the top gate of the driving transistor is electrically connected to the second node.

11. A driving method of a pixel driving circuit, applied to the pixel driving circuit according to any one of claims 1 to 10; wherein: The driving method of the pixel driving circuit includes: In the first working mode, threshold compensation is first performed on the pixel driving circuit, and then data is written to the pixel driving circuit; In the second working mode, threshold compensation and data writing are performed on the pixel driving circuit simultaneously.

12. The driving method of the pixel driving circuit according to claim 11, applied to the pixel driving circuit according to claim 3, wherein: The pixel driving circuit further includes a first light-emitting control transistor and a second light-emitting control transistor, wherein the first electrode of the first light-emitting control transistor is used to load a driving power supply voltage, the second electrode of the first light-emitting control transistor is electrically connected to the first node, and the control electrode of the first light-emitting control transistor is used to load a first light-emitting control signal; the first light-emitting control transistor is used to be turned on in response to a gating level of the first light-emitting control signal; The first electrode of the second light emitting control transistor is electrically connected to the third node, the second electrode of the second light emitting control transistor is electrically connected to the fourth node, and the control electrode of the second light emitting control transistor is used to load the second light emitting control signal; The second light emission control transistor is used to be turned on in response to the gating level of the second light emission control signal; The driving method of the pixel driving circuit includes: In the first working mode: In the reset stage, the gating levels of the first reset signal, the second reset signal, the first scanning signal, and the third scanning signal are applied to the pixel driving circuit; In the writing phase, a gating level of a second scanning signal is applied to the pixel driving circuit; In the light emitting stage, the second reset signal, the first light emitting control signal, and the gate level of the second light emitting control signal are applied to the pixel driving circuit.

13. The driving method of the pixel driving circuit according to claim 12, wherein: The driving method of the pixel driving circuit includes: In the second working mode: In the reset stage, the gating levels of the first reset signal, the second reset signal, the first scanning signal, and the third scanning signal are applied to the pixel driving circuit; In the writing stage, a first reset signal, a second reset signal, and a gating level of a second scanning signal are applied to the pixel driving circuit; In the light emitting stage, the second reset signal, the first light emitting control signal, and the gate level of the second light emitting control signal are applied to the pixel driving circuit.

14. The driving method of the pixel driving circuit according to claim 11, applied to the pixel driving circuit according to claim 5, wherein: The pixel driving circuit further includes a first light-emitting control transistor and a second light-emitting control transistor, wherein the first electrode of the first light-emitting control transistor is used to load a driving power supply voltage, the second electrode of the first light-emitting control transistor is electrically connected to the first node, and the control electrode of the first light-emitting control transistor is used to load a first light-emitting control signal; the first light-emitting control transistor is used to be turned on in response to a gating level of the first light-emitting control signal; The first electrode of the second light emitting control transistor is electrically connected to the third node, the second electrode of the second light emitting control transistor is electrically connected to the fourth node, and the control electrode of the second light emitting control transistor is used to load the second light emitting control signal; The second light emission control transistor is used to be turned on in response to the gating level of the second light emission control signal; The driving method of the pixel driving circuit includes: In the first working mode: In the reset stage, the first reset signal, the third reset signal, the first scan signal, and the gating level of the third scan signal are applied to the pixel driving circuit; In the writing stage, a fourth reset signal and a gating level of a second scanning signal are applied to the pixel driving circuit; In the light emitting stage, the gating levels of the first light emitting control signal and the second light emitting control signal are applied to the pixel driving circuit.

15. The driving method of the pixel driving circuit according to claim 14, wherein: The driving method of the pixel driving circuit includes: In the second working mode: In the reset stage, the first reset signal, the third reset signal, the fourth reset signal, the first scan signal, and the gating level of the third scan signal are applied to the pixel driving circuit; In the writing phase, the first reset signal, the third reset signal, and the gating level of the second scanning signal are applied to the pixel driving circuit; In the light emitting stage, the gating levels of the first light emitting control signal and the second light emitting control signal are applied to the pixel driving circuit.

16. A display panel, wherein: The invention comprises the pixel driving circuit according to any one of claims 1 to 10.

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