Pixel circuit, display panel and display device

Abstract

The invention provides a pixel circuit, a display panel and a display device. A pixel circuit according to an embodiment includes: a driving sub-circuit including a driving transistor electrically connected between a first power signal terminal and a second power signal terminal and configured to generate a driving current from the first power signal terminal to the second power signal terminal via the light emitting unit; the driving transistor is a double-gate or multi-gate transistor. According to the embodiment of the invention, the driving transistor is set to be a double-gate or multi-gate transistor, so that the characteristics of the driving transistor can be finely regulated and controlled, and the display effect is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a pixel circuit, a display panel, and a display device. Background Art

[0002] With the continuous development and progress of display technologies, consumers' pursuit of display effects is getting higher and higher, which promotes the continuous and sustainable development of display technologies. However, the problem of image sticking in display panels has always been a difficult problem to improve and solve. Summary of the Invention

[0003] To solve at least one of the above problems, a first aspect of the present disclosure provides a pixel circuit, including: a driving sub-circuit and a light-emitting unit,

[0004] The driving sub-circuit includes a driving transistor electrically connected between a first power signal terminal and a second power signal terminal, and is configured to generate a driving current from the first power signal terminal through the light-emitting unit to the second power signal terminal,

[0005] wherein the driving transistor is a double-gate or multi-gate transistor.

[0006] Optionally, the driving transistor includes: a first pole, a second pole, and a control pole. The first pole is electrically connected to the first power signal terminal, the second pole is electrically connected to a first electrode of the light-emitting unit, and the control pole is electrically connected to a first node.

[0007] The driving transistor includes: an active region formed on a substrate, a control pole, and a first pole and a second pole.

[0008] The active region is electrically connected between the first pole and the second pole and includes at least two channels connected in series.

[0009] The control pole includes: at least two sub-control poles corresponding to the channels one by one. The at least two sub-control poles are electrically connected to the first node, and the positive projection of the sub-control pole on the substrate covers the positive projection of the corresponding channel on the substrate.

[0010] Optionally, at least two of the at least two channels connected in series have different channel width-to-length ratios.

[0011] Optionally, the pixel circuit further includes: a first capacitor electrically connected to an intermediate node between two adjacent channels.

[0012] A first pole of the first capacitor is disposed in the active region between two adjacent channels, a second pole is disposed in a first metal layer, and the second pole receives a first regulation signal.

[0013] Optionally, the positive projection of the second pole of the first capacitor on the substrate does not overlap with the positive projection of the control pole on the substrate, and / or

[0014] The pixel circuit further includes: a first reset sub-circuit, which is electrically connected to a first reset signal terminal, a first reset control terminal, and a first or second pole of the driving transistor, and is configured to transmit the first reset signal of the first reset signal terminal to the first or second pole of the driving transistor based on the signal of the first reset control terminal.

[0015] The second pole of the first capacitor is electrically connected to the first reset signal terminal.

[0016] Optionally, the driving transistor includes: an auxiliary control pole, an active region, a control pole, and a first and a second pole, which are sequentially stacked on the substrate.

[0017] The auxiliary control pole includes: auxiliary sub-control poles corresponding to the sub-control poles one by one. The positive projection of the auxiliary sub-control pole on the substrate at least partially covers the positive projection of the corresponding sub-control pole on the substrate, and each auxiliary sub-control pole is connected to a corresponding auxiliary regulation signal.

[0018] Optionally, the driving transistor includes: an auxiliary control pole, an active region, a control pole, and a first and a second pole, which are sequentially stacked on the substrate.

[0019] The positive projection of the auxiliary control pole on the substrate overlaps at least partially with the positive projection of each sub-control pole in the control pole on the substrate, and the auxiliary sub-control pole is connected to the auxiliary regulation signal.

[0020] Optionally, the auxiliary regulation signal is a DC voltage signal.

[0021] When the driving transistor is a P-type transistor, the potential of the auxiliary regulation signal is greater than the threshold voltage of the corresponding part of the driving transistor.

[0022] When the driving transistor is an N-type transistor, the potential of the auxiliary regulation signal is less than the threshold voltage of the corresponding part of the driving transistor.

[0023] Optionally, the thicknesses of at least two auxiliary sub-control poles in the direction perpendicular to the substrate are different.

[0024] Optionally, the pixel circuit further includes: a writing sub-circuit.

[0025] The driving transistor includes a first pole, a second pole, and a control pole. The first pole is electrically connected to a first power signal terminal, the second pole is electrically connected to a first electrode of the light-emitting unit, and the control pole is electrically connected to a first node.

[0026] The writing sub-circuit is electrically connected to the first pole of the driving transistor, a writing control terminal, and a writing signal terminal, and is configured to transmit the signal of the writing signal terminal to the first pole of the driving transistor based on the signal of the writing control terminal, or

[0027] The write sub-circuit is electrically connected to the first node, the write control terminal, and the write signal terminal, and is configured to transmit the signal of the write signal terminal to the first node based on the signal of the write control terminal.

[0028] Optionally, the pixel circuit further includes: a second reset sub-circuit,

[0029] The second reset sub-circuit is electrically connected to the control electrode of the driving transistor, the second reset control terminal, and the second reset signal terminal, and is configured to transmit the second reset signal of the second reset signal terminal to the control electrode based on the signal of the second reset control terminal.

[0030] A second aspect of the present disclosure provides a display panel, including the pixel circuit described above.

[0031] A third aspect of the present disclosure provides a display device, including the display panel described above.

[0032] The beneficial effects of the present disclosure are as follows:

[0033] In view of the existing problems, the present disclosure provides a pixel circuit, a display panel, and a display device, and by setting the driving transistor in the pixel circuit as a double-gate or multi-gate transistor, the characteristics of the driving transistor can be finely regulated and managed, so as to achieve the effect of improving display afterimage, and has broad application prospects. Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0035] Figure 1 Shows the circuit schematic diagram of the pixel circuit according to an embodiment of the present disclosure;

[0036] Figure 2 Shows a schematic cross-sectional view of the driving transistor in the pixel circuit according to an embodiment of the present disclosure;

[0037] Figures 3 to 6 Shows a partial top view of the driving transistor according to an embodiment of the present disclosure;

[0038] Figures 7 to 9 Shows the circuit schematic diagram of the pixel circuit according to other embodiments of the present disclosure;

[0039] Figure 10 Shows according to Figure 9 The schematic cross-sectional view of the driving transistor in the pixel circuit of the embodiment;

[0040] Figures 11 to 12 Shows a circuit schematic diagram of a pixel circuit according to some other embodiments of the present disclosure;

[0041] Figure 13 Shows according to Figure 12 A schematic cross-sectional view of a driving transistor in a pixel circuit according to an embodiment of

[0042] Figure 14 Shows a circuit schematic diagram of a pixel circuit according to another embodiment of the present disclosure;

[0043] Figure 15 Shows according to Figure 14 A schematic cross-sectional view of a driving transistor in a pixel circuit according to an embodiment of

[0044] Figure 16 Shows a circuit schematic diagram of a pixel circuit according to another embodiment of the present disclosure. Detailed implementation manners

[0045] To more clearly illustrate the present disclosure, the present disclosure will be further described below in conjunction with preferred embodiments and the accompanying drawings. Similar components in the drawings are denoted by the same reference numerals. Those skilled in the art should understand that the content specifically described below is illustrative rather than restrictive, and should not be used to limit the protection scope of the present disclosure.

[0046] It should be noted that unless otherwise defined, the technical terms or scientific terms used in the present disclosure should have the ordinary meaning understood by those of ordinary skill in the field to which the present disclosure belongs. The "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "one" or "the" do not denote a quantity limitation, but mean that there is at least one. The terms such as "comprising" or "including" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects.

[0047] In the present disclosure, the term "same-layer setting" refers to that two layers, components, members, elements or parts can be formed by the same preparation process (such as a patterning process, etc.), and generally, these two layers, components, members, elements or parts are formed of the same material. For example, the same-layer setting of two or more functional layers means that these same-layer-set functional layers can be formed by using the same material layer and the same preparation process, thereby simplifying the preparation process of the display substrate.

[0048] In addition, the present disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are enlarged for clarity. Therefore, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Accordingly, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused by, for example, manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0049] Based on at least one of the above problems, an embodiment of the present disclosure provides a display panel, including:

[0050] a driving sub-circuit and a light-emitting unit,

[0051] The driving sub-circuit includes a driving transistor electrically connected between a first power signal terminal and a second power signal terminal and configured to generate a driving current from the first power signal terminal through the light-emitting unit to the second power signal terminal.

[0052] Wherein, the driving transistor is a double-gate or multi-gate transistor.

[0053] In this embodiment, by setting the driving transistor in the driving sub-circuit for generating the driving current as a double-gate or multi-gate transistor, fine adjustment and management of the characteristics of the driving transistor can be achieved, thereby improving the effect of display afterimage and enhancing the user experience.

[0054] To illustrate the structure and function of the present disclosure, the following continues with a detailed description in combination with specific examples.

[0055] In a specific example, referring to Figure 1 as shown, the pixel circuit includes: a driving sub-circuit 11-1 and a light-emitting unit D.

[0056] The light-emitting unit D can be an OLED, or a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, abbreviated as QLED) or a micro light-emitting diode (Micro Light Emitting Diodes, abbreviated as MicroLED), etc. In the embodiments of the present disclosure, any light-emitting element capable of emitting light under a driving current is acceptable. In addition, in the embodiments of the present disclosure, the light-emitting element is denoted by D, and Figure 1 one light-emitting element is shown therein, but it is only for illustration, and the light-emitting unit D may also include a series connection of multiple light-emitting elements.

[0057] The driving sub - circuit 11 - 1 includes a driving transistor T3. The driving transistor T3 is electrically connected between the first power signal terminal VDD and the second power signal terminal VSS, and is configured to generate a driving current from the first power signal terminal VDD via the light - emitting unit D to the second power signal terminal VSS.

[0058] Specifically, the driving transistor T3 is a double - gate transistor. In an embodiment of the present disclosure, the double - gate transistor is a device with a double - gate structure. For example, it can be a double - gate thin - film transistor, which can be regarded as the series connection of two thin - film transistors in terms of structure.

[0059] Figure 2 A schematic cross - sectional view of the driving transistor T3 showing an embodiment satisfying the present example is presented. Referring to Figure 2 As shown, the driving transistor T3 includes: a first pole 113, a second pole 123, and a control pole 102. Correspondingly, Figure 1 exemplarily, the first pole 113 is electrically connected to the first power signal line VDD, the second pole 123 is electrically connected to the first electrode of the light - emitting unit D, and the control pole 102 is electrically connected to the first node N1.

[0060] Continuing to refer to Figure 2 As shown, the driving transistor T3 includes: an active region 101, a control pole 102, and a first pole 113 and a second pole 123 formed on the substrate 100. In Figure 1 the circuit shown, if the driving transistor T3 is a P - type transistor, then in this example, the first pole 113 is the source and the second pole 123 is the drain.

[0061] Those skilled in the art should understand that the present disclosure does not limit the specific type of the driving transistor T3 in the pixel circuit. Therefore, according to the conduction type of the driving transistor T3 in the actual circuit, the specific electrode types of the first pole 113 and the second pole 123 can also vary, which will not be elaborated in this text.

[0062] In addition, Figure 2 the cross - sectional view schematically showing the driving transistor T3 can be a part of the driving transistor T3 in the pixel circuit. Here, the substrate 100 can also be a part of the substrate of the pixel circuit, which will not be elaborated in this text.

[0063] Continuing to refer to Figure 2 As shown, in an embodiment of the present disclosure, the active region 101 is electrically connected between the first pole 113 and the second pole 123 and includes two channels 111 and 121 connected in series.

[0064] Specifically, the control electrode 102 includes a sub-control electrode 102-1 corresponding to the channel 111 and a sub-control electrode 102-2 corresponding to the channel 121. That is, the two sub-control electrodes 102-1 and 102-2 included in the control electrode 102 correspond one-to-one to the two channels 111 and 121. The positive projection of the sub-control electrode 102-1 on the substrate 100 covers the positive projection of its corresponding sub-control electrode 102-1 on the substrate 100, and the positive projection of the sub-control electrode 102-2 on the substrate 100 covers the positive projection of its corresponding channel 121 on the substrate 100. Although Figure 2 not shown, referring to Figure 1 it can be understood that the two sub-control electrodes 102-1 and 102-2 are electrically connected to the first node N1.

[0065] It can be seen that the channels 111 and 121 corresponding to the two sub-control electrodes 102-1 and 102-2 in the driving transistor T3 are formed such that the first end of the channel 111 is electrically connected to the first electrode 113, the second end is electrically connected to the first end of the channel 121, and the second end of the channel 121 is electrically connected to the second electrode 123.

[0066] In other words, referring to Figure 1 and Figure 2 shown, it is equivalent to the driving transistor T3 including a first sub-driving transistor T3_1 and a second sub-driving transistor T3_2 connected in series. The first sub-driving transistor T3_1 has its first electrode 113 as the driving transistor electrically connected to the first power supply signal terminal VDD, its second electrode electrically connected to the first electrode of the second sub-driving transistor T3_2, the second electrode of the second sub-driving transistor T3_2 electrically connected to the first electrode of the light-emitting unit D, and the control electrodes of the first sub-driving transistor T3_1 and the second sub-driving transistor T3_2 electrically connected to the first node N1.

[0067] Continuing to refer to Figure 2 shown, the driving transistor T3 further includes a buffer layer 104 formed between the substrate 100 and the active region 101, a gate insulating layer 105 formed between the active region 101 and the control electrode 102, and a dielectric layer 106 formed on the control electrode 102. In addition, the driving transistor 103 may further include a planarization layer 107 covering the dielectric layer 106.

[0068] Exemplarily, the material of the active region 101 may be Poly polysilicon material, the control electrode 102 may be a multi-layer metal structure, and the film layer combination may be selected from one of molybdenum / aluminum / molybdenum (Mo / AlMo), molybdenum / copper (Mo / Cu), molybdenum-niobium alloy / copper (MoNb / Cu), molybdenum-niobium alloy / copper / molybdenum-titanium alloy (MoNb / Cu / MoTi) or its stack. The first electrode 113 and the second electrode 123 may be arranged in the same layer, and the film layer combination may be selected from one of Mo / Al / Mo, Mo / Cu, MoNb / Cu, MoNb / Cu / MoTi, etc. or its stack.

[0069] Additionally exemplarily, the material of the buffer layer 104 may be other inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, and it may be a single-layer or multi-layer structure. The material of the gate insulating layer 105 may be other inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, and the gate insulating layer 702 may be a single layer or multi-layer structure. The material of the dielectric layer 106 may be silicon oxide, silicon nitride, or other insulating and high-k materials. The planarization layer 107 may be a material film such as silicon oxide, silicon oxynitride, or photoresist.

[0070] It should be noted that although Figure 2 the driving transistor T3 is shown as a top-gate structure with the control electrode 102 located above the film layer of the active region 101, it is not intended to be limiting, and the driving transistor T3 with a bottom-gate structure is also within the scope of protection of this embodiment; in addition, although Figure 2 the sub-control electrode 102-1 and the sub-control electrode 103-2 are shown in the same film layer, the present disclosure is not limited thereto, and the two may not be in the same layer, which will not be elaborated here.

[0071] In this embodiment, by setting the driving transistor T3 as a double-gate transistor with two channels 111 and 121 formed in series connection in the active region 101, the two channels 111 and 121 can be independently turned on to form a current under the control of the corresponding sub-control electrodes, which is equivalent to having two transistors connected in series between the first power signal terminal VDD and the first electrode of the light-emitting unit D to jointly generate a driving current. Thus, the overall performance of the driving transistor T3 can be finely regulated by using the two channels of the double-gate transistor, thereby improving the hysteresis of the driving transistor and improving the display afterimage.

[0072] Optionally, the channel width-to-length ratios of the two channels connected in series are different.

[0073] Figures 3 to 6A schematic diagram of the structures of two channels and sub-control gates of the driving transistor T3 of a double-gate transistor structure is exemplarily shown, where other film layers are removed for clarity. Additionally, a, b, c, and d are added to the corresponding labels to distinguish each example. It should be understood that the specific structure names are based on the numbers before the letters. For example, the labels "101a, 101b, 101c, 101d" all represent the active region of the driving transistor T3 as the label "101" in the above text, which will not be elaborated here. Additionally, Figures 3 to 6 "S" in

[0074] refers to Figure 3 one end of the active region close to the first pole 113, and "D" refers to one end of the active region close to the second pole 123.

[0075] As shown in the reference

[0076] In this example, the orthographic projection shapes of the channel 111a and the channel 121a on the substrate 100 are both rectangular, and the channel widths of both are W. However, the channel length L1 of the channel 111a corresponding to the sub-control gate 102-1a and the channel length L2 of the channel 121a corresponding to the sub-control gate 102-2a have different channel width-to-length ratios. Figure 4 Through this setting, by using the different channel width-to-length ratios in the two serially connected channels 111a and 121a corresponding to the two sub-control gates, different transistor characteristics such as the threshold voltage (Vth) and data range of the two parts of the driving transistor T3 can be obtained, so that the overall performance of the driving transistor T3 can be finely adjusted, the hysteresis of the driving transistor can be improved, the effect of improving display afterimage can be achieved, and thus the display effect can be improved.

[0077] As shown in the reference

[0078] In this example, the orthographic projection shape of the channel 111b on the substrate 100 is rectangular, while the orthographic projection shape of the channel 121b on the substrate 100 is bent, and they have different channel shapes. Assuming that the channel widths of the channel 11b and the channel 121b are both W, the channel length of the channel 111b corresponding to the sub-control gate 102-1a is the length of the double-arrow broken line in the figure, which is different from the channel length L2 of the channel 121b corresponding to the sub-control gate 102-2a, resulting in different channel width-to-length ratios. Figure 5As shown, in this example, the orthographic projection shapes of the channels 111c and 121c on the substrate 100 are both bent shapes, but the bent portions of the two can be set to have different channel widths. That is, referring to Figure 5 As shown, the channel widths of some parts of the channels 111c and 121c are the same W3. The assumed channel width of the bent portion of the channel 111c is W1, and the channel width of the bent portion of the channel 121c is W2. In addition, the channel lengths of the channels 111c and 121c are different. Assuming that the final channel widths of the channels 111c and 121c are different, that is to say, different channel width-to-length ratios can be finally obtained by setting different channel widths and channel lengths.

[0079] Through this setting, by using the different patterns of the two serially connected channels 111c and 121c corresponding to the two sub-control electrodes, different channel width-to-length ratios are realized, so that the two parts of the driving transistor T3 have different transistor characteristics such as threshold voltage (Vth) and data range, etc., thereby enabling fine adjustment of the overall performance of the driving transistor T3, improving the hysteresis of the driving transistor, and achieving the effect of improving display afterimage.

[0080] Referring to Figure 6 As shown, in this example, the active region color is set to be strip-shaped in two intersecting directions, so that the orthographic projection shapes of the channels 111d and 121d on the substrate 100 are rectangles extending in the two intersecting directions. That is, referring to Figure 6 As shown, the channel 111d has a channel width W1 and a channel length L1, and the channel 121d has a channel width W2 and a channel length L2. By setting W1 = W2 and L1 ≠ L2, different width-to-length ratios of the two channel parts in the driving transistor T3 can be realized, and the specific width-to-length ratio values can be adjusted according to parameter requirements. Of course, because the channels 111d and 121d are located in two strip parts, it is also easy to set W1 ≠ W2 to achieve more fine adjustment.

[0081] Through this setting, when the active region is set to include intersecting rectangles extending in two different directions, different channel width-to-length ratios can also be realized by setting different widths and lengths of the rectangular parts, so that the two parts of the driving transistor T3 have different transistor characteristics such as threshold voltage (Vth) and data range, etc., thereby enabling fine adjustment of the overall performance of the driving transistor T3, improving the hysteresis of the driving transistor, and achieving the effect of improving display afterimage.

[0082] It should be noted that the above patterns and structural relationships are only for illustration and are not intended to be exhaustive. The channels 111 and 121 with other patterns and structures are also within the scope of protection of the present disclosure.

[0083] ContinuingFigure 1 As shown, the pixel circuit may further include: a writing sub-circuit 12, which is electrically connected to the first pole of the driving transistor T3, the writing control terminal PGate, and the writing signal terminal Data, and is configured to transmit the signal of the writing signal terminal Data to the first pole of the driving transistor T3 based on the signal of the writing control terminal PGate.

[0084] Specifically, the writing sub-circuit 12 may include a first transistor T1. The first pole of the first transistor T1 is electrically connected to the writing signal terminal Data, the second pole is electrically connected to the second node N2 corresponding to the first pole of the driving transistor T3, and the control pole is electrically connected to the writing control terminal PGate. When a valid signal is applied to the writing control terminal PGate, the writing signal terminal Data is electrically connected to the second node N2 to write the signal of the writing signal terminal Data to the first pole of the driving transistor T3.

[0085] Continue to refer to Figure 1 As shown, the pixel circuit may further include: a compensation sub-circuit 13, which is configured to be electrically connected to the third node N3 corresponding to the second pole of the driving transistor T3, the compensation control terminal NGate, and the first node N1, and is configured to electrically connect the second node N2 and the first node N1 based on the signal of the compensation control terminal NGate.

[0086] Specifically, the compensation sub-circuit 13 may include a second transistor T2. The first pole of the second transistor T2 is electrically connected to the third node N3, the second pole is electrically connected to the first node N1, and the control pole is electrically connected to the compensation control terminal NGate. When a valid level signal is applied to the compensation control terminal NGate, the second node N2 and the first node N1 are electrically connected to perform threshold compensation on the threshold voltage of the driving transistor T3.

[0087] Specifically in this example, the writing control terminal PGate and the compensation control terminal NGate may access valid levels in the same time period. Of course, in this example, the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor. Then, the valid level of the writing control terminal PGate is a low-level signal, and the compensation control terminal NGate is a high-level signal. By turning on the first transistor T1 and the second transistor T2 simultaneously, the data writing and threshold compensation processes can be performed simultaneously.

[0088] In addition, the pixel single path may further include a storage capacitor Cst, whose first pole is electrically connected to the first power signal terminal VDD and the second pole is electrically connected to the first node N1 to store the signal written to the first node N1.

[0089] Optionally, continue to refer to Figure 1As shown, the pixel circuit further includes: a first reset sub-circuit 14, the first reset sub-circuit 14 being electrically connected to a first reset signal terminal Vinit1, a first reset control terminal Reset1, and a third node N3 corresponding to the second pole of the driving transistor T3, and configured to transmit the first reset signal of the first reset signal terminal Vinit1 to the second pole of the driving transistor T3 based on the signal of the first reset control terminal Reset1.

[0090] Specifically, referring to Figure 1 As shown, the first reset sub-circuit 14 includes a fourth transistor T4, the first pole of the fourth transistor T4 being electrically connected to the first reset signal terminal Vinit1, the second pole being electrically connected to the third node N3, and the control pole being electrically connected to the first reset control terminal Reset1, and configured to transmit the first reset signal of the first reset signal terminal Vinit1 to the second pole of the driving transistor T3 based on the signal of the first reset control terminal Reset1.

[0091] Optionally, referring to Figure 1 As shown, the pixel circuit further includes: a first light-emitting control sub-circuit 15 and / or a second light-emitting control sub-circuit 16. The first light-emitting control sub-circuit 15 is electrically connected to a first power signal terminal VDD, a second node N2, and a light-emitting control terminal EM, and configured to connect the electrical connection from the first power signal terminal VDD to the second node N2 based on the signal of the light-emitting control terminal EM to form a light-emitting path. The second light-emitting control sub-circuit 16 is electrically connected to a fourth node N4 corresponding to the first electrode of the light-emitting unit D, the third node N3, and the light-emitting control terminal EM, and configured to connect the third node N3 and the second node N4 based on the signal of the light-emitting control terminal EM to form a light-emitting path, so as to transmit a driving current to the first electrode of the light-emitting unit D.

[0092] Specifically, referring to Figure 1 As shown, the first light-emitting control sub-circuit 15 includes a fifth transistor T5, the first pole of the fifth transistor T5 being electrically connected to the first power signal terminal VDD, the second pole being electrically connected to the second node N2, and the control pole being electrically connected to the light-emitting control terminal EM. When the signal accessed by the light-emitting control terminal EM is an effective level, the electrical connection from the first power signal terminal VDD to the second node N2 is made. The second light-emitting control sub-circuit 16 includes a sixth transistor T6, the first pole of the sixth transistor T6 being electrically connected to the fourth node N4, the second pole being electrically connected to the third node N3, and the control pole being electrically connected to the light-emitting control terminal EM. When the signal accessed by the light-emitting control terminal EM is an effective level, the third node N3 and the second node N4 are connected.

[0093] Optionally, continuing to refer to Figure 1As shown, the pixel circuit further includes: a second reset sub-circuit 17, which is electrically connected to a second reset control terminal Reset2, a second reset signal terminal Vinit2, and a fourth node N4, and is configured to electrically connect the second reset signal terminal Vinit2 and the fourth node N4 based on a signal of the second reset control terminal Reset2, so as to transmit a signal of the second reset signal terminal Vinit2 to the fourth node N4 to reset it.

[0094] Specifically, referring to Figure 1 As shown, the second reset sub-circuit 17 includes a seventh transistor T7. A first pole of the seventh transistor T7 is electrically connected to the second reset signal terminal Vinit2, a second pole is electrically connected to the fourth node N4, and a control pole is electrically connected to the second reset control terminal Reset2, and is configured to transmit a second reset signal of the second reset signal terminal Vinit2 to the fourth node N4 based on a signal of the second reset control terminal Reset2.

[0095] Continuing to refer to Figure 1 As shown, the pixel circuit may further include: another reset sub-circuit 18, which may also be referred to as a third reset sub-circuit, and is electrically connected to a reset control terminal Reset2, a reset signal terminal Vinit3, and a second node N2, and is configured to electrically connect the reset signal terminal Vinit3 and the second node N2 based on a signal of the reset control terminal Reset2, so as to transmit a reset signal of the reset signal terminal Vinit3 to the second node N2 to reset it.

[0096] Optionally, the reset sub-circuit 18 includes an eighth transistor T8. A first pole of the eighth transistor T8 is electrically connected to the reset signal terminal Vinit3, a second pole is electrically connected to the second node N2, and a control pole is electrically connected to the reset control terminal Reset2. When the signal of the reset control terminal Reset2 is at an effective level, the reset signal terminal Vinit3 and the second node N2 are electrically connected.

[0097] However, the overall structure of the pixel circuit in the embodiments of the present disclosure is not limited to the above structure.

[0098] Optionally, referring to Figure 7 As shown, the structure of this pixel circuit is different from the structure shown in Figure 1 As shown in that it includes a first reset sub-circuit 14-1. The first reset sub-circuit 14-1 is electrically connected to a first node N1, a first reset signal terminal Vinit1, and a first reset control terminal Reset1, and is configured to electrically connect the first reset signal terminal Vinit1 and the first node N1 based on a signal of the first reset control terminal Reset1 to reset the voltage of the first node N1.

[0099] Alternatively, referring to Figure 8 As shown, the structure of this pixel circuit is different fromFigure 1 and Figure 7 The difference from the structure shown in Figure 1 is that it provides an architecture with a separate writing and compensation function. The difference lies in that the pixel circuit includes a writing sub-circuit 12-2, and the writing sub-circuit 12-2 is electrically connected to the first node N1, the writing signal terminal Data, and the writing control terminal Gate, and is configured to transmit the data signal of the writing signal terminal Data to the first node N1 based on the signal of the writing control terminal Gate.

[0100] Specifically, the writing sub-circuit 12-2 includes a first transistor T1 and a first storage capacitor Cst1. The first pole of the first transistor T1 is electrically connected to the writing signal terminal Data, the second pole is electrically connected to the first pole of the first storage capacitor Cst1, the control pole is electrically connected to the writing control terminal Gate, and the second pole of the first storage capacitor Cst1 is electrically connected to the first node N1, and is configured to write the data signal to the first node N1 via the first storage capacitor Cst1 based on the signal of the writing control terminal Gate.

[0101] Through this setting, the compensation sub-circuit 13 can perform threshold compensation on the driving transistor T3 and the data writing of the writing sub-circuit 12-2 in different time periods, so that there is sufficient time for data writing in the case of a high refresh rate, and an excellent display effect can be achieved.

[0102] Optionally, in cooperation with the writing sub-circuit 12-2, the pixel circuit may further include a compensation control circuit 19, which may include a ninth transistor T9 and a second storage capacitor Cst2. The first pole of the ninth transistor T9 is electrically connected to the first power signal terminal VDD or the reference signal terminal Ref, the second pole is electrically connected to the first pole of the second storage capacitor Cst2, and the control pole is electrically connected to the compensation control terminal Gate1, and is configured to charge the control pole of the driving transistor T3 with the signal of the first power signal terminal VDD or the reference signal terminal Ref based on the signal of the compensation control terminal Gate1 to assist in completing the threshold compensation.

[0103] It should also be noted that the circuit architecture of the above pixel circuit is not intended to be limited. As long as the pixel circuit generates a driving current through the driving transistor T3 to drive the light-emitting unit to emit light, it is within the protection scope of the embodiments of the present disclosure.

[0104] Considering that the double-gate transistor is used as the driving transistor T3 for generating the driving current, and the double-gate structure works independently as two series-connected transistor parts, there must be an intermediate node. Once there is a floating signal or node in the circuit, the floating node voltage is easily interfered by other signal jumps, resulting in a problem of poor stability. The poor stability is manifested as a problem of deteriorated display uniformity on the driving transistor T3, affecting the display uniformity.

[0105] Thus, in another alternative embodiment, referring to Figure 9 as shown, the difference between this embodiment and the embodiment Figure 1 shown is that the driving sub-circuit 11-2 further includes: a first capacitor C1 electrically connected to an intermediate node between two adjacent channels.

[0106] Specifically, in combination with Figure 9 and Figure 10 as shown, a first pole of the first capacitor C1 is disposed in the active region between two adjacent channels, a second pole 109 is disposed in the first metal layer, and the second pole 109 receives a first regulation signal. Of course, there is at least one dielectric layer 108 between the first metal layer and the film layer where the active region 101 is located. The material of the dielectric layer 108 may be an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0107] Referring to Figure 10 as shown, the first metal layer may be disposed in a metal film layer located between the active region 101 and the substrate 100. For example, if the control electrode 102 is fabricated using a first gate layer, which is usually referred to as the Gate2 layer, the first metal layer may utilize another gate layer, which is usually referred to as the Gate1 layer. Additionally, the intermediate node is equivalent to the common connection end of the second pole of the first sub-driving transistor T3_1 and the first pole of the second sub-driving transistor T3_2.

[0108] With this arrangement, by utilizing the semiconductor characteristics of the active region 101, only a metal film layer with an intermediate insulating medium between the film layer where the active region 101 is located is required to form the first capacitor electrically connected to the intermediate node between the two channels 111 and 121 through a simple layout and wiring structure. By providing the first regulation signal to this capacitor, the voltage of the intermediate node can be stabilized, preventing the intermediate node between the two channels in the driving transistor T3 from being disturbed by the jump of other signals, ensuring driving stability, and guaranteeing display uniformity.

[0109] On the other hand, by providing the first capacitor electrically connected to the intermediate node between the two channels 111 and 121, the first regulation signal provided to the second pole can flexibly adjust the voltage of the capacitor plate, thereby achieving the effect of adjusting the transistor data range of the driving transistor T3.

[0110] Referring to Figure 9 as shown, the pixel circuit may include a first voltage regulation terminal Vin electrically connected to the second pole of the first capacitor C1. The first voltage regulation terminal Vin may receive an independent voltage signal through electrical connection to a chip outside the pixel circuit, such as a display driver integrated circuit (DIC).

[0111] Optionally, the first voltage control terminal Vin can be directly electrically connected to the reset signal terminal Vinit3 or the first reset signal terminal Vinit1, and the voltage stabilizing signal inside the pixel circuit is used as the first control signal, so as to realize the voltage stabilization of the driving transistor T3 and the optimization adjustment of its data range without external wiring. Optionally, usually the potential of the second reset signal terminal Vinit2 is the same as that of one of the first reset signal terminal Vinit1 or the reset signal terminal Vinit3. If the potential of the second reset signal terminal Vinit2 is appropriate, the first voltage control terminal Vin can also adopt this signal.

[0112] Optionally, the positive projection of the second pole 109 on the substrate 100 does not overlap with the positive projection of the control pole 102 on the substrate 100. The purpose of this is to form only a capacitor electrically connected between two channels and avoid the influence of the second pole 109 of the capacitor accessing the first control signal on the transistor's own transistor characteristics.

[0113] In some other alternative embodiments, referring to Figure 11 As shown, the first capacitor electrically connected to the intermediate node between the two channels 111 and 121 can adopt two additional metal film layers. Optionally, the first pole of the first capacitor is arranged on the first metal layer, and the second pole is arranged on the second metal layer. The first pole is electrically connected to the intermediate node between the adjacent two channels, and the second pole accesses the first control signal.

[0114] In this case, since the position of the capacitor plate is not limited to the active region 101, its position in the film layer is relatively flexible. For example, the first plate of the first capacitor C1 can adopt the film layer where the control pole 102 is located, and the other pole can adopt another metal film layer with an insulating layer between this layer, such as the SD1 and SD2 layers, etc. The first pole of the first capacitor C1 can be electrically connected to the intermediate node through a via penetrating into the active region 101, which will not be elaborated here.

[0115] It should be noted that although Figure 9 and Figure 11 show an overall architecture of a pixel circuit, the present disclosure is not limited to this. The separate data writing and compensation architecture, the architecture with different positions of the first reset sub-circuit, and other variant structures described in the above embodiments are also applicable to this embodiment.

[0116] In some other alternative embodiments, referring to Figure 12 and Figure 13 As shown, the difference between this pixel circuit and the above embodiment is that the pixel circuit includes a driving sub-circuit 11-3, and the driving sub-circuit includes a driving transistor T3.

[0117] In particular, the driving transistor T3 includes: an auxiliary control electrode, an active region 101, a control electrode 102, and a first electrode 113 and a second electrode 123, which are sequentially stacked on the substrate 100. The active region 101 is electrically connected between the first electrode 113 and the second electrode 123 and includes two channels 111 and 121 connected in series. The control electrode 102 includes at least sub-control electrodes 102-1 and 102-2 corresponding to the channels 111 and 121 one by one. The two sub-control electrodes are electrically connected to the first node N1. The positive projection of the sub-control electrode 102-1 on the substrate 100 covers the positive projection of the corresponding channel 111 on the substrate 100, and the positive projection of the sub-control electrode 102-2 on the substrate 100 covers the positive projection of the corresponding channel 121 on the substrate 100. The auxiliary control electrode includes: an auxiliary sub-control electrode 110-1 corresponding to the sub-control electrode 102-1 and an auxiliary sub-control electrode 110-2 corresponding to the sub-control electrode 102-2. Moreover, the positive projection of the auxiliary sub-control electrode 110-1 on the substrate 100 covers the positive projection of the corresponding sub-control electrode 102-1 on the substrate 100, and the positive projection of the auxiliary sub-control electrode 110-2 on the substrate 100 covers the positive projection of the corresponding sub-control electrode 102-2 on the substrate 100. Each of the auxiliary sub-control electrodes 110-1 and 110-2 receives the corresponding auxiliary regulation signal.

[0118] Exemplarily, as shown in Figure 12 the auxiliary sub-control electrode 110-1 can be electrically connected to the first auxiliary regulation terminal Sig1, and the auxiliary sub-control electrode 110-2 can be electrically connected to the second auxiliary regulation terminal Sig2. The first auxiliary regulation terminal Sig1 and the second auxiliary regulation terminal Sig2 can be electrically connected to a chip outside the pixel circuit, such as a DIC to receive the auxiliary regulation signal; they can also receive the auxiliary regulation signal by directly being electrically connected to the first reset signal terminal Vini1, the second reset signal terminal Vinit3, or the reset signal terminal Vinit3 inside the circuit. Optionally, usually the potential of the second reset signal terminal Vinit2 is the same as the potential of one of the first reset signal terminal Vinit1 or the reset signal terminal Vinit3. If the potential of the second reset signal terminal Vinit2 is appropriate, the first auxiliary regulation terminal Sig1 and / or the second auxiliary regulation terminal Sig2 can also adopt this signal.

[0119] With the above settings, by providing the auxiliary control electrodes 110-1 and 110-2 in the driving transistor T3 that respectively and independently correspond to the channel 111 and the channel 121, it is equivalent to adding an independent bottom gate structure in the driving transistor T3. By applying the auxiliary regulation signal to the two electrodes, the threshold voltage of the transistor part corresponding to each channel in the driving transistor T3 can be finely regulated, and transistor characteristics such as the subthreshold swing and carrier mobility of the transistor can be improved. Through fine adjustment, the characteristics of the driving transistor T3 can be significantly improved, the hysteresis of the driving transistor can be improved, the image sticking can be improved, and the display effect can be enhanced.

[0120] It is worth mentioning that, as a transistor structure with series channels, the transistor part corresponding to each channel in the driving transistor T3 has different transistor characteristics affected by the voltage of its corresponding sub-control electrode, that is, each transistor part has its independent threshold voltage. The existence of the two auxiliary sub-control electrodes is equivalent to adding a gate control under the channel and applying an additional gate signal to adjust the characteristics such as the threshold voltage and carrier mobility of the transistor part corresponding to the channel. The applied auxiliary regulation signal is an auxiliary signal of the data signal written to the first node N1 corresponding to the control electrode and cannot exceed the influence of the data signal.

[0121] Optionally, in this embodiment, the potential of each of the auxiliary regulation signals should not have the function of turning on the driving transistor part corresponding to the corresponding channel. In this way, only a DC voltage signal needs to be directly provided as the auxiliary regulation signal without worrying about the mis-turn-on of the driving transistor during the screen display stage, which greatly simplifies the adjustment difficulty.

[0122] Specifically, the auxiliary regulation signal is a DC voltage signal. When the driving transistor is a P-type transistor, the potential of the auxiliary regulation signal is greater than the threshold voltage of the corresponding driving transistor part. When the driving transistor is an N-type transistor, the potential of the auxiliary regulation signal is less than the threshold voltage of the corresponding driving transistor part.

[0123] It should be noted that although the figure shows that the orthographic projection of the auxiliary sub-control electrode 110-1 on the substrate 100 covers the orthographic projection of the channel 111 on the substrate 100, and the orthographic projection of the auxiliary sub-control electrode 110-2 on the substrate 100 covers the orthographic projection of the channel 121 on the substrate 100, the present disclosure is not limited thereto. As long as the corresponding auxiliary sub-control electrode can overlap with the corresponding channel, the adjustment effect on its threshold voltage and other characteristics can be achieved. Of course, the adjustment effect of complete coverage is better.

[0124] It should be noted that although not specifically stated, in this embodiment, the equivalent driving transistor T3 includes a first sub-driving transistor T3_1 and a second sub-driving transistor T3_2 connected in series. The first pole 113 of the first sub-driving transistor T3_1, which serves as the driving transistor, is electrically connected to the first power signal terminal VDD, the second pole is electrically connected to the first pole of the second sub-driving transistor T3_2, the second pole of the second sub-driving transistor T3_2 is electrically connected to the first electrode of the light-emitting unit D, the control poles of the first sub-driving transistor T3_1 and the second sub-driving transistor T3_2 are electrically connected to the first node N1, the first sub-driving transistor T3_1 further includes an auxiliary sub-control pole 110-1, which constitutes the bottom gate of the first sub-driving transistor T3_1, and the second sub-driving transistor T3_2 further includes an auxiliary sub-control pole 110-2, which constitutes the bottom gate of the second sub-driving transistor T3_2.

[0125] It should be noted that although this embodiment requires an auxiliary control pole to be provided under the channel, the first capacitor C1 can still be electrically connected to the intermediate node through vias, thereby stabilizing the intermediate node voltage, avoiding the intermediate node between the two channels in the driving transistor T3 from being disturbed by the jump of other signals, ensuring the driving stability, and guaranteeing the display uniformity; at the same time, the first capacitor C1 electrically connected to the intermediate node can also increase the regulation fineness of the driving transistor from another dimension through the first regulation voltage.

[0126] Similarly, although Figure 12 and Figure 13 show an overall architecture of a pixel circuit, the present disclosure is not limited thereto. The separate data writing and compensation architecture, the architecture with different positions of the first reset sub-circuit, and other variable structures described in the above embodiments are also applicable to this embodiment.

[0127] Optionally, the thicknesses of at least two auxiliary sub-control poles in the direction perpendicular to the substrate are different. Through this setting, the characteristic difference of the transistor parts corresponding to the two channels can be further increased, thereby improving the adjustment flexibility and refinement.

[0128] In some other alternative embodiments, referring to Figure 14 and Figure 15 shown, the auxiliary control pole can cover both the channel 111 and the channel 121 at the same time, so as to debug the characteristics of the two channels simultaneously by using an auxiliary regulation signal.

[0129] Specifically, referring to Figure 15 shown, the pixel circuit includes a driving sub-circuit 11-4 driving transistor T3, and this driving transistor is connected to Figure 14The difference of the embodiment is that it includes an auxiliary control electrode 110 located between the substrate and the active area 101, the positive projection of the auxiliary control electrode 110 on the substrate 100 covers the positive projection of the control electrode 102 on the substrate 100, and the auxiliary sub-control electrode is connected to the auxiliary control signal. Of course, this embodiment is not limited to complete coverage, as long as the auxiliary control electrode 110 and each sub-control electrode 102-1 and 102-2 have at least partial overlap, it can produce a regulating effect on the threshold voltage and other characteristics of the transistor part of the corresponding channel, which will not be repeated here.

[0130] It should be noted that, although not specifically stated, in this embodiment, the driving transistor T3 includes a first sub-driving transistor T3_1 and a second sub-driving transistor T3_2 connected in series, the first sub-driving transistor T3_1 as a driving transistor, the first electrode 113 is electrically connected to the first power signal terminal VDD, the second electrode is electrically connected to the first electrode of the second sub-driving transistor T3_2, the second electrode of the second sub-driving transistor T3_2 is electrically connected to the first electrode of the light-emitting unit D, the control electrode of the first sub-driving transistor T3_1 and the control electrode of the second sub-driving transistor T3_2 are electrically connected to the first node N1, the part of the auxiliary control electrode 110 corresponding to the channel 111 constitutes the bottom gate of the first sub-driving transistor T3_1, and the part corresponding to the channel 121 constitutes the bottom gate of the second sub-driving transistor T3_2.

[0131] In some other optional embodiments, refer to Figure 16 As shown, the pixel circuit shown in the figure includes a driving subcircuit 11-5, which differs from the various embodiments described above only in that the driving transistor T3 is a multi-gate transistor, the multi-gate transistor is an active region electrically connected between the first electrode and the second electrode and includes a plurality of channels connected in series, and three channels are shown by way of example in the figure, but this is only for illustration, and any series channel structure greater than two is protected in this embodiment.

[0132] Specifically, the control electrode includes: at least two sub-control electrodes corresponding to the channels one by one, the at least two sub-control electrodes are electrically connected to the first node, and the orthographic projections of the sub-control electrodes on the substrate cover the orthographic projections of the corresponding channels on the substrate.

[0133] By setting up multiple channels connected in series, more dimensions and finer control are further provided compared to the dual-gate structure of two channels, thereby effectively improving various characteristics of the driving transistor, improving transistor hysteresis, and thus improving display afterimages.

[0134] In addition, the features in the above embodiments are partially or completely included in this embodiment. Figure 16For the driving transistor T3 shown, the channel width-to-length ratios of at least two of the three channels can be different, thereby increasing the regulation fineness. For example, a first capacitor C1 is provided at an intermediate node between at least two adjacent channels, and the structure and signal input manner of the first capacitor C1 are the same as those in the above embodiments. For example, overlapping or partially overlapping is provided below at least two channels, and an auxiliary control electrode independent of or corresponding to two or more channels is provided, and the structure and signal input manner of the auxiliary control electrode are the same as those in the above embodiments.

[0135] In addition, the overall architecture of the pixel circuit applicable to this embodiment is not limited to Figure 16 As shown, other pixel circuit architectures described above or not shown are all applicable to this embodiment.

[0136] Based on the same inventive concept, an embodiment of the present disclosure also provides a display panel including the pixel circuit described in the above embodiments. Since the pixel circuit included in the display panel provided by the embodiment of the present disclosure corresponds to the pixel circuit provided by the above embodiment, the foregoing implementation manners are also applicable to the display device provided by this embodiment, and will not be described in detail in this embodiment.

[0137] By providing the pixel circuit including the above embodiments, the display panel can improve the afterimage problem in the picture display, improve the display stability and picture uniformity, and improve the user experience.

[0138] Based on the same inventive concept, an embodiment of the present disclosure also provides a display device including the display panel described in the above embodiments. Since the display panel included in the display device provided by the embodiment of the present disclosure corresponds to the display panel provided by the above embodiment, the foregoing implementation manners are also applicable to the display device provided by this embodiment, and will not be described in detail in this embodiment.

[0139] In this embodiment, the display device can be any product or component with a display function, such as an in-vehicle display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator. When the above display panel is used in a display device, the display afterimage problem can be significantly improved, and the user experience can be improved.

[0140] Obviously, the above embodiments of the present disclosure are merely examples for clearly explaining the present disclosure, and are not limitations on the implementation manners of the present disclosure. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is impossible to list all the implementation manners here. Any obvious changes or variations derived from the technical solutions of the present disclosure still fall within the protection scope of the present disclosure.

Claims

1. A pixel circuit, characterized in that: include: Driving sub-circuit and light-emitting unit, The driving subcircuit includes a driving transistor electrically connected between a first power signal terminal and a second power signal terminal, and configured to generate a driving current from the first power signal terminal to the second power signal terminal via the light emitting unit, Wherein, the driving transistor is a dual-gate or multi-gate transistor.

2. The pixel circuit according to claim 1, characterized in that: The driving transistor includes: a first electrode, a second electrode and a control electrode, the first electrode is electrically connected to the first power signal terminal, the second electrode is electrically connected to the first electrode of the light emitting unit, and the control electrode is electrically connected to the first node. The driving transistor includes: an active region formed on a substrate, the control electrode, and a first electrode and a second electrode. The active region is electrically connected between the first pole and the second pole and includes at least two channels connected in series, The control electrode comprises: at least two sub-control electrodes corresponding to the channels one by one, the at least two sub-control electrodes are electrically connected to a first node, and the orthographic projections of the sub-control electrodes on the substrate cover the orthographic projections of the corresponding channels on the substrate.

3. The pixel circuit according to claim 2, characterized in that: At least two of the at least two channels connected in series have different channel width-to-length ratios.

4. The pixel circuit according to claim 2, characterized in that: The driving sub-circuit further includes: a first capacitor electrically connected to an intermediate node between two adjacent channels, The first electrode of the first capacitor is arranged in the active region between the two adjacent channels, the second electrode is arranged in the first metal layer, and the second electrode is connected to the first control signal, or The first electrode of the first capacitor is arranged in the first metal layer, the second electrode is arranged in the second metal layer, the first electrode is electrically connected to the middle node between the two adjacent channels, and the second electrode is connected to the first control signal.

5. The pixel circuit according to claim 4, characterized in that: The orthographic projection of the second electrode of the first capacitor on the substrate does not overlap with the orthographic projection of the control electrode on the substrate, and / or The pixel circuit further includes: a first reset subcircuit, the first reset subcircuit is electrically connected to the first reset signal terminal, the first reset control terminal, and the first electrode or the second electrode of the driving transistor, and is configured to transmit the first reset signal of the first reset signal terminal to the first electrode or the second electrode of the driving transistor based on the signal of the first reset control terminal, The second electrode of the first capacitor is electrically connected to the first reset signal terminal.

6. The pixel circuit according to claim 2, characterized in that: The driving transistor comprises: an auxiliary control electrode, the active region, the control electrode, a first electrode and a second electrode which are sequentially stacked on the substrate. The auxiliary control electrode includes: auxiliary sub-control electrodes arranged in a one-to-one correspondence with the sub-control electrodes, the orthographic projection of the auxiliary sub-control electrode on the substrate at least partially covers the orthographic projection of the corresponding sub-control electrode on the substrate, and each of the auxiliary sub-control electrodes is connected to the corresponding auxiliary control signal.

7. The pixel circuit according to claim 2, characterized in that: The driving transistor comprises: an auxiliary control electrode, the active region, the control electrode, a first electrode and a second electrode which are sequentially stacked on the substrate. The orthographic projection of the auxiliary control electrode on the substrate at least partially overlaps with the orthographic projection of each sub-control electrode in the control electrode on the substrate, and the auxiliary sub-control electrode is connected to the auxiliary control signal.

8. The pixel circuit according to claim 6 or 7, characterized in that: The auxiliary control signal is a DC voltage signal. When the driving transistor is a P-type transistor, the potential of the auxiliary control signal is greater than the threshold voltage of the corresponding driving transistor part, When the driving transistor is an N-type transistor, the potential of the auxiliary control signal is less than the threshold voltage of the corresponding driving transistor part.

9. The pixel circuit according to claim 6, characterized in that: The thicknesses of the at least two auxiliary sub-control electrodes in a direction perpendicular to the substrate are different.

10. The pixel circuit according to claim 1, characterized in that: Also includes: Write the subcircuit, The driving transistor includes a first electrode, a second electrode and a control electrode, the first electrode is electrically connected to the first power signal terminal, the second electrode is electrically connected to the first electrode of the light emitting unit, and the control electrode is electrically connected to the first node. The write subcircuit is electrically connected to the first electrode, the write control terminal and the write signal terminal of the drive transistor, and is configured to transmit the signal of the write signal terminal to the first electrode of the drive transistor based on the signal of the write control terminal, or The write subcircuit is electrically connected to the first node, a write control terminal and a write signal terminal, and is configured to transmit a signal from the write signal terminal to the first node based on a signal from the write control terminal.

11. The pixel circuit according to claim 1, characterized in that: Also includes: The second reset subcircuit, The second reset subcircuit is electrically connected to the control electrode of the driving transistor, a second reset control terminal and a second reset signal terminal, and is configured to transmit a second reset signal from the second reset signal terminal to the control electrode based on a signal from the second reset control terminal.

12. A display panel, characterized in that: include: The pixel circuit according to any one of claims 1 to 11.

13. A display device, characterized in that: Includes the display panel as claimed in claim 12.

Images