Display device

Abstract

A display device according to an exemplary embodiment of the present disclosure includes a plurality of sub-pixels; a plurality of sub-pixel circuits disposed in the plurality of sub-pixels, respectively, and each of the plurality of sub-pixel circuits includes a driving transistor; and a plurality of constant voltage lines connected to each of the plurality of sub-pixel circuits, in which a gate of the driving transistor overlaps at least one of the plurality of constant voltage lines.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0181086, filed with the Korean Intellectual Property Office on December 13, 2023, the disclosure of which is incorporated herein by reference. Technical field

[0003] This specification relates to a display device, and more particularly, to a display device having improved display quality. Background art

[0004] With the advancement of technology in modern society, display devices are used to provide information to users in various ways. Display devices can be included in electronic display panels that simply transmit visual information in one direction, and are also included in various high - tech electronic devices that recognize user input and provide information in response to the recognized input.

[0005] As representative display devices, there can be liquid crystal display (LCD) devices, field emission display (FED) devices, electro - wetting display (EWD) devices, organic light - emitting display (OLED) devices, etc.

[0006] Among the above - mentioned display devices, an organic light - emitting display device is a display device that emits light by itself. Different from liquid crystal display devices, an organic light - emitting display device does not require a separate light source, and thus can be manufactured as a light and thin display device. In addition, since an organic light - emitting display device operates at a low voltage, it is advantageous in terms of power consumption. Additionally, since an organic light - emitting display device is also excellent in terms of color, response speed, viewing angle, and contrast ratio (CR), it is expected to be adopted in various fields. Summary of the invention

[0007] One object to be achieved by this specification is to provide a display device capable of optimizing a manufacturing process.

[0008] Another object to be achieved by this specification is to provide a display device capable of improving image quality.

[0009] The objects of the present disclosure are not limited to the above - mentioned objects, and other objects not mentioned above can be clearly understood by those of ordinary skill in the art from the following description.

[0010] A display device according to an exemplary embodiment of the present disclosure includes: a plurality of sub - pixels; a plurality of sub - pixel circuits respectively disposed in the plurality of sub - pixels, and each of the plurality of sub - pixel circuits includes a driving transistor; and a plurality of constant - voltage lines connected to each of the plurality of sub - pixel circuits, wherein a gate of the driving transistor overlaps at least one of the plurality of constant - voltage lines.

[0011] A display device according to another exemplary embodiment of the present disclosure includes a substrate on which a plurality of sub-pixels are defined, driving transistors respectively disposed in the plurality of sub-pixels on the substrate, a first constant voltage line connected to each of the plurality of sub-pixels and to which a first constant voltage is applied, and a second constant voltage line connected to each of the plurality of sub-pixels and to which a second constant voltage is applied, wherein a gate of the driving transistor overlaps at least one of the first constant voltage line and the second constant voltage line.

[0012] A display device according to still another exemplary embodiment of the present disclosure includes: a plurality of sub-pixels; a plurality of sub-pixel circuits respectively disposed in the plurality of sub-pixels, wherein each of the plurality of sub-pixel circuits includes: a driving transistor; a storage capacitor connected to the driving transistor; and at least one auxiliary capacitor disposed between the storage capacitor and a reference voltage line or a high-potential voltage line.

[0013] Other details of the exemplary embodiments are included in the detailed description and the drawings.

[0014] According to the present specification, by not including a metal layer and thus not including a masking process, the manufacturing process can be optimized.

[0015] According to the present specification, by minimizing the threshold voltage compensation error rate and the luminance deviation in the voltage compensation driving method, the display quality of the display device can be improved.

[0016] According to the present specification, the capacitor capacitance can be increased by using a conductive pattern connected to a constant voltage line.

[0017] The effects according to the present disclosure are not limited to the above-exemplified contents, and more various effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a functional block diagram of a display device according to an embodiment of the present specification;

[0020] Figure 2 is a functional block diagram of a gate driving circuit of a display device according to an embodiment of the present specification;

[0021] Figure 3 is a cross-sectional view showing a display area of a display device according to an embodiment of the present specification;

[0022] Figure 4 is a cross-sectional view showing a display area and a non-display area of a display device according to an embodiment of the present specification;

[0023] Figure 5 is a view showing an example of a sub-pixel circuit of a display device according to an embodiment of the present specification;

[0024] Figure 6 is a top view of a display device according to an embodiment of the present specification;

[0025] Figure 7 is along Figure 6 a cross-sectional view taken along line V-V' in

[0026] Figure 8 is a cross-sectional view of a display device according to another embodiment of the present specification;

[0027] Figure 9 is a top view of a display device according to still another embodiment of the present specification;

[0028] Figure 10 is along Figure 9 a cross-sectional view taken along line VIII-VIII' in

[0029] Figure 11 is a view showing an example of a sub-pixel circuit of a display device according to yet another embodiment of the present specification;

[0030] Figure 12 is a top view of a display device according to yet another embodiment of the present specification;

[0031] Figure 13 is along Figure 12 a cross-sectional view taken along line XI-XI' in

[0032] Figure 14 is a top view of a display device according to still yet another embodiment of the present specification;

[0033] Figure 15 is along Figure 14 a cross-sectional view taken along line XIII-XIII' in

[0034] Figure 16 is a view showing an example of a sub-pixel circuit of a display device according to still another embodiment of the present specification;

[0035] Figure 17 is a top view of a display device according to still another embodiment of the present specification;

[0036] Figure 18 is along Figure 17 a cross-sectional view taken along line XVI-XVI' in

[0037] Figure 19 is a top view of a display device according to still another embodiment of the present specification;

[0038] Figure 20 is taken along Figure 19 the line XVIII-XVIII' in the [figure]. DETAILED DESCRIPTION

[0039] The advantages and features of the present disclosure, and the method of achieving the advantages and features, will become clear by reference to the exemplary embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those of ordinary skill in the art can fully understand the disclosure content and the scope of the present disclosure. Therefore, the present disclosure will be defined only by the scope of the appended claims.

[0040] The shapes, sizes, ratios, angles, quantities, etc. illustrated in the drawings used to describe the exemplary embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. The same reference numerals generally denote the same elements throughout the specification. Additionally, in the following description of the present disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "comprising," "having," and "including" used herein generally intend to allow the addition of other components, unless the term is used together with the term "only." Any reference to the singular may include the plural, unless otherwise explicitly stated.

[0041] When describing the components of the exemplary embodiments of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are used to distinguish one component from another, but the nature, order, or quantity of the components is not limited by the terms. When one component is "linked," "coupled," or "connected" to another component, the component may be directly linked or connected to the other component. However, unless otherwise specified, it should be understood that a third component may be interposed between the above components that can be indirectly linked or connected.

[0042] When using terms such as "above," "over," "below," and "adjacent" to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless the term is used together with the term "immediately" or "directly."

[0043] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.

[0044] The features of the various embodiments of the present disclosure can be combined or combined partially or wholly with each other, and can be associated and operated in various ways technically, and the embodiments can be implemented independently of each other or in association with each other.

[0045] Embodiments of the organic light emitting display device will be described in detail below. However, the embodiments of the present specification are not limited to the organic light emitting display device and can be applied to various electroluminescent display devices. For example, the electroluminescent display device can use an organic light emitting diode (OLED) display device, a quantum dot light emitting diode display device, or an inorganic light emitting diode display device.

[0046] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0047] Figure 1 is a functional block diagram of a display device according to an embodiment of the present specification. Figure 2 is a functional block diagram of a gate driving circuit of a display device according to an embodiment of the present specification.

[0048] The electroluminescent display device according to an embodiment of the present specification can be applied as the display device 100. An organic light emitting diode display device, a quantum dot light emitting diode display device, or an inorganic light emitting diode display device can be used as the electroluminescent display device.

[0049] Referring to Figure 1 , the display device 100 may include a display panel PN including sub-pixels PXL, a data driving circuit DD, a gate driving circuit GD, and a timing controller TC.

[0050] The display panel PN may create an image to be provided to the user. For example, the display panel PN may create and display an image to be provided to the user through pixels provided with a plurality of sub-pixels PXL.

[0051] The data driving circuit DD, the gate driving circuit GD, and the timing controller TC may provide signals for operating the sub-pixels PXL through signal lines. For example, the signal lines may include data lines DL and gate lines GL.

[0052] The data lines DL may include a plurality of lines arranged in a column direction and connected to the sub-pixels PXL provided in a column direction. The gate lines GL may include a plurality of lines arranged in a row direction and connected to the sub-pixels PXL provided in a row direction.

[0053] In some examples, the display device 100 may further include a power supply unit. In this case, a power supply voltage for operating the sub-pixels PXL may be provided by connecting a power line of the power supply unit to the display panel PN. For example, the power supply unit may supply a high potential voltage Vdd, a low potential voltage Vss, and a reference voltage Vref to the sub-pixels PXL. Each of the high potential voltage Vdd, the low potential voltage Vss, and the reference voltage Vref may be a constant voltage of a predetermined level. In addition, the power supply unit may supply a power supply voltage to the data driving circuit DD and the gate driving circuit GD. The data driving circuit DD and the gate driving circuit GD may operate based on the power supply voltage provided from the power supply unit.

[0054] For example, the data driving circuit DD may apply a data voltage to the sub-pixels PXL through the data lines DL, the gate driving circuit GD may apply a gate signal to the sub-pixels PXL through the gate lines GL, and the power supply unit may supply a power supply voltage to the sub-pixels PXL through the power lines.

[0055] The timing controller TC may control the data driving circuit DD and the gate driving circuit GD. For example, the timing controller re-adjusts the digital video data RGB input from the outside to match the resolution of the display panel PN, and supplies the digital video data RGB to the data driving circuit DD. In addition, the timing controller TC may generate a data control signal DDC for controlling the operation timing of the data driving circuit DD and a gate control signal GDC for controlling the operation timing of the gate driving circuit GD based on timing signals (e.g., a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE).

[0056] The data driving circuit DD may convert the digital video data input from the timing controller TC into an analog data voltage based on the data control signal DDC, and supply the analog data voltage to the plurality of data lines DL.

[0057] The gate driving circuit GD may generate scan signals Scan1 and Scan2 and a light emission signal (or a light emission control signal) EM based on the gate control signal GDC, and supply the scan signals Scan1 and Scan2 and the light emission signal (or the light emission control signal) EM to the plurality of gate lines GL.

[0058] According to an embodiment, the gate driving circuit GD may be disposed on the display panel PN in an in-panel-gate-driver (GIP) manner. For example, the gate driving circuit GD may be divided into a plurality of gate drivers and respectively disposed on at least two side surfaces of the display panel PN.

[0059] The display panel PN may include a display area AA and a non-display area NA configured to surround the display area AA.

[0060] The display area AA of the display panel PN may include a plurality of sub-pixels PXL arranged in a row direction and a column direction. The sub-pixels PXL may be arranged in an area where a plurality of data lines DL and a plurality of gate lines GL cross each other.

[0061] One pixel may include a plurality of sub-pixels that emit light beams of different colors. For example, a pixel may be implemented with three sub-pixels PXL for blue, red, and green. However, this specification is not limited thereto. In some instances, a pixel may further include a sub-pixel PXL for further implementing a specific color (e.g., white).

[0062] In the sub-pixel PXL, the area for implementing blue may be referred to as a blue sub-pixel, the area for implementing red may be referred to as a red sub-pixel, and the area for implementing green may be referred to as a green sub-pixel.

[0063] The non-display area NA may be arranged along the periphery of the display area AA. Various components for operating the plurality of sub-pixels PXL may be arranged in the non-display area NA. For example, at least a part of the gate driving circuit GD may be arranged in the non-display area NA. The non-display area NA may be referred to as a border area.

[0064] Referring to Figure 2 , the gate driving circuit GD includes a plurality of stages STG1 to STGn arranged at opposite sides of the display area AA and symmetrically arranged in the non-display area NA.

[0065] The plurality of stages STG1 to STGn respectively include first scan driving parts SC1(1) to SC1(n), second scan driving parts SC2(1) to SC2(n), and light emitting driving parts EM1(1) to EM1(n). The plurality of stages STG1 to STGn may be arranged in the order of the second scan driving parts SC2(1) to SC2(n), the first scan driving parts SC1(1) to SC1(n), and the light emitting driving parts EM1(1) to EM1(n) starting from a position adjacent to the display area AA. However, this specification is not limited thereto. The plurality of stages may be changed according to the design.

[0066] The first scan driving parts SC1(1) to SC1(n) may output a first scan signal Scan1 in response to a gate control signal GDC from the timing controller TC.

[0067] The second scan driving parts SC2(1) to SC2(n) may output a second scan signal Scan2 in response to a gate control signal GDC from the timing controller TC.

[0068] The light-emitting driving units EM1(1) to EM1(n) may output a light-emitting signal EM in response to a gate control signal GDC from a timing controller TC. Figure 3 It is a cross-sectional view of a display device according to an embodiment of the present specification. Figure 4 It is a cross-sectional view showing a display area and a non-display area of a display device according to an embodiment of the present specification.

[0069] For ease of description, Figure 3 and Figure 4 only the substrate 101, the third transistor T3, the storage capacitor Cst, the buffer layer 102, the gate insulating layer 103, the interlayer insulating layers 104 and 105, the passivation layer 106, the outer coating layer 107, the light-emitting element 110, the bank layer 108, the encapsulation part 120, and the touch part 130 are shown.

[0070] Referring to Figure 3 and Figure 4 , the display device 100 according to an embodiment of the present specification includes a substrate 101, a third transistor T3, a storage capacitor Cst, a gate insulating layer 103, interlayer insulating layers 104 and 105, an outer coating layer 107, a light-emitting element 110, a bank layer 108, an encapsulation part 120, and a touch part 130.

[0071] The substrate 101 may support various components of the display device 100. The substrate 101 may be made of a flexible plastic material. When the substrate 101 is made of a plastic material, the substrate 110 may be made of polyimide (PI), for example. When the substrate 101 is made of polyimide (PI), moisture components penetrate the substrate 101 made of polyimide (PI) and penetrate into the third transistor T3 or the light-emitting element 110, which may reduce the performance of the display device 100.

[0072] The display device 100 according to an embodiment of the present specification may include two polyimide (PI) layers to suppress a reduction in the performance of the display device 100 caused by moisture penetration. In addition, an inorganic layer is formed between the two polyimide (PI) layers, which may suppress moisture components from penetrating the polyimide (PI) layer provided on the lower side, thereby improving the performance and reliability of the product.

[0073] In addition, in the case where an inorganic layer is formed between two polyimide (PI) layers, the generation of charged charges in the lower polyimide (PI) layer may affect the reverse bias voltage of the transistor T3. Therefore, it is necessary to form a separate metal layer to block the charged charges in the polyimide (PI) layer. However, in the display device 100 according to the embodiment of the present specification, an inorganic layer is formed between two polyimide (PI) layers, which may block the charged charges in the lower polyimide (PI) layer, thereby improving the reliability of the product. In addition, since the process of forming a metal layer for blocking the charged charges in the polyimide (PI) layer can be excluded, the process can be simplified and the production cost can be reduced.

[0074] For example, the substrate 101 of the display device 100 may include a first plastic substrate 101a, a second plastic substrate 101c, and an inorganic layer 101b formed between the first plastic substrate 101a and the second plastic substrate 101c. The first plastic substrate 101a may be referred to as a first organic layer, and the second plastic substrate 101c may be referred to as a second organic layer. When the first plastic substrate 101a is charged, the inorganic layer 101b may function to inhibit the charges from affecting the transistor T3 through the second plastic substrate 101c. In addition, the inorganic layer 101b formed between the first plastic substrate 101a and the second plastic substrate 101c may be used to inhibit the penetration of moisture components into the first plastic substrate 101b. The inorganic layer 101b may be configured as a single layer or multiple layers made of silicon nitride (SiN x ) or silicon oxide (SiO x ). However, the present specification is not limited thereto.

[0075] The buffer layer 102 may be provided on the substrate 101. The buffer layer 102 may be formed on the entire surface of the substrate 101. The buffer layer 102 may be configured as a single layer or multiple layers made of silicon nitride (SiN x ) or silicon oxide (SiO x ). The buffer layer 102 may function to increase the bonding force between the substrate 101 and the layer formed on the buffer layer 102 and prevent the leakage of alkaline materials from the substrate 101. In addition, the buffer layer 102 is not an essential component. The buffer layer 102 may be omitted according to the type and material of the substrate 101, the structure and type of the transistor, etc.

[0076] The third transistor T3 may be provided on the buffer layer 102. The third transistor T3 may include a third active layer ACT3, a third gate GE3, a third source SE3, and a third drain DE3. The third active layer ACT3 of the third transistor T3 may be provided on the buffer layer 102.

[0077] The third active layer ACT3 can be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but the present specification is not limited thereto.

[0078] The gate insulating layer 103 can be disposed on the third active layer ACT3 of the third transistor T3. The gate insulating layer 103 can be a single layer made of silicon nitride (SiN x ) or silicon oxide (SiO x ) or a multi-layer including the above layers. Contact holes for connecting the third source SE3 and the third drain DE3 of the third transistor T3 to the third active layer ACT3 of the third transistor T3 can be formed in the gate insulating layer 103.

[0079] The third gate GE3 of the third transistor T3 can be disposed on the gate insulating layer 103. The third gate GE3 can be configured as a single layer or a multi-layer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and their alloys. The third gate GE3 can be formed on the gate insulating layer 103 and overlap with the third active layer ACT3 of the third transistor T3.

[0080] The first interlayer insulating layer 104 can be disposed on the gate insulating layer 103 and the third gate GE3. The first interlayer insulating layer 104 can be a single layer made of silicon nitride (SiN x ) or silicon oxide (SiO x ) or a multi-layer including the above layers. Contact holes for exposing the third active layer ACT3 of the third transistor T3 can be formed in the first interlayer insulating layer 104.

[0081] The second interlayer insulating layer 105 can be disposed on the first interlayer insulating layer 104. Contact holes for exposing the third active layer ACT3 of the third transistor T3 can be formed in the second interlayer insulating layer 105. The second interlayer insulating layer 105 can be a single layer made of silicon nitride (SiN x ) or silicon oxide (SiO x ) or a multi-layer including the above layers.

[0082] The third source SE3 and the third drain DE3 of the third transistor T3 can be disposed on the second interlayer insulating layer 105.

[0083] The third source SE3 and the third drain DE3 of the third transistor T3 can be connected to the third active layer ACT3 of the third transistor T3 through contact holes formed in the gate insulating layer 103, the first interlayer insulating layer 104, and the second interlayer insulating layer 105. Therefore, the third source SE3 of the third transistor T3 can be connected to the third active layer ACT3 through contact holes formed in the gate insulating layer 103, the first interlayer insulating layer 104, and the second interlayer insulating layer 105. Additionally, the third drain DE3 of the third transistor T3 can be connected to the third active layer ACT3 through contact holes formed in the gate insulating layer 103, the first interlayer insulating layer 104, and the second interlayer insulating layer 105.

[0084] Although Figure 3 not shown in the figure, the active layer ACT, the gate GE, the source SE, and the drain DE of the driving transistor DT are respectively located on the same layers as the third active layer ACT3, the third gate GE3, the third source SE3, and the third drain DE3 of the third transistor T3. That is, the gate insulating layer 103 is disposed between the active layer ACT of the driving transistor DT and the gate GE of the driving transistor DT, and the first interlayer insulating layer 104 is disposed between the gate GE of the driving transistor DT and the source SE and the drain DE of the driving transistor DT.

[0085] The storage capacitor Cst can include a first capacitor electrode Cst1 and a second capacitor electrode Cst2.

[0086] The first capacitor electrode Cst1 can be disposed on the gate insulating layer 103. The first capacitor electrode Cst1 can be configured as a single layer or a multi-layer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and their alloys. The first capacitor electrode Cst1 can be made of the same material as the third gate GE3. However, this specification is not limited thereto.

[0087] The second capacitor electrode Cst2 can be disposed on the first interlayer insulating layer 104. The second capacitor electrode Cst2 can be disposed on the first interlayer insulating layer 104 and overlap with the first capacitor electrode Cst1. For example, the second capacitor electrode Cst2 can be configured as a single layer or a multi-layer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and their alloys.

[0088] The passivation layer 106 can be disposed on the third source SE3 and the third drain DE3 of the third transistor T3 and the second interlayer insulating layer 105. The passivation layer 106 can be an insulating layer for protecting the elements disposed below the passivation layer 106. The passivation layer 106 can be made of silicon nitride (SiNx ) or a single layer made of silicon oxide (SiO x ) or a multi-layer including the above layers.

[0089] The outer coating 107 may be provided on the passivation layer 106. The outer coating 107 may be a planarization layer for reducing the level difference of the underlying structure and may be made of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide-based resin, a polyimide-based resin, an unsaturated polyester-based resin, a polyphenyl resin, a polyphenylene sulfide-based resin, a benzocyclobutene, or a photoresist. However, the present specification is not limited thereto.

[0090] The light-emitting element 110 may be provided on the outer coating 107. The light-emitting element 110 may include a first electrode 111, a light-emitting structure 112, and a second electrode 113.

[0091] The first electrode 111 may be provided on the outer coating 107.

[0092] The first electrode 111 may be an anode and may be electrically connected to the third drain DE3 of the third transistor T3 through a contact hole.

[0093] Since the display device 100 according to an embodiment of the present specification is a top-emitting display device, the first electrode 111 may have a multi-layer structure including a transparent conductive layer and a reflective layer having a high reflection efficiency. The transparent conductive layer may be made of a material such as indium tin oxide (ITO) or indium zinc oxide (IZO) having a relatively large work function value. Additionally, the opaque conductive layer may have a single-layer structure or a multi-layer structure made of aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or an alloy thereof. For example, the first electrode 111 may have a structure in which a transparent conductive layer, an opaque conductive layer, and a transparent conductive layer are sequentially stacked. However, the present specification is not limited thereto. The first electrode may have a structure in which a transparent conductive layer and an opaque conductive layer are sequentially stacked.

[0094] The bank layer 108 may be provided on the first electrode 111 and the outer coating 107.

[0095] The bank layer 108 may have an opening for exposing the first electrode 111. Since the bank layer 108 may define the light-emitting area of the display device 100, the bank layer 108 may be referred to as a pixel defining layer. The bank layer 108 may be made of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide-based resin, a polyimide-based resin, an unsaturated polyester-based resin, a polyphenyl resin, a polyphenylene sulfide-based resin, a benzocyclobutene, or a photoresist. However, the present specification is not limited thereto.

[0096] The spacer 109 may be further provided on the bank layer 108.

[0097] The spacer 109 can function to support the mask when the mask is aligned on the bank layer 108 during the deposition of the first electrode 111. The spacer 109 can be integral with the bank layer 108. The spacer 109 can be made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide-based resin, polyimide-based resin, unsaturated polyester-based resin, polyphenyl-based resin, polyphenylene sulfide-based resin, benzocyclobutene, or photoresist. However, the present specification is not limited thereto.

[0098] The light-emitting structure 112 can be disposed on the first electrode 111. The light-emitting structure 112 can include a material capable of emitting light of a specific color. For example, the light-emitting structure 112 can include a light-emitting material capable of emitting any one of red light, green light, and blue light. Specifically, the light-emitting structure 112 can include at least one of a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (emission layer (EML)), an electron transport layer (ETL), and an electron injection layer (EIL). Depending on the structure or properties of the display device 100, some components of the light-emitting structure 112 may not be included.

[0099] The second electrode 113 can be further disposed on the light-emitting structure 112. The second electrode 113 can be a cathode and is disposed on the light-emitting structure 112 so as to face the first electrode 111 with the light-emitting structure 112 interposed therebetween. The second electrode 113 supplies electrons to the light-emitting structure 112. For example, the second electrode 113 can be made of a conductive material having a low work function. In the case where the display device 100 is a top-emitting display device, the second electrode 113 can be made of a transparent conductive oxide such as indium tin oxide or indium zinc oxide or a transparent conductive material such as ytterbium (Yb). However, the present specification is not limited thereto.

[0100] The encapsulation part 120 for suppressing moisture penetration can be further disposed on the second electrode 113.

[0101] The encapsulation part 120 can include a first encapsulation layer 121, a second encapsulation layer 122, and a third encapsulation layer 123.

[0102] The first encapsulation layer 121 can be disposed on the second electrode 113. The first encapsulation layer 121 can be made of a transparent inorganic material having an excellent effect of blocking moisture from penetrating into the light-emitting element 130 and can be deposited at a low temperature. For example, the first encapsulation layer 121 can be made of an inorganic material such as silicon nitride (SiN x ) or silicon oxide (SiO x ). However, the present specification is not limited thereto.

[0103] The second encapsulation layer 122 may be disposed on the first encapsulation layer 121. The second encapsulation layer 122 is an organic layer capable of compensating for the level difference caused by foreign substances by covering the foreign substances that may be generated in the manufacturing process. Foreign substances generated in the manufacturing process may cause defects in the light-emitting element 110 or break the inorganic layer (such as the first encapsulation layer 121 or the third encapsulation layer 123). Therefore, the second encapsulation layer 122 can function to cover the breakage caused by foreign substances or compensate for the level difference caused by foreign substances. In addition, the second encapsulation layer 122 can also function to flatten the surface on the light-emitting element 110. The second encapsulation layer 122 may be made of an organic material. For example, the second encapsulation layer 122 may be made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide-based resin, polyimide-based resin, unsaturated polyester-based resin, polyphenyl-based resin, polyphenylene sulfide-based resin, benzocyclobutene, or photoresist. However, this specification is not limited thereto.

[0104] The third encapsulation layer 123 may be disposed on the second encapsulation layer 122. The third encapsulation layer 123 may be made of a transparent inorganic material having an excellent effect of blocking moisture from penetrating into the light-emitting element 130 and may be deposited at a low temperature. For example, the third encapsulation layer 123 may be made of an inorganic material such as silicon nitride (SiN x ) or silicon oxide (SiO x ). However, this specification is not limited thereto.

[0105] The touch portion 130 may be disposed on the third encapsulation layer 123. The touch portion 130 may include a touch buffer layer 131, a bridge portion 132, a touch interlayer insulating layer 133, a first touch electrode 134, a second touch electrode 135, and a protective layer 136.

[0106] The touch buffer layer 131 may be a buffer layer located at the lowermost part of the touch portion 130 and made of an inorganic material. For example, the touch buffer layer may be configured as a single layer or multiple layers made of silicon nitride (SiN x ) or silicon oxide (SiO x ). The touch buffer layer 131 can improve the bonding force between the third encapsulation layer 123 and the layer formed on the touch buffer layer 131.

[0107] The bridge portion 132 may be disposed on the touch buffer layer 131. The bridge portion 132 can electrically connect a plurality of adjacent first touch electrodes 134 to each other. The bridge portion 132 may be made of a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or an alloy thereof.

[0108] The touch interlayer insulating layer 133 may be disposed on the touch buffer layer 131 and the bridge portion 132. The touch interlayer insulating layer 133 may be made of an inorganic material such as silicon nitride (SiN x ) or silicon oxide (SiO x ). However, the present specification is not limited thereto.

[0109] The first touch electrode 134 and the second touch electrode 135 may be disposed on the touch interlayer insulating layer 133. Although not illustrated in the drawings, the first touch electrode 134 may be arranged in a first direction in a plan view, and the second touch electrode 135 may be arranged in a second direction that is a different direction from the first direction.

[0110] The first touch electrode 134 may be electrically connected to the bridge portion 132 through a contact hole formed in the touch interlayer insulating layer 133. Accordingly, a plurality of first touch electrodes 134 arranged in the first direction may be electrically connected to each other through the bridge portion 132.

[0111] In addition, although not illustrated in the drawings, a connection pattern may be formed on the touch interlayer insulating layer 133 such that a plurality of second touch electrodes 135 arranged in a second direction different from the first direction may be electrically connected to each other.

[0112] The protective layer 136 may be disposed on the first touch electrode 134, the second touch electrode 135, and the touch interlayer insulating layer 133. The protective layer 136 may be made of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide-based resin, a polyimide-based resin, an unsaturated polyester-based resin, a polyphenyl-based resin, a polyphenylene sulfide-based resin, benzocyclobutene, or a photoresist. However, the present specification is not limited thereto.

[0113] The touch portion 130 may further include a plurality of touch routing lines 137. The first touch electrode 134 and the second touch electrode 135 may be electrically connected to a touch driving unit that operates the touch portion 130 through the touch routing lines 137.

[0114] Referring to Figure 4 , the auxiliary metal layer VSSL may be disposed on the gate insulating layer 103 in the non-display area NA. The auxiliary metal layer VSSL that is disposed on the same layer and made of the same material as the metal layer in the display area AA may be disposed in the non-display area NA. The auxiliary metal layer VSSL may also serve as a line for supplying the low potential voltage VSS. The auxiliary metal layer VSSL may be disposed on the same layer and made of the same material as the third source SE3 and the third drain DE3 of the third transistor T3. However, the present specification is not limited thereto. The auxiliary metal layer may be disposed on the same layer and made of the same material as the third gate GE3.

[0115] The dam portion DAM can be disposed in the non-display area NA and suppress the collapse of the second encapsulation layer 122. That is to say, the dam portion DAM can function to suppress the organic material layer included in the encapsulation portion 120 from overflowing to the outer periphery. The dam portion DAM can be located at the boundary point between the display area AA and the non-display area NA or at any point in the non-display area NA. The dam portion DAM can be provided to surround the display area AA in all directions or only at the outer periphery of a part of the display area AA. Only one dam portion DAM can be provided, or two or more dam portions DAM can be provided. For example, the dam portion DAM includes a first dam portion DAM1, a second dam portion DAM2, and a third dam portion DAM3.

[0116] The first dam portion DAM1 can be disposed adjacent to the display area AA and surround the display area AA, and the first dam portion DAM1 can mainly block the flow of the second encapsulation layer 122 of the encapsulation portion 120. The second dam portion DAM2 can surround the outer periphery of the first dam portion DAM1, and the third dam portion DAM3 can surround the outer periphery of the second dam portion DAM2.

[0117] The first dam portion DAM1 and the second dam portion DAM2 can be disposed on the first interlayer insulating layer 104 and overlap with the auxiliary metal layer VSSL.

[0118] The first dam portion DAM1 and the second dam portion DAM2 can each be configured as a single layer or a multi-layer. For example, the first dam portion DAM1 can include a first layer DM1 of the first dam portion, a second layer DM2 of the first dam portion, and a third layer DM3 of the first dam portion. The second dam portion DAM2 can include a first layer DM2-1 of the second dam portion, a second layer DM2-2 of the second dam portion, and a third layer DM2-3 of the second dam portion. The first layer DM1 of the first dam portion and the first layer DM2-1 of the second dam portion can be disposed on the first interlayer insulating layer 104.

[0119] The first layer DM1 of the first dam portion and the first layer DM2-1 of the second dam portion can be formed by the same process as the outer coating 107 and made of the same material as the outer coating 107.

[0120] The second layer DM2 of the first dam portion can be disposed on the first layer DM1 of the first dam portion, and the second layer DM2-2 of the second dam portion can be disposed on the first layer DM2-1 of the second dam portion. The second layer DM2 of the first dam portion and the second layer DM2-2 of the second dam portion can be formed by the same process as the bank layer 108 and made of the same material as the bank layer 108.

[0121] The third layer DM3 of the first dam portion can be disposed on the second layer DM2 of the first dam portion, and the third layer DM2-3 of the second dam portion can be disposed on the second layer DM2-2 of the second dam portion. The third layer DM3 of the first dam portion and the third layer DM2-3 of the second dam portion can be formed by the same process as the spacer 109 and made of the same material as the spacer 109.

[0122] In the embodiments of the present specification, the display device 100 is illustrated as including two dam portions DAM1 and DAM2 each having three layers. However, the present specification is not limited thereto. For example, the dam portion DAM may have two layers or four or more layers.

[0123] The third dam portion DAM3 can be disposed to surround the second dam portion DAM and block the flow of the protective layer 136. The third dam portion DAM3 can be configured as a single layer or multiple layers. For example, the third dam portion DAM3 can be configured as a single layer. The third dam portion DAM3 can be formed by the same process as the outer coating 107 and made of the same material as the outer coating 107. The third dam portion DAM3 can be disposed at the outer periphery of the second dam portion DAM2 and cover the ends of the first interlayer insulating layer 104 and the second interlayer insulating layer 105. Since the ends of the first interlayer insulating layer 104 and the second interlayer insulating layer 105 are vulnerable to damage, the third dam portion DAM3 can suppress damage by covering the ends of the first interlayer insulating layer 104 and the second interlayer insulating layer 105. The crack suppression pattern CPP can be disposed at the outer periphery of the third dam portion DAM3. The crack suppression pattern CPP can be disposed to surround the outer periphery of the third dam portion DAM33. The crack suppression pattern CPP can include an opening CH formed through the third encapsulation layer 123. That is, the crack suppression pattern CPP can be formed by patterning the third encapsulation layer 123 to suppress the rupture of the encapsulation portion 120 and suppress the expansion of the crack toward the display area AA. The substrate 101 can be exposed to the outside through the opening CH.

[0124] Figure 5 is a view showing an example of a sub-pixel circuit of a display device according to an embodiment of the present specification.

[0125] Referring to Figure 5 , the sub-pixel circuit can include six transistors, a storage capacitor Cst, and a light-emitting element 110.

[0126] For example, the sub-pixel circuit can include a driving transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a storage capacitor Cst, and a light-emitting element 110. A sub-pixel circuit including six transistors and a storage capacitor can be referred to as a 6T1C pixel circuit. However, the present specification is not limited by this term.Figure 5 It is shown that the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are implemented as p-type transistors. However, this specification is not limited thereto. In the case of p-type transistors, the low-level voltage of each of the driving signals can represent the voltage that turns on the transistor, and the high-level voltage of each of the driving signals can represent the voltage that turns off the transistor.

[0127] The first electrode or the second electrode of the transistor to be described below can represent the source or the drain. However, the terms "first electrode" and "second electrode" are only terms for distinguishing electrodes, and the corresponding electrodes are not limited. In addition, for each electrode, the first electrode may not refer to the same electrode.

[0128] The high-potential voltage Vdd, the low-potential voltage Vss, the reference voltage Vref, and the data voltage Vdata can be supplied to the sub-pixel circuit. The high-potential voltage Vdd, the low-potential voltage Vss, and the reference voltage Vref can be DC voltages (or direct current voltages), and the data voltage Vdata can be an AC voltage (or alternating current voltage). However, this specification is not limited thereto.

[0129] The sub-pixel circuit can be connected to a high-potential voltage line for supplying the high-potential voltage Vdd, a low-potential voltage line for supplying the low-potential voltage Vss, a reference voltage line for supplying the reference voltage Vref, and a data line for supplying the data voltage Vdata. The high-potential voltage Vdd can be referred to as the first voltage, and the low-potential voltage Vss can be referred to as the second voltage, and the second voltage has a value smaller than the first voltage. However, this specification is not limited thereto.

[0130] The high-potential voltage Vdd can have a voltage value higher than the low-potential voltage Vss and the reference voltage Vref. The low-potential voltage Vss can be equal to or lower than the reference voltage Vref. The data voltage Vdata can have a voltage value within a specific range. For example, the data voltage Vdata can have a value between 0V (volts) and 10V (volts). However, this specification is not limited thereto.

[0131] The driving transistor DT can be a transistor for operating the light-emitting element 110 and controls the driving current applied to the light-emitting element 110 according to the source-gate voltage. The first electrode of the driving transistor DT can be connected to the high-potential voltage line. The second electrode of the driving transistor DT can be connected to the third node N3. The gate of the driving transistor DT can be connected to the second node N2. The driving transistor DT can be turned on or off in response to the voltage of the second node N2. When the driving transistor DT is turned on, the driving transistor DT can supply the high-potential voltage Vdd supplied by the high-potential voltage line to the third node N3.

[0132] The first transistor T1 can supply the data voltage Vdata from the data line providing the data voltage Vdata to the first node N1. The first electrode of the first transistor T1 can be connected to the data line. The second electrode of the first transistor T1 can be connected to the first node N1. For example, the second electrode of the first transistor T1 can be connected to the storage capacitor Cst and to the first electrode of the fifth transistor T5.

[0133] The gate of the first transistor T1 can be connected to the first scan line providing the first scan signal Scan1. The first transistor T1 can be turned on or off in response to the first scan signal Scan1. When the first transistor T1 is turned on, the first transistor T1 can be connected to the first node N1 and the data line. In this case, the data voltage Vdata is supplied to the first node N1 through the data line.

[0134] The second transistor T2 can connect the gate and the drain of the driving transistor DT in a diode configuration. The first electrode of the second transistor T2 can be connected to the second node N2. The first electrode of the second transistor T2 can be connected to the storage capacitor Cst and to the gate of the driving transistor DT. The second electrode of the second transistor T2 can be connected to the third node N3. The second electrode of the second transistor T2 can be connected to the first electrode of the third transistor T3 and to the second electrode of the driving transistor DT.

[0135] The gate of the second transistor T2 can be connected to the second scan line providing the second scan signal Scan2. The second transistor T2 can be turned on or off in response to the second scan signal Scan2. When the second transistor T2 is turned on, the second transistor T2 can connect the second node N2 and the third node N3.

[0136] The second transistor T2 can include a plurality of sub-transistors. In this case, the second transistor T2 can be referred to as a multi-transistor, a dual transistor, or a double transistor. Alternatively, the second transistor T2 can include a plurality of gates. In this case, the second transistor T2 can be referred to as a multi-gate transistor, a dual-gate transistor, or a double-gate transistor.

[0137] In the case where the second transistor T2 includes a plurality of sub-transistors or a plurality of gates, the amount of current leaking from the second transistor T2, such as the leakage current between the second node N2 and the reference voltage line, can be effectively reduced.

[0138] The third transistor T3 can define a current path between the driving transistor DT and the light-emitting element 110. The third transistor T3 can be connected between a third node N3 and a fourth node N4. The first electrode of the third transistor T3 can be connected to the third node N3. For example, the first electrode of the third transistor T3 can be connected to the second electrode of the second transistor T2 and the second electrode of the driving transistor DT. The second electrode of the third transistor T3 can be connected to the fourth node N4. For example, the second electrode of the third transistor T3 can be connected to the second electrode of the fourth transistor T4 and the light-emitting element 110.

[0139] The gate of the third transistor T3 can be connected to a light-emitting signal line that provides a light-emitting signal EM. The third transistor T3 can be turned on or off in response to the light-emitting signal EM provided through the light-emitting signal line. When the third transistor T3 is turned on, the third transistor T3 can define a current path between the driving transistor DT and the light-emitting element 110 by connecting the third node N3 and the fourth node N4.

[0140] The fourth transistor T4 can apply a reference voltage Vref to the first electrode of the light-emitting element 110. The fourth transistor T4 can be connected to a reference voltage line that supplies the reference voltage Vref, a fifth transistor T5, and the fourth node N4. The first electrode of the fourth transistor T4 can be connected to the fifth transistor T5 and the reference voltage line. For example, the first electrode of the fourth transistor T4 can be connected to the second electrode of the fifth transistor T5 and the reference voltage line. The second electrode of the fourth transistor T4 can be connected to the fourth node N4. The second electrode of the fourth transistor T4 can be connected to the third transistor T3 and the light-emitting element 110. For example, the second electrode of the fourth transistor T4 can be connected to the second electrode of the third transistor T3 and the first electrode of the light-emitting element 110.

[0141] The gate of the fourth transistor T4 can be connected to a second scan line that provides a second scan signal Scan2. The fourth transistor T4 can be turned on or off in response to the second scan signal Scan2 provided through the second scan line. When the fourth transistor T4 is turned on, the fourth transistor T4 can charge the reference voltage Vref into the fourth node N4 by connecting the fourth node N4 and the reference voltage line.

[0142] In the case where the fourth node N4 is charged with the reference voltage Vref as described above, even when the second transistor T2 is turned on, the effect of increasing the voltage of the electrode (e.g., the first electrode) of the fourth node N4 connected to the light-emitting element 110 can be reduced. As the increase in the voltage of the first electrode is reduced, the initial peak phenomenon in which the voltage increases excessively in the initial portion can be reduced. Since the initial peak is reduced, it is possible to suppress luminance non-uniformity, such as black dot phenomena at the edges and center of the display panel, and improve luminance uniformity.

[0143] The fifth transistor T5 can apply a reference voltage Vref to the first node N1. The first electrode of the fifth transistor T5 can be connected to the first node N1. For example, the first electrode of the fifth transistor T5 can be connected to the storage capacitor Cst and to the second electrode of the first transistor T1. The second electrode of the fifth transistor T5 can be connected to the fourth transistor T4 and to a reference voltage line that provides the reference voltage Vref. For example, the second electrode of the fifth transistor T5 can be connected to the first electrode of the fourth transistor T4 and to the reference voltage line.

[0144] The gate of the fifth transistor T5 can be connected to a light-emitting signal line that provides a light-emitting signal EM. The fifth transistor T5 can be turned on or off in response to the light-emitting signal EM input through the light-emitting signal line. When the fifth transistor T5 is turned on, the fifth transistor T5 can charge the reference voltage Vref into the first node N1 by connecting the first node N1 and the reference voltage line.

[0145] The light-emitting element 110 can be connected between the fourth node N4 and a low-potential voltage line that supplies a low-potential voltage Vss. For example, the first electrode of the light-emitting element 110 can be connected to the fourth node N4, and the second electrode of the light-emitting element 110 can be connected to the low-potential voltage line. The low-potential voltage Vss can be a voltage lower than the above-mentioned high-potential voltage Vdd. For example, the voltage supplied through the low-potential voltage line can include a ground voltage. The low-potential voltage Vss and the high-potential voltage Vdd can each be preset.

[0146] The storage capacitor Cst can be connected between the first node N1 and the second node N2. For example, the first capacitor electrode of the storage capacitor Cst can be connected to the second node N2 that is connected to the gate of the driving transistor DT. The second capacitor electrode of the storage capacitor Cst can be connected to the first node N1 that is connected to the first transistor T1 and the fifth transistor T5.

[0147] The storage capacitor Cst can be configured to charge electrical energy (e.g., charge or data voltage) to maintain a constant voltage for one frame. For example, when the input of the data voltage is stopped by the first transistor T1 during the operation of the sub-pixel circuit, the storage capacitor Cst supplies the stored data voltage to the driving transistor DT to maintain the operation of the driving transistor DT within one frame.

[0148] The sub-pixel circuit can further include an auxiliary capacitor Cgv. The auxiliary capacitor Cgv can be provided between the first capacitor electrode of the storage capacitor Cst and the reference voltage line that provides the reference voltage Vref. The auxiliary capacitor Cgv can suppress the voltage of the gate of the driving transistor DT from rising due to the backflow phenomenon.

[0149] Reference will be made to Figure 6 andFigure 7 Describe the auxiliary capacitor Cgv in more detail.

[0150] Figure 6 is a top view of a display device according to an embodiment of the present specification. Figure 6 Shows the plane of a sub-pixel. Figure 7 Is along Figure 6 The cross-sectional view taken along the line V-V' in. For ease of description, Figure 6 Only the data line DL, the first constant voltage line CVL1, the second constant voltage line CVL2, the first scan signal line SL1, the second scan signal line SL2, the emission signal line EML, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the driving transistor DT, and the storage capacitor Cst are shown. For ease of description, Figure 7 Only the substrate 101, the buffer layer 102, the gate insulating layer 103, the first interlayer insulating layer 104, the second interlayer insulating layer 105, the first constant voltage line CVL1, and the auxiliary capacitor Cgv are shown.

[0151] Referring to Figure 6 , the data line DL, the first constant voltage line CVL1, and the second constant voltage line CVL2 can be disposed in the sub-pixel and extend in the column direction. The data line DL, the first constant voltage line CVL1, and the second constant voltage line CVL2 can be spaced apart from each other and disposed parallel to each other. For example, the data line DL, the first constant voltage line CVL1, and the second constant voltage line CVL2 can be disposed in sequence from the left. The data line DL, the first constant voltage line CVL1, and the second constant voltage line CVL2 can be disposed on the same layer on the substrate 101 and made of the same material. For example, each of the data line DL, the first constant voltage line CVL1, and the second constant voltage line CVL2 can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present specification is not limited thereto.

[0152] The data line DL can extend in the column direction in the sub-pixel and transmit a data voltage Vdata. The data line DL can be electrically connected to the first transistor T1 and transmit the data voltage Vdata to the first transistor T1.

[0153] The first constant voltage line CVL1 can extend in the column direction in the sub-pixel and transmit a first constant voltage at a predetermined voltage level. For example, the first constant voltage line CVL1 can be a reference voltage line that transmits a reference voltage Vref to the sub-pixel. The first constant voltage line CVL1 can be electrically connected to the fourth transistor T4 and the fifth transistor T5 and transmit the reference voltage Vref to the fourth transistor T4 and the fifth transistor T5.

[0154] The second constant voltage line CVL2 can extend in the column direction in the sub-pixel and transmit a second constant voltage at a predetermined voltage level. For example, the second constant voltage line CVL2 can be a high-potential voltage line that transmits a high-potential voltage Vdd to the sub-pixel. The second constant voltage line CVL2 can be electrically connected to the driving transistor DT and transmit the high-potential voltage Vdd to the driving transistor DT.

[0155] Referring to Figure 6 , the first scan signal line SL1, the second scan signal line SL2, and the emission signal line EML can be provided in the sub-pixel and extend in the row direction. The first scan signal line SL1, the second scan signal line SL2, and the emission signal line EML can be spaced apart from each other and arranged parallel to each other. The first scan signal line SL1, the second scan signal line SL2, and the emission signal line EML can be provided on the same layer of the substrate 101 and made of the same material. For example, the first scan signal line SL1, the second scan signal line SL2, and the emission signal line EML can each be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, this specification is not limited thereto.

[0156] The first scan signal line SL1 can extend in the row direction in the sub-pixel and cross the data line DL, the first constant voltage line CVL1, and the second constant voltage line CVL2 that extend in the column direction. The first scan signal line SL1 can transmit a first scan signal Scan1 to the sub-pixel. A part of the first scan signal line SL1 can serve as the second gate GE1 of the first transistor T1.

[0157] The second scan signal line SL2 can extend in the row direction in the sub-pixel and cross the data line DL, the first constant voltage line CVL1, and the second constant voltage line CVL2 that extend in the column direction. The second scan signal line SL2 can transmit a second scan signal Scan2 to the sub-pixel. A part of the second scan signal line SL2 can serve as the second gate GE2 of the second transistor T2 and the fourth gate GE4 of the fourth transistor T4. Figure 6 It shows that two second scan signal lines SL2 are configured to provide the second scan signal Scan2. However, the present disclosure is not limited thereto. According to the design, one second scan signal line SL2 can be provided.

[0158] The emission signal line EML can extend in the row direction in the sub-pixel and cross the data line DL, the first constant voltage line CVL1, and the second constant voltage line CVL2 that extend in the column direction. The emission signal line EML can transmit an emission signal EM to the sub-pixel. A part of the emission signal line EML can serve as the third gate GE3 of the third transistor T3 and the fifth gate GE5 of the fifth transistor T5. Figure 6Two light-emitting signal lines EML are shown configured to provide a light-emitting signal EM. However, the present disclosure is not limited thereto. According to the design, one light-emitting signal line EML can be provided.

[0159] The first transistor T1 may include a first active layer ACT1, a first gate GE1, a first source SE1, and a first drain DE1. The first source SE1 may be electrically connected to the data line DL through a contact hole, and the first drain DE1 may be electrically connected to the storage capacitor Cst. The first gate GE1 may be a part of the first scan signal line SL1 overlapping with the first active layer ACT1.

[0160] The second transistor T2 may include a second active layer ACT2, a second gate GE2, a second source SE2, and a second drain DE2. The second source SE2 may be electrically connected to the gate GE of the driving transistor DT and the storage capacitor Cst, and the second drain DE2 may be electrically connected to the third source SE3 of the third transistor T3 and the drain DE of the driving transistor DT. The second gate GE2 may be a part of the second scan signal line SL2 overlapping with the second active layer ACT2.

[0161] The third transistor T3 may include a third active layer ACT3, a third gate GE3, a third source SE3, and a third drain DE3. The third source SE3 may be electrically connected to the second drain DE2 of the second transistor T2 and the drain DE of the driving transistor DT. For example, the third source SE3 may be integrated with the second drain DE2. The third drain DE3 may be electrically connected to the fourth drain DE4 of the fourth transistor T4. For example, the third drain DE3 may be integrated with the fourth drain DE4. The third gate GE3 may be a part of the light-emitting signal line EML overlapping with the third active layer ACT3.

[0162] The fourth transistor T4 may include a fourth active layer ACT4, a fourth gate GE4, a fourth source SE4, and a fourth drain DE4. The fourth source SE4 may be electrically connected to the first constant voltage line CVL1 through a contact hole. The fourth drain DE4 may be electrically connected to the third drain DE3 of the third transistor T3. For example, the fourth drain DE4 may be integrated with the third drain DE3. The fourth gate GE4 may be a part of the second scan signal line SL2 overlapping with the fourth active layer ACT4.

[0163] The fifth transistor T5 may include a fifth active layer ACT5, a fifth gate GE5, a fifth source SE5, and a fifth drain DE5. The fifth source SE5 may be electrically connected to the first constant voltage line CVL1 through a contact hole. The fifth drain DE5 may be electrically connected to the first drain DE1 of the first transistor T1. For example, the fifth drain DE5 may be integrated with the first drain DE1. The fifth gate GE5 may be a part of the light emitting signal line EML that overlaps with the fifth active layer ACT5.

[0164] The driving transistor DT may include an active layer ACT, a gate GE, a source SE, and a drain DE. The source SE may be electrically connected to the second constant voltage line CVL2 through a contact hole. The drain DE may be electrically connected to the second drain DE2 of the second transistor T2 and the third source SE3 of the third transistor T3. The gate GE may be a part of the first capacitor electrode Cst1 that overlaps with the active layer ACT.

[0165] The storage capacitor Cst may include a first capacitor electrode Cst1 and a second capacitor electrode Cst2 disposed on the first capacitor electrode Cst1 and configured to overlap with the first capacitor electrode Cst1. The first capacitor electrode Cst1 may be electrically connected to the gate GE of the driving transistor DT. For example, the first capacitor electrode Cst1 may be integrated with the gate GE. The second capacitor electrode Cst2 may be electrically connected to the first drain DE1 of the first transistor T1 and the fifth drain DE5 of the fifth transistor T5.

[0166] Refer to Figure 6 and Figure 7 As shown in FIGS. and, the gate GE of the driving transistor DT may overlap with the first constant voltage line CVL1. The gate GE of the driving transistor DT may extend and at least partially overlap with the first constant voltage line CVL1. For example, the gate GE of the driving transistor DT may overlap with the first constant voltage line CVL1 that provides a reference voltage Vref (i.e., a constant voltage). Therefore, an auxiliary capacitor Cgv may be formed between the first constant voltage line CVL1 that provides the first constant voltage and the gate GE of the driving transistor DT. For example, a first portion of the gate GE of the driving transistor DT may overlap with the active layer ACT of the driving transistor DT, and a second portion of the gate GE of the driving transistor DT may extend from the first portion in the direction of the first constant voltage line CVL1. That is, the first portion of the gate GE may overlap with the active layer ACT, and the second portion extending from the first portion in the direction of the first constant voltage line CVL1 may overlap with the first constant voltage line CVL1.

[0167] In a display device in the related art, a metal layer is disposed below an active layer of a driving transistor to suppress a situation in which a working defect occurs when the amount of current flowing through the active layer of the driving transistor decreases due to a charge flow on a substrate made of polyimide (PI). In this case, the metal layer is electrically connected to a source electrode of the driving transistor to suppress the floating of the metal layer. Accordingly, an auxiliary capacitor is formed between a gate electrode of the driving transistor and the metal layer, such that a problem in which the voltage of the gate electrode of the driving transistor increases due to a backflow phenomenon can be suppressed.

[0168] However, in the case where the metal layer is disposed below the active layer of the driving transistor, a separate process for forming the metal layer and a separate mask process for connecting the metal layer to the source electrode are required, which causes problems of increased manufacturing costs and a complicated manufacturing process.

[0169] For this reason, in the case where the metal layer disposed below the driving transistor is removed, the auxiliary capacitor formed by the metal layer can be removed. For this reason, there are problems in that the voltage of the gate electrode of the driving transistor increases due to a backflow phenomenon, the voltage leaks through a second transistor, threshold voltage compensation occurs at a lower voltage, the compensation error rate increases, and a brightness deviation of the display device occurs.

[0170] Accordingly, in the display device 100 according to an embodiment of the present specification, a gate electrode GE of a driving transistor DT and a first constant voltage line CVL1 that provides a first constant voltage are disposed to overlap each other, such that an auxiliary capacitor Cgv can be formed. Accordingly, in the display device 100 according to an embodiment of the present specification, a separate metal layer may not be included, and a mask process for forming the metal layer may not be included, such that manufacturing costs can be reduced and the manufacturing process can be optimized.

[0171] In addition, in the display device 100 according to an embodiment of the present specification, a gate electrode GE of a driving transistor DT and a first constant voltage line CVL1 that transmits a first constant voltage (e.g., a reference voltage Vref) are disposed to overlap each other, such that an auxiliary capacitor Cgv can be formed. Accordingly, in the display device 100 according to an embodiment of the present specification, even if a separate metal layer is not included, the auxiliary capacitor Cgv can be ensured. The threshold voltage compensation error rate of the driving transistor DT and the brightness deviation of the display device 100 can be minimized, which can improve the display quality.

[0172] Figure 8 is a cross-sectional view of a display device according to another embodiment of the present specification. Except for a substrate 201, Figure 8 the display device 200 in Figures 1 to 7 is substantially the same in configuration as the display device 100 in

[0173] Refer toFigure 8 According to another embodiment of the present specification, the display device 200 includes a substrate 201. The substrate 201 may be made of a glass material and configured as a single layer.

[0174] In a display device in the related art, a metal layer is disposed under the active layer of a driving transistor to suppress a case where a working defect occurs when the amount of current flowing through the active layer of the driving transistor decreases due to charge flow when a substrate made of polyimide (PI) is used. In the case where the metal layer is disposed under the active layer of the driving transistor, a separate mask process for forming the metal layer is required, which causes problems of increased manufacturing cost and complicated manufacturing process.

[0175] Therefore, in the display device 200 according to another embodiment of the present specification, the substrate 201 made of a glass material may be provided instead of the substrate 101 made of polyimide (PI). Therefore, in the display device 200 according to another embodiment of the present specification, a problem that the amount of current flowing through the active layer ACT of the driving transistor DT decreases does not occur, so that the metal layer disposed under the driving transistor DT may not be included. That is, a separate metal layer may not be included, and a mask process for forming the metal layer may not be included, so that the manufacturing cost may be reduced and the manufacturing process may be optimized.

[0176] Meanwhile, since the substrate is made of a glass material, the necessity of a separate metal layer may be eliminated. However, in the case where the metal layer is removed, an auxiliary capacitor formed by the metal layer may be removed. For this reason, there are problems as follows: the voltage of the gate of the driving transistor increases due to the backflow phenomenon, the voltage leaks through the second transistor, threshold voltage compensation occurs at a lower voltage, the compensation error rate increases, and a brightness deviation of the display device occurs.

[0177] Therefore, in the display device 200 according to another embodiment of the present specification, the gate GE of the driving transistor DT and the first constant voltage line CVL1 for transmitting a first constant voltage (for example, a reference voltage Vref) are disposed to overlap each other, so that an auxiliary capacitor Cgv may be formed. Therefore, in the display device 200 according to another embodiment of the present specification, even if a separate metal layer is not included, the auxiliary capacitor Cgv may be ensured. The threshold voltage compensation error rate of the driving transistor DT and the brightness deviation of the display device 200 may be minimized, which may improve the display quality.

[0178] Figure 9 is a top view of a display device according to still another embodiment of the present specification. Figure 10 is along Figure 9 in the line VIII-VIII'. The cross-sectional view taken. Except for the conductive pattern 350, Figure 9 and Figure 10The display device 300 therein is basically the same in configuration as Figures 1 to 7 the display device 100 therein. Accordingly, a repetitive description of the same components will be omitted.

[0179] Referring to Figure 9 and Figure 10 , the display device 300 further includes a conductive pattern 350 connected to one of a plurality of constant voltage lines CVL1 and CVL2 and configured to overlap with the gate GE of the driving transistor DT. For example, the conductive pattern 350 may be connected to the first constant voltage line CVL1 among the plurality of constant voltage lines.

[0180] The conductive pattern 350 may be disposed between the gate GE of the driving transistor DT and the first constant voltage line CVL1. The conductive pattern 350 may be disposed between the first interlayer insulating layer 104 and the second interlayer insulating layer 150. The conductive pattern 350 may overlap with the gate GE of the driving transistor DT. The conductive pattern 350 may be disposed on the same layer as the second capacitor electrode Cst2 and integrated with the second capacitor electrode Cst2. However, the present specification is not limited thereto. For example, like the second capacitor electrode Cst2, the conductive pattern 350 may be configured as a single layer or a multi-layer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and their alloys.

[0181] The conductive pattern 350 may extend from the second capacitor electrode Cst2 in the direction of the first constant voltage line CVL1 and overlap with a second portion of the gate GE. In addition, the conductive pattern 350 may at least partially overlap with the first constant voltage line CVL1 and be electrically connected to the first constant voltage line CVL1. For example, the conductive pattern 350 may be electrically connected to the first constant voltage line CVL1 through a contact hole formed in the second interlayer insulating layer 105. The first constant voltage line CVL1 may extend in a column direction in the sub-pixel and transmit a first constant voltage at a predetermined voltage level. For example, the first constant voltage line CVL1 may be a reference voltage line that transmits a reference voltage Vref to the sub-pixel. Accordingly, the first constant voltage may be applied to the conductive pattern 350 electrically connected to the first constant voltage line CVL1 that provides the first constant voltage, and an auxiliary capacitor Cgv may be formed between the conductive pattern 350 and the gate GE of the driving transistor DT.

[0182] In the display device 300 according to still another embodiment of the present specification, the gate GE of the driving transistor DT and the first constant voltage line CVL1 that transmits the first constant voltage (e.g., the reference voltage Vref) are disposed to overlap each other such that an auxiliary capacitor Cgv may be formed. Accordingly, in the display device 300 according to still another embodiment of the present specification, a separate metal layer may not be included, and a mask process for forming the metal layer may not be included, such that the manufacturing cost may be reduced, and the manufacturing process may be optimized.

[0183] In the display device 300 according to still another embodiment of the present specification, the gate GE of the driving transistor DT and the first constant voltage line CVL1 for transmitting the first constant voltage (e.g., the reference voltage Vref) are arranged to overlap each other, so that the auxiliary capacitor Cgv can be formed. Therefore, in the display device 300 according to still another embodiment of the present specification, even if a separate metal layer is not included, the auxiliary capacitor Cgv can be ensured. The threshold voltage compensation error rate of the driving transistor DT and the luminance deviation of the display device 300 can be minimized, which can improve the display quality.

[0184] In the display device 300 according to still another embodiment of the present specification, the conductive pattern 350 is disposed between the gate GE of the driving transistor DT and the first constant voltage line CVL1 to which the constant voltage is applied. The conductive pattern 350 is electrically connected to the first constant voltage line CVL1 and overlaps with the gate GE of the driving transistor DT. Therefore, the conductive pattern 350 electrically connected to the first constant voltage line CVL1 is arranged closer to the gate GE of the driving transistor DT than the first constant voltage line CVL1, so that the auxiliary capacitor Cgv can be formed. Therefore, in the display device 300 according to still another embodiment of the present specification, the capacitance of the auxiliary capacitor Cgv can be increased, which can ensure a sufficient capacitance of the auxiliary capacitor Cgv.

[0185] Figure 11 is a view showing an example of a sub-pixel circuit of a display device according to still another embodiment of the present specification. Figure 12 is a top view of a display device according to still another embodiment of the present specification. Figure 13 is along Figure 12 the cross-sectional view taken along the line XI-XI' in. Except for the auxiliary capacitor Cgv, the first constant voltage line CVL1, and the second constant voltage line CVL2, Figures 11 to 13 the display device 400 in Figure 8 is substantially the same as the display device 200 in

[0186] Referring to Figure 11 , the auxiliary capacitor Cgv can be disposed between the first capacitor electrode of the storage capacitor Cst and the high potential voltage line for supplying the high potential voltage Vdd. The auxiliary capacitor Cgv can suppress the voltage of the gate of the driving transistor DT from rising due to the backrush phenomenon.

[0187] Referring to Figure 12 and Figure 13 , the first constant voltage line CVL1 and the second constant voltage line CVL2 can be disposed in the sub-pixel and extend in the column direction.

[0188] The first constant voltage line CVL1 may extend in the column direction in a sub-pixel and transmit a first constant voltage at a predetermined voltage level. For example, the first constant voltage line CVL1 may be a high potential voltage line that transmits a high potential voltage Vdd to the sub-pixel. The first constant voltage line CVL1 may be electrically connected to the driving transistor DT and transmit the high potential voltage Vdd to the driving transistor DT.

[0189] The second constant voltage line CVL2 may extend in the column direction in a sub-pixel and transmit a second constant voltage at a predetermined voltage level. For example, the second constant voltage line CVL2 may be a reference voltage line that transmits a reference voltage Vref to the sub-pixel. The second constant voltage line CVL2 may be electrically connected to the fourth transistor T4 and the fifth transistor T5 and transmit the reference voltage Vref to the fourth transistor T4 and the fifth transistor T5.

[0190] The gate GE of the driving transistor DT may overlap with the first constant voltage line CVL1. The gate GE of the driving transistor DT may extend and at least partially overlap with the first constant voltage line CVL1. For example, the gate GE of the driving transistor DT may overlap with the first constant voltage line CVL1 that provides the high potential voltage Vdd (i.e., the constant voltage). Thus, the auxiliary capacitor Cgv may be formed between the first constant voltage line CVL1 that provides the first constant voltage and the gate GE of the driving transistor DT. For example, a first portion of the gate GE of the driving transistor DT may overlap with the active layer ACT of the driving transistor DT, and a second portion of the gate GE of the driving transistor DT may extend from the first portion in the direction of the first constant voltage line CVL1. That is, the first portion of the gate GE may overlap with the active layer ACT, and the second portion extending from the first portion in the direction of the first constant voltage line CVL1 may overlap with the first constant voltage line CVL1.

[0191] In the display device 400 according to another embodiment of the present specification, the gate GE of the driving transistor DT and the first constant voltage line CVL1 that provides the first constant voltage are arranged to overlap each other so that the auxiliary capacitor Cgv can be formed. Thus, in the display device 400 according to another embodiment of the present specification, a separate metal layer may not be included, and a mask process for forming the metal layer may not be included, so that the manufacturing cost can be reduced, and the manufacturing process can be optimized.

[0192] In a display device 400 according to another embodiment of the present specification, a gate GE of a driving transistor DT and a first constant voltage line CVL1 that transmits a first constant voltage (e.g., a high potential voltage Vdd) are arranged to overlap each other, so that an auxiliary capacitor Cgv can be formed. Accordingly, in the display device 400 according to another embodiment of the present specification, even without including a separate metal layer, the auxiliary capacitor Cgv can be ensured. An error rate of threshold voltage compensation of the driving transistor DT and a luminance deviation of the display device 400 can be minimized, which can improve display quality.

[0193] In a display device 400 according to another embodiment of the present specification, a gate GE of a driving transistor DT may overlap with a first constant voltage line CVL1 to which a high potential voltage Vdd having a voltage level higher than a reference voltage Vref is applied, so that an auxiliary capacitor Cgv can be formed. Accordingly, in the display device 400 according to another embodiment of the present specification, the capacitance of the capacitor Cgv can be increased, and fluctuations in a voltage value of a gate of the driving transistor can be reduced.

[0194] Figure 14 is a top view of a display device according to still another embodiment of the present specification. Figure 15 is along Figure 14 A cross-sectional view taken along line XIII-XIII' in. Except for the conductive pattern 550, Figure 14 and Figure 15 The display device 500 in is substantially the same in configuration as the display device 400 in Figures 11 to 13 Accordingly, a repeated description of the same components will be omitted.

[0195] Referring to Figure 14 and Figure 15 the display device 500 further includes a conductive pattern 550 that is connected to one of the plurality of constant voltage lines CVL1 and CVL2 and is configured to overlap with a gate GE of the driving transistor DT. For example, the conductive pattern 550 may be connected to the first constant voltage line CVL1 among the plurality of constant voltage lines.

[0196] The conductive pattern 550 may be disposed between the gate GE of the driving transistor DT and the first constant voltage line CVL1. The conductive pattern 550 may be disposed between the first interlayer insulating layer 104 and the second interlayer insulating layer 150. The conductive pattern 550 may overlap with the gate GE of the driving transistor DT. The conductive pattern 550 may be disposed on the same layer as the second capacitor electrode Cst2 and integrated with the second capacitor electrode Cst2. However, the present specification is not limited thereto. For example, like the second capacitor electrode Cst2, the conductive pattern 550 may be configured as a single layer or a multi-layer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and their alloys. For example, the conductive pattern 550 may extend from the second capacitor electrode Cst2 in the direction of the first constant voltage line CVL1 and overlap with the second portion of the gate GE. In addition, the conductive pattern 550 may at least partially overlap with the first constant voltage line CVL1 and be electrically connected to the first constant voltage line CVL1. For example, the conductive pattern 550 may be electrically connected to the first constant voltage line CVL1 through a contact hole formed in the second interlayer insulating layer 105. The first constant voltage line CVL1 may extend in the column direction in the sub-pixel and transmit the first constant voltage at a predetermined voltage level. For example, the first constant voltage line CVL1 may be a high potential voltage line that transmits the high potential voltage Vdd to the sub-pixel. Accordingly, the first constant voltage may be applied to the conductive pattern 550 electrically connected to the first constant voltage line CVL1 that provides the first constant voltage, and an auxiliary capacitor Cgv may be formed between the conductive pattern 550 and the gate GE of the driving transistor DT.

[0197] In the display device 500 according to still another embodiment of the present specification, the gate GE of the driving transistor DT and the first constant voltage line CVL1 that provides the first constant voltage are disposed to overlap each other, so that an auxiliary capacitor Cgv may be formed. Accordingly, in the display device 500 according to still another embodiment of the present specification, a separate metal layer may not be included, and a mask process for forming the metal layer may not be included, so that the manufacturing cost may be reduced and the manufacturing process may be optimized.

[0198] In the display device 500 according to still another embodiment of the present specification, the gate GE of the driving transistor DT and the first constant voltage line CVL1 that transmits the first constant voltage (e.g., the high potential voltage Vdd) are disposed to overlap each other, so that an auxiliary capacitor Cgv may be formed. Accordingly, in the display device 500 according to still another embodiment of the present specification, even if a separate metal layer is not included, the auxiliary capacitor Cgv may be ensured. The threshold voltage compensation error rate of the driving transistor DT and the luminance deviation of the display device 500 may be minimized, which may improve the display quality.

[0199] In a display device 500 according to still another embodiment of the present specification, a conductive pattern 550 is disposed between a gate GE of a driving transistor DT and a first constant voltage line CVL1 to which a constant voltage is applied. The conductive pattern 550 is electrically connected to the first constant voltage line CVL1 and overlaps with the gate GE of the driving transistor DT. Accordingly, the conductive pattern 550 electrically connected to the first constant voltage line CVL1 is disposed closer to the gate GE of the driving transistor DT than the first constant voltage line CVL1, such that an auxiliary capacitor Cgv can be formed. Accordingly, in the display device 500 according to still another embodiment of the present specification, the capacitance of the auxiliary capacitor Cgv can be increased, which can ensure a sufficient capacitance of the auxiliary capacitor Cgv.

[0200] In a display device 500 according to still another embodiment of the present specification, the gate GE of the driving transistor DT may overlap with a first constant voltage line CVL1 to which a high potential voltage Vdd having a voltage level higher than a reference voltage Vref is applied, such that an auxiliary capacitor Cgv can be formed. Accordingly, in the display device 500 according to still another embodiment of the present specification, the capacitance of the capacitor Cgv can be increased, and fluctuations in the voltage value of the gate of the driving transistor can be reduced.

[0201] Figure 16 is a view showing an example of a sub-pixel circuit of a display device according to still another embodiment of the present specification. Figure 17 is a top view of a display device according to still another embodiment of the present specification. Figure 18 is along Figure 17 a cross-sectional view taken along line XVI-XVI' in Figures 16 to 18 The display device 600 in Figures 11 to 13 is substantially the same in configuration as the display device 400 in

[0202] Referring to Figure 16 , the auxiliary capacitor Cgv may include a first auxiliary capacitor Cgv1 and a second auxiliary capacitor Cgv2. The first auxiliary capacitor Cgv1 may be formed between a first capacitor electrode of a storage capacitor Cst and a high potential voltage line supplying a high potential voltage Vdd. The second auxiliary capacitor Cgv2 may be formed between the first capacitor electrode of the storage capacitor Cst and the high potential voltage line supplying the high potential voltage Vdd. The first auxiliary capacitor Cgv1 and the second auxiliary capacitor Cgv2 may suppress an increase in the voltage of the gate of the driving transistor DT due to a kickback phenomenon.

[0203] Referring to Figure 17 and Figure 18 , the first constant voltage line CVL1 and the second constant voltage line CVL2 may be disposed in the sub-pixel and extend in a column direction.

[0204] The first constant voltage line CVL1 may extend in the column direction in the sub-pixel and transmit a first constant voltage at a predetermined voltage level. For example, the first constant voltage line CVL1 may be a reference voltage line that transmits a reference voltage Vref to the sub-pixel. The first constant voltage line CVL1 may be electrically connected to the fourth transistor T4 and the fifth transistor T5 and transmit the reference voltage Vref to the fourth transistor T4 and the fifth transistor T5.

[0205] The second constant voltage line CVL2 may extend in the column direction in the sub-pixel and transmit a second constant voltage at a predetermined voltage level. For example, the second constant voltage line CVL2 may be a high potential voltage line that transmits a high potential voltage Vdd to the sub-pixel. The second constant voltage line CVL2 may be electrically connected to the driving transistor DT and transmit the high potential voltage Vdd to the driving transistor DT.

[0206] The gate GE of the driving transistor DT may overlap with the first constant voltage line CVL1 and the second constant voltage line CVL2. The gate GE of the driving transistor DT may extend and overlap at least partially with the first constant voltage line CVL1 and the second constant voltage line CVL2. For example, the gate GE of the driving transistor DT may overlap with the first constant voltage line CVL1 that provides the reference voltage Vref (i.e., the constant voltage), and overlap with the second constant voltage line CVL2 that provides the high potential voltage Vdd (i.e., the constant voltage). Accordingly, the first auxiliary capacitor Cgv1 and the second auxiliary capacitor Cgv2 may be formed between the first constant voltage line CVL1 that provides the first constant voltage, the second constant voltage line CVL2 that provides the second constant voltage, and the gate GE of the driving transistor DT. For example, a first portion of the gate GE of the driving transistor DT may overlap with the active layer ACT of the driving transistor DT, and a second portion of the gate GE of the driving transistor DT may extend from the first portion in the direction of the second constant voltage line CVL2. That is, the first portion of the gate GE may overlap with the active layer ACT, and the second portion extending from the first portion in the direction of the second constant voltage line CVL2 may overlap with the first constant voltage line CVL1 and the second constant voltage line CVL2, such that the first auxiliary capacitor Cgv1 and the second auxiliary capacitor Cgv2 may be formed.

[0207] In the display device 600 according to another embodiment of the present specification, the gate GE of the driving transistor DT, the first constant voltage line CVL1 that provides the first constant voltage, and the second constant voltage line CVL2 that provides the second constant voltage are arranged to overlap with each other, such that an auxiliary capacitor Cgv may be formed. Accordingly, in the display device 600 according to another embodiment of the present specification, a separate metal layer may not be included, and a mask process for forming the metal layer may not be included, such that the manufacturing cost may be reduced, and the manufacturing process may be optimized.

[0208] In a display device 600 according to another embodiment of the present specification, the gate GE of the driving transistor DT, the first constant voltage line CVL1 for transmitting a first constant voltage (e.g., a reference voltage Vref), and the second constant voltage line CVL2 for transmitting a second constant voltage (e.g., a high potential voltage Vdd) are arranged to overlap each other, so that an auxiliary capacitor Cgv can be formed. Therefore, in the display device 600 according to another embodiment of the present specification, even without including a separate metal layer, the auxiliary capacitor Cgv can be ensured. The threshold voltage compensation error rate of the driving transistor DT and the luminance deviation of the display device 600 can be minimized, which can improve the display quality.

[0209] In a display device 600 according to another embodiment of the present specification, the gate GE of the driving transistor DT, the first constant voltage line CVL1 for providing a first constant voltage, and the second constant voltage line CVL2 for providing a second constant voltage are arranged to overlap each other, so that a first auxiliary capacitor Cgv1 and a second auxiliary capacitor Cgv2 can be formed. Therefore, in the display device 600 according to another embodiment of the present specification, compared with the case where the gate GE of the driving transistor DT overlaps only one of the first constant voltage line CVL1 and the second constant voltage line CVL2, the capacitance of the auxiliary capacitor Cgv can be increased, and a sufficient capacitance of the auxiliary capacitor Cgv can be ensured.

[0210] Figure 19 is a top view of a display device according to still another embodiment of the present specification. Figure 20 is along Figure 19 The cross-sectional view taken along the line XVIII-XVIII' in. Except for the conductive pattern 750, Figure 19 and Figure 20 The display device 700 in is basically the same in configuration as the display device 600 in Figures 16 to 18 Therefore, the repeated description of the same components will be omitted.

[0211] Referring to Figure 19 and Figure 20 The display device 700 further includes a conductive pattern 750 connected to one of the plurality of constant voltage lines CVL1 and CVL2 and configured to overlap with the gate GE of the driving transistor DT. For example, the conductive pattern 750 may be connected to the second constant voltage line CVL2 among the plurality of constant voltage lines.

[0212] The conductive pattern 750 may be disposed between the gate GE of the driving transistor DT and the second constant voltage line CVL2. The conductive pattern 750 may be disposed between the first interlayer insulating layer 104 and the second interlayer insulating layer 150. The conductive pattern 750 may overlap with the gate GE of the driving transistor DT. The conductive pattern 750 may be disposed on the same layer as the second capacitor electrode Cst2. For example, like the second capacitor electrode Cst2, the conductive pattern 750 may be configured as a single layer or a multi-layer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and alloys thereof. For example, the conductive pattern 750 may overlap with the second portion of the gate GE. In addition, the conductive pattern 750 may overlap with the second constant voltage line CVL2 and be electrically connected to the second constant voltage line CVL2. For example, the conductive pattern 750 may be electrically connected to the second constant voltage line CVL2 through a contact hole formed in the second interlayer insulating layer 105. The second constant voltage line CVL2 may extend in the column direction in the sub-pixel and transmit the second constant voltage at a predetermined voltage level. For example, the second constant voltage line CVL2 may be a high potential voltage line that transmits the high potential voltage Vdd to the sub-pixel. Therefore, the second constant voltage may be applied to the conductive pattern 750 electrically connected to the second constant voltage line CVL2 that provides the second constant voltage, and the auxiliary capacitor Cgv may be formed between the conductive pattern 750 and the gate GE of the driving transistor DT. That is, the second portion of the gate GE may overlap with the first constant voltage line CVL1 so that the first auxiliary capacitor Cgv1 may be formed. The second portion of the gate GE may overlap with the conductive pattern 750 electrically connected to the second constant voltage line CVL2 so that the second auxiliary capacitor Cgv2 may be formed.

[0213] In the display device 700 according to still another embodiment of the present specification, the gate GE of the driving transistor DT, the first constant voltage line CVL1 that provides the first constant voltage, and the second constant voltage line CVL2 that provides the second constant voltage are disposed to overlap each other so that the auxiliary capacitor Cgv may be formed. Therefore, in the display device 700 according to still another embodiment of the present specification, a separate metal layer may not be included, and a mask process for forming the metal layer may not be included, so that the manufacturing cost may be reduced, and the manufacturing process may be optimized.

[0214] In a display device 700 according to still another embodiment of the present specification, a gate GE of a driving transistor DT, a first constant voltage line CVL1 that transmits a first constant voltage (e.g., a reference voltage Vref), and a second constant voltage line CVL2 that transmits a second constant voltage (e.g., a high potential voltage Vdd) are arranged to overlap with each other, so that an auxiliary capacitor Cgv can be formed. Accordingly, in the display device 700 according to still another embodiment of the present specification, even without including a separate metal layer, the auxiliary capacitor Cgv can be ensured. An error rate of threshold voltage compensation of the driving transistor DT and a luminance deviation of the display device 100 can be minimized, which can improve display quality.

[0215] In a display device 700 according to still another embodiment of the present specification, a gate GE of a driving transistor DT may overlap with a first constant voltage line CVL1 that provides a first constant voltage, so that a first auxiliary capacitor Cgv1 can be formed, and the gate GE of the driving transistor DT may overlap with a conductive pattern 750 electrically connected to a second constant voltage line CVL2, so that a second auxiliary capacitor Cgv2 can be formed. Accordingly, compared with a case where the gate GE of the driving transistor DT overlaps with only one of the first constant voltage line CVL1 and the second constant voltage line CVL2, the capacitance of the auxiliary capacitor Cgv can be increased and a sufficient capacitance of the auxiliary capacitor Cgv can be ensured.

[0216] In a display device 700 according to still another embodiment of the present specification, a conductive pattern 750 is disposed between a gate GE of a driving transistor DT and a second constant voltage line CVL2 to which a constant voltage is applied. The conductive pattern 750 is electrically connected to the second constant voltage line CVL2 and overlaps with the gate GE of the driving transistor DT. Accordingly, the conductive pattern 750 electrically connected to the second constant voltage line CVL2 is disposed closer to the gate GE of the driving transistor DT than the second constant voltage line CVL2, so that a second auxiliary capacitor Cgv2 can be formed. Accordingly, in the display device 700 according to still another embodiment of the present specification, the capacitance of the auxiliary capacitor Cgv can be increased, which can ensure a sufficient capacitance of the auxiliary capacitor Cgv.

[0217] In a display device 700 according to still another embodiment of the present specification, a gate GE of a driving transistor DT may overlap with a conductive pattern 750 electrically connected to a second constant voltage line CVL2 to which a high potential voltage Vdd having a voltage level higher than a reference voltage Vref is applied, so that a second auxiliary capacitor Cgv2 can be formed. Accordingly, in the display device 700 according to still another embodiment of the present specification, the capacitance of the auxiliary capacitor Cgv can be increased, and fluctuations in the voltage value of the gate of the driving transistor can be reduced.

[0218] A display device according to an exemplary embodiment of the present disclosure may also be described as follows:

[0219] A display device according to an exemplary embodiment of the present disclosure includes a plurality of sub-pixels; a plurality of sub-pixel circuits respectively disposed in the plurality of sub-pixels, and each of the plurality of sub-pixel circuits includes a driving transistor; and a plurality of constant voltage lines connected to each of the plurality of sub-pixel circuits, wherein a gate of the driving transistor overlaps at least one of the plurality of constant voltage lines.

[0220] The plurality of constant voltage lines may include a first constant voltage line to which a first constant voltage is applied, and the gate of the driving transistor may overlap the first constant voltage line.

[0221] The first constant voltage may be one of a reference voltage and a high potential power supply voltage.

[0222] The plurality of constant voltage lines may further include a second constant voltage line to which a second constant voltage is applied, and the gate of the driving transistor overlaps the first constant voltage line and the second constant voltage line.

[0223] One of the reference voltage and the high potential power supply voltage may be the first constant voltage, and the other of the reference voltage and the high potential power supply voltage may be the second constant voltage.

[0224] The display device may further include a substrate, a gate insulating layer disposed between the active layer of the driving transistor and the gate of the driving transistor, and an interlayer insulating layer disposed between the gate of the driving transistor and the source and drain of the driving transistor, wherein at least one of the plurality of constant voltage lines is disposed on the interlayer insulating layer.

[0225] The substrate may include a first plastic substrate, a second plastic substrate, and an inorganic layer disposed between the first plastic substrate and the second plastic substrate.

[0226] The substrate may be made of glass.

[0227] The gate of the driving transistor may include a first portion configured to overlap the active layer of the driving transistor and a second portion extending from the first portion and configured to overlap at least one of the plurality of constant voltage lines.

[0228] The display device may further include a conductive pattern connected to at least one of the plurality of constant voltage lines and configured to overlap the gate of the driving transistor.

[0229] Each of the plurality of sub-pixel circuits may include a driving transistor configured to control a driving current to be applied to a light-emitting element, a first transistor configured to supply a data voltage to a first node in response to a first scan signal, a second transistor configured to supply a voltage of a second node to a third node in response to a second scan signal, a third transistor configured to supply a voltage of the third node to a fourth node in response to a light-emitting signal, a fourth transistor configured to supply a reference voltage to the fourth node in response to the second scan signal, and a fifth transistor configured to supply a reference voltage to the first node in response to the light-emitting signal.

[0230] Each of the plurality of sub-pixel circuits may further include a storage capacitor, and wherein a gate of the driving transistor may form an auxiliary capacitor with at least one of a plurality of constant voltage lines.

[0231] A display device according to another exemplary embodiment of the present disclosure includes a substrate on which a plurality of sub-pixels are defined, a driving transistor provided in each of the plurality of sub-pixels on the substrate, a first constant voltage line connected to each of the plurality of sub-pixels and to which a first constant voltage is applied, and a second constant voltage line connected to each of the plurality of sub-pixels and to which a second constant voltage is applied, wherein a gate of the driving transistor overlaps at least one of the first constant voltage line and the second constant voltage line.

[0232] The substrate may include a first organic layer, a second organic layer on the first organic layer, and an inorganic layer between the first organic layer and the second organic layer.

[0233] The substrate may be made of glass.

[0234] The first constant voltage may be one of a reference voltage and a high potential voltage, and the second constant voltage may be the other of the reference voltage and the high potential voltage.

[0235] The gate of the driving transistor may overlap the first constant voltage line and the second constant voltage line.

[0236] The display device may further include a conductive pattern configured to overlap at least one of the first constant voltage line and the second constant voltage line, wherein the conductive pattern overlaps the gate of the driving transistor.

[0237] The conductive pattern may be electrically connected to at least one of the first constant voltage line and the second constant voltage line.

[0238] A display device according to still another exemplary embodiment of the present disclosure includes: a plurality of sub-pixels; a plurality of sub-pixel circuits respectively provided in the plurality of sub-pixels, wherein each of the plurality of sub-pixel circuits includes: a driving transistor; a storage capacitor connected to the driving transistor; and at least one auxiliary capacitor provided between the storage capacitor and a reference voltage line or a high potential voltage line.

[0239] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The protection scope of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be construed as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: Multiple sub-pixels; a plurality of sub-pixel circuits, respectively disposed in the plurality of sub-pixels and each of the plurality of sub-pixel circuits comprising a driving transistor; as well as a plurality of constant voltage lines connected to each of the plurality of sub-pixel circuits; Wherein, the gate of the driving transistor overlaps with at least one of the plurality of constant voltage lines.

2. The display device according to claim 1, wherein: The plurality of constant voltage lines include a first constant voltage line to which a first constant voltage is applied, and the gate of the driving transistor overlaps the first constant voltage line.

3. The display device according to claim 2, wherein: The first constant voltage is one of a reference voltage and a high potential power supply voltage.

4. The display device according to claim 2, wherein: The plurality of constant voltage lines further include a second constant voltage line to which a second constant voltage is applied, and the gate of the driving transistor overlaps the first constant voltage line and the second constant voltage line.

5. The display device according to claim 4, wherein: One of a reference voltage and a high potential power supply voltage is the first constant voltage, and the other of the reference voltage and the high potential power supply voltage is the second constant voltage.

6. The display device according to claim 1, further comprising: substrate; a gate insulating layer, disposed between the active layer of the driving transistor and the gate of the driving transistor; as well as an interlayer insulating layer, disposed between the gate electrode of the driving transistor and the source electrode and the drain electrode of the driving transistor, Wherein, at least one of the plurality of constant voltage lines is arranged on the interlayer insulating layer.

7. The display device according to claim 6, wherein: The substrate comprises: a first plastic substrate; a second plastic substrate; and The inorganic layer is disposed between the first plastic substrate and the second plastic substrate.

8. The display device according to claim 6, wherein: The substrate is made of glass.

9. The display device according to claim 6, wherein: The gate of the driving transistor includes: a first portion configured to overlap the active layer of the driving transistor; and The second portion extends from the first portion and is configured to overlap with at least one of the plurality of constant pressure lines.

10. The display device according to claim 1, further comprising: A conductive pattern connected to at least one of the plurality of constant voltage lines and configured to overlap the gate of the driving transistor.

11. The display device according to claim 1, wherein: Each of the plurality of sub-pixel circuits comprises: The driving transistor is configured to control a driving current to be applied to the light emitting element; a first transistor configured to provide a data voltage to a first node in response to a first scan signal; a second transistor configured to provide a voltage of the second node to the third node in response to a second scan signal; a third transistor configured to provide a voltage of the third node to a fourth node in response to a light emitting signal; a fourth transistor configured to provide a reference voltage to the fourth node in response to the second scan signal; and A fifth transistor is configured to provide the reference voltage to the first node in response to the light emitting signal.

12. The display device according to claim 1, wherein: Each of the plurality of sub-pixel circuits further includes a storage capacitor, and The gate of the driving transistor and the at least one of the plurality of constant voltage lines form an auxiliary capacitor.

13. A display device, comprising: a substrate on which a plurality of sub-pixels are defined; a driving transistor disposed in each of the plurality of sub-pixels on the substrate; a first constant voltage line connected to each of the plurality of sub-pixels and applied with a first constant voltage; as well as a second constant voltage line connected to each of the plurality of sub-pixels and applied with a second constant voltage, The gate of the driving transistor overlaps with at least one of the first constant voltage line and the second constant voltage line.

14. The display device according to claim 13, wherein: The substrate comprises: A first organic layer; a second organic layer on the first organic layer; and An inorganic layer is between the first organic layer and the second organic layer.

15. The display device according to claim 13, wherein: The substrate is made of glass.

16. The display device according to claim 13, wherein: The first constant voltage is one of a reference voltage and a high potential voltage, and the second constant voltage is the other of the reference voltage and the high potential voltage.

17. The display device according to claim 16, wherein: The gate of the driving transistor overlaps the first constant voltage line and the second constant voltage line.

18. The display device according to claim 16, further comprising: a conductive pattern configured to overlap at least one of the first constant voltage line and the second constant voltage line, Wherein, the conductive pattern overlaps with the gate of the driving transistor.

19. The display device according to claim 18, wherein: The conductive pattern is electrically connected to at least one of the first constant voltage line and the second constant voltage line.

20. A display device, comprising: Multiple sub-pixels; A plurality of sub-pixel circuits are respectively arranged in the plurality of sub-pixels, Wherein, each of the plurality of sub-pixel circuits comprises: Driver transistor; a storage capacitor connected to the driving transistor; and At least one auxiliary capacitor is provided between the storage capacitor and a reference voltage line or a high potential voltage line.

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