Display driving circuit and display device

Abstract

The embodiment of the invention provides a display driving circuit and a display device, relates to the technical field of display, and is used for solving the problems of complex wiring and large wiring occupied space of the display device. The display driving circuit comprises at least one driving circuit group, a data channel and a time schedule controller, wherein the driving circuit group comprises at least two source electrode driving circuits; one data channel is electrically connected with at least one source driving circuit of the driving circuit group, and the data channel is electrically connected to the time schedule controller; wherein the time schedule controller is configured to provide a data group signal for the at least one driving circuit group through the data channel, and the data group signal comprises a plurality of data signals respectively required by the at least two source driving circuits in the driving circuit group; the source electrode driving circuit is configured to receive the data set signals, identify data signals needed by the source electrode driving circuit from the data set signals and output gray scale data signals according to the identified data signals.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display driving circuit and a display device. Background Art

[0002] As one of the mainstream display technologies, the liquid crystal display (LCD) has been widely used in consumer electronics (such as smart phones and tablet computers), industrial equipment, medical displays, vehicle-mounted displays, etc. due to its low power consumption, high resolution, and mature manufacturing process.

[0003] However, the complex wiring and large space occupied by the wiring of the display device have become one of the important factors hindering the evolution of display technologies towards high refresh rates, ultra-thinness, flexibility, etc. Summary of the Invention

[0004] The purpose of the embodiments of the present disclosure is to provide a display driving circuit and a display device, which are used to solve the problems of complex wiring and large space occupied by the wiring of the display device.

[0005] To achieve the above purpose, the embodiments of the present disclosure provide the following technical solutions:

[0006] On the one hand, a display driving circuit is provided, including: at least one driving circuit group, a data channel, and a timing controller. The driving circuit group includes at least two source driving circuits. One of the data channels is electrically connected to at least one of the source driving circuits of the driving circuit group. The data channel is electrically connected to the timing controller. Wherein, the timing controller is configured to provide a data group signal to at least one of the driving circuit groups through the data channel, and the data group signal includes a plurality of data signals required by at least two of the source driving circuits in the driving circuit group respectively. The source driving circuit is configured to receive the data group signal, identify the data signal required by itself from the data group signal, and output a grayscale data signal according to the identified data signal.

[0007] The number of data channels is less than the number of source driving circuits and equal to the number of driving circuit groups, which not only greatly reduces the number of data channels in the display driving circuit, but also shortens the wiring length from the timing controller to the source driving circuit, saving a large amount of wiring space.

[0008] In addition, each source driving circuit included in each driving circuit group needs to receive N data signals in the data group signal simultaneously, and then match and output the data signals required by itself, so the transmission rate at this time is N times that when transmitting a single data signal alone, greatly improving the transmission rate of the data signal. Wherein N is an integer greater than or equal to 2.

[0009] In a feasible embodiment, the display driving circuit includes a plurality of the driving circuit groups and a plurality of the data channels. The plurality of data channels are electrically connected to the plurality of driving circuit groups in a one-to-one correspondence, and the plurality of data channels are all electrically connected to the timing controller.

[0010] In a feasible embodiment, the multiple source driving circuits included in the driving circuit group are cascaded in sequence through the one data channel. The input end of the first-stage source driving circuit is electrically connected to the corresponding data channel to receive the data group signal. Among two adjacent stages of source driving circuits, the output end of the previous-stage source driving circuit is electrically connected to the input end of the next-stage source driving circuit, and the previous-stage source driving circuit transmits the data group signal to the next-stage source driving circuit.

[0011] The transmission path of the data signal is output from the timing controller to each corresponding source driving circuit respectively and becomes a direct transmission between adjacent source driving circuits, greatly reducing the attenuation loss of the data signal during transmission. It can ensure the signal quality under a higher transmission rate, thereby improving the display effect of the display device.

[0012] In a feasible embodiment, the source driving circuit includes an equalization sub-circuit and a cache sub-circuit. The equalization sub-circuit is configured to receive the data group signal and compensate the data group signal. The cache sub-circuit is electrically connected to the equalization sub-circuit and is configured to store the compensated data group signal. The equalization sub-circuit is electrically connected to the cache sub-circuit of the previous-stage source driving circuit to receive the data group signal stored in the cache sub-circuit.

[0013] In a feasible embodiment, the cache sub-circuit includes a first cache unit and a second cache unit, which are respectively electrically connected to the equalization sub-circuit and are configured to store the compensated data group signal. The equalization sub-circuit is electrically connected to the second cache unit of the previous-stage source driving circuit to receive the data group signal stored in the second cache unit.

[0014] Since at least two source driving circuits in the driving circuit group are in a cascaded form, the data group signal passes through the equalization sub-circuits of multiple source driving circuits, and the distal signal is output after passing through multiple source driving circuits. That is, multiple signal optimization means can be superimposed. When passing through the equalization sub-circuit of each source driving circuit, the data group signal can be compensated once. After the data group signal reaches the target source driving circuit, the equalization sub-circuit of the target source driving circuit can also perform a compensation, further improving the signal quality.

[0015] In a feasible embodiment, the input ends of the multiple source driver circuits included in the driver circuit group are respectively electrically connected to the corresponding data channels, and are configured to respectively receive the data group signals from the data channels.

[0016] The multiple source driver circuits included in the driver circuit group simultaneously perform matching reading of the data group signals, avoiding abnormalities of the data group signals due to factors such as component differences, timing, and noise during the transmission process, ensuring data consistency, and improving the display quality of the display device.

[0017] In a feasible embodiment, each data signal includes a first identification bit, and the first identification bits included in different data signals in the same data group signal are different; each source driver circuit has a second identification, and the second identifications of different source driver circuits in the same driver circuit group are different; one first identification bit matches one second identification.

[0018] In a feasible embodiment, the driver circuit group further includes an identification circuit. The identification circuit includes multiple identification modules, and the identification modules are configured to provide second identifications corresponding to the source driver circuits.

[0019] In a feasible embodiment, the identification module includes a first resistor and a second resistor. The first resistor of at least one identification module is configured to be electrically connected to a first voltage terminal, and the second resistor of at least one identification module is configured to be electrically connected to a second voltage terminal. At least one of the multiple voltage terminals to which different identification modules are electrically connected is different, and the voltage signals output by the first resistor and the second resistor of the identification module are used to form the second identification.

[0020] In a feasible embodiment, the display driver circuit further includes a first circuit board and multiple second circuit boards. The timing control circuit is disposed on the first circuit board. The multiple source driver circuits of one driver circuit group are electrically connected to one second circuit board, and the multiple second circuit boards are respectively electrically connected to the first circuit board. The first resistor and the second resistor are disposed on the second circuit board.

[0021] In a feasible embodiment, the first resistor is electrically connected to a first voltage terminal on the second circuit board; the display driver circuit further includes a power management circuit disposed on the first circuit board, and the second resistor is electrically connected to the second voltage terminal of the power management circuit through a power line.

[0022] In a feasible embodiment, the source driver circuit includes a logic control sub-circuit. The logic control sub-circuit is electrically connected to the corresponding identification module to read the second identification provided by the identification module.

[0023] In a feasible embodiment, the source driver circuit further includes an output sub-circuit. The output sub-circuit is electrically connected to the logic control sub-circuit to receive the second identifier transmitted by the logic control sub-circuit. The output sub-circuit is configured to identify, from the data group signal, the data signal corresponding to the first identification bit that matches the second identifier, and output a grayscale data signal according to the identified data signal.

[0024] The logic control sub-circuit and the output sub-circuit in the source driver circuit obtain the second identifier corresponding to the source driver circuit through the identification module, then read the first identification bits of the respective data signals in the data group signal, and output a grayscale data signal according to the data signal corresponding to the first identification bit that matches the second identifier.

[0025] In a feasible embodiment, the data channel includes a first sub-data channel and a second sub-data channel, and the signals transmitted by the first sub-data channel and the signals transmitted by the second sub-data channel are opposite in phase.

[0026] On the other hand, a display device is provided, including a display panel and the above-mentioned display driver circuit, and the display driver circuit is electrically connected to the display panel.

[0027] The above display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual dimensions of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present disclosure.

[0029] Figure 1 Structural diagram of a display device according to some embodiments;

[0030] Figure 2 Structural diagram of a display device according to some embodiments;

[0031] Figure 3 Structural diagram of another display device according to some embodiments;

[0032] Figure 4 For Figure 2 Structural diagram of the source driver circuit in

[0033] Figure 5 A signal compensation diagram of a display device according to some embodiments;

[0034] Figure 6 A compensation flow chart of a display device according to some embodiments;

[0035] Figure 7 For Figure 6 The signal diagram of the receiving end of the timing controller in

[0036] Figure 8 For Figure 6 The signal diagram after compensation by the timing controller in

[0037] Figure 9 A structural diagram of another display device according to some embodiments;

[0038] Figure 10 For Figure 9 A partial enlarged view of the AA area in the display device;

[0039] Figure 11 For Figure 10 A partial enlarged view of the BB area in

[0040] Figure 12 For Figure 11 The signal timing diagram of the differential pair trace in

[0041] Figure 13 A structural diagram of another display device according to some embodiments;

[0042] Figure 14 A structural diagram of another display device according to some embodiments;

[0043] Figure 15 A structural diagram of a driving circuit group according to some embodiments;

[0044] Figure 16 A signal structure diagram of a data signal according to some embodiments;

[0045] Figure 17 For Figure 9 A partial enlarged view of the AA area in

[0046] Figure 18 A structural diagram of another driving circuit group according to some embodiments;

[0047] Figure 19 Another signal compensation diagram of a display device according to some embodiments;

[0048] Figure 20 The data signal diagram output by the source driver circuit after one compensation;

[0049] Figure 21 The data signal diagram output by the source driver circuit after two compensations;

[0050] Figure 22 The data signal diagram output by the source driver circuit after three compensations;

[0051] Figure 23 The structural diagram of another display device according to some embodiments. Detailed implementation manners

[0052] Next, the technical solutions in some embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0053] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted in an open, inclusive sense, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples" or "some examples", etc., are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily directed to the same embodiment or example. In addition, the described specific features, structures, materials or characteristics can be included in any one or more embodiments or examples in any appropriate manner.

[0054] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.

[0055] When describing some embodiments, the expressions "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium; it may be an electrical connection or a mechanical connection. The embodiments disclosed herein are not necessarily limited to the content herein.

[0056] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0057] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0058] As used herein, depending on the context, the term "if" is optionally interpreted to mean "when", "while", "in response to determining", or "in response to detecting". Similarly, depending on the context, the phrase "if it is determined that..." or "if [the stated condition or event] is detected" is optionally interpreted to mean "when it is determined that...", "in response to determining...", "when [the stated condition or event] is detected", or "in response to detecting [the stated condition or event]".

[0059] The use of "configured to" in this document means open and inclusive language, which does not exclude devices configured to perform additional tasks or steps.

[0060] As used herein, "about", "substantially", or "approximately" includes the stated value and the average value within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurement being discussed and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).

[0061] As used herein, "parallel", "perpendicular", "equal" include the stated situations and situations similar to the stated situations, and the range of the similar situations is within an acceptable deviation range, where the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurement being discussed and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and approximate parallel, where the acceptable deviation range of approximate parallel can be, for example, within 5° deviation; "perpendicular" includes absolute perpendicular and approximate perpendicular, where the acceptable deviation range of approximate perpendicular can also be, for example, within 5° deviation. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range of approximate equality can be, for example, the difference between the two equal values is less than or equal to 5% of either one of them.

[0062] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can also be an intermediate layer between the layer or element and the other layer or substrate.

[0063] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Accordingly, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations resulting from, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0064] Figure 1 The figure is a structural diagram of a display device according to some embodiments. As Figure 1 shown, embodiments of the present disclosure provide a display device 1000, and the display device 1000 is a product with an image display function. Exemplarily, the display device 1000 may be any device that displays whether it is moving (e.g., video) or stationary (e.g., still image) and whether it is text or image.

[0065] Exemplarily, the display device 1000 may be a television, a laptop computer, a tablet computer, a personal digital assistant (PDA), a mobile phone (cell phone), a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a display of a camera view (e.g., a display of a rear-view camera in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, an in-vehicle display, a flight display, or any other product or component with a display function. For example, as Figure 1 shown, the display device 1000 may be a mobile phone.

[0066] In terms of the light-emitting type of the display device 1000, the above-mentioned display device 1000 may be a liquid crystal display (LCD) device, an organic light-emitting diode (OLED) display device, or a quantum dot light-emitting diode (QLED) display device. In terms of the form of the display device 1000, the above-mentioned display device 1000 may be a flat display device, a curved display device, or a foldable display device, etc. In terms of the shape of the display device 1000, the above-mentioned display device 1000 may be rectangular or circular, etc.

[0067] Here, taking a liquid crystal display device in which the display device 1000 is rectangular and planar as an example, some embodiments of the present disclosure will be schematically described. However, the embodiments of the present disclosure are not limited thereto, and any other display device may also be considered as long as the same technical concept is applied.

[0068] Figure 2 It is a structural diagram of a display device according to some embodiments. The display device 1000 includes a display panel 100, a display driving circuit 200, and a plurality of data lines 603.

[0069] The display panel 100 includes a plurality of pixel units (not shown in the figure) arranged in an array. The display driving circuit 200 is connected to the plurality of data lines 603. The display driving circuit 200 provides a plurality of grayscale data signals corresponding to the number of data lines 603, and provides the plurality of grayscale data signals to the selected pixel units in the display panel 100, so that the display device 1000 realizes image display. Exemplarily, the display panel 100 may be a 4k, 60Hz display panel.

[0070] The display driving circuit 200 includes a timing controller 301, a first circuit board 302, a source driving circuit 502, a second circuit board 503, a first connection portion 601, and a second connection portion 602.

[0071] The source driving circuit 502 is selected from a chip on film (COF) package. Exemplarily, each source driving circuit 502 can provide 960 channels. To cover the entire display panel 100, 12 source driving circuits 502 are required. In Figure 2 Among them, the 12 source driving circuits 502 are divided into four groups, with three source driving circuits 502 in each group, and the source driving circuits 502 in the same group are arranged on the same second circuit board 503, that is, three source driving circuits 502 are respectively provided on the second circuit boards 503a, 503b, 503c, and 503d.

[0072] The timing controller 301 is disposed on the first circuit board 302. The timing controller 301 is configured to provide corresponding data signals to each source driving circuit 502 through a plurality of data channels 401. Exemplarily, the display driving circuit 200 includes 12 data channels 401. One ends of the 12 data channels 401 are all connected to the timing controller 301, and the other ends are respectively connected to the source driving circuits 502 to provide the data signals provided by the timing controller 301 to the corresponding source driving circuits 502.

[0073] In some feasible embodiments, the timing controller 301 and the multiple source driver circuits 502 are respectively located on different circuit boards. Therefore, the multiple data channels 401 are respectively connected to the source driver circuits 502 on the corresponding circuit boards through the first connection portion 601 and / or the second connection portion 602. Exemplarily, 3 data channels 401 are connected to the second circuit board 503b through the first connection portion 601, and then connected to the corresponding source driver circuit 502 located on the second circuit board 503a through the second connection portion 602. 3 data channels 401 are connected to the corresponding source driver circuit 502 on the second circuit board 503b through the first connection portion 601. 3 data channels 401 are connected to the corresponding source driver circuit 502 on the second circuit board 503c through the first connection portion 601. 3 data channels 401 are connected to the second circuit board 503c through the first connection portion 601, and then connected to the corresponding source driver circuit 502 located on the second circuit board 503d through the second connection portion 602.

[0074] In Figure 3 In the shown display driving circuit 200, the rate of each source driver circuit 502, data rate = (Htotal * Vtotal * RGB * ColorDeepth * FreameRate) / (number of Sources * number of pairs * (24 / 28)), where Htotal is the number of pixels in the horizontal direction of the display panel 100, Vtotal is the number of pixels in the vertical direction of the display panel 100, RGB = 3, Color Deepth is the bit depth of the display panel 100, Frame Rate is the refresh rate of the display panel 100, and the number of Sources is the number of source driver circuits 502 included in the display device 1000. Substituting the parameters of the display device 1000, the rate of each source driver circuit 502, data rate = (4400 * 2200 * 3 * 8 * 60) / (12 * 1 *

[0075] (24 / 28)) = 1.36 Gbps.

[0076] Figure 3 It is a structural diagram of another display device according to some embodiments. The display device 1000 includes a display panel 100 and a display driving circuit 200. The display driving circuit 200 is connected to the display panel 100 through, for example, a data line 603 to provide a grayscale data signal to the display panel 100. Exemplarily, the display panel 100 can be a 4k, 60Hz display panel.

[0077] The display driving circuit 200 includes a timing controller 301, a first circuit board 302, a source driving circuit 502, a second circuit board 503, a first connection portion 601, and a second connection portion 602. Exemplarily, the display driving circuit 200 includes six source driving circuits 502. In Figure 3 , the six source driving circuits 502 are divided into two groups, with three source driving circuits 502 in each group, and the source driving circuits 502 in the same group are disposed on the same second circuit board 503, that is, three source driving circuits 502 are respectively provided on the second circuit board 503a and the second circuit board 503b.

[0078] The timing controller 301 is disposed on the first circuit board 302, and the timing controller 301 is configured to provide corresponding data signals to each source driving circuit 502 through a plurality of data channels 401. Exemplarily, the display driving circuit 200 includes six data channels 401. One ends of the six data channels 401 are all connected to the timing controller 301, and the other ends are respectively connected to the source driving circuits 502 to provide the data signals provided by the timing controller 301 to the corresponding source driving circuits 502.

[0079] In some feasible embodiments, the timing controller 301 and the plurality of source driving circuits 502 are respectively located on different circuit boards. Therefore, the plurality of data channels 401 are respectively connected to the source driving circuits 502 on the corresponding circuit boards through the first connection portion 601. Exemplarily, three data channels 401 are connected to the corresponding source driving circuits 502 on the second circuit board 503a through the first connection portion 601, and three data channels 401 are connected to the corresponding source driving circuits 502 on the second circuit board 503b through the first connection portion 601.

[0080] In Figure 4 In the shown display driving circuit 200, the rate data rate of each source driving circuit 502 = (Htotal * Vtotal * RGB * ColorDeepth * FreameRate) / (Source number * pair number * (24 / 28)). Substituting the parameters of the display device 1000, the rate data rate of each source driving circuit 502 = (4400 * 2200 * 3 * 8 * 60) / (6 * 1 * (24 / 28)) = 2.72 Gbps.

[0081] In Figure 3In the shown display driving circuit 200, each source driving circuit 502 corresponds to a data channel 401. Multiple data channels 401 pass through a Printed Circuit Board (PCB), a Flexible Printed Circuit Board (FPC), and / or a connector (Connect, CNT), which will occupy a large amount of routing space. On the one hand, a large amount of space needs to be reserved for the routing of the data channels 401, and it is impossible to reduce the number of circuit board layers and / or the number of pins. On the other hand, at least some of the data channels 401 are too long, and the attenuation loss is large during the transmission of data signals, affecting the display quality of the display device 1000.

[0082] Figure 4 For Figure 2 is the structural diagram of the source driving circuit in. The source driving circuit 502 includes a serial-to-parallel conversion sub-circuit 801, a shift register sub-circuit 802, a latch sub-circuit 803, a digital-to-analog conversion sub-circuit 804, a multi-channel output sub-circuit 805, and a logic control sub-circuit 806.

[0083] The serial-to-parallel conversion sub-circuit 801 is configured to receive a first data signal data1, a second data signal data2, and a third data signal data3, and convert one or more data signals from a serial signal to a parallel signal. The shift register sub-circuit 802 is connected to a first operating voltage VCCD and a second operating voltage VSSD, and is connected to the latch sub-circuit 803. Exemplarily, the shift register sub-circuit 802 can be a bidirectional shift register. The latch sub-circuit 803 is connected to the serial-to-parallel conversion sub-circuit 801, and the first operating voltage VCCD and the second operating voltage VSSD to receive and latch one or more data signals that have been converted into parallel signals. Exemplarily, the latch sub-circuit 803 includes a first latch and a second latch. The digital-to-analog conversion sub-circuit 804 is connected to the latch sub-circuit 803 and receives a gamma signal GMA<1:18> to convert the data signal provided by the latch sub-circuit 803 into a grayscale data signal. The multi-channel output sub-circuit 805 is connected to the digital-to-analog conversion sub-circuit 804 to provide the grayscale signal provided by the digital-to-analog conversion sub-circuit 804 to the display panel 100. The logic control sub-circuit 806 is respectively connected to the serial-to-parallel conversion sub-circuit 801 and the multi-channel output sub-circuit 805, for example, to control the serial-to-parallel conversion of one or more data signals in the serial-to-parallel conversion sub-circuit 801, and the output of one or more grayscale signals in the multi-channel output sub-circuit 805.

[0084] Exemplarily, after one or more data signals are serially-parallel converted by the serial-parallel conversion sub-circuit 801 and shifted by the shift register sub-circuit 802, under the control of the logic control sub-circuit 806 and / or the shift register sub-circuit 802, the data of the nth row is transmitted to the first latch of the latch sub-circuit 803. After the second latch of the latch sub-circuit 803 provides the data of the (n - 1)th row to the digital-to-analog conversion sub-circuit 804, the data of the nth row is then transmitted to the second latch of the latch sub-circuit 803. The digital-to-analog conversion sub-circuit 804 generates corresponding grayscale data signals according to the gamma signal GMA<1:18> and the data signals provided by the latch sub-circuit 803. Exemplarily, the digital-to-analog conversion sub-circuit 804 subdivides the data signals into 256 grayscale voltages to provide to the multi-output sub-circuit 805.

[0085] Figure 5 A signal compensation diagram of a display device according to some embodiments. Figure 5 shows a partial structure of the display device 1000, in combination with Figure 2 and Figure 6 The signal compensation process of the display device 1000 will be described. The source driver circuit 502a, the source driver circuit 502b, and the source driver circuit 502c are connected to the same second circuit board 503. The source driver circuit 502a receives the first data signal data1, compensates the first data signal data1, converts it into a grayscale data signal, and provides it to the display panel 100. The source driver circuit 502b receives the second data signal data2, compensates the second data signal data2, converts it into a grayscale data signal, and provides it to the display panel 100. The source driver circuit 502c receives the third data signal data3, compensates the third data signal data3, converts it into a grayscale data signal, and provides it to the display panel 100.

[0086] Figure 6 A compensation flow chart of a display device according to some embodiments, Figure 7 is Figure 6 a signal diagram of the receiving end of the timing controller in Figure 8 is Figure 6 a signal diagram of the timing controller after compensation. In Figure 6In [the figure], the display device 1000 further includes a third circuit board 303. The third circuit board 303 may be a System on Chip (SOC). The timing controller 301 is connected to the third circuit board 303. The timing controller 301 receives an initial signal TX. The feed-forward equalization circuit 304 performs feed-forward equalization compensation (FFE) on the initial signal TX and provides the compensated initial signal TX to the timing controller 301. Due to attenuation and loss in the connection line between the third circuit board 303 and the timing controller 301, the signal of the initial signal TX is already distorted to a certain extent when it reaches the receiving end of the timing controller 301. Exemplarily, if the initial signal TX is an eye diagram, it has become Figure 8 the eye diagram shown. The continuous-time linear equalization (CTLE) circuit 305 of the timing controller 301 receives the initial signal TX and performs continuous-time linear equalization compensation on it to generate a data group signal data, and provides the data group signal data to the corresponding source driver circuit 502. The eye diagram after being compensated by the continuous-time linear equalization (CTLE) circuit 305 is as Figure 7 shown. However, after providing the data group signal data compensated by the continuous-time linear equalization (CTLE) circuit 305 to the source driver circuit 502, the source driver circuit 502 compensates it sequentially, which is not sufficient to well compensate for the loss and attenuation of the data group signal data. Especially for the source driver circuit 502 with a long data channel 401 far from the timing controller 301, it is likely to cause abnormal display of the display device 1000.

[0087] Figure 9 It is a structural diagram of another display device according to some embodiments. The display device 1000 includes a display panel 100 and a display driving circuit 200. The display driving circuit 200 is connected to the display panel 100 through, for example, a data line 603 to provide a grayscale data signal to the display panel 100. Exemplarily, the display panel 100 may be a 4K, 60Hz display panel.

[0088] The display driving circuit 200 includes a timing controller 301, a first circuit board 302, a driving circuit group 501, a second circuit board 503, a first connection portion 601, and a second connection portion 602. The display driving circuit 200 includes one or more driving circuit groups 501, and each driving circuit group 501 includes at least two source driving circuits 502. Each driving circuit group 501 is located on a different second circuit board 503. The data channel 401 is connected to at least one source driving circuit 502 in the driving circuit group 501, and the data channel 401 is connected to the timing controller 301. The timing controller 301 is located on the first circuit board 302, and the timing controller 301 is configured to provide a corresponding data group signal data to at least one driving circuit group 501 through the data channel 401. The data group signal data includes a plurality of data signals required by at least two source driving circuits 502 in the driving circuit group 501. The source driving circuit 502 is configured to receive the data group signal data, identify the data signal required by itself from the data group signal data, and output a grayscale data signal to the display panel 100 according to the identified data signal.

[0089] In some feasible embodiments, the display driving circuit 200 includes four driving circuit groups 501, namely, a driving circuit group 501a, a driving circuit group 501b, a driving circuit group 501c, and a driving circuit group 501d. Each driving circuit group 501 includes 3 source driving circuits 502 respectively. Exemplarily, the timing controller 301 and a plurality of source driving circuits 502 are located on different circuit boards respectively. Therefore, multiple data channels 401 are connected to the source driving circuits 502 on the corresponding circuit boards through the first connection portion 601 and / or the second connection portion 602 respectively. The timing controller 301 is connected to the driving circuit group 501a through the data channel 401a, that is, connected to the second circuit board 503 where the driving circuit group 501b is located through the first connection portion 601, and then connected to the driving circuit group 501b through the second connection portion 602. The timing controller 301 is connected to the driving circuit group 501b through the data channel 401b, that is, connected to the driving circuit group 501b through the first connection portion 601. The timing controller 301 is connected to the driving circuit group 501c through the data channel 401c, that is, connected to the driving circuit group 501c through the first connection portion 601. The timing controller 301 is connected to the driving circuit group 501d through the data channel 401d, that is, connected to the second circuit board 503 where the driving circuit group 501c is located through the first connection portion 601, and then connected to the driving circuit group 501d through the second connection portion 602.

[0090] Inside each driving circuit group 501, the input end of the first-stage source driving circuit 502 is connected to the corresponding data channel 401 to receive the data group signal data. Among adjacent two-stage source driving circuits 502, the output end of the previous-stage source driving circuit 502 is connected to the input end of the next-stage source driving circuit 502, and the previous-stage source driving circuit 502 transmits the data group signal data to the next-stage source driving circuit 502, as Figure 10 shown, Figure 10 is Figure 9 a partial enlarged view of the AA area in the display device.

[0091] Taking the second circuit board 503 where the driving circuit group 501b is located as an example, the connection method of multiple source driving circuits 502 in the driving circuit group 501 in the Figure 9 shown display driving circuit 200 will be described. The driving circuit group 501b includes a total of 3 source driving circuits 502, namely a source driving circuit 502a, a source driving circuit 502b, and a source driving circuit 502c. The timing controller 301 is connected to the input end of the source driving circuit 502a through the data channel 401b via the first connection part 601 to provide the data group signal data to the source driving circuit 502a. One of the output ends of the source driving circuit 502a is connected to the input end of the source driving circuit 502b to transmit the data group signal data to the source driving circuit 502b. One of the output ends of the source driving circuit 502b is connected to the source driving circuit 502c to transmit the data group signal data to the source driving circuit 502c.

[0092] In some feasible embodiments, one end of the flip-chip thin film package of the source driving circuit 502 is directly connected to the display panel 100, and the other end is directly connected to the second circuit board 503. In Figure 9 , the inside of the dashed box of the display driving circuit 200 also includes a part of the display panel 100. This is for the purpose of clear drawing and convenient description, and does not mean that a part of the structure of the display panel 100 is a component of the display driving circuit 200.

[0093] In some feasible embodiments, the data channel 401 can be differential pair traces, as Figure 11 and Figure 12 shown. Figure 11 is Figure 10 a partial enlarged view of the BB area in Figure 12 is Figure 11 the signal timing diagram of the differential pair traces in. The data channel 401 can be differential pair signal lines. 401a includes a first sub-data channel 401aa and a second sub-data channel 401ab. Figure 12From top to bottom are the first differential sub-signal Vcedn, the second differential sub-signal Vcedp, and the signal difference Vdiff. Among them, the dashed line is 0V, and the dotted line is the common-mode voltage Vcm (Input Common Mode Voltage). The first sub-data channel 401aa transmits the first differential sub-signal Vcedn, for example, and the second sub-data channel 401ab transmits the second differential sub-signal Vcedp, for example. The difference between the first differential sub-signal Vcedn and the second differential sub-signal Vcedp is the signal difference Vdiff, for example. Since the difference between the first differential sub-signal Vcedn and the second differential sub-signal Vcedp has positive and negative values, the signal difference Vdiff also includes a part greater than or equal to 0V and a part less than or equal to 0V. For the first differential sub-signal Vcedn and the second differential sub-signal Vcedp, the common-mode voltage Vcm clock is in the middle position. It can be seen that before and after the moment t0, when the common-mode voltage Vcm changes and the change amount is ΔVcm, the first differential sub-signal Vcedn and the second differential sub-signal Vcedp change together with the common-mode voltage Vcm, and their signal difference Vdiff remains unchanged.

[0094] In some feasible embodiments, the signal difference Vdiff greater than 1 represents the digital signal 1, and the signal difference Vdiff less than 1 represents the digital signal 0.

[0095] In some feasible embodiments, the connection of multiple source driver circuits 502 in the driver circuit group 501 also adopts the differential pair signal line method.

[0096] Figure 9 In the shown display device 1000, the display driver circuit 200 includes a total of 12 source driver circuits 502 and 4 data channels 401. The number of data channels 401 is less than the number of source driver circuits 502 and equal to the number of driver circuit groups 501. This not only greatly reduces the number of data channels 401 in the display driver circuit 200 but also shortens the wiring length from the timing controller 301 to the source driver circuits 502, saving a large amount of wiring space. The transmission path of the data signal is output from the timing controller 301 to each corresponding source driver circuit 502 respectively and becomes a direct transfer between adjacent source driver circuits 502, greatly reducing the attenuation loss. It can ensure the signal quality under a higher transmission rate, thereby improving the display effect of the display device 1000.

[0097] In addition, the source driver circuit 502 needs to receive 3 data signals simultaneously and then output the data signals required by itself through matching. So the transmission rate at this time is Figure 2 3 times that of the shown display device 1000, which is 1.36G * 3 =

[0098] 4.08Gbps.

[0099] Figure 13 The figure is a structural diagram of another display device according to some embodiments. The display device 1000 includes a display panel 100 and a display driving circuit 200. The display driving circuit 200 is connected to the display panel 100 through a data line 603 to provide a grayscale data signal to the display panel 100.

[0100] The display driving circuit 200 includes a timing controller 301, a first circuit board 302, a driving circuit group 501, a second circuit board 503, and a first connection portion 601. The display driving circuit 200 includes two driving circuit groups 501, namely a driving circuit group 501a and a driving circuit group 501b. Each driving circuit group 501 includes three source driving circuits 502, and each driving circuit group 501 is located on a different second circuit board 503. The timing controller 301 is connected to the driving circuit group 501a through a data channel 401a to provide a corresponding data group signal data to the driving circuit group 501a. The timing controller 301 is connected to the driving circuit group 501b through a data channel 401b to provide a corresponding data group signal data to the driving circuit group 501b. The data channel 401a and the data channel 401b are connected to the corresponding driving circuit groups 501 through the first connection portion 601, for example. Inside each driving circuit group 501, the input end of the first-stage source driving circuit 502 is connected to the corresponding data channel 401 to receive the data group signal data. Among adjacent two-stage source driving circuits 502, the output end of the previous-stage source driving circuit 502 is connected to the input end of the next-stage source driving circuit 502, and the previous-stage source driving circuit 502 transmits the data group signal data to the next-stage source driving circuit 502. The source driving circuit 502 is further configured to receive the data group signal data, identify the data signal required by itself from the data group signal data, and output a grayscale data signal to the display panel 100 according to the identified data signal.

[0101] Figure 13 In the shown display device 1000, the display driving circuit 200 includes a total of 6 source driving circuits 502 and 2 data channels 401.

[0102] Figure 14 The figure is a structural diagram of another display device according to some embodiments. The display device 1000 includes a display panel 100 and a display driving circuit 200. The display driving circuit 200 is connected to the display panel 100 through a data line 603 to provide a grayscale data signal to the display panel 100.

[0103] The display driving circuit 200 includes a timing controller 301, a first circuit board 302, a driving circuit group 501, a second circuit board 503, and a first connection portion 601. The display driving circuit 200 includes three driving circuit groups 501, namely, a driving circuit group 501a, a driving circuit group 501b, and a driving circuit group 501c. Each driving circuit group 501 includes three source driving circuits 502, and each driving circuit group 501 is located on a different second circuit board 503. The timing controller 301 is connected to the driving circuit group 501a through a data channel 401a to provide a corresponding data group signal data to the driving circuit group 501a. The timing controller 301 is connected to the driving circuit group 501b through a data channel 401b to provide a corresponding data group signal data to the driving circuit group 501b. The timing controller 301 is connected to the driving circuit group 501c through a data channel 401c to provide a corresponding data group signal data to the driving circuit group 501c. Inside each driving circuit group 501, the input end of the first-stage source driving circuit 502 is connected to the corresponding data channel 401 to receive the data group signal data. Among adjacent two-stage source driving circuits 502, the output end of the previous-stage source driving circuit 502 is connected to the input end of the next-stage source driving circuit 502, and the previous-stage source driving circuit 502 transmits the data group signal data to the next-stage source driving circuit 502. The source driving circuit 502 is further configured to receive the data group signal data, identify the data signal required by itself from the data group signal data, and output a grayscale data signal to the display panel 100 according to the identified data signal.

[0104] Figure 14 In the shown display device 1000, the display driving circuit 200 includes a total of six source driving circuits 502 and three data channels 401.

[0105] Figure 15 It is a structural diagram of a driving circuit group according to some embodiments. In combination with Figure 9 and Figure 10 the structure of the driving circuit group 501 in some embodiments will be described. The driving circuit group 501 includes three source driving circuits 502, and each source driving circuit 502 includes a receiving sub-circuit 701, an equalizing sub-circuit 702, a caching sub-circuit 703, a restoring sub-circuit 704, a latching sub-circuit 705, a digital-to-analog conversion sub-circuit 706, 797, and a logic control sub-circuit 708.

[0106] The receiving sub - circuit 701 is configured to receive the data group signal data. The equalization sub - circuit 702 is connected to the receiving sub - circuit 701 and is configured to receive the data group signal data and compensate the data group signal data. The caching sub - circuit 703 is connected to the equalization sub - circuit 702 and is configured to store the compensated data group signal data. The recovery sub - circuit 704 is connected to the caching sub - circuit 703 and is configured to perform clock - data recovery on the compensated data group signal data. The latching sub - circuit 705 is connected to the recovery sub - circuit 704 and is configured to receive the data group signal data after clock - data recovery and latch the data group signal data. The digital - to - analog conversion sub - circuit 706 is connected to the latching sub - circuit 705 and is configured to receive the data group signal data and perform digital - to - analog conversion on the data group signal data, converting the data group signal data into a digital signal. Exemplarily, the digital - to - analog conversion sub - circuit 706 also receives a gamma signal and converts the gamma signal according to the data group signal data. The logic control sub - circuit 708 is configured to receive the second identifier cn. The output sub - circuit 707 is connected to the logic control sub - circuit 708 to receive the second identifier cn transmitted by the logic control sub - circuit 708. The output sub - circuit 707 is configured to identify the data group signal data corresponding to the first identification bit cf that matches the second identifier cn from the data group signal data and output the corresponding grayscale data signal according to the identified data group signal data.

[0107] Exemplarily, the receiving sub - circuit 701 of the source driver circuit 502a is connected to the data channel 401 to receive the data group signal data provided by the timing controller 301. The receiving sub - circuit 701 of the source driver circuit 502b is connected to the caching sub - circuit 703 of the source driver circuit 502a to receive the data group signal data transmitted by the source driver circuit 502a. The receiving sub - circuit 701 of the source driver circuit 502c is connected to the caching sub - circuit 703 of the source driver circuit 502b to receive the data group signal data transmitted by the source driver circuit 502b.

[0108] In some feasible embodiments, for the output sub - circuit 707 to identify the first identification bit cf of each data signal in the data group signal data, reference can be made to Figure 16 , Figure 16It is a signal structure diagram of a data signal according to some embodiments. The data signal is a Clock Embedded Differential Signal (CEDS), and the data signal includes an Initial Clock Training, a first frame signal, a second frame signal... an nth frame signal. A Vertical Blank Period is further included between two adjacent frame signals. Among them, before the Initial Clock Training, there is a meaningless random signal Unk (Unknown) before the signal transmission starts.

[0109] Each frame signal includes multiple lines of data signals. Taking the third line of data signal 3 rd Line as an example, the data signal includes a Configuration signal, a Pixel Data signal, and a Clock Training signal. A first identification bit cf is added to the Configuration signal to enable the output sub-circuit 707 to identify the first identification bit cf that matches the second identification cn from each data signal of the data group signal data. Exemplarily, the first identification bit cf includes two bit positions and can generate four different first identification bits: HH, HL, LH, and LL.

[0110] Exemplarily, the data signal can also be any one of a Unified Standard Interface for TV (USIT) or a China BOE Point-to-Point Interface (CHPI).

[0111] In some feasible embodiments, for the logic control sub-circuit 708 to receive the second identification cn, reference can be made to Figure 17 , Figure 17 is Figure 9 a partial enlarged view of the AA area in Figure 17Shows a partial structure related to the second identifier cn, and shows that the display driving circuit 200 further includes an identification circuit 901, a first voltage terminal 903, and a second voltage terminal 904. The identification circuit 901 includes a plurality of identification modules 902, and the identification module 902 is configured to provide a second identifier cn corresponding to the source driving circuit 502. Exemplarily, the identification module 902 includes a first resistor R1 and a second resistor R2. The first resistor R1 of at least one identification module 902 is configured to be connected to the first voltage terminal 903, and the second resistor R2 of at least one identification module 902 is configured to be connected to the second voltage terminal 904. The first voltage terminal 903 is provided on the first circuit board 302 and is configured to provide a first voltage. The second voltage terminal 904 is provided on the second circuit board 503, and the second voltage terminal 904 may be a ground terminal.

[0112] In some feasible embodiments, corresponding to the number of source driving circuits 502 included in a driving circuit group 501, the identification module 902 includes an identification module 902a, an identification module 902b, and an identification module 902c. In the identification module 902a, one end of the first resistor R1 is connected to the first voltage terminal 903, and the other end is connected to the source driving circuit 502a. One end of the second resistor R2 is connected to the first voltage terminal 903, and the other end is connected to the source driving circuit 502a. The identification module 902a provides a second identifier cna to the source driving circuit 502a, and the second identifier cna may be HH. In the identification module 902b, one end of the first resistor R1 is connected to the second voltage terminal 904, and the other end is connected to the source driving circuit 502b. One end of the second resistor R2 is connected to the first voltage terminal 903, and the other end is connected to the source driving circuit 502b. The identification module 902b provides a second identifier cnb to the source driving circuit 502b, and the second identifier cnb may be LH. In the identification module 902c, one end of the first resistor R1 is connected to the second voltage terminal 904, and the other end is connected to the source driving circuit 502c. One end of the second resistor R2 is connected to the first voltage terminal 903, and the other end is connected to the source driving circuit 502c. The identification module 902c provides a second identifier cnc to the source driving circuit 502c, and the second identifier cnc may be LL.

[0113] Continue to refer to Figure 15, the data group signal data received by the source driver circuit 502a includes a first data signal data1, a second data signal data2, and a third data signal data3. The output sub-circuit 707 receives the second identifier cna transmitted by the logic control sub-circuit 708 and identifies the first identification bit cf of the first data signal data1, the second data signal data2, and the third data signal data3. Since the first identification bit cf of the first data signal data1 is HH and matches the second identifier cna, the output sub-circuit 707 of the source driver circuit 502a outputs the first data signal data1 as the grayscale data signal. The data group signal data received by the source driver circuit 502b includes a first data signal data1, a second data signal data2, and a third data signal data3. The output sub-circuit 707 receives the second identifier cnb transmitted by the logic control sub-circuit 708 and identifies the first identification bit cf of the first data signal data1, the second data signal data2, and the third data signal data3. Since the first identification bit cf of the second data signal data2 is LH and matches the second identifier cnb, the output sub-circuit 707 of the source driver circuit 502b outputs the second data signal data2 as the grayscale data signal. The data group signal data received by the source driver circuit 502c includes a first data signal data1, a second data signal data2, and a third data signal data3. The output sub-circuit 707 receives the second identifier cnc transmitted by the logic control sub-circuit 708 and identifies the first identification bit cf of the first data signal data1, the second data signal data2, and the third data signal data3. Since the first identification bit cf of the third data signal data3 is LL and matches the second identifier cnc, the output sub-circuit 707 of the source driver circuit 502b outputs the third data signal data3 as the grayscale data signal.

[0114] In some feasible embodiments, the logic control sub-circuit 708 and the output sub-circuit 707 in the source driver circuit 502 obtain the second identifier cn corresponding to the source driver circuit 502 by reading the identification module 902, then read the first identification bit cf of each data signal in the data group signal data, and output the grayscale data signal according to the data signal corresponding to the first identification bit cf that matches the second identifier cn.

[0115] The display device 1000 realizes transmitting the data that multiple source driver circuits 502 need to receive simultaneously on one data channel 401. For example, the data group signals data of three source driver circuits 502 are transmitted on the bus. Among them, the data group signal data includes a first data signal data1, a second data signal data2, and a third data signal data3. Each source driver circuit 502 individually outputs the required first data signal data1 or second data signal data2 or third data signal data3.

[0116] In some feasible embodiments, refer to Figure 18 , Figure 18 which is a structural diagram of another driving circuit group according to some embodiments. In Figure 18 , the buffer sub - circuit 703 of the source driver circuit 502 includes 703a and 703b. 703a receives the compensated data group signal data from the equalization sub - circuit 702, and the restoration sub - circuit 704 is connected to 703a to receive the compensated data group signal data. 703b is connected to the equalization sub - circuit 702 to receive the compensated data group signal data from the equalization sub - circuit 702, and transmits the compensated data group signal data to the next - stage source driver circuit 502. Figure 18 The remaining structure of the source driver circuit 502 shown in Figure 15 is similar to that of the source driver circuit 502 shown in

[0117] Figure 18 Figure 18 If the source driver circuit shown in Figure 19 is adopted, signal compensation can be performed as shown in Figure 19 which is another signal compensation diagram of the display device according to some embodiments. Figure 20 is the data signal diagram output by the source driver circuit after one - time compensation, Figure 21 is the data signal diagram output by the source driver circuit after two - time compensation, Figure 22 is the data signal diagram output by the source driver circuit after three - time compensation. Figure 19 shows a partial structure of the display device 1000. Combining Figure 9The signal compensation process of the display device 1000 will be described. The source driver circuits 502a, 502b, and 502c are connected to the same second circuit board 503. The source driver circuit 502a receives the data group signal data provided by the timing controller 301, compensates the data group signal data, and converts the first data signal data1 matching the source driver circuit 502a into a grayscale data signal and provides it to the display panel 100. The source driver circuit 502b receives the data group signal data transmitted by the source driver circuit 502a, can compensate the data group signal data again, and converts the second data signal data2 matching the source driver circuit 502b into a grayscale data signal and provides it to the display panel 100. The source driver circuit 502c receives the data group signal data transmitted by the source driver circuit 502b, compensates the data group signal data, and converts the third data signal data3 matching the source driver circuit 502c into a grayscale data signal and provides it to the display panel 100. It can be seen that the second data signal data2 output by the source driver circuit 502b can be compensated twice, and the third data signal data3 output by the source driver circuit 502c can be compensated three times.

[0118] Exemplarily, if the third data signal data3 provided by the source driver circuit 502c undergoes one compensation, the output data signal diagram is as Figure 19 shown. If the third data signal data3 provided by the source driver circuit 502c undergoes two compensations, the output data signal diagram is as Figure 20 shown. If the third data signal data3 provided by the source driver circuit 502c undergoes three compensations, the output data signal diagram is as Figure 21 shown.

[0119] In Figure 18 the source driver circuit 502 shown, the equalization sub-circuit 702 can independently modulate the gear position, compensate the data group signal data to different degrees, so as to ensure that the signal quality of the data group signal data meets the requirements when it reaches each source driver circuit 502, and achieve a balance between signal quality and power consumption. Exemplarily, the cache sub-circuit 703 includes 0 - 3 gear positions, 0 - 3 are arranged from small to large, and the 0th gear position is to turn off compensation. If the equalization sub-circuit 702 in the source driver circuit 502a is set to the 2nd gear position, the signal quality of the data group signal data still meets the requirements when it reaches the source driver circuit 502b after transmission loss and attenuation. The equalization sub-circuit 702 of the source driver circuit 502b can be set to the 0th gear position to reduce the power consumption of the display device 1000. When the data group signal data is transmitted to the source driver circuit 502c, the gear position of the equalization sub-circuit 702 of the source driver circuit 502c is adjusted according to the signal quality.

[0120] Since at least two source driver circuits 502 in the driving circuit group 501 are in a cascaded form, the data group signal data passes through the equalization sub-circuits 702 of multiple source driver circuits 502, and the remote signal is output after passing through multiple source driver circuits 502. That is, multiple signal optimization means can be superimposed, and the data group signal data can be compensated once when passing through the equalization sub-circuit 702 of each source driver circuit 502. After the data group signal data reaches the target source driver circuit 502, the equalization sub-circuit 702 of the target source driver circuit 502 can also perform a compensation to further improve the signal quality.

[0121] Figure 23 It is a structural diagram of another display device according to some embodiments. In each driving circuit group 501 of the display driving circuit 200, the input ends of multiple source driver circuits 502 are respectively connected to the corresponding data channels 401 to receive the data group signal data provided by the timing controller 301. Figure 23 The shown display device 1000 and Figure 9 the remaining structures of the shown display device 1000 are basically the same, so they will not be described in detail.

[0122] Figure 23 In the shown display device 1000, multiple source driver circuits 502 included in the driving circuit group 501 perform matching reading of the data group signal data simultaneously, avoiding abnormalities of the data group signal data due to factors such as component differences, timing, and noise during the transmission process, ensuring data consistency, and improving the display quality of the display device 1000.

[0123] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure, thinking of changes or substitutions, should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claimed rights.

Claims

1. A display driving circuit, characterized in that: include: at least one driving circuit group, the driving circuit group comprising at least two source driving circuits; A data channel, wherein one of the data channels is electrically connected to at least one source driving circuit of the driving circuit group; A timing controller, the data channel being electrically connected to the timing controller; Wherein, the timing controller is configured to provide a data group signal to at least one of the driving circuit groups through the data channel, wherein the data group signal includes a plurality of data signals required by at least two of the source driving circuits in the driving circuit group respectively; The source driving circuit is configured to receive the data group signal, identify the data signal required by itself from the data group signal, and output a grayscale data signal according to the identified data signal.

2. The display driving circuit according to claim 1, characterized in that: include: a plurality of said driving circuit groups; A plurality of data channels, wherein the plurality of data channels are electrically connected to the plurality of driving circuit groups in a one-to-one correspondence; The plurality of data channels are electrically connected to the timing controller.

3. The display driving circuit according to claim 1, characterized in that: The plurality of source driving circuits included in the driving circuit group are cascaded in sequence through one of the data channels; The input end of the first-stage source driving circuit is electrically connected to the corresponding data channel to receive the data group signal; In the two adjacent source driving circuits, the output end of the source driving circuit of the previous stage is electrically connected to the input end of the source driving circuit of the next stage, and the source driving circuit of the previous stage transmits the data group signal to the source driving circuit of the next stage.

4. The display driving circuit according to claim 3, characterized in that: The source driving circuit comprises: an equalization subcircuit, configured to receive the data group signal and compensate the data group signal; a buffer subcircuit, electrically connected to the equalization subcircuit, configured to store the compensated data group signal; The equalization sub-circuit is electrically connected to the cache sub-circuit of the source driving circuit of the previous stage to receive the data group signal stored in the cache sub-circuit.

5. The display driving circuit according to claim 4, characterized in that: The cache subcircuit comprises: A first cache unit and a second cache unit, respectively electrically connected to the equalization subcircuit, and configured to store the compensated data group signal; The equalization sub-circuit is electrically connected to the second cache unit of the source driving circuit of the previous stage to receive the data group signal stored in the second cache unit.

6. The display driving circuit according to claim 1, characterized in that: Input terminals of a plurality of source driving circuits included in the driving circuit group are respectively electrically connected to the corresponding data channels, and are configured to respectively receive the data group signals from the data channels.

7. The display driving circuit according to any one of claims 1 to 6, characterized in that: Each of the data signals includes a first identification bit, and different data signals in the same data group signal include different first identification bits; Each of the source driving circuits has a second identifier, and different source driving circuits in the same driving circuit group have different second identifiers; one first identifier matches one second identifier.

8. The display driving circuit according to claim 7, characterized in that: The driving circuit group further includes: The identification circuit includes a plurality of identification modules, wherein the identification modules are configured to provide a second identification corresponding to the source driving circuit.

9. The display driving circuit according to claim 8, characterized in that: The identification module comprises a first resistor and a second resistor, the first resistor of at least one identification module is configured to be electrically connected to a first voltage terminal, and the second resistor of at least one identification module is configured to be electrically connected to a second voltage terminal; At least one of the multiple voltage terminals to which different identification modules are electrically connected is different, and the voltage signals output by the first resistor and the second resistor of the identification module are used to form the second identification.

10. The display driving circuit according to claim 9, characterized in that: The display driving circuit also includes a first circuit board and a plurality of second circuit boards; The timing control circuit is arranged on the first circuit board, a plurality of source driving circuits of one driving circuit group is electrically connected to one second circuit board, and the plurality of second circuit boards are electrically connected to the first circuit board respectively; The first resistor and the second resistor are arranged on the second circuit board.

11. The display driving circuit according to claim 10, characterized in that: The first resistor is electrically connected to a first voltage terminal on the second circuit board; The display driving circuit further includes a power management circuit disposed on the first circuit board, and the second resistor is electrically connected to the second voltage terminal of the power management circuit via a power line.

12. The display driving circuit according to claim 8, characterized in that: The source driving circuit comprises: The logic control subcircuit is electrically connected to the corresponding identification module to read the second identification provided by the identification module.

13. The display driving circuit according to claim 12, characterized in that: The source driving circuit further includes: an output subcircuit, electrically connected to the logic control subcircuit to receive the second identifier transmitted by the logic control subcircuit; The output subcircuit is configured to identify, from the data group signal, a data signal corresponding to a first identification bit that matches the second identification bit, and output a grayscale data signal according to the identified data signal.

14. The display driving circuit according to any one of claims 1 to 6, characterized in that: The data channel includes: A first sub-data channel and a second sub-data channel, wherein a signal transmitted by the first sub-data channel and a signal transmitted by the second sub-data channel are in opposite phases.

15. A display device, characterized in that: include: Display panel; The display driving circuit according to any one of claims 1 to 14, wherein the display driving circuit is electrically connected to the display panel.

Images